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581c2943f5
- reset was broken! - need to account for wait - merging read/write wait for simplicity, otherwise you would need to reset the packets to figure out if it's a read or write transaction...and I don't want to reset every packet throughout the pipe.
394 lines
14 KiB
Verilog
394 lines
14 KiB
Verilog
module erx_core (/*AUTOARG*/
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// Outputs
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rx_rd_wait, rx_wr_wait, idelay_value, load_taps, rxrd_access,
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rxrd_packet, rxrr_access, rxrr_packet, rxwr_access, rxwr_packet,
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erx_cfg_wait, mailbox_full, mailbox_not_empty,
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// Inputs
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reset, clk, rx_packet, rx_access, rx_burst, rxrd_wait, rxrr_wait,
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rxwr_wait, erx_cfg_access, erx_cfg_packet
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h800;
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//clock and reset
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input reset; //synced to clk
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input clk;
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//IO Interface
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input [PW-1:0] rx_packet;
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input rx_access;
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input rx_burst;
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output rx_rd_wait;
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output rx_wr_wait;
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output [44:0] idelay_value;
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output load_taps;
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//FIFO Access
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output rxrd_access;
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output [PW-1:0] rxrd_packet;
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input rxrd_wait;
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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input rxrr_wait;
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output rxwr_access;
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output [PW-1:0] rxwr_packet;
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input rxwr_wait;
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//register interface
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input erx_cfg_access;
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input [PW-1:0] erx_cfg_packet;
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output erx_cfg_wait;
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//mailbox outputs
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output mailbox_full; //need to sync to sys_clk
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output mailbox_not_empty; //need to sync to sys_clk
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire ecfg_access; // From erx_cfgif of ecfg_if.v
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wire [PW-1:0] ecfg_packet; // From erx_cfgif of ecfg_if.v
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wire edma_access; // From erx_dma of edma.v
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wire edma_wait; // From erx_arbiter of erx_arbiter.v
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wire emesh_remap_access; // From erx_remap of erx_remap.v
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wire [PW-1:0] emesh_remap_packet; // From erx_remap of erx_remap.v
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wire emmu_access; // From erx_mmu of emmu.v
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wire [PW-1:0] emmu_packet; // From erx_mmu of emmu.v
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wire [PW-1:0] erx_packet; // From erx_protocol of erx_protocol.v
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wire erx_rdwr_access; // From erx_protocol of erx_protocol.v
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wire erx_rr_access; // From erx_protocol of erx_protocol.v
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wire erx_test_access; // From erx_protocol of erx_protocol.v
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wire [31:0] erx_test_data; // From erx_protocol of erx_protocol.v
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wire [14:0] mi_addr; // From erx_cfgif of ecfg_if.v
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wire [DW-1:0] mi_cfg_dout; // From erx_cfg of erx_cfg.v
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wire mi_cfg_en; // From erx_cfgif of ecfg_if.v
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wire [63:0] mi_din; // From erx_cfgif of ecfg_if.v
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wire [DW-1:0] mi_dma_dout; // From erx_dma of edma.v
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wire mi_dma_en; // From erx_cfgif of ecfg_if.v
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wire [63:0] mi_mailbox_dout; // From erx_mailbox of emailbox.v
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wire [DW-1:0] mi_mmu_dout; // From erx_mmu of emmu.v
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wire mi_mmu_en; // From erx_cfgif of ecfg_if.v
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wire mi_we; // From erx_cfgif of ecfg_if.v
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wire mmu_enable; // From erx_cfg of erx_cfg.v
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wire [31:0] remap_base; // From erx_cfg of erx_cfg.v
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wire [1:0] remap_mode; // From erx_cfg of erx_cfg.v
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wire [11:0] remap_pattern; // From erx_cfg of erx_cfg.v
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wire [11:0] remap_sel; // From erx_cfg of erx_cfg.v
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wire test_mode; // From erx_cfg of erx_cfg.v
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// End of automatics
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//regs
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wire [8:0] gpio_datain; // To erx_cfg of erx_cfg.v
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wire [15:0] rx_status;
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wire rxwr_full;
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wire rxrr_full;
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wire rxrd_full;
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wire rxrd_empty;
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wire rxwr_empty;
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wire rxrr_empty;
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wire [103:0] edma_packet; // From edma of edma.v, ...
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/**************************************************************/
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/*ELINK PROTOCOL LOGIC */
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/**************************************************************/
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defparam erx_protocol.ID=ID;
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erx_protocol erx_protocol (/*AUTOINST*/
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// Outputs
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.erx_test_access (erx_test_access),
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.erx_test_data (erx_test_data[31:0]),
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.erx_rdwr_access (erx_rdwr_access),
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.erx_rr_access (erx_rr_access),
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.erx_packet (erx_packet[PW-1:0]),
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// Inputs
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.clk (clk),
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.test_mode (test_mode),
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.rx_packet (rx_packet[PW-1:0]),
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.rx_burst (rx_burst),
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.rx_access (rx_access));
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/**************************************************************/
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/*ADDRESS REMPAPPING */
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/**************************************************************/
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/*erx_remap AUTO_TEMPLATE (
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.emesh_\(.*\)_out (emesh_remap_\1[]),
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//Inputs
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.emesh_access_in (erx_rdwr_access),
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.emesh_\(.*\)_in (erx_\1[]),
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.mmu_en (ecfg_rx_mmu_enable),
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.emesh_packet_hi_out (),
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);
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*/
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defparam erx_remap.ID = ID;
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erx_remap erx_remap (/*AUTOINST*/
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// Outputs
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.emesh_access_out(emesh_remap_access), // Templated
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.emesh_packet_out(emesh_remap_packet[PW-1:0]), // Templated
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// Inputs
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.clk (clk),
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.emesh_access_in(erx_rdwr_access), // Templated
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.emesh_packet_in(erx_packet[PW-1:0]), // Templated
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.remap_mode (remap_mode[1:0]),
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.remap_sel (remap_sel[11:0]),
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.remap_pattern (remap_pattern[11:0]),
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.remap_base (remap_base[31:0]));
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/************************************************************/
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/*ELINK MEMORY MANAGEMENT UNIT */
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/************************************************************/
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/*emmu AUTO_TEMPLATE (
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.emesh_\(.*\)_out (emmu_\1[]),
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//Inputs
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.emesh_\(.*\)_in (emesh_remap_\1[]),
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.mmu_en (mmu_enable),
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.rd_clk (clk),
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.wr_clk (clk),
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.mi_dout (mi_mmu_dout[DW-1:0]),
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.emesh_packet_hi_out (),
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.mi_en (mi_mmu_en),
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);
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*/
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emmu erx_mmu (.mmu_bp (1'b0), //why is this zero??
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.emesh_wait (1'b0),
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
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.emesh_access_out (emmu_access), // Templated
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.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
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.emesh_packet_hi_out (), // Templated
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// Inputs
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.rd_clk (clk), // Templated
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.wr_clk (clk), // Templated
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.mmu_en (mmu_enable), // Templated
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.mi_en (mi_mmu_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[DW-1:0]),
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.emesh_access_in (emesh_remap_access), // Templated
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.emesh_packet_in (emesh_remap_packet[PW-1:0])); // Templated
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/************************************************************/
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/*EMAILBOX */
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/************************************************************/
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/*emailbox AUTO_TEMPLATE (
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.mi_en (mi_cfg_en),
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.mi_dout (mi_mailbox_dout[]),
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.wr_clk (clk),
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.rd_clk (clk),
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.emesh_access (emmu_access),
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.emesh_packet (emmu_packet[PW-1:0]),
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.rd_reset (reset),
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.wr_reset (reset),
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);
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*/
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defparam erx_mailbox.ID=ID;
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emailbox erx_mailbox(
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_mailbox_dout[63:0]), // Templated
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.mailbox_full (mailbox_full),
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.mailbox_not_empty(mailbox_not_empty),
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// Inputs
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.wr_reset (reset), // Templated
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.wr_clk (clk), // Templated
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.rd_clk (clk), // Templated
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.rd_reset (reset), // Templated
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.emesh_access (emmu_access), // Templated
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.emesh_packet (emmu_packet[PW-1:0]), // Templated
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.mi_en (mi_cfg_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[RFAW+1:0]),
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.mi_din (mi_din[63:0]));
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/************************************************************/
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/* CONFIGURATION INTERFACE */
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/************************************************************/
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/*ecfg_if AUTO_TEMPLATE (
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.wait_in (erx_cfg_wait),
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.\(.*\)_in (erx_cfg_\1[]),
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.\(.*\)_out (ecfg_\1[]),
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.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}),
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.mi_dout1 ({32'b0,mi_dma_dout[31:0]}),
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.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}),
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.mi_dout3 (mi_mailbox_dout[63:0]),
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);
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*/
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defparam erx_cfgif.RX=1;
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ecfg_if erx_cfgif (/*AUTOINST*/
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// Outputs
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.mi_mmu_en (mi_mmu_en),
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.mi_dma_en (mi_dma_en),
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.mi_cfg_en (mi_cfg_en),
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[63:0]),
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.access_out (ecfg_access), // Templated
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.packet_out (ecfg_packet[PW-1:0]), // Templated
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// Inputs
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.clk (clk),
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.access_in (erx_cfg_access), // Templated
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.packet_in (erx_cfg_packet[PW-1:0]), // Templated
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.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
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.mi_dout1 ({32'b0,mi_dma_dout[31:0]}), // Templated
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.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
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.mi_dout3 (mi_mailbox_dout[63:0]), // Templated
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.wait_in (erx_cfg_wait)); // Templated
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/************************************************************/
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/* ERX CONFIGURATION */
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/************************************************************/
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/*erx_cfg AUTO_TEMPLATE (.mi_dout (mi_cfg_dout[DW-1:0]),
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.mi_en (mi_cfg_en),
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);
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*/
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assign rx_status[15:0] = {16'b0};
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assign gpio_datain[8:0]=9'b0;
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/*
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assign gpio_datain[8:0]= {rx_frame_par[0],
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rx_data_par[7],
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rx_data_par[6],
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rx_data_par[5],
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rx_data_par[4],
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rx_data_par[3],
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rx_data_par[2],
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rx_data_par[1],
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rx_data_par[0]
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};
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*/
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erx_cfg erx_cfg (.rx_status (rx_status[15:0]),
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.timer_cfg (),
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.rx_enable (),//TODO:what to do with this??
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_cfg_dout[DW-1:0]), // Templated
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.mmu_enable (mmu_enable),
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.remap_mode (remap_mode[1:0]),
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.remap_base (remap_base[31:0]),
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.remap_pattern (remap_pattern[11:0]),
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.remap_sel (remap_sel[11:0]),
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.idelay_value (idelay_value[44:0]),
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.load_taps (load_taps),
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.test_mode (test_mode),
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// Inputs
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.reset (reset),
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.clk (clk),
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.mi_en (mi_cfg_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[31:0]),
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.erx_test_access (erx_test_access),
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.erx_test_data (erx_test_data[31:0]),
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.gpio_datain (gpio_datain[8:0]));
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/************************************************************/
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/*ELINK DMA */
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/************************************************************/
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/*edma AUTO_TEMPLATE (
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.mi_en (mi_dma_en),
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.edma_access (edma_access),
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.mi_dout (mi_dma_dout[DW-1:0]),
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);
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*/
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edma erx_dma(/*AUTOINST*/
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// Outputs
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.mi_dout (mi_dma_dout[DW-1:0]), // Templated
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.edma_access (edma_access), // Templated
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.edma_packet (edma_packet[PW-1:0]),
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// Inputs
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.reset (reset),
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.clk (clk),
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.mi_en (mi_dma_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[RFAW+1:0]),
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.mi_din (mi_din[63:0]),
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.edma_wait (edma_wait));
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/************************************************************/
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/*ELINK RECEIVE DISTRIBUTOR ("DEMUX") */
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/*(figures out who RX transaction belongs to) */
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/************************************************************/
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/*erx_arbiter AUTO_TEMPLATE (
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//Inputs
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.mmu_en (ecfg_rx_mmu_enable),
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.ecfg_wait (erx_cfg_wait),
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)
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*/
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defparam erx_arbiter.ID = ID;
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erx_arbiter erx_arbiter (.timeout (1'b0),//TODO
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/*AUTOINST*/
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// Outputs
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.rx_rd_wait (rx_rd_wait),
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.rx_wr_wait (rx_wr_wait),
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.edma_wait (edma_wait),
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.ecfg_wait (erx_cfg_wait), // Templated
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.rxrr_access (rxrr_access),
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.rxrr_packet (rxrr_packet[PW-1:0]),
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// Inputs
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.erx_rr_access (erx_rr_access),
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.erx_packet (erx_packet[PW-1:0]),
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.emmu_access (emmu_access),
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.emmu_packet (emmu_packet[PW-1:0]),
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.edma_access (edma_access),
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.edma_packet (edma_packet[PW-1:0]),
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.ecfg_access (ecfg_access),
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.ecfg_packet (ecfg_packet[PW-1:0]),
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.rxwr_wait (rxwr_wait),
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.rxrd_wait (rxrd_wait),
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.rxrr_wait (rxrr_wait));
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endmodule // erx_core
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// Local Variables:
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// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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