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c627827a6b
-Adding model (one source..) -generate for 104x32 for xilinx -making prog_full the default full indicator -bringing out almost_full for future use -fixing interface change in all modules
This folder contains basic Xilinx verilog primitives
All primitives should be written in "synthesizable" code that can be simulated in Verilator and which should work correctly when synthesized.