1
0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
oh/asiclib/hdl/asic_dffrqn.v
aolofsson 9e41b55f22 Adding default property to all cells
-Can be used to select between different cells (like sizes) that have the exact same logical function
2021-07-27 22:55:45 -04:00

22 lines
739 B
Verilog

//#############################################################################
//# Function: Positive edge-triggered static inverting D-type flop-flop with #
// async active low reset. #
//# Copyright: OH Project Authors. ALl rights Reserved. #
//# License: MIT (see LICENSE file in OH repository) #
//#############################################################################
module asic_dffrqn #(parameter PROP = "DEFAULT") (
input d,
input clk,
input nreset,
output reg qn
);
always @ (posedge clk or negedge nreset)
if(!nreset)
qn <= 1'b1;
else
qn <= ~d;
endmodule