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24 lines
440 B
Tcl
24 lines
440 B
Tcl
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#Design name ("system" recommended)
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set design system
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#Project directory ("." recommended)
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set projdir ./
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#Device name
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set partname "xc7z020clg400-1"
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#Paths to all IP blocks to use in Vivado "system.bd"
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set ip_repos [list "."]
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#All source files
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set hdl_files []
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#All constraints files
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set constraints_files [list \
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../../parallella/fpga/parallella_io.xdc \
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../../parallella/fpga/parallella_7020_io.xdc \
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./axi_spi_timing.xdc \
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]
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