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17 lines
769 B
Systemverilog
17 lines
769 B
Systemverilog
//64 bit registers, maps to addr[6:3]
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`ifndef GPIO_REGMAP_VH_
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`define GPIO_REGMAP_VH_
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`define GPIO_DIR 4'h0 // set direction of pin
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`define GPIO_IN 4'h1 // input data (read only)
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`define GPIO_OUT 4'h2 // output data (write only)
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`define GPIO_OUTCLR 4'h3 // alias, clears specific bits in GPIO_OUT
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`define GPIO_OUTSET 4'h4 // alias, sets specific bits in GPIO_OUT
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`define GPIO_OUTXOR 4'h5 // alias, toggles specific bits in GPIO_OUT
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`define GPIO_IMASK 4'h6 // interrupt mask
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`define GPIO_ITYPE 4'h7 // interrupt type (level/edge)
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`define GPIO_IPOL 4'h8 // interrupt polarity (falling/rising edge)
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`define GPIO_ILAT 4'h9 // latched interrupts (read only)
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`define GPIO_ILATCLR 4'hA // clear an interrupt
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`endif
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