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55 lines
1.2 KiB
Verilog
55 lines
1.2 KiB
Verilog
/*
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* ---- E4 PACKET FORMAT (104 bits) ----
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* [1] write bit
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* [2:1] datamode
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* [6:3] ctrlmode
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* [7] reserved
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* [39:8] f0 = dstaddr(lo)
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* [71:40] f1 = data (lo)
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* [103:72] f2 = srcaddr(lo) / data (hi)
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*
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*/
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module emesh2packet(/*AUTOARG*/
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// Outputs
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packet_out,
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// Inputs
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write_out, datamode_out, ctrlmode_out, dstaddr_out, data_out,
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srcaddr_out
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);
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parameter AW = 32;
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localparam PW = (2*AW+40);
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//Emesh signal bundle
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input write_out;
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input [1:0] datamode_out;
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input [4:0] ctrlmode_out;
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input [AW-1:0] dstaddr_out;
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input [AW-1:0] data_out;
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input [AW-1:0] srcaddr_out;
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//Output packet
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output [PW-1:0] packet_out;
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assign packet_out[0] = write_out;
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assign packet_out[2:1] = datamode_out[1:0];
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assign packet_out[7:3] = ctrlmode_out[4:0];
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generate
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if(AW==32 & PW==104)
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begin
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assign packet_out[39:8] = dstaddr_out[AW-1:0];
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assign packet_out[71:40] = data_out[AW-1:0];
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assign packet_out[103:72] = srcaddr_out[AW-1:0];
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end
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else
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begin
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initial
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$display ("Only AW=32 and PW=104 is supported");
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end
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endgenerate
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endmodule // emesh2packet
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