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63 lines
2.4 KiB
Markdown
63 lines
2.4 KiB
Markdown
OH!: Synthesis Flow
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=====================================
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This guide documents the OH! fron end synthesis flow that compiles Verilog HDL into a gate level netlist. The flow requires certain TCL and Shell variables to be setup, as defined [HERE](../README.md).
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The synthesis flow scripts call EDA specific scipts as needed.
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# SYNTHESIS FLOW
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| FILE | NOTES |
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|------------------------|---------------------------------------------|
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| 01_setup_tool.tcl | Setup synthesis tool |
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| 02_read_design.tcl | Read in design files |
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| 03_read_constraints.tcl| Read in design constaints |
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| 04_setup_corners.tcl | Setup up operating conditions |
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| 05_floorplan.tcl | Read floorplan information |
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| 06_check_design.tcl | Check design integrity |
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| 07_compile.tcl | Comile HDL to gates |
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| 08_dft.tcl | Insert test features (scan) |
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| 09_optimize.tcl | Seconday optimization step |
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| 10_write_netlist.tcl | Write out netlists and reports |
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## Example Setup File ("example.tcl")
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```tcl
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set OH_VENDOR "synopsys"
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set OH_TOOl "dc"
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set OH_DESIGN "ecore"
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set OH_LIBS "svtlib"
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set OH_MACROS "sram64x1024"
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set OH_FILES "../../../hdl/$OH_DESIGN.v \
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-y $env(OH_HOME)/emesh/hdl \
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-y $env(OH_HOME)/common/hdl \
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-y $env(EPIPHANY_HOME)/chip/hdl \
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-y $env(EPIPHANY_HOME)/ecore/hdl \
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-y $env(EPIPHANY_HOME)/emesh/hdl \
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-y $env(EPIPHANY_HOME)/edma/hdl \
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-y $env(EPIPHANY_HOME)/compute/hdl \
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-y $env(EPIPHANY_HOME)/memory/hdl \
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-y $env(EPIPHANY_HOME)/fpumm/hdl \
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+incdir+$env(EPIPHANY_HOME)/emesh/hdl \
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+incdir+$env(EPIPHANY_HOME)/ecore/hdl \
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+incdir+$env(EPIPHANY_HOME)/edma/hdl"
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set OH_CONSTRAINTS "${OH_DESIGN}.sdc"
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set OH_FLOORPLAN "${OH_DESIGN}_floorplan.tcl"
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```
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## Usage
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```
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>> cd
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>> dc_shell -topographical_mode
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dc_shell> source $env(OH_HOME)/chip/synthesis/example.tcl
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```
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