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93 lines
3.0 KiB
Verilog
93 lines
3.0 KiB
Verilog
module MMCME2_ADV # (
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parameter BANDWIDTH = "OPTIMIZED",
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parameter real CLKFBOUT_MULT_F = 5.000,
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parameter real CLKFBOUT_PHASE = 0.000,
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parameter CLKFBOUT_USE_FINE_PS = "FALSE",
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parameter real CLKIN1_PERIOD = 0.000,
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parameter real CLKIN2_PERIOD = 0.000,
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parameter real CLKOUT0_DIVIDE_F = 1.000,
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parameter real CLKOUT0_DUTY_CYCLE = 0.500,
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parameter real CLKOUT0_PHASE = 0.000,
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parameter CLKOUT0_USE_FINE_PS = "FALSE",
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parameter integer CLKOUT1_DIVIDE = 1,
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parameter real CLKOUT1_DUTY_CYCLE = 0.500,
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parameter real CLKOUT1_PHASE = 0.000,
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parameter CLKOUT1_USE_FINE_PS = "FALSE",
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parameter integer CLKOUT2_DIVIDE = 1,
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parameter real CLKOUT2_DUTY_CYCLE = 0.500,
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parameter real CLKOUT2_PHASE = 0.000,
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parameter CLKOUT2_USE_FINE_PS = "FALSE",
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parameter integer CLKOUT3_DIVIDE = 1,
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parameter real CLKOUT3_DUTY_CYCLE = 0.500,
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parameter real CLKOUT3_PHASE = 0.000,
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parameter CLKOUT3_USE_FINE_PS = "FALSE",
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parameter CLKOUT4_CASCADE = "FALSE",
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parameter integer CLKOUT4_DIVIDE = 1,
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parameter real CLKOUT4_DUTY_CYCLE = 0.500,
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parameter real CLKOUT4_PHASE = 0.000,
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parameter CLKOUT4_USE_FINE_PS = "FALSE",
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parameter integer CLKOUT5_DIVIDE = 1,
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parameter real CLKOUT5_DUTY_CYCLE = 0.500,
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parameter real CLKOUT5_PHASE = 0.000,
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parameter CLKOUT5_USE_FINE_PS = "FALSE",
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parameter integer CLKOUT6_DIVIDE = 1,
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parameter real CLKOUT6_DUTY_CYCLE = 0.500,
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parameter real CLKOUT6_PHASE = 0.000,
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parameter CLKOUT6_USE_FINE_PS = "FALSE",
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parameter COMPENSATION = "ZHOLD",
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parameter integer DIVCLK_DIVIDE = 1,
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parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
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parameter [0:0] IS_PSEN_INVERTED = 1'b0,
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parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0,
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parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
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parameter [0:0] IS_RST_INVERTED = 1'b0,
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parameter real REF_JITTER1 = 0.010,
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parameter real REF_JITTER2 = 0.010,
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parameter SS_EN = "FALSE",
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parameter SS_MODE = "CENTER_HIGH",
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parameter integer SS_MOD_PERIOD = 10000,
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parameter STARTUP_WAIT = "FALSE"
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)(
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output CLKFBOUT, //feedback clock to connect to CLKFBIN
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output CLKFBOUTB, //inverted feedback clock output
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output CLKFBSTOPPED, //indicates that FB clock as stoppped
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output CLKINSTOPPED, //indicates that input clock has stopped
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output CLKOUT0, //clock output
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output CLKOUT0B, //inverted clock output
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output CLKOUT1,
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output CLKOUT1B,
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output CLKOUT2,
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output CLKOUT2B,
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output CLKOUT3,
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output CLKOUT3B,
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output CLKOUT4,
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output CLKOUT5,
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output CLKOUT6,
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output [15:0] DO,
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output DRDY,
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output LOCKED,
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output PSDONE, //phase shift done
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input CLKFBIN,
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input CLKIN1,
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input CLKIN2,
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input CLKINSEL,
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input [6:0] DADDR,
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input DCLK,
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input DEN,
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input [15:0] DI,
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input DWE,
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input PSCLK, //phase shift clock
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input PSEN, //phase shift enable
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input PSINCDEC, //phase shift decrement/increment
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input PWRDWN, //global power down pin
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input RST //async global reset
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);
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//No mult function, but insert divider
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endmodule // MMCME2_ADV
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