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128 lines
3.4 KiB
Verilog
128 lines
3.4 KiB
Verilog
//`timescale 1 ns / 100 ps
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module dv_ecfg();
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//Stimulus to drive
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reg clk;
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reg reset;
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reg mi_access;
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reg [19:0] mi_addr;
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reg [31:0] mi_data_in;
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reg mi_write;
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reg [1:0] test_state;
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//Reset
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initial
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begin
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$display($time, " << Starting the Simulation >>");
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#0
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clk = 1'b0; // at time 0
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reset = 1'b1; // reset is active
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mi_write = 1'b0;
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mi_access = 1'b0;
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mi_addr[19:0] = 20'hf0340;
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mi_data_in[31:0] = 32'h0;
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test_state[1:0] = 2'b00;
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#100
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reset = 1'b0; // at time 100 release reset
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#100
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mi_write = 1'b1;
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mi_access = 1'b1;
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#10000
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$finish;
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end
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//Clock
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always
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#10 clk = ~clk;
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//Pattern generator
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always @ (posedge clk)
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if(mi_access)
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case(test_state[1:0])
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2'b00:
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if(~done)
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begin
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mi_addr[19:0] <= mi_addr[19:0]+20'h4;
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mi_data_in[5:0] <= mi_data_in[5:0]+1'b1;
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end
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else
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begin
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test_state <= 2'b01;
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mi_addr[19:0] <= 20'hf0340;
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mi_write <= 1'b0;
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end
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2'b01:
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if(~done)
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begin
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mi_addr[19:0] <= mi_addr[19:0]+20'h4;
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mi_data_in[5:0] <= 32'hffffffff;
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end
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else
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test_state <= 2'b01;
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endcase// case (test_state[1:0])
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wire done = (mi_addr[19:0]==20'hf0360);
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [3:0] ecfg_cclk_div; // From ecfg of ecfg.v
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wire ecfg_cclk_en; // From ecfg of ecfg.v
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wire [3:0] ecfg_cclk_pllcfg; // From ecfg of ecfg.v
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wire [11:0] ecfg_coreid; // From ecfg of ecfg.v
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wire [11:0] ecfg_dataout; // From ecfg of ecfg.v
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wire ecfg_rx_enable; // From ecfg of ecfg.v
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wire ecfg_rx_gpio_mode; // From ecfg of ecfg.v
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wire ecfg_rx_loopback_mode; // From ecfg of ecfg.v
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wire ecfg_rx_mmu_mode; // From ecfg of ecfg.v
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wire ecfg_sw_reset; // From ecfg of ecfg.v
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wire [3:0] ecfg_tx_clkdiv; // From ecfg of ecfg.v
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wire [3:0] ecfg_tx_ctrl_mode; // From ecfg of ecfg.v
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wire ecfg_tx_enable; // From ecfg of ecfg.v
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wire ecfg_tx_gpio_mode; // From ecfg of ecfg.v
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wire ecfg_tx_mmu_mode; // From ecfg of ecfg.v
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wire [31:0] mi_data_out; // From ecfg of ecfg.v
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// End of automatics
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//DUT
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ecfg ecfg(.param_coreid (12'h808),
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/*AUTOINST*/
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// Outputs
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.mi_data_out (mi_data_out[31:0]),
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.ecfg_sw_reset (ecfg_sw_reset),
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.ecfg_tx_enable (ecfg_tx_enable),
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.ecfg_tx_mmu_mode (ecfg_tx_mmu_mode),
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.ecfg_tx_gpio_mode (ecfg_tx_gpio_mode),
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.ecfg_tx_ctrl_mode (ecfg_tx_ctrl_mode[3:0]),
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.ecfg_tx_clkdiv (ecfg_tx_clkdiv[3:0]),
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.ecfg_rx_enable (ecfg_rx_enable),
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.ecfg_rx_mmu_mode (ecfg_rx_mmu_mode),
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.ecfg_rx_gpio_mode (ecfg_rx_gpio_mode),
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.ecfg_rx_loopback_mode (ecfg_rx_loopback_mode),
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.ecfg_cclk_en (ecfg_cclk_en),
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.ecfg_cclk_div (ecfg_cclk_div[3:0]),
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.ecfg_cclk_pllcfg (ecfg_cclk_pllcfg[3:0]),
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.ecfg_coreid (ecfg_coreid[11:0]),
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.ecfg_dataout (ecfg_dataout[11:0]),
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// Inputs
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.clk (clk),
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.reset (reset),
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.mi_access (mi_access),
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.mi_write (mi_write),
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.mi_addr (mi_addr[19:0]),
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.mi_data_in (mi_data_in[31:0]));
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//Waveform dump
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initial
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begin
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$dumpfile("test.vcd");
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$dumpvars(0, dv_ecfg);
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end
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endmodule // dv_ecfg
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../memory/hdl ")
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// End:
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