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132 lines
4.2 KiB
Verilog
132 lines
4.2 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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module esaxi_cfg (/*AUTOARG*/
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// Outputs
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s_axi_arready, s_axi_awready, s_axi_bresp, s_axi_bvalid,
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s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_wready, mi_clk,
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mi_en, mi_we, mi_addr, mi_din,
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// Inputs
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s_axi_aclk, s_axi_aresetn, s_axi_araddr, s_axi_arprot,
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s_axi_arvalid, s_axi_awaddr, s_axi_awprot, s_axi_awvalid,
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s_axi_bready, s_axi_rready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
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mi_rd_data
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);
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parameter RFAW = 13;
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/*****************************/
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/*AXI 32 bit lite interface */
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/*****************************/
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input s_axi_aclk;
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input s_axi_aresetn;
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//read address channel
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input [15:0] s_axi_araddr;
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input [2:0] s_axi_arprot;
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output s_axi_arready;
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input s_axi_arvalid;
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//write address channel
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input [15:0] s_axi_awaddr;
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input [2:0] s_axi_awprot;
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output s_axi_awready;
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input s_axi_awvalid;
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//buffered read response channel
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input s_axi_bready;
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output [1:0] s_axi_bresp;
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output s_axi_bvalid;
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//read channel
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output [31:0] s_axi_rdata;
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input s_axi_rready;
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output [1:0] s_axi_rresp;
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output s_axi_rvalid;
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//write channel
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input [31:0] s_axi_wdata;
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output s_axi_wready;
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input [3:0] s_axi_wstrb;
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input s_axi_wvalid;
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/*****************************/
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/*Simple memory interface */
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/*****************************/
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output mi_clk;
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output mi_en;
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output [3:0] mi_we;
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output [15:0] mi_addr;
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output [31:0] mi_din;
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input [31:0] mi_rd_data;
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`ifdef TARGET_XILINX
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/*axi_bram_ctrl_16b AUTO_TEMPLATE (
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//Outputs
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.bram_rst_a (),
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.bram_clk_a (mi_clk),
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.bram_en_a (mi_en),
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.bram_we_a (mi_we[3:0]),
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.bram_addr_a (mi_addr[15:0]),
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.bram_wrdata_a (mi_din[31:0]),
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.bram_rddata_a (mi_rd_data[31:0]),
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);
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*/
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axi_bram_ctrl_16b axi_bram_ctrl_16b(/*AUTOINST*/
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// Outputs
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.s_axi_awready (s_axi_awready),
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.s_axi_wready (s_axi_wready),
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.s_axi_bresp (s_axi_bresp[1:0]),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_arready (s_axi_arready),
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.s_axi_rdata (s_axi_rdata[31:0]),
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.s_axi_rresp (s_axi_rresp[1:0]),
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.s_axi_rvalid (s_axi_rvalid),
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.bram_rst_a (), // Templated
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.bram_clk_a (mi_clk), // Templated
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.bram_en_a (mi_en), // Templated
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.bram_we_a (mi_we[3:0]), // Templated
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.bram_addr_a (mi_addr[15:0]), // Templated
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.bram_wrdata_a (mi_din[31:0]), // Templated
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// Inputs
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_awaddr (s_axi_awaddr[15:0]),
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.s_axi_awprot (s_axi_awprot[2:0]),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_wdata (s_axi_wdata[31:0]),
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.s_axi_wstrb (s_axi_wstrb[3:0]),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_bready (s_axi_bready),
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.s_axi_araddr (s_axi_araddr[15:0]),
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.s_axi_arprot (s_axi_arprot[2:0]),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_rready (s_axi_rready),
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.bram_rddata_a (mi_rd_data[31:0])); // Templated
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`endif // `ifdef TARGET_XILINX
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endmodule // esaxi_cfg
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// Local Variables:
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// verilog-library-directories:("." "../../stubs/hdl")
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// End:
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