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oh/asiclib/hdl/asic_ao222.v
aolofsson 9e41b55f22 Adding default property to all cells
-Can be used to select between different cells (like sizes) that have the exact same logical function
2021-07-27 22:55:45 -04:00

20 lines
615 B
Verilog

//#############################################################################
//# Function: And-Or (ao222) Gate #
//# Copyright: OH Project Authors. ALl rights Reserved. #
//# License: MIT (see LICENSE file in OH repository) #
//#############################################################################
module asic_ao222 #(parameter PROP = "DEFAULT") (
input a0,
input a1,
input b0,
input b1,
input c0,
input c1,
output z
);
assign z = (a0 & a1) | (b0 & b1) | (c0 & c1);
endmodule