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9e41b55f22
-Can be used to select between different cells (like sizes) that have the exact same logical function
24 lines
783 B
Verilog
24 lines
783 B
Verilog
//#############################################################################
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//# Function: Positive edge-triggered static inverting D-type flop-flop with #
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// async active low set and scan input #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_sdffsqn #(parameter PROP = "DEFAULT") (
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input d,
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input si,
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input se,
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input clk,
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input nset,
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output reg qn
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);
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always @ (posedge clk or negedge nset)
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if(!nset)
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qn <= 1'b0;
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else
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qn <= se ? ~si : ~d;
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endmodule
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