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e123650d06
-This will cause a lot of nasty bugs, but it's the right thing to do to be more consistent with standard buses going forward. -Change is made from access/wait tp valid/ready
99 lines
2.9 KiB
Verilog
99 lines
2.9 KiB
Verilog
//WARNING: Pass through logic
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module emesh_if (/*AUTOARG*/
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// Outputs
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cmesh_ready_out, cmesh_access_out, cmesh_packet_out,
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rmesh_ready_out, rmesh_access_out, rmesh_packet_out,
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xmesh_ready_out, xmesh_access_out, xmesh_packet_out,
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emesh_ready_out, emesh_access_out, emesh_packet_out,
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// Inputs
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cmesh_access_in, cmesh_packet_in, cmesh_ready_in, rmesh_access_in,
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rmesh_packet_in, rmesh_ready_in, xmesh_access_in, xmesh_packet_in,
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xmesh_ready_in, emesh_access_in, emesh_packet_in, emesh_ready_in
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);
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parameter AW = 32;
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parameter PW = 2*AW+40;
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//##Cmesh##
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input cmesh_access_in;
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input [PW-1:0] cmesh_packet_in;
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output cmesh_ready_out;
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output cmesh_access_out;
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output [PW-1:0] cmesh_packet_out;
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input cmesh_ready_in;
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//##Rmesh##
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input rmesh_access_in;
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input [PW-1:0] rmesh_packet_in;
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output rmesh_ready_out;
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output rmesh_access_out;
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output [PW-1:0] rmesh_packet_out;
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input rmesh_ready_in;
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//##Xmesh##
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input xmesh_access_in;
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input [PW-1:0] xmesh_packet_in;
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output xmesh_ready_out;
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output xmesh_access_out;
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output [PW-1:0] xmesh_packet_out;
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input xmesh_ready_in;
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//##Emesh##
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input emesh_access_in;
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input [PW-1:0] emesh_packet_in;
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output emesh_ready_out;
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//core-->io
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output emesh_access_out;
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output [PW-1:0] emesh_packet_out;
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input emesh_ready_in;
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//#####################################################
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//# EMESH-->(RMESH/XMESH/CMESH)
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//#####################################################
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assign cmesh_access_out = emesh_access_in & emesh_packet_in[0];
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assign rmesh_access_out = emesh_access_in & ~emesh_packet_in[0];
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//Don't drive on xmesh for now
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assign xmesh_access_out = 1'b0;
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//Distribute emesh to xmesh,cmesh, rmesh
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assign cmesh_packet_out[PW-1:0] = emesh_packet_in[PW-1:0];
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assign rmesh_packet_out[PW-1:0] = emesh_packet_in[PW-1:0];
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assign xmesh_packet_out[PW-1:0] = emesh_packet_in[PW-1:0];
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assign emesh_ready_out = cmesh_ready_in &
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rmesh_ready_in &
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xmesh_ready_in;
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//#####################################################
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//# (RMESH/XMESH/CMESH)-->EMESH
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//#####################################################
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assign emesh_access_out = cmesh_access_in &
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rmesh_access_in &
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xmesh_access_in;
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//TODO: Make round robin?? (Fancify)
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assign emesh_packet_out[PW-1:0] = cmesh_access_in ? cmesh_packet_in[PW-1:0] :
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rmesh_access_in ? rmesh_packet_in[PW-1:0] :
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xmesh_packet_in[PW-1:0];
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assign cmesh_ready_out = ~(cmesh_access_in & ~emesh_ready_in);
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assign rmesh_ready_out = ~(rmesh_access_in &
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(~emesh_ready_in | ~cmesh_ready_in));
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assign xmesh_ready_out = ~(xmesh_access_in &
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(~emesh_ready_in | ~cmesh_access_in | ~rmesh_access_in));
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endmodule // emesh_if
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