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oh/memory/hdl
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Andreas Olofsson 65708a2be9 Added wait generator for fifo (experimental) 
- found it very difficult to get to some of the hard to reach scenarios
- the wait circuit helps generate fifo full
- off by default!
2015-11-24 01:05:04 -05:00
..
fifo_async_emesh.v
Moving to MIT license
2015-11-06 11:25:05 -05:00
fifo_async.v
Added wait generator for fifo (experimental)
2015-11-24 01:05:04 -05:00
fifo_cdc.v
Added wait generator for fifo (experimental)
2015-11-24 01:05:04 -05:00
fifo_empty_block.v
Moving to MIT license
2015-11-06 11:25:05 -05:00
fifo_full_block.v
Moving to MIT license
2015-11-06 11:25:05 -05:00
fifo_sync.v
Cleaning up fifo interface
2015-11-09 13:20:46 -05:00
memory_dp.v
Moving to MIT license
2015-11-06 11:25:05 -05:00
memory_sp.v
Moving to MIT license
2015-11-06 11:25:05 -05:00