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114 lines
2.8 KiB
Verilog
114 lines
2.8 KiB
Verilog
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/*
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Emesh interface wrapper for asynchronous fifo
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*/
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module fifo_async_emesh (/*AUTOARG*/
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// Outputs
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emesh_access_out, emesh_write_out, emesh_datamode_out,
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emesh_ctrlmode_out, emesh_dstaddr_out, emesh_data_out,
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emesh_srcaddr_out, fifo_full, fifo_progfull,
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// Inputs
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rd_clk, wr_clk, reset, emesh_access_in, emesh_write_in,
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emesh_datamode_in, emesh_ctrlmode_in, emesh_dstaddr_in,
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emesh_data_in, emesh_srcaddr_in, fifo_read
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);
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//Clocks
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input rd_clk;
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input wr_clk;
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input reset;
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//input-data
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input emesh_access_in;
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input emesh_write_in;
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input [1:0] emesh_datamode_in;
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input [3:0] emesh_ctrlmode_in;
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input [31:0] emesh_dstaddr_in;
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input [31:0] emesh_data_in;
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input [31:0] emesh_srcaddr_in;
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//output-data
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output emesh_access_out;
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output emesh_write_out;
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output [1:0] emesh_datamode_out;
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output [3:0] emesh_ctrlmode_out;
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output [31:0] emesh_dstaddr_out;
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output [31:0] emesh_data_out;
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output [31:0] emesh_srcaddr_out;
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//FIFO controls
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input fifo_read;
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output fifo_full;
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output fifo_progfull;
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//wires
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wire [103:0] fifo_din;
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wire [103:0] fifo_dout;
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wire fifo_empty;
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//Inputs to FIFO
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assign fifo_din[103:0]={emesh_srcaddr_in[31:0],
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emesh_data_in[31:0],
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emesh_dstaddr_in[31:0],
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emesh_ctrlmode_in[3:0],
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emesh_datamode_in[1:0],
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emesh_write_in,
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1'b0
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};
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//Outputs
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assign emesh_access_out = ~fifo_empty;
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assign emesh_write_out = fifo_dout[1];
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assign emesh_datamode_out[1:0] = fifo_dout[3:2];
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assign emesh_ctrlmode_out[3:0] = fifo_dout[7:4];
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assign emesh_dstaddr_out[31:0] = fifo_dout[39:8];
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assign emesh_data_out[31:0] = fifo_dout[71:40];
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assign emesh_srcaddr_out[31:0] = fifo_dout[103:72];
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`ifdef TARGET_XILINX
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fifo_async_104x32 fifo_async_104x32 (.dout (fifo_dout[103:0]),
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.full (fifo_full),
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.empty (fifo_empty),
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.prog_full (fifo_progfull),
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//inputs
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.rst (reset),
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.wr_clk (wr_clk),
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.rd_clk (rd_clk),
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.din (fifo_din[103:0]),
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.wr_en (emesh_access_in),
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.rd_en (fifo_read)
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);
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`elsif TARGET_CLEAN
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wire tmp_progfull;
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assign fifo_progfull = tmp_progfull | fifo_full;//HACK, need to fix this
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fifo_async #(.DW(104), .AW(5)) fifo_async (
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.rd_data (fifo_dout[103:0]),
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.wr_fifo_progfull (tmp_progfull),
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.wr_fifo_full (fifo_full),
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.rd_fifo_empty (fifo_empty),
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//inputs
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.reset (reset),
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.wr_clk (wr_clk),
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.rd_clk (rd_clk),
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.wr_data (fifo_din[103:0]),
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.wr_write (emesh_access_in),
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.rd_read (fifo_read)
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);
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`elsif TARGET_ALTERA
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//SOMETHING
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`endif
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endmodule // fifo_sync
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// Local Variables:
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// verilog-library-directories:("." "../../stubs/hdl")
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// End:
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