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oh/common/dv/cfg_random.v
Andreas Olofsson bb4a602f7f New "dut files"
- new clocks (clk1 and 2)
- simpler names
- fifo dut
2016-02-24 14:19:57 -05:00

3 lines
50 B
Verilog

`define CFG_RANDOM 1
`define CFG_TARGET "GENERIC"