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63bf5d25a4
- Because this is the right thing to do for chips - Not going to tell you why...
48 lines
1.2 KiB
Verilog
48 lines
1.2 KiB
Verilog
module edma (/*AUTOARG*/
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// Outputs
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mi_dout, edma_access, edma_packet,
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// Inputs
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nreset, clk, mi_en, mi_we, mi_addr, mi_din, edma_wait
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);
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/******************************/
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/*Compile Time Parameters */
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/******************************/
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parameter RFAW = 6;
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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/******************************/
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/*HARDWARE RESET (EXTERNAL) */
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/******************************/
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input nreset; //async reset
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input clk;
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/*****************************/
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/*REGISTER INTERFACE */
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/*****************************/
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input mi_en;
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input mi_we;
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input [RFAW+1:0] mi_addr;
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input [63:0] mi_din;
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output [31:0] mi_dout;
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/*****************************/
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/*DMA TRANSACTION */
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/*****************************/
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output edma_access;
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output [PW-1:0] edma_packet;
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input edma_wait;
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//Tieoffs for now
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assign edma_access = 'b0;
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assign edma_packet = 'd0;
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assign mi_dout = 'd0;
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endmodule // edma
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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