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ce7c89ce1e
- Should only pass back read response EGROUP_RR - Otherwise there would be a match on writing to MAILBOX
121 lines
3.1 KiB
Verilog
121 lines
3.1 KiB
Verilog
`include "elink_regmap.v"
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module erx_arbiter (/*AUTOARG*/
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// Outputs
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rx_rd_wait, rx_wr_wait, edma_wait, ecfg_wait, rxwr_access,
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rxwr_packet, rxrd_access, rxrd_packet, rxrr_access, rxrr_packet,
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// Inputs
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erx_access, erx_packet, edma_access, edma_packet, ecfg_access,
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ecfg_packet, rxwr_wait, rxrd_wait, rxrr_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter ID = 12'h800; //link id
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parameter RFAW = 6;
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//Incoming packet (writes)
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input erx_access; //from MMU
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input [PW-1:0] erx_packet;
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output rx_rd_wait; //for IO
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output rx_wr_wait; //for IO
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//From DMA
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input edma_access;
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input [PW-1:0] edma_packet;
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output edma_wait;
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//From ETX
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input ecfg_access;
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input [PW-1:0] ecfg_packet;
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output ecfg_wait;
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//To Master Write FIFO
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output rxwr_access;
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output [PW-1:0] rxwr_packet;
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input rxwr_wait;
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//To Master Read FIFO
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output rxrd_access;
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output [PW-1:0] rxrd_packet;
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input rxrd_wait;
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//To Slave Read Response FIFO
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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input rxrr_wait;
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//####################################
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//Splicing pakets
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//####################################
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wire erx_write;
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wire [AW-1:0] erx_dstaddr;
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wire erx_read;
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packet2emesh #(.AW(AW))
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p2e (// Outputs
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.write_in (erx_write),
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.datamode_in (),
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.ctrlmode_in (),
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.data_in (),
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.dstaddr_in (erx_dstaddr[AW-1:0]),
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.srcaddr_in (),
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// Inputs
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.packet_in (erx_packet[PW-1:0]));
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//#######################################################
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//Read response path (from IO or elink register readback)
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//#######################################################
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assign rxrr_access = ecfg_access |
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(erx_access &
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(erx_dstaddr[31:20]==ID) &
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(erx_dstaddr[19:16]==`EGROUP_RR));
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assign rxrr_packet[PW-1:0] = ecfg_access ? ecfg_packet[PW-1:0] :
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erx_packet[PW-1:0];
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//####################################
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//Write Path (from IO through MMU)
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//####################################
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assign rxwr_access = erx_access &
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erx_write &
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~(erx_dstaddr[31:20]==ID);
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assign rxwr_packet[PW-1:0] = erx_packet[PW-1:0];
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//########################################
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//Read Request Path (from IO through MMU)
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//########################################
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assign erx_read = erx_access & ~erx_write;
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assign rxrd_access = erx_read | edma_access;
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assign rxrd_packet[PW-1:0] = erx_read ? erx_packet[PW-1:0] :
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edma_packet[PW-1:0];
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//####################################
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//Wait Signals
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//####################################
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assign ecfg_wait = rxrr_wait;
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assign edma_wait = rxrd_wait | erx_read;
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assign rx_rd_wait = rxrd_wait;
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assign rx_wr_wait = ecfg_access |
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rxwr_wait |
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rxrr_wait;
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endmodule // erx_arbiter
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl" "../../emesh/hdl")
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// End:
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