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e8bbc6a675
- Very thin file with simulation control specific to simulators - A similar file needed for Verilator - The idea is that the testbench can be instantiated in an FPGA/Verilator
STDLIB
- STDLIB is a library of low level vectoried building blocks for control and datapath logic.
- Where appropriate, parameters are included to enable soft and hard-coded implementation.
- Some library cells call on others cells within the library