FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-02-07 06:44:09 +08:00
Code Issues Projects Releases Wiki Activity
oh/stdlib/testbench
History
aolofsson e8bbc6a675 Adding Top level simulation file for icarus 
- Very thin file with simulation control specific to simulators
- A similar file needed for Verilator
- The idea is that the testbench can be instantiated in an FPGA/Verilator
2022-06-27 00:26:09 -04:00
..
tests
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
cfg_random.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
dut_clockdiv.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
dut_debouncer.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
dut_fifo_generic.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
dut_gray.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
dut_template.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
dv_driver.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
dv_random.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
dv_stimulus.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
dv_top.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
firmware_example.hex
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
libs.cmd
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
oh_simchecker.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
oh_simctrl.v
Removing dut feedback loop from simulation control
2022-06-27 00:22:02 -04:00
oh.gtkw
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
README.md
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
run.sh
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
sim.v
Adding Top level simulation file for icarus
2022-06-27 00:26:09 -04:00
stimulus.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
tb_dut.v
Adding stub file for tb_dut wrapper
2022-06-24 22:17:21 -04:00
tb_oh_pulse.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
tb_oh_random.v
Changing testbench hiearchy
2022-06-27 00:24:07 -04:00
tb_oh_stimulus.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
test.mem
Changing name dv to testbench
2022-06-22 11:12:51 -04:00
testbench.v
Changing testbench to be a stub
2022-06-27 00:23:48 -04:00
timescale.v
Changing name dv to testbench
2022-06-22 11:12:51 -04:00

README.md

What defines are used

iverilog -g2005 -DTARGET_SIM=1 $cfg $core.v $DV -f $LIBS -o $core.bin

How to compile all duts?

The script "build_all.sh" builds all dut files in this directory with random

./build_all.sh