mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
20 lines
288 B
Verilog
20 lines
288 B
Verilog
module oh_parity (/*AUTOARG*/
|
|
// Outputs
|
|
out,
|
|
// Inputs
|
|
in
|
|
);
|
|
|
|
parameter DW = 64; // width of converter
|
|
|
|
input [DW-1:0] in; // data input
|
|
output out; // calculated parity bit
|
|
|
|
assign parity = ^data[DW-1:0];
|
|
|
|
endmodule // oh_parity
|
|
|
|
|
|
|
|
|