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781121fc61
-setting DMA access to zero for now -taking away wait for elink2 (messes up the access pattern) -fixing typo in register mape ERX
50 lines
1.8 KiB
Verilog
50 lines
1.8 KiB
Verilog
//MEMORY MAP
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//[31:20] = LINKID
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//[19:16] = GROUP SELECT
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//[15] = MMU SELECT (for RX/TX)
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//[14:11] = USED BY MMU ONLY
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//[10:8] = register group
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//[7:2] = REGISTER ADDRESS (0..63)
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//[1:0] = IGNORED (no byte access)
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//Link register groups addr[19:16]
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`define EGROUP_MMR 4'hF //reserved for registers
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`define EGROUP_MMU 4'hE // RX & TX MMU
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//ETX-REGS
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`define E_RESET 6'd0 //F0200-reset
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`define E_CLK 6'd1 //F0204-clock configuration
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`define E_CHIPID 6'd2 //F0208-Epiphany chip id for colid/rowid pins
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`define E_VERSION 6'd3 //F020C-version #
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`define ETX_CFG 6'd4 //F0210-config
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`define ETX_STATUS 6'd5 //F0214-tx status
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`define ETX_GPIO 6'd6 //F0218-direct data for tx pins
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//ERX-REGS
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`define ERX_CFG 6'd0 //F0300-config
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`define ERX_STATUS 6'd1 //F0304-status register
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`define ERX_GPIO 6'd2 //F0308-sampled data
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`define ERX_RR 6'd3 //F030C-read response address
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`define ERX_OFFSET 6'd4 //F0310-memory base for remap
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`define E_MAILBOXLO 6'd5 //F0314-reserved-->move?
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`define E_MAILBOXHI 6'd6 //F0318-reserved
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//DMA (same numbering as in Epiphany, limit to 4 channels)
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`define DMACFG 5'd0 //F0500/F0520
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`define DMACOUNT 5'd1 //F0504/F0524
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`define DMASTRIDE 5'd2 //F0508/F0528
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`define DMASRCADDR 5'd3 //F050C/F052c
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`define DMADSTADDR 5'd4 //F0510/F0530
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`define DMAAUTO0 5'd5 //F0514/F0534
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`define DMAAUTO1 5'd6 //F0518/F0538
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`define DMASTATUS 5'd7 //F051C/F053c
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//DMA descriptors (limited to 4 channels)
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`define DMADESCR0 5'd0 //F0580/F05A0
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`define DMADESCR1 5'd1 //F0584/F05A4
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`define DMADESCR2 5'd2 //F0588/F05A8
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`define DMADESCR3 5'd3 //F058c/F05Ac
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`define DMADESCR4 5'd4 //F0590/F05B0
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`define DMADESCR5 5'd5 //F0594/F05B4
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