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49 lines
2.1 KiB
Markdown
49 lines
2.1 KiB
Markdown
=======
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# OH! : Open Hardware for FPGA and ASIC designers
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## CONTENT
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| Module | Status | Description |
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|----------------------------|---------|------------------------------------------|
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| [accelerator](accelerator) | FPGA | Accelerator tutorial |
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| [chip](chip) | SILICON | Chip design reference flow |
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| [common](common) | SILICON*| Library of generally useful components |
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| [emesh](emesh) | SILICON | Emesh interface utility circuits |
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| [elink](elink) | SILICON | Point to point LVDS link |
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| [emailbox](emailbox) | FPGA | Mailbox with interrupt output |
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| [emmu](emmu) | FPGA | Memory transaction translation unit |
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| [irqc](irqc) | SILICON | Epiphany nested interrupt controller |
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| [xilibs](xilibs) | FPGA | Simulation modules for Xilinx primitives |
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**NOTES:**
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* "SILICON": Silicon validated
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* "FPGA": FPGA validated
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* "SIM": Simulation only
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* Common folder includes modules with mixed status. Some are silicon validated, others have only been simulated.
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## LICENSE
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The OH! repository source code is licensed under the MIT license unless otherwise specified. See [LICENSE](LICENSE) for MIT copyright terms. Design specific licenses can be found in the folder root (eg: aes/LICENSE)
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## CONTRIBUTING
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Instructions for contributing can be found [HERE](CONTRIBUTING.md).
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## RECOMMEND TOOLS
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* [Verilator Simulator](http://www.veripool.org/wiki/verilator)
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* [Emacs Verilog Mode](http://www.veripool.org/wiki/verilog-mode)
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* [Icarus Simulator](http://iverilog.icarus.com)
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* [GTKWave](http://gtkwave.sourceforge.net)
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* [Verilog-Perl](http://www.veripool.org/wiki/verilog-perl)
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## RECOMMENDED READING
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* [Glossary](chip/docs/glossary.md)
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* [Chip constants](chip/docs/constants.md)
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* [Verilog Reference](verilog/verilog_reference.md)
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----
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[picture-license](https://commons.wikimedia.org/wiki/File:Lego_Color_Bricks.jpg)
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