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41 lines
1.3 KiB
Verilog
41 lines
1.3 KiB
Verilog
//#############################################################################
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//# Function: Carry Save Adder (3:2) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_csa32
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#(parameter N = 1, // vector width
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parameter SYN = "TRUE", // synthesizable (or not)
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parameter TYPE = "DEFAULT" // scell type/size
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)
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( input [N-1:0] in0, // input
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input [N-1:0] in1, // input
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input [N-1:0] in2, // input
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output [N-1:0] s, // sum
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output [N-1:0] c // carry
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);
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generate
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if(SYN == "TRUE") begin
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assign s[N-1:0] = in0[N-1:0] ^ in1[N-1:0] ^ in2[N-1:0];
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assign c[N-1:0] = (in0[N-1:0] & in1[N-1:0]) |
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(in1[N-1:0] & in2[N-1:0]) |
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(in2[N-1:0] & in0[N-1:0] );
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end
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else begin
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genvar i;
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for (i=0;i<N;i=i+1) begin
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asic_csa32 #(.TYPE(TYPE))
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asic_csa32 (.s(s[i]),
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.c(c[i]),
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.in2(in2[i]),
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.in1(in1[i]),
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.in0(in0[i]));
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end
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end
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endgenerate
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endmodule
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