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78 lines
2.0 KiB
Verilog
78 lines
2.0 KiB
Verilog
//#############################################################################
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//# Function: Carry Save Adder (4:2) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_csa42
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#(parameter N = 1, // number of sync stages
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parameter SYN = "TRUE", // synthesizable (or not)
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parameter TYPE = "DEFAULT" // scell type/size
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)
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( input [N-1:0] in0, // input
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input [N-1:0] in1, // input
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input [N-1:0] in2, // input
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input [N-1:0] in3, // input
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input cin, // intra stage carry in
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output cout, // intra stage carry out (2x sum)
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output [N-1:0] s, // sum
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output [N-1:0] c // carry (=2x sum)
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);
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generate
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if(SYN == "TRUE") begin
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wire [N-1:0] sum_int;
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wire [N:0] carry_int;
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//Edges
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assign carry_int[0] = cin;
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assign cout = carry_int[N];
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//Full Adders
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oh_csa32 #(.N(N))
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fa0 (//inputs
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.in0(in0[N-1:0]),
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.in1(in1[N-1:0]),
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.in2(in2[N-1:0]),
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//outputs
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.c(carry_int[N:1]),
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.s(sum_int[N-1:0]));
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oh_csa32 #(.N(N))
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fa1 (//inputs
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.in0(in3[N-1:0]),
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.in1(sum_int[N-1:0]),
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.in2(carry_int[N-1:0]),
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//outputs
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.c(c[N-1:0]),
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.s(s[N-1:0]));
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end
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else begin
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wire [N-1:0] carry_out;
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wire [N-1:0] carry_in;
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assign carry_in[N-1:0] = {carry_out[N-1:1],cin};
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for (i=1;i<N;i=i+1) begin
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asic_csa42 #(.TYPE(TYPE))
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asic_csa42(// Outputs
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.cout (carry_out[i]),
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.s (s[i]),
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.c (c[i]),
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// Inputs
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.in0 (in0[i]),
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.in1 (in1[i]),
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.in2 (in2[i]),
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.in3 (in3[i]),
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.cin ({carry_in[i]}));
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end
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assign cout = carry[N-1];
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end
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endgenerate
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endmodule // oh_csa42
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