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50 lines
1.6 KiB
Verilog
50 lines
1.6 KiB
Verilog
//#############################################################################
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//# Function: Binary multiplier #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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defparam oh_mult.N = 16;
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module oh_mult
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#(parameter N = 32, // block width
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parameter SYN = "TRUE", // synthesizable
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parameter TYPE = "DEFAULT" // implementation type
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)
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(
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//Inputs
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input [N-1:0] a, // a input (multiplier)
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input [N-1:0] b, // b input (multiplicand)
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input asigned, // a operand is signed
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input bsigned, // b oeprand is signed
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//Outputs
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output [2*N-1:0] product, // a*b final product
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output [2*N-1:0] sum, // a*b partial sum
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output [2*N-1:0] carry // a*b partial carry
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);
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generate
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if(SYN=="TRUE") begin
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wire a_sext = asigned & a[N-1];
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wire b_sext = bsigned & b[N-1];
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assign product[2*N-1:0] = $signed({a_sext,a[N-1:0]}) *
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$signed({b_sext,b[N-1:0]});
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end
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else begin
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asic_mult #(.TYPE(TYPE),
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.N(N))
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asic_mult (// Outputs
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.product (product[2*N-1:0]),
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.sum (sum[2*N-1:0]),
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.carry (carry[2*N-1:0]),
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// Inputs
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.a (a[N-1:0]),
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.b (b[N-1:0]),
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.asigned (asigned),
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.bsigned (bsigned));
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end
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endgenerate
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endmodule
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