Andreas Olofsson eb3051ea93 Cleaning up logic to fit new access/packet interface ...

(pre-debug)

2015-05-09 08:56:51 -04:00

..

axi_elink.v

Adding elink with axi interfaces

2015-05-09 08:52:55 -04:00

ecfg_clocks.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

ecfg_if.v

Adding emesh as basic building block

2015-05-05 21:38:41 -04:00

eclocks.v

Fixing instances errors from fpga synthesis

2015-05-08 20:55:31 -04:00

elink_constants.v

Using fifo_cdc instead of fifo_async

2015-05-07 23:45:36 -04:00

elink_example.v

Fixing instances errors from fpga synthesis

2015-05-08 20:55:31 -04:00

elink_regmap.v

MILESTONE: register read/write working!

2015-05-04 10:49:17 -04:00

elink.v

Using fifo_cdc instead of fifo_async

2015-05-07 23:45:36 -04:00

emaxi.v

Cleaning up logic to fit new access/packet interface

2015-05-09 08:56:51 -04:00

ereset.v

Cleanup

2015-05-01 17:31:45 -04:00

erx_cfg.v

Renaming for my sanity (etx/erx split)

2015-05-05 14:56:35 -04:00

erx_disty.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

erx_io.v

Cleaning up clocks

2015-05-06 12:23:15 -04:00

erx_protocol.v

Adding emesh as basic building block

2015-05-05 21:38:41 -04:00

erx_remap.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

erx_timer.v

Adding timeout circuit

2015-04-27 16:02:15 -04:00

erx.v

Using fifo_cdc instead of fifo_async

2015-05-07 23:45:36 -04:00

esaxi.v

Cleaning up logic to fit new access/packet interface

2015-05-09 08:56:51 -04:00

etx_arbiter.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

etx_cfg.v

Renaming for my sanity (etx/erx split)

2015-05-05 14:56:35 -04:00

etx_io.v

MILESTONE: Read/write works back and forth

2015-05-04 17:13:51 -04:00

etx_protocol.v

Baking in the IO wait signal into rd/wr wait

2015-05-04 17:10:32 -04:00

etx_remap.v

Separate rd/wr stalls

2015-05-04 17:09:50 -04:00

etx.v

Using fifo_cdc instead of fifo_async

2015-05-07 23:45:36 -04:00