mirror of
https://github.com/aolofsson/oh.git
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269 lines
7.0 KiB
Verilog
269 lines
7.0 KiB
Verilog
/*###########################################################################
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# Function: Clock generator for elink
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#
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# cclk_p/n - Epiphany Output Clock (>600MHz)
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#
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# tx_lclk_div4 - Parallel data clock (125Mhz)
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#
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# tx_lclk - Serial DDR data clock (500MHz)
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#
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# tx_lclk90 - DDR "Clock" clock, to generate tx_lclk_p/n output
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# Same as lclk, shifted by 90 degrees
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#
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############################################################################
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*/
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module eclocks (/*AUTOARG*/
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// Outputs
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cclk_p, cclk_n, tx_lclk, tx_lclk90, tx_lclk_div4,
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// Inputs
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hard_reset, pll_clkin
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);
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parameter CLKIN_PERIOD = 10.000; // (2.5-100ns, set by system)
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// must match actual sytem clock
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//
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//Input clock, reset, config interface
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input hard_reset; // hardware reset
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input pll_clkin; // primary input clock
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//outputs
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output cclk_p, cclk_n; // high speed Epiphany clock (up to 1GHz)
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output tx_lclk; // elink tx serdes clock
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output tx_lclk90; // center aligned output clock for elink tx
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output tx_lclk_div4; // lclk/4 slow clock for tx parallel logic
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// Wires
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wire cclk_clkfb;
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wire lclk_clkfb;
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`ifdef TARGET_XILINX
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//###########################
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// MMCM/PLL FOR CCLK
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//###########################
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parameter CCLK_VCO_MULT =12;
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parameter CCLK_DIVIDE = 2;
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MMCME2_ADV
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#(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT_F(CCLK_VCO_MULT),
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(CLKIN_PERIOD),
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.CLKOUT0_DIVIDE_F(CCLK_DIVIDE), // cclk
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.CLKOUT1_DIVIDE(CCLK_DIVIDE*2), // cclk/2
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.CLKOUT2_DIVIDE(CCLK_DIVIDE*4), // cclk/4
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.CLKOUT3_DIVIDE(CCLK_DIVIDE*8), // cclk/8
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.CLKOUT4_DIVIDE(CCLK_DIVIDE*16), // cclk/16
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.CLKOUT5_DIVIDE(CCLK_DIVIDE*32), // cclk/32
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(0.0),
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.CLKOUT5_PHASE(0.0),
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.DIVCLK_DIVIDE(1.0),
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.REF_JITTER1(0.01),
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.STARTUP_WAIT("FALSE")
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) pll_cclk
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(
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.CLKOUT0(cclk),
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.CLKOUT0B(),
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.CLKOUT1(),
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.CLKOUT1B(),
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.CLKOUT2(),
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.CLKOUT2B(),
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.CLKOUT3(),
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.CLKOUT3B(),
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.CLKOUT4(),
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.CLKOUT5(),
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.CLKOUT6(),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.CLKFBIN(cclk_clkfb),
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.CLKFBOUT(cclk_clkfb),
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.CLKIN1(pll_clkin),
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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.DADDR(7'b0),
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.DCLK(1'b0),
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.DEN(1'b0),
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.DI(16'b0),
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.DWE(1'b0),
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.DRDY(),
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.DO(),
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.LOCKED(),
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.PSCLK(1'b0),
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.PSEN(1'b0),
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.PSDONE(),
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.PSINCDEC(1'b0),
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.CLKFBSTOPPED(),
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.CLKINSTOPPED()
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);
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OBUFDS cclk_obuf (.O (cclk_p),
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.OB (cclk_n),
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.I (cclk)
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);
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//###########################
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// MMCM/PLL FOR LCLK
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//###########################
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parameter LCLK_VCO_MULT =10;
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parameter LCLK_DIVIDE = 2;
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PLLE2_ADV
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#(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT(LCLK_VCO_MULT),
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(CLKIN_PERIOD),
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.CLKOUT0_DIVIDE(LCLK_DIVIDE), // lclk
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.CLKOUT1_DIVIDE(LCLK_DIVIDE), // lclk90
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.CLKOUT2_DIVIDE(LCLK_DIVIDE*4), // lclkdiv4
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.CLKOUT3_DIVIDE(LCLK_DIVIDE*4), // lclk/4
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.CLKOUT4_DIVIDE(LCLK_DIVIDE*4), // lclk/4 with 90 deg
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.CLKOUT5_DIVIDE(LCLK_DIVIDE*16), // lclk/4-->div4
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(90.0), // tx_lclk90 shifted by 90 degrees
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.CLKOUT2_PHASE(0.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(90.0), //slow mode shifted by 90 degrees
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.CLKOUT5_PHASE(0.0),
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.DIVCLK_DIVIDE(1.0),
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.REF_JITTER1(0.01),
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.STARTUP_WAIT("FALSE")
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) pll_lclk
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(
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.CLKOUT0(tx_lclk), //tx_lclk
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.CLKOUT1(tx_lclk90), //tx_lclk90
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.CLKOUT2(tx_lclk_div4), //tx_lclk_div4
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.CLKOUT3(),
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.CLKOUT4(),
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.CLKOUT5(),
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.PWRDWN(1'b0),
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.RST(1'b0),
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.CLKFBIN(lclk_clkfb),
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.CLKFBOUT(lclk_clkfb),
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.CLKIN1(pll_clkin),
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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.DADDR(7'b0),
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.DCLK(1'b0),
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.DEN(1'b0),
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.DI(16'b0),
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.DWE(1'b0),
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.DRDY(),
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.DO(),
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.LOCKED()
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);
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`endif // `ifdef TARGET_XILINX
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/*
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`elsif TARGET_CLEAN
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clock_divider cclk_divider(
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// Outputs
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.clkout (cclk),
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.clkout90 (),
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// Inputs
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.clkin (clkin),
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.reset (hard_reset),
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.divcfg (clk_config[7:4])
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)
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;
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clock_divider lclk_divider(
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// Outputs
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.clkout (lclk),
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.clkout90 (lclk90),
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// Inputs
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.clkin (clkin),
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.reset (hard_reset),
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.divcfg (clk_config[11:8])
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);
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//This clock is always on!
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clock_divider lclk_par_divider(
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// Outputs
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.clkout (lclk_div4),
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.clkout90 (),
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// Inputs
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.clkin (clkin),
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.reset (hard_reset),
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.divcfg (clk_config[11:8] + 4'd2)
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);
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//cclk (hack for sim)
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//lclk (hack for sim)
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assign tx_lclk = hard_reset ? clkin :
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lclk_bp ? pll_bypass[1] :
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lclk;
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assign tx_lclk90 = hard_reset ? clkin :
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lclk_bp ? pll_bypass[2] :
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lclk90;
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assign tx_lclk_div4 = hard_reset ? clkin :
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lclk_bp ? pll_bypass[3] :
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lclk_div4;
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`endif
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reg clkint;
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initial
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begin
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clkint=1'b0;
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end
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always
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#0.5 clkint = ~clkint;
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*/
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endmodule // eclocks
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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