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25 lines
489 B
Verilog
25 lines
489 B
Verilog
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module IBUFDS_INTERMDISABLE_INT (O, I, IB, IBUFDISABLE, INTERMDISABLE);
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`ifdef XIL_TIMING
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parameter LOC = "UNPLACED";
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`endif // `ifdef XIL_TIMING
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parameter DIFF_TERM = "FALSE";
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parameter DQS_BIAS = "FALSE";
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parameter IBUF_LOW_PWR = "TRUE";
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parameter IOSTANDARD = "DEFAULT";
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parameter USE_IBUFDISABLE = "TRUE";
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localparam MODULE_NAME = "IBUFDS_INTERMDISABLE_INT";
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output O;
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input I;
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input IB;
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input IBUFDISABLE;
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input INTERMDISABLE;
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endmodule
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