mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-17 20:02:53 +08:00
35 lines
741 B
Verilog
35 lines
741 B
Verilog
module IDELAYE3 #(
|
|
`ifdef XIL_TIMING
|
|
parameter LOC = "UNPLACED",
|
|
`endif
|
|
parameter CASCADE = "NONE",
|
|
parameter DELAY_FORMAT = "TIME",
|
|
parameter DELAY_SRC = "IDATAIN",
|
|
parameter DELAY_TYPE = "FIXED",
|
|
parameter integer DELAY_VALUE = 0,
|
|
parameter [0:0] IS_CLK_INVERTED = 1'b0,
|
|
parameter [0:0] IS_RST_INVERTED = 1'b0,
|
|
parameter LOOPBACK = "FALSE",
|
|
parameter real REFCLK_FREQUENCY = 300.0,
|
|
parameter real SIM_VERSION = 2.0,
|
|
parameter UPDATE_MODE = "ASYNC"
|
|
)(
|
|
output CASC_OUT,
|
|
output [8:0] CNTVALUEOUT,
|
|
output DATAOUT,
|
|
|
|
input CASC_IN,
|
|
input CASC_RETURN,
|
|
input CE,
|
|
input CLK,
|
|
input [8:0] CNTVALUEIN,
|
|
input DATAIN,
|
|
input EN_VTC,
|
|
input IDATAIN,
|
|
input INC,
|
|
input LOAD,
|
|
input RST
|
|
);
|
|
|
|
endmodule
|