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103 lines
3.4 KiB
Verilog
103 lines
3.4 KiB
Verilog
/*WARNING: INCOMPLETE MODEL, DON'T USE. I RECOMMEND AGAINST USING THIS
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*BLOCK ALL TOGETHER. NOT OPEN SOURCE FRIENDLY /AO
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*/
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module ISERDESE2 (/*AUTOARG*/
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// Outputs
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O, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, SHIFTOUT1, SHIFTOUT2,
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// Inputs
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BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, CLKDIVP, D, DDLY,
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DYNCLKDIVSEL, DYNCLKSEL, OCLK, OCLKB, OFB, RST, SHIFTIN1, SHIFTIN2
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);
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parameter DATA_RATE = 0; // "DDR" or "SDR"
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parameter DATA_WIDTH = 0; // 4,2,3,5,6,7,8,10,14
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parameter DYN_CLK_INV_EN = 0; // "FALSE", "TRUE"
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parameter DYN_CLKDIV_INV_EN = 0; // "FALSE", "TRUE"
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parameter INIT_Q1 = 0; // 1'b0 to 1'b1
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parameter INIT_Q2 = 0; // 1'b0 to 1'b1
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parameter INIT_Q3 = 0; // 1'b0 to 1'b1
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parameter INIT_Q4 = 0; // 1'b0 to 1'b1
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parameter INTERFACE_TYPE = 0; // "MEMORY","MEMORY_DDR3", "MEMORY_QDR",
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// "NETWORKING", "OVERSAMPLE"
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parameter IOBDELAY = 0; // "NONE", "BOTH", "IBUF", "IFD"
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parameter NUM_CE = 0; // 2,1
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parameter OFB_USED = 0; // "FALSE", "TRUE"
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parameter SERDES_MODE = 0; // "MASTER" or "SLAVE"
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parameter SRVAL_Q1 = 0; // 1'b0 or 1'b1
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parameter SRVAL_Q2 = 0; // 1'b0 or 1'b1
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parameter SRVAL_Q3 = 0; // 1'b0 or 1'b1
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parameter SRVAL_Q4 = 0; // 1'b0 or 1'b1
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input BITSLIP; // performs bitslip operation
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input CE1; // clock enable
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input CE2; // clock enable
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input CLK; // high speed clock input
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input CLKB; // high speed clock input (inverted)
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input CLKDIV; // divided clock (for bitslip and CE module)
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input CLKDIVP; // for MIG only
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input D; // serial input data pin
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input DDLY; // serial input data from IDELAYE2
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input DYNCLKDIVSEL; // dynamically select CLKDIV inversion
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input DYNCLKSEL; // dynamically select CLK and CLKB inversion.
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input OCLK; // clock for strobe based memory interfaces
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input OCLKB; // clock for strobe based memory interfaces
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input OFB; // data feebdack from OSERDESE2?
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input RST; // asynchronous reset
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input SHIFTIN1; // slave of multie serdes
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input SHIFTIN2; // slave of multie serdes
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//outputs
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output O; // pass through from D or DDLY
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output Q1; // parallel data out (last bit)
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output Q2;
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output Q3;
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output Q4;
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output Q5;
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output Q6;
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output Q7;
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output Q8; // first bit of D appears here
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output SHIFTOUT1; // master of multi serdes
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output SHIFTOUT2; // master of multi serdes
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reg [3:0] even_samples;
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reg [3:0] odd_samples;
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reg Q1;
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reg Q2;
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reg Q3;
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reg Q4;
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reg Q5;
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reg Q6;
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reg Q7;
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reg Q8;
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always @ (posedge CLK)
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odd_samples[3:0] <= {odd_samples[2:0],D};//#0.1
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always @ (negedge CLK)
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even_samples[3:0] <= {even_samples[2:0],D};//#0.1
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always @ (posedge CLKDIV)
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begin
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Q1 <= odd_samples[0];
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Q2 <= even_samples[0];
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Q3 <= odd_samples[1];
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Q4 <= even_samples[1];
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Q5 <= odd_samples[2];
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Q6 <= even_samples[2];
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Q7 <= odd_samples[3];
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Q8 <= even_samples[3];
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end
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//pass through
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assign O=D;
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//not implemented
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assign SHIFTOUT1=1'b0;
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assign SHIFTOUT2=1'b0;
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endmodule // ISERDESE2
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