Andreas Olofsson 581c2943f5 Fixing pushback bug in emmu ...

- reset was broken!
- need to account for wait
- merging read/write wait for simplicity, otherwise you would need to reset the packets to figure out if it's a read or write transaction...and I don't want to reset every packet throughout the pipe.

2015-10-19 11:08:28 -04:00

..

axi_elink.v

TX clock and reset cleanup

2015-10-07 19:15:29 -04:00

ecfg_elink.v

TX clock and reset cleanup

2015-10-07 19:15:29 -04:00

ecfg_if.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

eclocks.v

Making reset async

2015-10-07 14:46:12 -04:00

elink_constants.v

Removing ephycard define

2015-08-25 12:40:48 +02:00

elink_regmap.v

Adding testmode for RX

2015-10-07 21:58:50 -04:00

elink.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

emaxi.v

Making reset async

2015-10-07 14:46:12 -04:00

ereset.v

Adding software programmable IDELAY

2015-10-07 11:49:46 -04:00

erx_arbiter.v

Adding testmode for RX

2015-10-07 21:58:50 -04:00

erx_cfg.v

Adding testmode for RX

2015-10-07 21:58:50 -04:00

erx_clocks.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

erx_core.v

Fixing pushback bug in emmu

2015-10-19 11:08:28 -04:00

erx_fifo.v

Copyright cleanup

2015-08-07 09:19:37 -04:00

erx_io.v

Fixing pushback bug in emmu

2015-10-19 11:08:28 -04:00

erx_protocol.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

erx_remap.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

erx_timer.v

Converting to synchronous reset

2015-05-17 23:00:53 -04:00

erx.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

esaxi.v

Making reset async

2015-10-07 14:46:12 -04:00

etx_arbiter.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

etx_cfg.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

etx_clocks.v

Improving sys_reset timing

2015-10-08 10:33:38 -04:00

etx_core.v

Fixing pushback bug in emmu

2015-10-19 11:08:28 -04:00

etx_fifo.v

Fifo parameter change

2015-07-02 16:55:42 -04:00

etx_io.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

etx_protocol.v

Reset timing optimization

2015-10-08 10:34:59 -04:00

etx_remap.v

Separate rd/wr stalls

2015-05-04 17:09:50 -04:00

etx.v

Reset timing optimization

2015-10-08 10:34:59 -04:00