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191 lines
6.3 KiB
Verilog
191 lines
6.3 KiB
Verilog
module MMCME2_ADV # (
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parameter BANDWIDTH = "OPTIMIZED",
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parameter real CLKFBOUT_MULT_F = 5.000,
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parameter real CLKFBOUT_PHASE = 0.000,
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parameter CLKFBOUT_USE_FINE_PS = "FALSE",
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parameter real CLKIN1_PERIOD = 10.000,
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parameter real CLKIN2_PERIOD = 0.000,
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parameter real CLKOUT0_DIVIDE_F = 1.000,
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parameter real CLKOUT0_DUTY_CYCLE = 0.500,
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parameter real CLKOUT0_PHASE = 0.000,
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parameter CLKOUT0_USE_FINE_PS = "FALSE",
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parameter integer CLKOUT1_DIVIDE = 1,
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parameter real CLKOUT1_DUTY_CYCLE = 0.500,
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parameter real CLKOUT1_PHASE = 0.000,
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parameter CLKOUT1_USE_FINE_PS = "FALSE",
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parameter integer CLKOUT2_DIVIDE = 1,
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parameter real CLKOUT2_DUTY_CYCLE = 0.500,
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parameter real CLKOUT2_PHASE = 0.000,
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parameter CLKOUT2_USE_FINE_PS = "FALSE",
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parameter integer CLKOUT3_DIVIDE = 1,
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parameter real CLKOUT3_DUTY_CYCLE = 0.500,
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parameter real CLKOUT3_PHASE = 0.000,
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parameter CLKOUT3_USE_FINE_PS = "FALSE",
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parameter CLKOUT4_CASCADE = "FALSE",
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parameter integer CLKOUT4_DIVIDE = 1,
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parameter real CLKOUT4_DUTY_CYCLE = 0.500,
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parameter real CLKOUT4_PHASE = 0.000,
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parameter CLKOUT4_USE_FINE_PS = "FALSE",
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parameter integer CLKOUT5_DIVIDE = 1,
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parameter real CLKOUT5_DUTY_CYCLE = 0.500,
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parameter real CLKOUT5_PHASE = 0.000,
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parameter CLKOUT5_USE_FINE_PS = "FALSE",
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parameter integer CLKOUT6_DIVIDE = 1,
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parameter real CLKOUT6_DUTY_CYCLE = 0.500,
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parameter real CLKOUT6_PHASE = 0.000,
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parameter CLKOUT6_USE_FINE_PS = "FALSE",
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parameter COMPENSATION = "ZHOLD",
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parameter integer DIVCLK_DIVIDE = 1,
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parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
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parameter [0:0] IS_PSEN_INVERTED = 1'b0,
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parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0,
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parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
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parameter [0:0] IS_RST_INVERTED = 1'b0,
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parameter real REF_JITTER1 = 0.010,
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parameter real REF_JITTER2 = 0.010,
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parameter SS_EN = "FALSE",
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parameter SS_MODE = "CENTER_HIGH",
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parameter integer SS_MOD_PERIOD = 10000,
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parameter STARTUP_WAIT = "FALSE"
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)(
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output CLKFBOUT, //feedback clock to connect to CLKFBIN
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output CLKFBOUTB, //inverted feedback clock output
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output CLKFBSTOPPED, //indicates that FB clock as stoppped
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output CLKINSTOPPED, //indicates that input clock has stopped
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output CLKOUT0, //clock output
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output CLKOUT0B, //inverted clock output
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output CLKOUT1,
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output CLKOUT1B,
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output CLKOUT2,
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output CLKOUT2B,
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output CLKOUT3,
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output CLKOUT3B,
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output CLKOUT4,
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output CLKOUT5,
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output CLKOUT6,
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output LOCKED, //indicates PLL is locked
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output PSDONE, //phase shift done
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input CLKFBIN,
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input CLKIN1,
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input CLKIN2,
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input CLKINSEL, //selects between two input clocks,1=primary
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output DRDY, //dynamic reconfig ready
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input [6:0] DADDR, //Address port for dynamic reconfig
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input DCLK, //clock port for dynamic reconfig
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input DEN, //enable for dynamic reconfig
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input [15:0] DI, //data for dynamic reconfig
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input DWE, //dynamic reconfig write enable
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output [15:0] DO, //readback data for dyanmic reconfig
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input PSCLK, //phase shift clock
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input PSEN, //phase shift enable
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input PSINCDEC, //phase shift decrement/increment
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input PWRDWN, //global power down pin
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input RST //async global reset
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);
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//#LOCAL DERIVED PARAMETERS
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parameter VCO_PERIOD = (CLKIN1_PERIOD * DIVCLK_DIVIDE) / CLKFBOUT_MULT_F;
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parameter CLK0_DELAY = VCO_PERIOD * CLKOUT0_DIVIDE_F * (CLKOUT0_PHASE/360);
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parameter CLK1_DELAY = VCO_PERIOD * CLKOUT1_DIVIDE * (CLKOUT1_PHASE/360);
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parameter CLK2_DELAY = VCO_PERIOD * CLKOUT2_DIVIDE * (CLKOUT2_PHASE/360);
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parameter CLK3_DELAY = VCO_PERIOD * CLKOUT3_DIVIDE * (CLKOUT3_PHASE/360);
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parameter CLK4_DELAY = VCO_PERIOD * CLKOUT4_DIVIDE * (CLKOUT4_PHASE/360);
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parameter CLK5_DELAY = VCO_PERIOD * CLKOUT5_DIVIDE * (CLKOUT5_PHASE/360);
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parameter CLK6_DELAY = VCO_PERIOD * CLKOUT6_DIVIDE * (CLKOUT6_PHASE/360);
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//##############
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//#VCO
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//##############
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reg vco_clk;
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initial
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begin
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vco_clk = 1'b0;
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end
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always
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#(VCO_PERIOD/2) vco_clk = ~vco_clk;
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//##############
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//#DIVIDERS
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//##############
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wire [3:0] DIVCFG[6:0];
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wire [6:0] CLKOUT_DIV;
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assign DIVCFG[0] = $clog2(CLKOUT0_DIVIDE_F);
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assign DIVCFG[1] = $clog2(CLKOUT1_DIVIDE);
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assign DIVCFG[2] = $clog2(CLKOUT2_DIVIDE);
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assign DIVCFG[3] = $clog2(CLKOUT3_DIVIDE);
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assign DIVCFG[4] = $clog2(CLKOUT4_DIVIDE);
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assign DIVCFG[5] = $clog2(CLKOUT5_DIVIDE);
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assign DIVCFG[6] = $clog2(CLKOUT6_DIVIDE);
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//ugly POR reset
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reg POR;
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initial
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begin
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POR=1'b1;
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#1
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POR=1'b0;
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end
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genvar i;
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generate for(i=0; i<7; i=i+1)
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begin : gen_clkdiv
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clock_divider clkdiv (/*AUTOINST*/
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// Outputs
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.clkout (CLKOUT_DIV[i]),
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// Inputs
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.clkin (vco_clk),
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.divcfg (DIVCFG[i]),
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.reset (RST | POR));
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end
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endgenerate
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//##############
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//#PHASE DELAY
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//##############
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reg CLKOUT0;
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reg CLKOUT1;
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reg CLKOUT2;
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reg CLKOUT3;
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reg CLKOUT4;
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reg CLKOUT5;
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reg CLKOUT6;
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always @ (CLKOUT_DIV)
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begin
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CLKOUT0 <= #(CLK0_DELAY) CLKOUT_DIV[0];
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CLKOUT1 <= #(CLK1_DELAY) CLKOUT_DIV[1];
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CLKOUT2 <= #(CLK2_DELAY) CLKOUT_DIV[2];
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CLKOUT3 <= #(CLK3_DELAY) CLKOUT_DIV[3];
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CLKOUT4 <= #(CLK4_DELAY) CLKOUT_DIV[4];
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CLKOUT5 <= #(CLK5_DELAY) CLKOUT_DIV[5];
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CLKOUT6 <= #(CLK6_DELAY) CLKOUT_DIV[6];
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end
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//##############
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//#DUMMY DRIVES
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//##############
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assign CLKFBOUT=CLKIN1;
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//###########################
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//#SANITY CHECK LOCK COUNTER
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//############################
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parameter LCW=4;
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reg [LCW-1:0] lock_counter;
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wire reset = POR | RST;
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always @ (posedge CLKIN1 or posedge reset)
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if(reset)
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lock_counter[LCW-1:0] <= {(LCW){1'b1}};
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else if(~LOCKED)
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lock_counter[LCW-1:0] <= lock_counter[LCW-1:0] - 1'b1;
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assign LOCKED = ~(|lock_counter[LCW-1:0]);
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endmodule // MMCME2_ADV
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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