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32 lines
654 B
Verilog
32 lines
654 B
Verilog
/* Simple combinatorial priority arbiter
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* (lowest position has highest priority)
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*
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*/
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module arbiter_priority(/*AUTOARG*/
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// Outputs
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grant, await,
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// Inputs
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request
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);
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parameter ARW=99;
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input [ARW-1:0] request; //request vector
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output [ARW-1:0] grant; //grant (one hot)
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output [ARW-1:0] await; //grant mask
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genvar j;
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assign await[0] = 1'b0;
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generate for (j=ARW-1; j>=1; j=j-1) begin : gen_arbiter
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assign await[j] = |request[j-1:0];
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end
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endgenerate
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//grant circuit
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assign grant[ARW-1:0] = request[ARW-1:0] & ~await[ARW-1:0];
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endmodule // arbiter_priority
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