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55ba8ff635
- removing unconnected ports - only one rst input for async_fifo - synchronizing the reset input toe emaxi fifo
30 lines
486 B
Verilog
30 lines
486 B
Verilog
/*
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* This module stretches a pulse by DW+1 clock cycles
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* Can be useful for synchronous clock transfers from fast to slow.
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*
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*/
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module pulse_stretcher (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, in
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);
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parameter DW = 1;
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input clk;
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input in;
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output out;
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reg [DW-1:0] wide_pulse;
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always @ (posedge clk)
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wide_pulse[DW-1:0] <= {wide_pulse[DW-2:0],in};
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assign out = (|{wide_pulse[DW-1:0],in});
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endmodule // pulse_stretcher
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