Andreas Olofsson 61eb56c6f7 Final Vivado fixups: ...

- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks

2015-11-09 16:09:12 -05:00

..

dv

Fixing synchronization reset speed path

2015-11-09 00:16:35 -05:00

fpga

Adding hdmi pins for parallella

2015-11-09 13:22:08 -05:00

hdl

Final Vivado fixups:

2015-11-09 16:09:12 -05:00