Andreas Olofsson f141a0e320 Clock cleanup ...

-Adding enable signal to clock out. Definitely right decision to keep
separate bit from the divider field.
-Fixed settings for to fit new register field
-XILINX version is still broken!!

2015-04-18 16:24:26 -04:00

..

ecfg.v

Fixed to fit with new register map

2015-04-18 16:23:35 -04:00

eclocks.v

Clock cleanup

2015-04-18 16:24:26 -04:00

elink_regmap.v

Changed register map

2015-04-18 16:21:45 -04:00

elink.v

Spell checking comments

2015-04-18 06:36:33 -04:00

emaxi.v

AXI bug fixes

2015-04-14 20:26:58 -04:00

ereset.v

Cleaning up licenses for consistency

2015-04-17 22:21:08 -04:00

erx_disty.v

MILESTONE: Open souce simulation elink loopback working!

2015-04-17 15:51:55 -04:00

erx_io.v

Adding documentation to elink top level module

2015-04-17 22:10:14 -04:00

erx_protocol.v

Verilator lint cleanup

2015-04-14 14:00:23 -04:00

erx.v

MILESTONE: Open souce simulation elink loopback working!

2015-04-17 15:51:55 -04:00

esaxi.v

ESAXI cleanup

2015-04-18 16:18:41 -04:00

etx_arbiter.v

Fixing startup issues in transmit path:

2015-04-15 16:33:20 -04:00

etx_io.v

Removed synchronizer on TXLCLK

2015-04-18 16:17:44 -04:00

etx_protocol.v

Man that's a lot of yak shaving....

2015-04-13 23:35:21 -04:00

etx.v

Continued work to create clean design:

2015-04-15 11:54:43 -04:00