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Patrik Lindström f232d9d297 Changed rx_ref_clk PLL divider
2015-06-30 12:35:38 +02:00
common
Changing default to simplify instantiation
2015-05-14 22:46:23 -04:00
edma
Making reset sync in emmu
2015-05-23 22:26:15 -04:00
elink
Changed rx_ref_clk PLL divider
2015-06-30 12:35:38 +02:00
emailbox
Making FIFO/memories easier to use
2015-05-07 23:50:34 -04:00
emesh
Reorg
2015-06-25 19:52:28 -04:00
emmu
Making reset sync in emmu
2015-05-23 22:26:15 -04:00
memory
Removing custom xilinx primitives
2015-05-21 22:54:29 -04:00
parallella/package/xilinx
Adding parallella block design
2015-05-22 21:38:39 -04:00
xilibs
Adding OBUF model
2015-06-25 15:42:20 -04:00
.gitignore
Adding register access from RX
2015-04-27 23:51:00 -04:00
CONTRIBUTING.md
Basic infrastructure
2015-04-21 21:36:37 -04:00
COPYING
Basic infrastructure
2015-04-21 21:36:37 -04:00
README.md
Massive commit sequence coming...
2015-04-23 17:48:12 -04:00

README.md

=======

OH!

Open Hardware (Pure and Simple)

(work in progress...)

Description
No description provided
Readme MIT 43 MiB
Languages
Verilog 81.1%
Tcl 10.7%
C 5.6%
Shell 0.8%
Python 0.6%
Other 1.2%