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f77938e9b0
- The logic was a mess, causing me to go around in circles for days. In the end, by adding a missing sync circuit (duh!) between the fast and slow clock to align the edges and removing a redundant pipeline stage ("double") the nasty logic just fell away. Looks good now.
-Write bursts mostly works and design looks clean.
-one bug left to fix on streams of writes...
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OH!
An Open Hardware Library for Chip and FPGA designers written in Verilog
CONTENT
| Spec | Description |
|---|---|
| common | Common utility modules and scripts |
| edma | DMA module |
| emesh | Epiphany emesh related circuits |
| elink | Epiphany point to point LVDS link |
| emailbox | Simple mailbox with interrupt output |
| emmu | Simple memory transaction translation unit |
| memory | Various simple memory structures (RAM/FIFO) |
| xilibs | Simulation modules for Xilinx primitives |
LICENSE
The OH! repository source code is licensed under the MIT license unless otherwise specified. See LICENSE for full copyright terms.
CONTRIBUTING
Instructions for contributing can be found HERE.