Ola Jeppsson f7e8ddfe7d fpga/system_build.tcl: Write raw BIN bitstream file ...

Write raw BIN bitstream file without metadata, as well as BIT file.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>

2017-02-07 18:40:01 +01:00

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accelerator

Reorg! Why?

2016-03-22 08:13:40 -04:00

aes

Reorg! Why?

2016-03-22 08:13:40 -04:00

axi

AXI: emaxi: added nreset to instantiation of oh_dsync

2016-08-17 15:57:25 +01:00

chip

Fixing readme

2016-04-15 22:38:06 -04:00

common

fpga/system_build.tcl: Write raw BIN bitstream file

2017-02-07 18:40:01 +01:00

edma

Updating dma with new packet format

2016-05-15 15:49:39 -04:00

elink

elink: Migrate to Ultrascale+ IO primitives

2017-02-04 21:17:11 +01:00

emailbox

TARGET changed back to XILINX from GENERIC

2016-08-17 15:30:38 +01:00

emesh

Updating to new emesh packet mappers

2016-05-15 15:46:49 -04:00

emmu

Using DEPTH as specifier for memory

2016-04-14 10:29:49 -04:00

etrace

Synthesis cleanup

2016-06-19 17:12:24 -04:00

gpio

Fefactoring to clarify register usage

2016-08-25 11:44:30 -04:00

mio

Fixing reset bug for MIO emode

2016-08-28 19:14:45 -04:00

parallella

Apply CFG_ASIC at the top level

2016-08-17 14:22:04 +01:00

pic

Cleaning up PIC code

2016-05-15 15:31:42 -04:00

risc-v

Adding preliminary r5 opcodes

2016-09-26 15:16:00 -04:00

spi

Adding DV hook into SPI block

2016-08-26 23:50:05 -04:00

xilibs

ip: fifo_async_104x32: Regenerate IP

2017-02-04 21:17:11 +01:00

zcu102

zcu102: zcu102_base: Fix Makefile dependencies and clean target

2017-02-06 19:45:01 +01:00