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bf614a9873
- removing redundant signals - configuring to put synchronizer inside fifo - one reset only (not two)
136 lines
4.5 KiB
Verilog
136 lines
4.5 KiB
Verilog
module etx_fifo(/*AUTOARG*/
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// Outputs
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txrd_wait, txwr_wait, txrr_wait, txrd_fifo_access,
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txrd_fifo_packet, txrr_fifo_access, txrr_fifo_packet,
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txwr_fifo_access, txwr_fifo_packet,
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// Inputs
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sys_nreset, sys_clk, tx_lclk_div4, txrd_access, txrd_packet,
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txwr_access, txwr_packet, txrr_access, txrr_packet, txrd_fifo_wait,
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txrr_fifo_wait, txwr_fifo_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h000;
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//Clocks,reset,config
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input sys_nreset;
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input sys_clk;
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input tx_lclk_div4; // slow speed parallel clock
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//Read Request Channel Input
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input txrd_access;
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input [PW-1:0] txrd_packet;
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output txrd_wait;
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//Write Channel Input
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input txwr_access;
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input [PW-1:0] txwr_packet;
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output txwr_wait;
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//Read Response Channel Input
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input txrr_access;
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input [PW-1:0] txrr_packet;
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output txrr_wait;
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//Read request for pins
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output txrd_fifo_access;
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output [PW-1:0] txrd_fifo_packet;
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input txrd_fifo_wait;
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//Read response for pins
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output txrr_fifo_access;
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output [PW-1:0] txrr_fifo_packet;
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input txrr_fifo_wait;
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//Write for pins
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output txwr_fifo_access;
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output [PW-1:0] txwr_fifo_packet;
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input txwr_fifo_wait;
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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/************************************************************/
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/*FIFOs */
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/************************************************************/
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//TODO: Minimize depth and width
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/*fifo_cdc AUTO_TEMPLATE (
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// Outputs
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.access_out (@"(substring vl-cell-name 0 4)"_fifo_access),
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.packet_out (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
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.wait_out (@"(substring vl-cell-name 0 4)"_wait),
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.wait_in (@"(substring vl-cell-name 0 4)"_fifo_wait),
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.clk_out (tx_lclk_div4),
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.clk_in (sys_clk),
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.access_in (@"(substring vl-cell-name 0 4)"_access),
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.rd_en (@"(substring vl-cell-name 0 4)"_fifo_read),
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.nreset (sys_nreset),
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.packet_in (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
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);
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*/
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//Write fifo (from slave)
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fifo_cdc #(.DW(104), .DEPTH(32)) txwr_fifo(
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/*AUTOINST*/
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// Outputs
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.wait_out (txwr_wait), // Templated
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.access_out (txwr_fifo_access), // Templated
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.packet_out (txwr_fifo_packet[PW-1:0]), // Templated
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// Inputs
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.nreset (sys_nreset), // Templated
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.clk_in (sys_clk), // Templated
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.access_in (txwr_access), // Templated
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.packet_in (txwr_packet[PW-1:0]), // Templated
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.clk_out (tx_lclk_div4), // Templated
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.wait_in (txwr_fifo_wait)); // Templated
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//Read request fifo (from slave)
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fifo_cdc #(.DW(104), .DEPTH(32)) txrd_fifo(
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/*AUTOINST*/
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// Outputs
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.wait_out (txrd_wait), // Templated
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.access_out (txrd_fifo_access), // Templated
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.packet_out (txrd_fifo_packet[PW-1:0]), // Templated
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// Inputs
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.nreset (sys_nreset), // Templated
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.clk_in (sys_clk), // Templated
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.access_in (txrd_access), // Templated
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.packet_in (txrd_packet[PW-1:0]), // Templated
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.clk_out (tx_lclk_div4), // Templated
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.wait_in (txrd_fifo_wait)); // Templated
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//Read response fifo (from master)
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fifo_cdc #(.DW(104), .DEPTH(32)) txrr_fifo(
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/*AUTOINST*/
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// Outputs
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.wait_out (txrr_wait), // Templated
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.access_out (txrr_fifo_access), // Templated
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.packet_out (txrr_fifo_packet[PW-1:0]), // Templated
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// Inputs
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.nreset (sys_nreset), // Templated
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.clk_in (sys_clk), // Templated
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.access_in (txrr_access), // Templated
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.packet_in (txrr_packet[PW-1:0]), // Templated
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.clk_out (tx_lclk_div4), // Templated
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.wait_in (txrr_fifo_wait)); // Templated
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endmodule // elink
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// Local Variables:
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// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
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// End:
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