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71 lines
1.9 KiB
Verilog
71 lines
1.9 KiB
Verilog
//############################################################
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//#This block handles the autoincrement needed for bursting
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//############################################################
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module erx_protocol (/*AUTOARG*/
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// Outputs
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erx_access, erx_packet,
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// Inputs
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clk, test_mode, rx_packet, rx_burst, rx_access
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter ID = 12'h999; //link id
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// System reset input
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input clk;
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//test mode
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input test_mode; //block all traffic in test mode
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// Parallel interface, 8 eLink bytes at a time
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input [PW-1:0] rx_packet;
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input rx_burst;
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input rx_access;
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// Output to MMU / filter
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output erx_access;
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output [PW-1:0] erx_packet;
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//wires
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reg [31:0] dstaddr_reg;
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wire [31:0] dstaddr_next;
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wire [31:0] dstaddr_mux;
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reg erx_access;
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reg [PW-1:0] erx_packet;
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wire [31:0] rx_addr;
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//parsing inputs
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assign rx_addr[31:0] = rx_packet[39:8];
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//Address generator for bursting
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always @ (posedge clk)
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if(rx_access)
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dstaddr_reg[31:0] <= dstaddr_mux[31:0];
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assign dstaddr_next[31:0] = dstaddr_reg[31:0] + 4'b1000;
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assign dstaddr_mux[31:0] = rx_burst ? dstaddr_next[31:0] :
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rx_addr[31:0];
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//Pipeline stage and decode
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always @ (posedge clk)
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begin
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//Write/read request
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erx_access <= ~test_mode & rx_access;
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//Common packet
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erx_packet[PW-1:0] <= {rx_packet[PW-1:40],
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dstaddr_mux[31:0],
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{1'b0,rx_packet[7:1]} //NOTE: remvoing redundant access packet bit
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}; //This is to conform to new format
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end
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endmodule // erx_protocol
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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