21 lines
877 B
Plaintext
21 lines
877 B
Plaintext
|
transcript on
|
||
|
|
if {[file exists rtl_work]} {
|
||
|
|
vdel -lib rtl_work -all
|
||
|
|
}
|
||
|
|
vlib rtl_work
|
||
|
|
vmap work rtl_work
|
||
|
|
|
||
|
|
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v}
|
||
|
|
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v}
|
||
|
|
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v}
|
||
|
|
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v}
|
||
|
|
|
||
|
|
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v}
|
||
|
|
|
||
|
|
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb
|
||
|
|
|
||
|
|
add wave *
|
||
|
|
view structure
|
||
|
|
view signals
|
||
|
|
run -all
|