124 lines
2.4 KiB
Coq
124 lines
2.4 KiB
Coq
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module timer_pwm(
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clk_tim,
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rst_n,
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tim_cr,
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tim_cnt,
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tim_psc,
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tim_arr,
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tim_ccr,
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tim_ccr1,
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tim_ccr2,
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tim_ccr3,
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tim_ccr4,
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tim_ch
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);
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input clk_tim;
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input rst_n;
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input [15:0] tim_cnt;
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input [15:0] tim_psc;
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input [15:0] tim_arr;
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input [15:0] tim_ccr;
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input [31:0] tim_cr;
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input [15:0] tim_ccr1;
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input [15:0] tim_ccr2;
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input [15:0] tim_ccr3;
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input [15:0] tim_ccr4;
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output reg [7:0] tim_ch;//[7:0] {...tim_ch1,tim_ch1n}
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reg [31:0] r_tim_cr;
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reg [15:0] r_tim_cnt;
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reg [15:0] r_tim_psc;
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reg [15:0] r_tim_arr;
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reg [15:0] r_tim_ccr;
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reg [15:0] r_tim_ccr1;
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reg [15:0] r_tim_ccr2;
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reg [15:0] r_tim_ccr3;
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reg [15:0] r_tim_ccr4;
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reg [15:0] cnt_psc;//分频计数器，多久计数一次等于clk/( r_tim_psc[15:0]+1)。
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reg [15:0] cnt; //整个定时器的计数值
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always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn
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if(!rst_n)
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tim_ch[1:0] <= 2'b01;
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else if(cnt < r_tim_ccr1)
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tim_ch[1:0] <= 2'b01;
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else
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tim_ch[1:0] <= 2'b10;
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always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn
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if(!rst_n)
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tim_ch[3:2] <= 2'b01;
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else if(cnt < r_tim_ccr2)
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tim_ch[3:2] <= 2'b01;
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else
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tim_ch[3:2] <= 2'b10;
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always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn
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if(!rst_n)
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tim_ch[5:4] <= 2'b01;
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else if(cnt < r_tim_ccr3)
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tim_ch[5:4] <= 2'b01;
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else
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tim_ch[5:4] <= 2'b10;
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always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn
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if(!rst_n)
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tim_ch[7:6] <= 2'b01;
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else if(cnt < r_tim_ccr4)
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tim_ch[7:6] <= 2'b01;
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else
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tim_ch[7:6] <= 2'b10;
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always @ (posedge clk_tim or negedge rst_n)
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if(!rst_n)
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cnt <= 16'd0;
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else if(cnt >= tim_arr)
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cnt <= 16'd0;
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else if(cnt_psc >= r_tim_psc)
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cnt <= cnt + 1'b1;
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always @ (posedge clk_tim or negedge rst_n)
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if(!rst_n)
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cnt_psc <= 16'd0;
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else if(cnt_psc >= r_tim_psc)
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cnt_psc <= 16'd0;
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else
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cnt_psc <= cnt_psc + 1'b1;
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always @ (posedge clk_tim or negedge rst_n)
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if(!rst_n) begin
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r_tim_cnt <= 16'd0;
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r_tim_psc <= 16'd0;
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r_tim_arr <= 16'd0;
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r_tim_ccr <= 16'd0;
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r_tim_cr <= 32'd0;
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r_tim_ccr1 <= 16'd0;
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r_tim_ccr2 <= 16'd0;
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r_tim_ccr3 <= 16'd0;
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r_tim_ccr4 <= 16'd0;
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end
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else
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begin
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r_tim_cnt <= tim_cnt;
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r_tim_psc <= tim_psc;
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r_tim_arr <= tim_arr;
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r_tim_ccr <= tim_ccr;
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r_tim_cr <= tim_cr;
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r_tim_ccr1 <= tim_ccr1;
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r_tim_ccr2 <= tim_ccr2;
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r_tim_ccr3 <= tim_ccr3;
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r_tim_ccr4 <= tim_ccr4;
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end
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endmodule
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