commit fef5d7bde7a064fd27543975d4b07704f3095adb Author: sansi Date: Tue Jun 9 15:54:49 2020 +0800 first commit diff --git a/dpwm/db/.cmp.kpt b/dpwm/db/.cmp.kpt new file mode 100644 index 0000000..76f557b Binary files /dev/null and b/dpwm/db/.cmp.kpt differ diff --git a/dpwm/db/.ipregen.qmsg b/dpwm/db/.ipregen.qmsg new file mode 100644 index 0000000..958c4f9 --- /dev/null +++ b/dpwm/db/.ipregen.qmsg @@ -0,0 +1,2 @@ +{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "d:/intelfpga/18.0/quartus/common/tcl/internal/ip_regen/ip_regen.tcl " "Evaluation of Tcl script d:/intelfpga/18.0/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful" { } { } 0 23030 "Evaluation of Tcl script %1!s! was successful" 0 0 "Shell" 0 -1 1541422418928 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Shell 0 s 0 s Quartus Prime " "Quartus Prime Shell was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4903 " "Peak virtual memory: 4903 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541422418929 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 20:53:38 2018 " "Processing ended: Mon Nov 05 20:53:38 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541422418929 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541422418929 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:31 " "Total CPU time (on all processors): 00:00:31" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541422418929 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1541422418929 ""} diff --git a/dpwm/db/dpwm.(0).cnf.cdb b/dpwm/db/dpwm.(0).cnf.cdb new file mode 100644 index 0000000..8460474 Binary files /dev/null and b/dpwm/db/dpwm.(0).cnf.cdb differ diff --git a/dpwm/db/dpwm.(0).cnf.hdb b/dpwm/db/dpwm.(0).cnf.hdb new file mode 100644 index 0000000..d61c24a Binary files /dev/null and b/dpwm/db/dpwm.(0).cnf.hdb differ diff --git a/dpwm/db/dpwm.(1).cnf.cdb b/dpwm/db/dpwm.(1).cnf.cdb new file mode 100644 index 0000000..c6f201d Binary files /dev/null and b/dpwm/db/dpwm.(1).cnf.cdb differ diff --git a/dpwm/db/dpwm.(1).cnf.hdb b/dpwm/db/dpwm.(1).cnf.hdb new file mode 100644 index 0000000..d3a4175 Binary files /dev/null and b/dpwm/db/dpwm.(1).cnf.hdb differ diff --git a/dpwm/db/dpwm.(2).cnf.cdb b/dpwm/db/dpwm.(2).cnf.cdb new file mode 100644 index 0000000..922947e Binary files /dev/null and b/dpwm/db/dpwm.(2).cnf.cdb differ diff --git a/dpwm/db/dpwm.(2).cnf.hdb b/dpwm/db/dpwm.(2).cnf.hdb new file mode 100644 index 0000000..826392b Binary files /dev/null and b/dpwm/db/dpwm.(2).cnf.hdb differ diff --git a/dpwm/db/dpwm.(3).cnf.cdb b/dpwm/db/dpwm.(3).cnf.cdb new file mode 100644 index 0000000..a4db61e Binary files /dev/null and b/dpwm/db/dpwm.(3).cnf.cdb differ diff --git a/dpwm/db/dpwm.(3).cnf.hdb b/dpwm/db/dpwm.(3).cnf.hdb new file mode 100644 index 0000000..2a38b76 Binary files /dev/null and b/dpwm/db/dpwm.(3).cnf.hdb differ diff --git a/dpwm/db/dpwm.(4).cnf.cdb b/dpwm/db/dpwm.(4).cnf.cdb new file mode 100644 index 0000000..8686fa7 Binary files /dev/null and b/dpwm/db/dpwm.(4).cnf.cdb differ diff --git a/dpwm/db/dpwm.(4).cnf.hdb b/dpwm/db/dpwm.(4).cnf.hdb new file mode 100644 index 0000000..17186ba Binary files /dev/null and b/dpwm/db/dpwm.(4).cnf.hdb differ diff --git a/dpwm/db/dpwm.(5).cnf.cdb b/dpwm/db/dpwm.(5).cnf.cdb new file mode 100644 index 0000000..8960654 Binary files /dev/null and b/dpwm/db/dpwm.(5).cnf.cdb differ diff --git a/dpwm/db/dpwm.(5).cnf.hdb b/dpwm/db/dpwm.(5).cnf.hdb new file mode 100644 index 0000000..519b53c Binary files /dev/null and b/dpwm/db/dpwm.(5).cnf.hdb differ diff --git a/dpwm/db/dpwm.(6).cnf.cdb b/dpwm/db/dpwm.(6).cnf.cdb new file mode 100644 index 0000000..f829801 Binary files /dev/null and b/dpwm/db/dpwm.(6).cnf.cdb differ diff --git a/dpwm/db/dpwm.(6).cnf.hdb b/dpwm/db/dpwm.(6).cnf.hdb new file mode 100644 index 0000000..41bb304 Binary files /dev/null and b/dpwm/db/dpwm.(6).cnf.hdb differ diff --git a/dpwm/db/dpwm.ace_cmp.bpm b/dpwm/db/dpwm.ace_cmp.bpm new file mode 100644 index 0000000..9584558 Binary files /dev/null and b/dpwm/db/dpwm.ace_cmp.bpm differ diff --git a/dpwm/db/dpwm.ace_cmp.cdb b/dpwm/db/dpwm.ace_cmp.cdb new file mode 100644 index 0000000..beafc11 Binary files /dev/null and b/dpwm/db/dpwm.ace_cmp.cdb differ diff --git a/dpwm/db/dpwm.ace_cmp.hdb b/dpwm/db/dpwm.ace_cmp.hdb new file mode 100644 index 0000000..93cdb62 Binary files /dev/null and b/dpwm/db/dpwm.ace_cmp.hdb differ diff --git a/dpwm/db/dpwm.asm.qmsg b/dpwm/db/dpwm.asm.qmsg new file mode 100644 index 0000000..0c127d1 --- /dev/null +++ b/dpwm/db/dpwm.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541424071884 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541424071904 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 21:21:11 2018 " "Processing started: Mon Nov 05 21:21:11 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541424071904 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1541424071904 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off dpwm -c dpwm " "Command: quartus_asm --read_settings_files=off --write_settings_files=off dpwm -c dpwm" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1541424071904 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1541424072628 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1541424073164 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1541424073193 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4693 " "Peak virtual memory: 4693 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541424073380 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:21:13 2018 " "Processing ended: Mon Nov 05 21:21:13 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541424073380 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541424073380 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541424073380 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1541424073380 ""} diff --git a/dpwm/db/dpwm.asm.rdb b/dpwm/db/dpwm.asm.rdb new file mode 100644 index 0000000..0ae2660 Binary files /dev/null and b/dpwm/db/dpwm.asm.rdb differ diff --git a/dpwm/db/dpwm.asm_labs.ddb b/dpwm/db/dpwm.asm_labs.ddb new file mode 100644 index 0000000..cf20e58 Binary files /dev/null and b/dpwm/db/dpwm.asm_labs.ddb differ diff --git a/dpwm/db/dpwm.cmp.bpm b/dpwm/db/dpwm.cmp.bpm new file mode 100644 index 0000000..9584558 Binary files /dev/null and b/dpwm/db/dpwm.cmp.bpm differ diff --git a/dpwm/db/dpwm.cmp.cdb b/dpwm/db/dpwm.cmp.cdb new file mode 100644 index 0000000..beafc11 Binary files /dev/null and b/dpwm/db/dpwm.cmp.cdb differ diff --git a/dpwm/db/dpwm.cmp.hdb b/dpwm/db/dpwm.cmp.hdb new file mode 100644 index 0000000..93cdb62 Binary files /dev/null and b/dpwm/db/dpwm.cmp.hdb differ diff --git a/dpwm/db/dpwm.cmp.idb b/dpwm/db/dpwm.cmp.idb new file mode 100644 index 0000000..31b80c7 Binary files /dev/null and b/dpwm/db/dpwm.cmp.idb differ diff --git a/dpwm/db/dpwm.cmp.logdb b/dpwm/db/dpwm.cmp.logdb new file mode 100644 index 0000000..a3d5b07 --- /dev/null +++ b/dpwm/db/dpwm.cmp.logdb @@ -0,0 +1,61 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;19;0;0;19;19;0;9;0;0;10;0;9;10;0;0;0;9;0;0;0;0;0;19;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,19;19;19;19;19;0;19;19;0;0;19;10;19;19;9;19;10;9;19;19;19;10;19;19;19;19;19;0;19;19, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,delay_out[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,delay_out[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,delay_out[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,delay_out[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,delay_out[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,delay_out[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,delay_out[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,delay_out[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,pwm_out,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,clk,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,dpid[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,dpid[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,dpid[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,dpid[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,dpid[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,dpid[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,dpid[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,dpid[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,rst_n,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21, diff --git a/dpwm/db/dpwm.cmp.rdb b/dpwm/db/dpwm.cmp.rdb new file mode 100644 index 0000000..292f7e2 Binary files /dev/null and b/dpwm/db/dpwm.cmp.rdb differ diff --git a/dpwm/db/dpwm.cmp_merge.kpt b/dpwm/db/dpwm.cmp_merge.kpt new file mode 100644 index 0000000..c4e09d6 Binary files /dev/null and b/dpwm/db/dpwm.cmp_merge.kpt differ diff --git a/dpwm/db/dpwm.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/dpwm/db/dpwm.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd new file mode 100644 index 0000000..ad05395 Binary files /dev/null and b/dpwm/db/dpwm.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd differ diff --git a/dpwm/db/dpwm.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd b/dpwm/db/dpwm.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd new file mode 100644 index 0000000..26a6227 Binary files /dev/null and b/dpwm/db/dpwm.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd differ diff --git a/dpwm/db/dpwm.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd b/dpwm/db/dpwm.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd new file mode 100644 index 0000000..d62e787 Binary files /dev/null and b/dpwm/db/dpwm.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd differ diff --git a/dpwm/db/dpwm.db_info b/dpwm/db/dpwm.db_info new file mode 100644 index 0000000..6ea6d03 --- /dev/null +++ b/dpwm/db/dpwm.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +Version_Index = 469919232 +Creation_Time = Mon Nov 05 19:55:20 2018 diff --git a/dpwm/db/dpwm.eco.cdb b/dpwm/db/dpwm.eco.cdb new file mode 100644 index 0000000..468d5e1 Binary files /dev/null and b/dpwm/db/dpwm.eco.cdb differ diff --git a/dpwm/db/dpwm.eda.qmsg b/dpwm/db/dpwm.eda.qmsg new file mode 100644 index 0000000..e0b8421 --- /dev/null +++ b/dpwm/db/dpwm.eda.qmsg @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541424079556 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541424079571 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 21:21:19 2018 " "Processing started: Mon Nov 05 21:21:19 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541424079571 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1541424079571 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off dpwm -c dpwm " "Command: quartus_eda --read_settings_files=off --write_settings_files=off dpwm -c dpwm" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1541424079571 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1541424080305 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_8_1200mv_85c_slow.vo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_8_1200mv_85c_slow.vo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541424080470 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_8_1200mv_0c_slow.vo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_8_1200mv_0c_slow.vo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541424080503 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_min_1200mv_0c_fast.vo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_min_1200mv_0c_fast.vo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541424080541 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm.vo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm.vo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541424080581 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_8_1200mv_85c_v_slow.sdo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_8_1200mv_85c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541424080604 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_8_1200mv_0c_v_slow.sdo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_8_1200mv_0c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541424080634 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_min_1200mv_0c_v_fast.sdo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_min_1200mv_0c_v_fast.sdo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541424080661 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_v.sdo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_v.sdo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541424080684 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4661 " "Peak virtual memory: 4661 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541424080732 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:21:20 2018 " "Processing ended: Mon Nov 05 21:21:20 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541424080732 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541424080732 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541424080732 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1541424080732 ""} diff --git a/dpwm/db/dpwm.fit.qmsg b/dpwm/db/dpwm.fit.qmsg new file mode 100644 index 0000000..30d5865 --- /dev/null +++ b/dpwm/db/dpwm.fit.qmsg @@ -0,0 +1,51 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1541424064271 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1541424064271 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "dpwm EP4CE10F17C8 " "Selected device EP4CE10F17C8 for design \"dpwm\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1541424064309 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1541424064406 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1541424064406 ""} +{ "Critical Warning" "WCUT_CUT_YGR_PLL_MODE_CHANGED" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1 No Compensation " "Changed operation mode of PLL \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1\" to No Compensation" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 50 -1 0 } } { "" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 51 14177 15141 0 0 "" 0 "" "" } } } } } 1 15090 "Changed operation mode of PLL \"%1!s!\" to %2!s!" 0 0 "Fitter" 0 -1 1541424064465 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1\" as Cyclone IV E PLL type" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 50 -1 0 } } { "" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 51 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1541424064474 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1541424064566 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Device EP4CE6F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1541424064780 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1541424064780 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1541424064780 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1541424064780 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 133 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541424064783 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 135 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541424064783 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 137 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541424064783 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 139 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541424064783 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 141 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541424064783 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1541424064783 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1541424064784 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "19 19 " "No exact pin location assignment(s) for 19 pins of 19 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1541424065099 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "dpwm.sdc " "Synopsys Design Constraints File file not found: 'dpwm.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1541424065441 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1541424065442 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1541424065444 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1541424065444 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1541424065444 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1541424065457 ""} } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 11 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 116 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1541424065457 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1541424065458 ""} } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 12 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 125 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1541424065458 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|locked " "Automatically promoted node my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|locked " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1541424065458 ""} } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 39 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 57 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1541424065458 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1541424065697 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1541424065697 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1541424065697 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1541424065698 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1541424065699 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1541424065699 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1541424065699 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1541424065699 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1541424065699 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1541424065700 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1541424065700 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "17 unused 2.5V 8 9 0 " "Number of I/O pins in group: 17 (unused VREF, 2.5V VCCIO, 8 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1541424065703 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1541424065703 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1541424065703 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 12 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541424065704 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 18 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541424065704 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 26 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541424065704 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 27 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541424065704 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 25 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541424065704 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 13 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541424065704 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 26 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541424065704 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 26 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541424065704 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1541424065704 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1541424065704 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541424065727 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1541424065732 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1541424066339 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541424066372 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1541424066383 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1541424067041 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541424067041 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1541424067270 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y12 X34_Y24 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24" { } { { "loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24"} { { 12 { 0 ""} 23 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1541424067754 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1541424067754 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1541424068044 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1541424068044 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541424068047 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.16 " "Total time spent on timing analysis during the Fitter is 0.16 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1541424068209 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1541424068216 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1541424068405 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1541424068405 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1541424068604 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541424069035 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/Code/FPGA/reserve/dpwm/output_files/dpwm.fit.smsg " "Generated suppressed messages file F:/Code/FPGA/reserve/dpwm/output_files/dpwm.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1541424069432 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5562 " "Peak virtual memory: 5562 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541424069962 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:21:09 2018 " "Processing ended: Mon Nov 05 21:21:09 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541424069962 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541424069962 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541424069962 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1541424069962 ""} diff --git a/dpwm/db/dpwm.hier_info b/dpwm/db/dpwm.hier_info new file mode 100644 index 0000000..c683619 --- /dev/null +++ b/dpwm/db/dpwm.hier_info @@ -0,0 +1,141 @@ +|dpwm_top +clk => clk.IN2 +rst_n => areset.IN1 +dpid[0] => dpid[0].IN1 +dpid[1] => dpid[1].IN1 +dpid[2] => dpid[2].IN1 +dpid[3] => dpid[3].IN1 +dpid[4] => dpid[4].IN1 +dpid[5] => dpid[5].IN1 +dpid[6] => dpid[6].IN1 +dpid[7] => dpid[7].IN1 +delay_out[0] << dpwm:dpwm.delay_out +delay_out[1] << dpwm:dpwm.delay_out +delay_out[2] << dpwm:dpwm.delay_out +delay_out[3] << dpwm:dpwm.delay_out +delay_out[4] << dpwm:dpwm.delay_out +delay_out[5] << dpwm:dpwm.delay_out +delay_out[6] << dpwm:dpwm.delay_out +delay_out[7] << dpwm:dpwm.delay_out +pwm_out << dpwm:dpwm.pwm_out + + +|dpwm_top|my_pll:my_pll +areset => areset.IN1 +inclk0 => sub_wire1[0].IN1 +c0 <= altpll:altpll_component.clk +locked <= altpll:altpll_component.locked + + +|dpwm_top|my_pll:my_pll|altpll:altpll_component +inclk[0] => my_pll_altpll1:auto_generated.inclk[0] +inclk[1] => my_pll_altpll1:auto_generated.inclk[1] +fbin => ~NO_FANOUT~ +pllena => ~NO_FANOUT~ +clkswitch => ~NO_FANOUT~ +areset => my_pll_altpll1:auto_generated.areset +pfdena => ~NO_FANOUT~ +clkena[0] => ~NO_FANOUT~ +clkena[1] => ~NO_FANOUT~ +clkena[2] => ~NO_FANOUT~ +clkena[3] => ~NO_FANOUT~ +clkena[4] => ~NO_FANOUT~ +clkena[5] => ~NO_FANOUT~ +extclkena[0] => ~NO_FANOUT~ +extclkena[1] => ~NO_FANOUT~ +extclkena[2] => ~NO_FANOUT~ +extclkena[3] => ~NO_FANOUT~ +scanclk => ~NO_FANOUT~ +scanclkena => ~NO_FANOUT~ +scanaclr => ~NO_FANOUT~ +scanread => ~NO_FANOUT~ +scanwrite => ~NO_FANOUT~ +scandata => ~NO_FANOUT~ +phasecounterselect[0] => ~NO_FANOUT~ +phasecounterselect[1] => ~NO_FANOUT~ +phasecounterselect[2] => ~NO_FANOUT~ +phasecounterselect[3] => ~NO_FANOUT~ +phaseupdown => ~NO_FANOUT~ +phasestep => ~NO_FANOUT~ +configupdate => ~NO_FANOUT~ +fbmimicbidir <> +clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE +clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE +clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE +clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE +clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE +extclk[0] <= +extclk[1] <= +extclk[2] <= +extclk[3] <= +clkbad[0] <= +clkbad[1] <= +enable1 <= +enable0 <= +activeclock <= +clkloss <= +locked <= my_pll_altpll1:auto_generated.locked +scandataout <= +scandone <= +sclkout0 <= +sclkout1 <= +phasedone <= +vcooverrange <= +vcounderrange <= +fbout <= +fref <= +icdrclk <= + + +|dpwm_top|my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated +areset => pll_lock_sync.ACLR +areset => pll1.ARESET +clk[0] <= pll1.CLK +clk[1] <= pll1.CLK1 +clk[2] <= pll1.CLK2 +clk[3] <= pll1.CLK3 +clk[4] <= pll1.CLK4 +inclk[0] => pll1.CLK +inclk[1] => pll1.CLK1 +locked <= locked.DB_MAX_OUTPUT_PORT_TYPE + + +|dpwm_top|dpwm:dpwm +clk => n_bit_high_syn.CLK +clk => bit_high_syn.CLK +clk => out_8bit[0].CLK +clk => out_8bit[1].CLK +clk => out_8bit[2].CLK +clk => out_8bit[3].CLK +clk => out_8bit[4].CLK +clk => out_8bit[5].CLK +clk => out_8bit[6].CLK +clk => out_8bit[7].CLK +clk_0 => ~NO_FANOUT~ +rst_n => out_8bit[0].ACLR +rst_n => out_8bit[1].ACLR +rst_n => out_8bit[2].ACLR +rst_n => out_8bit[3].ACLR +rst_n => out_8bit[4].ACLR +rst_n => out_8bit[5].ACLR +rst_n => out_8bit[6].ACLR +rst_n => out_8bit[7].ACLR +pwm_crl[0] => LessThan0.IN8 +pwm_crl[1] => LessThan0.IN7 +pwm_crl[2] => LessThan0.IN6 +pwm_crl[3] => LessThan0.IN5 +pwm_crl[4] => LessThan0.IN4 +pwm_crl[5] => LessThan0.IN3 +pwm_crl[6] => LessThan0.IN2 +pwm_crl[7] => LessThan0.IN1 +delay_out[0] <= delay_out[0].DB_MAX_OUTPUT_PORT_TYPE +delay_out[1] <= delay_out[1].DB_MAX_OUTPUT_PORT_TYPE +delay_out[2] <= delay_out[2].DB_MAX_OUTPUT_PORT_TYPE +delay_out[3] <= delay_out[3].DB_MAX_OUTPUT_PORT_TYPE +delay_out[4] <= delay_out[4].DB_MAX_OUTPUT_PORT_TYPE +delay_out[5] <= delay_out[5].DB_MAX_OUTPUT_PORT_TYPE +delay_out[6] <= delay_out[6].DB_MAX_OUTPUT_PORT_TYPE +delay_out[7] <= delay_out[7].DB_MAX_OUTPUT_PORT_TYPE +pwm_out <= comb.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/dpwm/db/dpwm.hif b/dpwm/db/dpwm.hif new file mode 100644 index 0000000..796a397 Binary files /dev/null and b/dpwm/db/dpwm.hif differ diff --git a/dpwm/db/dpwm.lpc.html b/dpwm/db/dpwm.lpc.html new file mode 100644 index 0000000..571b789 --- /dev/null +++ b/dpwm/db/dpwm.lpc.html @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
dpwm11010900000000
my_pll|altpll_component|auto_generated3000600000000
my_pll2000200000000
diff --git a/dpwm/db/dpwm.lpc.rdb b/dpwm/db/dpwm.lpc.rdb new file mode 100644 index 0000000..b41d4cf Binary files /dev/null and b/dpwm/db/dpwm.lpc.rdb differ diff --git a/dpwm/db/dpwm.lpc.txt b/dpwm/db/dpwm.lpc.txt new file mode 100644 index 0000000..06253b7 --- /dev/null +++ b/dpwm/db/dpwm.lpc.txt @@ -0,0 +1,9 @@ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; dpwm ; 11 ; 0 ; 1 ; 0 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; my_pll|altpll_component|auto_generated ; 3 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; my_pll ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/dpwm/db/dpwm.map.ammdb b/dpwm/db/dpwm.map.ammdb new file mode 100644 index 0000000..aff7571 Binary files /dev/null and b/dpwm/db/dpwm.map.ammdb differ diff --git a/dpwm/db/dpwm.map.bpm b/dpwm/db/dpwm.map.bpm new file mode 100644 index 0000000..3833d6c Binary files /dev/null and b/dpwm/db/dpwm.map.bpm differ diff --git a/dpwm/db/dpwm.map.cdb b/dpwm/db/dpwm.map.cdb new file mode 100644 index 0000000..5b9cf05 Binary files /dev/null and b/dpwm/db/dpwm.map.cdb differ diff --git a/dpwm/db/dpwm.map.hdb b/dpwm/db/dpwm.map.hdb new file mode 100644 index 0000000..7319066 Binary files /dev/null and b/dpwm/db/dpwm.map.hdb differ diff --git a/dpwm/db/dpwm.map.kpt b/dpwm/db/dpwm.map.kpt new file mode 100644 index 0000000..d5c4ce5 Binary files /dev/null and b/dpwm/db/dpwm.map.kpt differ diff --git a/dpwm/db/dpwm.map.logdb b/dpwm/db/dpwm.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/dpwm/db/dpwm.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/dpwm/db/dpwm.map.qmsg b/dpwm/db/dpwm.map.qmsg new file mode 100644 index 0000000..db24c14 --- /dev/null +++ b/dpwm/db/dpwm.map.qmsg @@ -0,0 +1,29 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541424042641 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541424042661 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 21:20:42 2018 " "Processing started: Mon Nov 05 21:20:42 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541424042661 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541424042661 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dpwm -c dpwm " "Command: quartus_map --read_settings_files=on --write_settings_files=off dpwm -c dpwm" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541424042662 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1541424043429 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1541424043429 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ip/my_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file ip/my_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_pll " "Found entity 1: my_pll" { } { { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541424059570 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541424059570 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/dpwm_top.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/dpwm_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm_top " "Found entity 1: dpwm_top" { } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541424059575 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541424059575 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testbench/dpwm_top_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file testbench/dpwm_top_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm_top_tb " "Found entity 1: dpwm_top_tb" { } { { "testbench/dpwm_top_tb.v" "" { Text "F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541424059580 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541424059580 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/dpwm.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/dpwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm " "Found entity 1: dpwm" { } { { "rtl/dpwm.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541424059584 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541424059584 ""} +{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "delay_out packed dpwm.v(30) " "Verilog HDL Port Declaration warning at dpwm.v(30): data type declaration for \"delay_out\" declares packed dimensions but the port declaration declaration does not" { } { { "rtl/dpwm.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 30 0 0 } } } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "Analysis & Synthesis" 0 -1 1541424059585 ""} +{ "Info" "IVRFX_HDL_SEE_DECLARATION" "delay_out dpwm.v(28) " "HDL info at dpwm.v(28): see declaration for object \"delay_out\"" { } { { "rtl/dpwm.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 28 0 0 } } } 0 10499 "HDL info at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541424059585 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "dpwm_top " "Elaborating entity \"dpwm_top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1541424059642 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_pll my_pll:my_pll " "Elaborating entity \"my_pll\" for hierarchy \"my_pll:my_pll\"" { } { { "rtl/dpwm_top.v" "my_pll" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 30 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541424059653 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll my_pll:my_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"my_pll:my_pll\|altpll:altpll_component\"" { } { { "ip/my_pll.v" "altpll_component" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 103 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541424059732 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "my_pll:my_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"my_pll:my_pll\|altpll:altpll_component\"" { } { { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 103 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541424059734 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "my_pll:my_pll\|altpll:altpll_component " "Instantiated megafunction \"my_pll:my_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Parameter \"clk0_multiply_by\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=my_pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=my_pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Parameter \"port_areset\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Parameter \"port_clk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541424059735 ""} } { { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 103 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1541424059735 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/my_pll_altpll1.v 1 1 " "Found 1 design units, including 1 entities, in source file db/my_pll_altpll1.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_pll_altpll1 " "Found entity 1: my_pll_altpll1" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541424059860 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541424059860 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_pll_altpll1 my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated " "Elaborating entity \"my_pll_altpll1\" for hierarchy \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541424059863 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpwm dpwm:dpwm " "Elaborating entity \"dpwm\" for hierarchy \"dpwm:dpwm\"" { } { { "rtl/dpwm_top.v" "dpwm" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541424059869 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "is_zero dpwm.v(37) " "Verilog HDL or VHDL warning at dpwm.v(37): object \"is_zero\" assigned a value but never read" { } { { "rtl/dpwm.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 37 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1541424059870 "|dpwm_top|dpwm:dpwm"} +{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "LCELL buffer " "Synthesized away the following LCELL buffer node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "de1 " "Synthesized away node \"de1\"" { } { } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424059885 ""} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "de2 " "Synthesized away node \"de2\"" { } { } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424059885 ""} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "de3 " "Synthesized away node \"de3\"" { } { } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424059885 ""} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "de3~ " "Synthesized away node \"de3~ \"" { } { } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424059885 ""} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "de2~ " "Synthesized away node \"de2~ \"" { } { } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424059885 ""} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "de1~ " "Synthesized away node \"de1~ \"" { } { } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424059885 ""} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "de0 " "Synthesized away node \"de0\"" { } { } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424059885 ""} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1541424059885 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1541424059885 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "delay_out\[4\] GND " "Pin \"delay_out\[4\]\" is stuck at GND" { } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1541424060588 "|dpwm_top|delay_out[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "delay_out\[5\] GND " "Pin \"delay_out\[5\]\" is stuck at GND" { } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1541424060588 "|dpwm_top|delay_out[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "delay_out\[6\] GND " "Pin \"delay_out\[6\]\" is stuck at GND" { } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1541424060588 "|dpwm_top|delay_out[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "delay_out\[7\] GND " "Pin \"delay_out\[7\]\" is stuck at GND" { } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1541424060588 "|dpwm_top|delay_out[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1541424060588 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1541424060702 ""} +{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|de7 " "Logic cell \"dpwm:dpwm\|de7\"" { } { { "rtl/dpwm.v" "de7" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 42 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424061296 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|de6 " "Logic cell \"dpwm:dpwm\|de6\"" { } { { "rtl/dpwm.v" "de6" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 42 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424061296 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|de5 " "Logic cell \"dpwm:dpwm\|de5\"" { } { { "rtl/dpwm.v" "de5" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 42 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424061296 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|de4 " "Logic cell \"dpwm:dpwm\|de4\"" { } { { "rtl/dpwm.v" "de4" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 42 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424061296 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|delay0 " "Logic cell \"dpwm:dpwm\|delay0\"" { } { { "rtl/dpwm.v" "delay0" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 46 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424061296 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|delay1 " "Logic cell \"dpwm:dpwm\|delay1\"" { } { { "rtl/dpwm.v" "delay1" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 47 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424061296 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|delay2 " "Logic cell \"dpwm:dpwm\|delay2\"" { } { { "rtl/dpwm.v" "delay2" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 48 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424061296 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|delay3 " "Logic cell \"dpwm:dpwm\|delay3\"" { } { { "rtl/dpwm.v" "delay3" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 49 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541424061296 ""} } { } 0 17016 "Found the following redundant logic cells in design" 0 0 "Analysis & Synthesis" 0 -1 1541424061296 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1541424061611 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541424061611 ""} +{ "Warning" "WCUT_PLL_COMPENSATE_CLOCK_NOT_CONNECTED" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1 compensate_clock clock0 CLK\[0\] " "PLL \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1\" has parameter compensate_clock set to clock0 but port CLK\[0\] is not connected" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 50 -1 0 } } { "altpll.tdf" "" { Text "d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 103 0 0 } } { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 30 0 0 } } } 0 15897 "PLL \"%1!s!\" has parameter %2!s! set to %3!s! but port %4!s! is not connected" 0 0 "Analysis & Synthesis" 0 -1 1541424061687 ""} +{ "Warning" "WCUT_PLL_MULT_DIV_SPECIFIED_CLOCK_NOT_CONNECTED" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1 CLK\[0\] clk0_multiply_by clk0_divide_by " "PLL \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1\" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK\[0\] is not connected" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 50 -1 0 } } { "altpll.tdf" "" { Text "d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 103 0 0 } } { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 30 0 0 } } } 0 15899 "PLL \"%1!s!\" has parameters %3!s! and %4!s! specified but port %2!s! is not connected" 0 0 "Analysis & Synthesis" 0 -1 1541424061688 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "56 " "Implemented 56 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1541424061716 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1541424061716 ""} { "Info" "ICUT_CUT_TM_LCELLS" "36 " "Implemented 36 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1541424061716 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1541424061716 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1541424061716 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4790 " "Peak virtual memory: 4790 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541424061740 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:21:01 2018 " "Processing ended: Mon Nov 05 21:21:01 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541424061740 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541424061740 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541424061740 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1541424061740 ""} diff --git a/dpwm/db/dpwm.map.rdb b/dpwm/db/dpwm.map.rdb new file mode 100644 index 0000000..c74d2e0 Binary files /dev/null and b/dpwm/db/dpwm.map.rdb differ diff --git a/dpwm/db/dpwm.map_bb.cdb b/dpwm/db/dpwm.map_bb.cdb new file mode 100644 index 0000000..f0ffba8 Binary files /dev/null and b/dpwm/db/dpwm.map_bb.cdb differ diff --git a/dpwm/db/dpwm.map_bb.hdb b/dpwm/db/dpwm.map_bb.hdb new file mode 100644 index 0000000..69ceb32 Binary files /dev/null and b/dpwm/db/dpwm.map_bb.hdb differ diff --git a/dpwm/db/dpwm.map_bb.logdb b/dpwm/db/dpwm.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/dpwm/db/dpwm.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/dpwm/db/dpwm.npp.qmsg b/dpwm/db/dpwm.npp.qmsg new file mode 100644 index 0000000..1f682cb --- /dev/null +++ b/dpwm/db/dpwm.npp.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541424329227 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541424329245 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 21:25:29 2018 " "Processing started: Mon Nov 05 21:25:29 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541424329245 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1541424329245 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp dpwm -c dpwm --netlist_type=sgate " "Command: quartus_npp dpwm -c dpwm --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1541424329245 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1541424329636 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4565 " "Peak virtual memory: 4565 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541424329649 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:25:29 2018 " "Processing ended: Mon Nov 05 21:25:29 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541424329649 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541424329649 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541424329649 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1541424329649 ""} diff --git a/dpwm/db/dpwm.pre_map.hdb b/dpwm/db/dpwm.pre_map.hdb new file mode 100644 index 0000000..f93f8d0 Binary files /dev/null and b/dpwm/db/dpwm.pre_map.hdb differ diff --git a/dpwm/db/dpwm.root_partition.map.reg_db.cdb b/dpwm/db/dpwm.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..f6f4b46 Binary files /dev/null and b/dpwm/db/dpwm.root_partition.map.reg_db.cdb differ diff --git a/dpwm/db/dpwm.routing.rdb b/dpwm/db/dpwm.routing.rdb new file mode 100644 index 0000000..1293733 Binary files /dev/null and b/dpwm/db/dpwm.routing.rdb differ diff --git a/dpwm/db/dpwm.rtlv.hdb b/dpwm/db/dpwm.rtlv.hdb new file mode 100644 index 0000000..cc5791d Binary files /dev/null and b/dpwm/db/dpwm.rtlv.hdb differ diff --git a/dpwm/db/dpwm.rtlv_sg.cdb b/dpwm/db/dpwm.rtlv_sg.cdb new file mode 100644 index 0000000..42efbcc Binary files /dev/null and b/dpwm/db/dpwm.rtlv_sg.cdb differ diff --git a/dpwm/db/dpwm.rtlv_sg_swap.cdb b/dpwm/db/dpwm.rtlv_sg_swap.cdb new file mode 100644 index 0000000..70952dc Binary files /dev/null and b/dpwm/db/dpwm.rtlv_sg_swap.cdb differ diff --git a/dpwm/db/dpwm.sgate.nvd b/dpwm/db/dpwm.sgate.nvd new file mode 100644 index 0000000..2589e05 Binary files /dev/null and b/dpwm/db/dpwm.sgate.nvd differ diff --git a/dpwm/db/dpwm.sgate_sm.nvd b/dpwm/db/dpwm.sgate_sm.nvd new file mode 100644 index 0000000..fc7163e Binary files /dev/null and b/dpwm/db/dpwm.sgate_sm.nvd differ diff --git a/dpwm/db/dpwm.sld_design_entry.sci b/dpwm/db/dpwm.sld_design_entry.sci new file mode 100644 index 0000000..f47c39c Binary files /dev/null and b/dpwm/db/dpwm.sld_design_entry.sci differ diff --git a/dpwm/db/dpwm.sld_design_entry_dsc.sci b/dpwm/db/dpwm.sld_design_entry_dsc.sci new file mode 100644 index 0000000..f47c39c Binary files /dev/null and b/dpwm/db/dpwm.sld_design_entry_dsc.sci differ diff --git a/dpwm/db/dpwm.smart_action.txt b/dpwm/db/dpwm.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/dpwm/db/dpwm.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/dpwm/db/dpwm.sta.qmsg b/dpwm/db/dpwm.sta.qmsg new file mode 100644 index 0000000..9f396ac --- /dev/null +++ b/dpwm/db/dpwm.sta.qmsg @@ -0,0 +1,42 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541424075683 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541424075701 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 21:21:15 2018 " "Processing started: Mon Nov 05 21:21:15 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541424075701 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1541424075701 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta dpwm -c dpwm " "Command: quartus_sta dpwm -c dpwm" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1541424075701 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #2" { } { } 0 0 "qsta_default_script.tcl version: #2" 0 0 "Timing Analyzer" 0 0 1541424075944 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1541424076179 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1541424076179 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424076258 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424076258 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "dpwm.sdc " "Synopsys Design Constraints File file not found: 'dpwm.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1541424076495 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424076495 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1541424076496 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541424076496 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1541424076497 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541424076497 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1541424076498 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1541424076510 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1541424076522 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1541424076522 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.399 " "Worst-case setup slack is -1.399" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424076525 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424076525 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.399 -8.279 clk " " -1.399 -8.279 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424076525 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424076525 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.465 " "Worst-case hold slack is 0.465" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424076529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424076529 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.465 0.000 clk " " 0.465 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424076529 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424076529 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541424076533 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541424076539 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424076542 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424076542 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -17.870 clk " " -3.000 -17.870 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424076542 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424076542 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1541424076559 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1541424076587 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1541424076923 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541424076995 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1541424077001 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1541424077001 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.191 " "Worst-case setup slack is -1.191" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077005 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077005 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.191 -6.874 clk " " -1.191 -6.874 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077005 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424077005 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.417 " "Worst-case hold slack is 0.417" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077009 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.417 0.000 clk " " 0.417 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077009 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424077009 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541424077013 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541424077017 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -17.870 clk " " -3.000 -17.870 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077024 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424077024 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1541424077041 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541424077230 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.003 " "Worst-case setup slack is 0.003" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077236 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077236 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.003 0.000 clk " " 0.003 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077236 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424077236 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 clk " " 0.193 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077241 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424077241 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541424077244 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541424077248 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1541424077248 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1541424077248 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077252 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -13.675 clk " " -3.000 -13.675 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541424077252 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541424077252 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1541424077832 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1541424077832 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4776 " "Peak virtual memory: 4776 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541424077893 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:21:17 2018 " "Processing ended: Mon Nov 05 21:21:17 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541424077893 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541424077893 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541424077893 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1541424077893 ""} diff --git a/dpwm/db/dpwm.sta.rdb b/dpwm/db/dpwm.sta.rdb new file mode 100644 index 0000000..6e5182a Binary files /dev/null and b/dpwm/db/dpwm.sta.rdb differ diff --git a/dpwm/db/dpwm.sta_cmp.8_slow_1200mv_85c.tdb b/dpwm/db/dpwm.sta_cmp.8_slow_1200mv_85c.tdb new file mode 100644 index 0000000..b08a4da Binary files /dev/null and b/dpwm/db/dpwm.sta_cmp.8_slow_1200mv_85c.tdb differ diff --git a/dpwm/db/dpwm.tis_db_list.ddb b/dpwm/db/dpwm.tis_db_list.ddb new file mode 100644 index 0000000..ade9cdb Binary files /dev/null and b/dpwm/db/dpwm.tis_db_list.ddb differ diff --git a/dpwm/db/dpwm.tiscmp.fast_1200mv_0c.ddb b/dpwm/db/dpwm.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..fc03e87 Binary files /dev/null and b/dpwm/db/dpwm.tiscmp.fast_1200mv_0c.ddb differ diff --git a/dpwm/db/dpwm.tiscmp.fastest_slow_1200mv_0c.ddb b/dpwm/db/dpwm.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..63d9e0b Binary files /dev/null and b/dpwm/db/dpwm.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/dpwm/db/dpwm.tiscmp.fastest_slow_1200mv_85c.ddb b/dpwm/db/dpwm.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..f8fa6fd Binary files /dev/null and b/dpwm/db/dpwm.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/dpwm/db/dpwm.tiscmp.slow_1200mv_0c.ddb b/dpwm/db/dpwm.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..ace7f34 Binary files /dev/null and b/dpwm/db/dpwm.tiscmp.slow_1200mv_0c.ddb differ diff --git a/dpwm/db/dpwm.tiscmp.slow_1200mv_85c.ddb b/dpwm/db/dpwm.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..cca63f1 Binary files /dev/null and b/dpwm/db/dpwm.tiscmp.slow_1200mv_85c.ddb differ diff --git a/dpwm/db/dpwm.vpr.ammdb b/dpwm/db/dpwm.vpr.ammdb new file mode 100644 index 0000000..8074164 Binary files /dev/null and b/dpwm/db/dpwm.vpr.ammdb differ diff --git a/dpwm/db/dpwm_partition_pins.json b/dpwm/db/dpwm_partition_pins.json new file mode 100644 index 0000000..1613289 --- /dev/null +++ b/dpwm/db/dpwm_partition_pins.json @@ -0,0 +1,69 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "delay_out[0]", + "strict" : false + }, + { + "name" : "delay_out[1]", + "strict" : false + }, + { + "name" : "delay_out[2]", + "strict" : false + }, + { + "name" : "delay_out[3]", + "strict" : false + }, + { + "name" : "pwm_out", + "strict" : false + }, + { + "name" : "clk", + "strict" : false + }, + { + "name" : "dpid[7]", + "strict" : false + }, + { + "name" : "dpid[6]", + "strict" : false + }, + { + "name" : "dpid[5]", + "strict" : false + }, + { + "name" : "dpid[4]", + "strict" : false + }, + { + "name" : "dpid[3]", + "strict" : false + }, + { + "name" : "dpid[2]", + "strict" : false + }, + { + "name" : "dpid[1]", + "strict" : false + }, + { + "name" : "dpid[0]", + "strict" : false + }, + { + "name" : "rst_n", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/dpwm/db/my_pll_altpll.v b/dpwm/db/my_pll_altpll.v new file mode 100644 index 0000000..7ef948e --- /dev/null +++ b/dpwm/db/my_pll_altpll.v @@ -0,0 +1,113 @@ +//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=3 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=3 clk1_phase_shift="3333" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=my_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +//VERSION_BEGIN 18.0 cbx_altclkbuf 2018:04:24:18:04:18:SJ cbx_altiobuf_bidir 2018:04:24:18:04:18:SJ cbx_altiobuf_in 2018:04:24:18:04:18:SJ cbx_altiobuf_out 2018:04:24:18:04:18:SJ cbx_altpll 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_counter 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END +//CBXI_INSTANCE_NAME="my_pll_altpll_altpll_component" +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + + +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + + +//synthesis_resources = cycloneive_pll 1 reg 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *) +module my_pll_altpll + ( + areset, + clk, + inclk, + locked) /* synthesis synthesis_clearbox=1 */; + input areset; + output [4:0] clk; + input [1:0] inclk; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; + tri0 [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + reg pll_lock_sync; + wire [4:0] wire_pll1_clk; + wire wire_pll1_fbout; + wire wire_pll1_locked; + + // synopsys translate_off + initial + pll_lock_sync = 0; + // synopsys translate_on + always @ ( posedge wire_pll1_locked or posedge areset) + if (areset == 1'b1) pll_lock_sync <= 1'b0; + else pll_lock_sync <= 1'b1; + cycloneive_pll pll1 + ( + .activeclock(), + .areset(areset), + .clk(wire_pll1_clk), + .clkbad(), + .fbin(wire_pll1_fbout), + .fbout(wire_pll1_fbout), + .inclk(inclk), + .locked(wire_pll1_locked), + .phasedone(), + .scandataout(), + .scandone(), + .vcooverrange(), + .vcounderrange() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .clkswitch(1'b0), + .configupdate(1'b0), + .pfdena(1'b1), + .phasecounterselect({3{1'b0}}), + .phasestep(1'b0), + .phaseupdown(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + defparam + pll1.bandwidth_type = "auto", + pll1.clk0_divide_by = 1, + pll1.clk0_duty_cycle = 50, + pll1.clk0_multiply_by = 3, + pll1.clk0_phase_shift = "0", + pll1.clk1_divide_by = 1, + pll1.clk1_duty_cycle = 50, + pll1.clk1_multiply_by = 3, + pll1.clk1_phase_shift = "3333", + pll1.compensate_clock = "clk0", + pll1.inclk0_input_frequency = 20000, + pll1.operation_mode = "normal", + pll1.pll_type = "auto", + pll1.self_reset_on_loss_lock = "off", + pll1.lpm_type = "cycloneive_pll"; + assign + clk = {wire_pll1_clk[4:0]}, + locked = (wire_pll1_locked & pll_lock_sync); +endmodule //my_pll_altpll +//VALID FILE diff --git a/dpwm/db/my_pll_altpll1.v b/dpwm/db/my_pll_altpll1.v new file mode 100644 index 0000000..8d7a102 --- /dev/null +++ b/dpwm/db/my_pll_altpll1.v @@ -0,0 +1,109 @@ +//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=5 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=my_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +//VERSION_BEGIN 18.0 cbx_altclkbuf 2018:04:24:18:04:18:SJ cbx_altiobuf_bidir 2018:04:24:18:04:18:SJ cbx_altiobuf_in 2018:04:24:18:04:18:SJ cbx_altiobuf_out 2018:04:24:18:04:18:SJ cbx_altpll 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_counter 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END +//CBXI_INSTANCE_NAME="dpwm_top_my_pll_my_pll_altpll_altpll_component" +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + + +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + + +//synthesis_resources = cycloneive_pll 1 reg 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *) +module my_pll_altpll1 + ( + areset, + clk, + inclk, + locked) /* synthesis synthesis_clearbox=1 */; + input areset; + output [4:0] clk; + input [1:0] inclk; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; + tri0 [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + reg pll_lock_sync; + wire [4:0] wire_pll1_clk; + wire wire_pll1_fbout; + wire wire_pll1_locked; + + // synopsys translate_off + initial + pll_lock_sync = 0; + // synopsys translate_on + always @ ( posedge wire_pll1_locked or posedge areset) + if (areset == 1'b1) pll_lock_sync <= 1'b0; + else pll_lock_sync <= 1'b1; + cycloneive_pll pll1 + ( + .activeclock(), + .areset(areset), + .clk(wire_pll1_clk), + .clkbad(), + .fbin(wire_pll1_fbout), + .fbout(wire_pll1_fbout), + .inclk(inclk), + .locked(wire_pll1_locked), + .phasedone(), + .scandataout(), + .scandone(), + .vcooverrange(), + .vcounderrange() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .clkswitch(1'b0), + .configupdate(1'b0), + .pfdena(1'b1), + .phasecounterselect({3{1'b0}}), + .phasestep(1'b0), + .phaseupdown(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + defparam + pll1.bandwidth_type = "auto", + pll1.clk0_divide_by = 1, + pll1.clk0_duty_cycle = 50, + pll1.clk0_multiply_by = 5, + pll1.clk0_phase_shift = "0", + pll1.compensate_clock = "clk0", + pll1.inclk0_input_frequency = 20000, + pll1.operation_mode = "normal", + pll1.pll_type = "auto", + pll1.self_reset_on_loss_lock = "off", + pll1.lpm_type = "cycloneive_pll"; + assign + clk = {wire_pll1_clk[4:0]}, + locked = (wire_pll1_locked & pll_lock_sync); +endmodule //my_pll_altpll1 +//VALID FILE diff --git a/dpwm/db/prev_cmp_dpwm.qmsg b/dpwm/db/prev_cmp_dpwm.qmsg new file mode 100644 index 0000000..5fe5829 --- /dev/null +++ b/dpwm/db/prev_cmp_dpwm.qmsg @@ -0,0 +1,153 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541423698949 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541423698965 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 21:14:58 2018 " "Processing started: Mon Nov 05 21:14:58 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541423698965 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541423698965 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dpwm -c dpwm " "Command: quartus_map --read_settings_files=on --write_settings_files=off dpwm -c dpwm" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541423698965 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1541423699796 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1541423699796 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ip/my_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file ip/my_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_pll " "Found entity 1: my_pll" { } { { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541423717472 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541423717472 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/dpwm_top.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/dpwm_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm_top " "Found entity 1: dpwm_top" { } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541423717475 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541423717475 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testbench/dpwm_top_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file testbench/dpwm_top_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm_top_tb " "Found entity 1: dpwm_top_tb" { } { { "testbench/dpwm_top_tb.v" "" { Text "F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541423717478 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541423717478 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/dpwm.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/dpwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm " "Found entity 1: dpwm" { } { { "rtl/dpwm.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541423717485 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541423717485 ""} +{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "delay_out packed dpwm.v(30) " "Verilog HDL Port Declaration warning at dpwm.v(30): data type declaration for \"delay_out\" declares packed dimensions but the port declaration declaration does not" { } { { "rtl/dpwm.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 30 0 0 } } } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "Analysis & Synthesis" 0 -1 1541423717486 ""} +{ "Info" "IVRFX_HDL_SEE_DECLARATION" "delay_out dpwm.v(28) " "HDL info at dpwm.v(28): see declaration for object \"delay_out\"" { } { { "rtl/dpwm.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 28 0 0 } } } 0 10499 "HDL info at %2!s!: see declaration for object \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541423717487 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "dpwm_top " "Elaborating entity \"dpwm_top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1541423717550 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_pll my_pll:my_pll " "Elaborating entity \"my_pll\" for hierarchy \"my_pll:my_pll\"" { } { { "rtl/dpwm_top.v" "my_pll" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 30 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541423717561 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll my_pll:my_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"my_pll:my_pll\|altpll:altpll_component\"" { } { { "ip/my_pll.v" "altpll_component" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 103 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541423717632 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "my_pll:my_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"my_pll:my_pll\|altpll:altpll_component\"" { } { { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 103 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541423717638 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "my_pll:my_pll\|altpll:altpll_component " "Instantiated megafunction \"my_pll:my_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 5 " "Parameter \"clk0_multiply_by\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=my_pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=my_pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Parameter \"port_areset\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Parameter \"port_clk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541423717638 ""} } { { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 103 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1541423717638 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/my_pll_altpll1.v 1 1 " "Found 1 design units, including 1 entities, in source file db/my_pll_altpll1.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_pll_altpll1 " "Found entity 1: my_pll_altpll1" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541423717723 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541423717723 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_pll_altpll1 my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated " "Elaborating entity \"my_pll_altpll1\" for hierarchy \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541423717724 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpwm dpwm:dpwm " "Elaborating entity \"dpwm\" for hierarchy \"dpwm:dpwm\"" { } { { "rtl/dpwm_top.v" "dpwm" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 39 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541423717729 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "is_zero dpwm.v(37) " "Verilog HDL or VHDL warning at dpwm.v(37): object \"is_zero\" assigned a value but never read" { } { { "rtl/dpwm.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 37 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1541423717731 "|dpwm_top|dpwm:dpwm"} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1541423718377 ""} +{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|delay1 " "Logic cell \"dpwm:dpwm\|delay1\"" { } { { "rtl/dpwm.v" "delay1" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 47 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541423718877 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|delay2 " "Logic cell \"dpwm:dpwm\|delay2\"" { } { { "rtl/dpwm.v" "delay2" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 48 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541423718877 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|delay3 " "Logic cell \"dpwm:dpwm\|delay3\"" { } { { "rtl/dpwm.v" "delay3" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 49 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541423718877 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|delay4 " "Logic cell \"dpwm:dpwm\|delay4\"" { } { { "rtl/dpwm.v" "delay4" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 50 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541423718877 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|delay5 " "Logic cell \"dpwm:dpwm\|delay5\"" { } { { "rtl/dpwm.v" "delay5" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 51 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541423718877 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|delay6 " "Logic cell \"dpwm:dpwm\|delay6\"" { } { { "rtl/dpwm.v" "delay6" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 52 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541423718877 ""} { "Info" "ISCL_SCL_CELL_NAME" "dpwm:dpwm\|delay7 " "Logic cell \"dpwm:dpwm\|delay7\"" { } { { "rtl/dpwm.v" "delay7" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v" 53 -1 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1541423718877 ""} } { } 0 17016 "Found the following redundant logic cells in design" 0 0 "Analysis & Synthesis" 0 -1 1541423718877 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1541423719033 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541423719033 ""} +{ "Warning" "WCUT_PLL_COMPENSATE_CLOCK_NOT_CONNECTED" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1 compensate_clock clock0 CLK\[0\] " "PLL \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1\" has parameter compensate_clock set to clock0 but port CLK\[0\] is not connected" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 50 -1 0 } } { "altpll.tdf" "" { Text "d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 103 0 0 } } { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 30 0 0 } } } 0 15897 "PLL \"%1!s!\" has parameter %2!s! set to %3!s! but port %4!s! is not connected" 0 0 "Analysis & Synthesis" 0 -1 1541423719074 ""} +{ "Warning" "WCUT_PLL_MULT_DIV_SPECIFIED_CLOCK_NOT_CONNECTED" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1 CLK\[0\] clk0_multiply_by clk0_divide_by " "PLL \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1\" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK\[0\] is not connected" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 50 -1 0 } } { "altpll.tdf" "" { Text "d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm/ip/my_pll.v" 103 0 0 } } { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 30 0 0 } } } 0 15899 "PLL \"%1!s!\" has parameters %3!s! and %4!s! specified but port %2!s! is not connected" 0 0 "Analysis & Synthesis" 0 -1 1541423719074 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "56 " "Implemented 56 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1541423719099 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1541423719099 ""} { "Info" "ICUT_CUT_TM_LCELLS" "36 " "Implemented 36 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1541423719099 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1541423719099 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1541423719099 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4789 " "Peak virtual memory: 4789 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541423719120 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:15:19 2018 " "Processing ended: Mon Nov 05 21:15:19 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541423719120 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Elapsed time: 00:00:21" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541423719120 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:46 " "Total CPU time (on all processors): 00:00:46" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541423719120 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1541423719120 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1541423721401 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541423721418 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 21:15:20 2018 " "Processing started: Mon Nov 05 21:15:20 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541423721418 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1541423721418 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off dpwm -c dpwm " "Command: quartus_fit --read_settings_files=off --write_settings_files=off dpwm -c dpwm" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1541423721419 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1541423721649 ""} +{ "Info" "0" "" "Project = dpwm" { } { } 0 0 "Project = dpwm" 0 0 "Fitter" 0 0 1541423721650 ""} +{ "Info" "0" "" "Revision = dpwm" { } { } 0 0 "Revision = dpwm" 0 0 "Fitter" 0 0 1541423721650 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1541423721750 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1541423721751 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "dpwm EP4CE10F17C8 " "Selected device EP4CE10F17C8 for design \"dpwm\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1541423721796 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1541423721887 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1541423721887 ""} +{ "Critical Warning" "WCUT_CUT_YGR_PLL_MODE_CHANGED" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1 No Compensation " "Changed operation mode of PLL \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1\" to No Compensation" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 50 -1 0 } } { "" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 51 14177 15141 0 0 "" 0 "" "" } } } } } 1 15090 "Changed operation mode of PLL \"%1!s!\" to %2!s!" 0 0 "Fitter" 0 -1 1541423721948 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1\" as Cyclone IV E PLL type" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 50 -1 0 } } { "" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 51 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1541423721956 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1541423722051 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Device EP4CE6F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1541423722248 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1541423722248 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1541423722248 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1541423722248 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 132 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541423722250 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 134 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541423722250 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 136 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541423722250 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 138 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541423722250 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 140 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541423722250 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1541423722250 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1541423722251 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "19 19 " "No exact pin location assignment(s) for 19 pins of 19 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1541423722587 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "dpwm.sdc " "Synopsys Design Constraints File file not found: 'dpwm.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1541423722904 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1541423722904 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1541423722906 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1541423722906 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1541423722906 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1541423722923 ""} } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 11 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 123 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1541423722923 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1541423722923 ""} } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v" 12 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1541423722923 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|locked " "Automatically promoted node my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|locked " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1541423722923 ""} } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v" 39 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 0 { 0 ""} 0 57 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1541423722923 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1541423723150 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1541423723150 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1541423723150 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1541423723151 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1541423723151 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1541423723151 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1541423723151 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1541423723151 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1541423723151 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1541423723152 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1541423723152 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "17 unused 2.5V 8 9 0 " "Number of I/O pins in group: 17 (unused VREF, 2.5V VCCIO, 8 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1541423723153 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1541423723153 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1541423723153 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 12 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541423723154 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 18 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541423723154 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 26 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541423723154 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 27 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541423723154 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 25 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541423723154 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 13 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541423723154 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 26 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541423723154 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 26 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541423723154 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1541423723154 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1541423723154 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541423723177 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1541423723185 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1541423723765 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541423723800 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1541423723813 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1541423724213 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541423724213 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1541423724451 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y12 X34_Y24 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24" { } { { "loc" "" { Generic "F:/Code/FPGA/reserve/dpwm/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24"} { { 12 { 0 ""} 23 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1541423724949 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1541423724949 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1541423725218 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1541423725218 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541423725223 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.14 " "Total time spent on timing analysis during the Fitter is 0.14 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1541423725370 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1541423725378 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1541423725534 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1541423725534 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1541423725709 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541423726155 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/Code/FPGA/reserve/dpwm/output_files/dpwm.fit.smsg " "Generated suppressed messages file F:/Code/FPGA/reserve/dpwm/output_files/dpwm.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1541423726525 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5564 " "Peak virtual memory: 5564 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541423726935 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:15:26 2018 " "Processing ended: Mon Nov 05 21:15:26 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541423726935 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541423726935 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541423726935 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1541423726934 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1541423728684 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541423728701 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 21:15:28 2018 " "Processing started: Mon Nov 05 21:15:28 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541423728701 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1541423728701 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off dpwm -c dpwm " "Command: quartus_asm --read_settings_files=off --write_settings_files=off dpwm -c dpwm" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1541423728702 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1541423729249 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1541423729651 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1541423729673 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4693 " "Peak virtual memory: 4693 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541423729854 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:15:29 2018 " "Processing ended: Mon Nov 05 21:15:29 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541423729854 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541423729854 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541423729854 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1541423729854 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1541423730631 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1541423731963 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541423731977 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 21:15:31 2018 " "Processing started: Mon Nov 05 21:15:31 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541423731977 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1541423731977 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta dpwm -c dpwm " "Command: quartus_sta dpwm -c dpwm" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1541423731977 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #2" { } { } 0 0 "qsta_default_script.tcl version: #2" 0 0 "Timing Analyzer" 0 0 1541423732210 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1541423732470 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1541423732470 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423732552 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423732552 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "dpwm.sdc " "Synopsys Design Constraints File file not found: 'dpwm.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1541423732795 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423732795 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1541423732796 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541423732796 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1541423732799 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541423732799 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1541423732800 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1541423732816 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1541423732831 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1541423732831 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.399 " "Worst-case setup slack is -1.399" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423732834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423732834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.399 -8.278 clk " " -1.399 -8.278 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423732834 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423732834 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.465 " "Worst-case hold slack is 0.465" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423732839 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423732839 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.465 0.000 clk " " 0.465 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423732839 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423732839 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541423732846 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541423732852 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423732854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423732854 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -17.870 clk " " -3.000 -17.870 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423732854 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423732854 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1541423732874 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1541423732903 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1541423733279 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541423733349 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1541423733355 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1541423733355 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.192 " "Worst-case setup slack is -1.192" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733360 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.192 -6.884 clk " " -1.192 -6.884 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733360 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423733360 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.416 " "Worst-case hold slack is 0.416" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733365 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733365 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.416 0.000 clk " " 0.416 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733365 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423733365 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541423733369 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541423733373 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733377 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -17.870 clk " " -3.000 -17.870 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733377 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423733377 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1541423733397 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541423733540 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.003 " "Worst-case setup slack is 0.003" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733547 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733547 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.003 0.000 clk " " 0.003 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733547 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423733547 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.193 " "Worst-case hold slack is 0.193" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 clk " " 0.193 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733551 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423733551 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541423733554 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541423733558 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1541423733559 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1541423733559 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733563 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733563 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -13.662 clk " " -3.000 -13.662 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541423733563 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541423733563 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1541423734045 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1541423734045 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4773 " "Peak virtual memory: 4773 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541423734099 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:15:34 2018 " "Processing ended: Mon Nov 05 21:15:34 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541423734099 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541423734099 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541423734099 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1541423734099 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1541423735720 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541423735736 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 21:15:35 2018 " "Processing started: Mon Nov 05 21:15:35 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541423735736 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1541423735736 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off dpwm -c dpwm " "Command: quartus_eda --read_settings_files=off --write_settings_files=off dpwm -c dpwm" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1541423735736 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1541423736528 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_8_1200mv_85c_slow.vo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_8_1200mv_85c_slow.vo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541423736687 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_8_1200mv_0c_slow.vo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_8_1200mv_0c_slow.vo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541423736728 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_min_1200mv_0c_fast.vo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_min_1200mv_0c_fast.vo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541423736776 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm.vo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm.vo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541423736806 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_8_1200mv_85c_v_slow.sdo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_8_1200mv_85c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541423736836 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_8_1200mv_0c_v_slow.sdo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_8_1200mv_0c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541423736860 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_min_1200mv_0c_v_fast.sdo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_min_1200mv_0c_v_fast.sdo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541423736883 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_v.sdo F:/Code/FPGA/reserve/dpwm/simulation/modelsim/ simulation " "Generated file dpwm_v.sdo in folder \"F:/Code/FPGA/reserve/dpwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541423736916 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4660 " "Peak virtual memory: 4660 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541423736964 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:15:36 2018 " "Processing ended: Mon Nov 05 21:15:36 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541423736964 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541423736964 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541423736964 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1541423736964 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 17 s " "Quartus Prime Full Compilation was successful. 0 errors, 17 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1541423737724 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541423827325 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541423827342 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 05 21:17:07 2018 " "Processing started: Mon Nov 05 21:17:07 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541423827342 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1541423827342 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp dpwm -c dpwm --netlist_type=sgate " "Command: quartus_npp dpwm -c dpwm --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1541423827342 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1541423827768 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4563 " "Peak virtual memory: 4563 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541423827783 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 05 21:17:07 2018 " "Processing ended: Mon Nov 05 21:17:07 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541423827783 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541423827783 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541423827783 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1541423827783 ""} diff --git a/dpwm/dpwm.ipregen.rpt b/dpwm/dpwm.ipregen.rpt new file mode 100644 index 0000000..b9b2f52 --- /dev/null +++ b/dpwm/dpwm.ipregen.rpt @@ -0,0 +1,55 @@ +IP Upgrade report for dpwm +Mon Nov 05 20:53:38 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. IP Upgrade Summary + 3. IP Upgrade Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------+ +; IP Upgrade Summary ; ++------------------------------+-------------------------------------------------+ +; IP Components Upgrade Status ; Failed - Mon Nov 05 20:53:38 2018 ; +; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ; +; Revision Name ; dpwm ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; ++------------------------------+-------------------------------------------------+ + + ++---------------------+ +; IP Upgrade Messages ; ++---------------------+ +Info (23030): Evaluation of Tcl script d:/intelfpga/18.0/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful +Info: Quartus Prime Shell was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4903 megabytes + Info: Processing ended: Mon Nov 05 20:53:38 2018 + Info: Elapsed time: 00:00:13 + Info: Total CPU time (on all processors): 00:00:31 + + diff --git a/dpwm/dpwm.out.sdc b/dpwm/dpwm.out.sdc new file mode 100644 index 0000000..33becdf --- /dev/null +++ b/dpwm/dpwm.out.sdc @@ -0,0 +1,107 @@ +## Generated SDC file "dpwm.out.sdc" + +## Copyright (C) 2018 Intel Corporation. All rights reserved. +## Your use of Intel Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Intel Program License +## Subscription Agreement, the Intel Quartus Prime License Agreement, +## the Intel FPGA IP License Agreement, or other applicable license +## agreement, including, without limitation, that your use is for +## the sole purpose of programming logic devices manufactured by +## Intel and sold by Intel or its authorized distributors. Please +## refer to the applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus Prime" +## VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" + +## DATE "Sun Nov 04 21:56:00 2018" + +## +## DEVICE "EP4CE10F17C8" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clk0_180} -period 4.800 -waveform { 0.000 2.250 } [get_keepers {my_pll:my_pll|altpll:altpll_component|my_pll_altpll:auto_generated|pll_lock_sync}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/dpwm/dpwm.out.sdc.bak b/dpwm/dpwm.out.sdc.bak new file mode 100644 index 0000000..0dc4292 --- /dev/null +++ b/dpwm/dpwm.out.sdc.bak @@ -0,0 +1,107 @@ +## Generated SDC file "dpwm.out.sdc" + +## Copyright (C) 2018 Intel Corporation. All rights reserved. +## Your use of Intel Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Intel Program License +## Subscription Agreement, the Intel Quartus Prime License Agreement, +## the Intel FPGA IP License Agreement, or other applicable license +## agreement, including, without limitation, that your use is for +## the sole purpose of programming logic devices manufactured by +## Intel and sold by Intel or its authorized distributors. Please +## refer to the applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus Prime" +## VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" + +## DATE "Sun Nov 04 21:56:00 2018" + +## +## DEVICE "EP4CE10F17C8" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clk0_180} -period 4.500 -waveform { 0.000 2.250 } [get_keepers {my_pll:my_pll|altpll:altpll_component|my_pll_altpll:auto_generated|pll_lock_sync}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/dpwm/dpwm.qpf b/dpwm/dpwm.qpf new file mode 100644 index 0000000..d9343f5 --- /dev/null +++ b/dpwm/dpwm.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +# Date created = 19:55:05 November 03, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.0" +DATE = "19:55:05 November 03, 2018" + +# Revisions + +PROJECT_REVISION = "dpwm" diff --git a/dpwm/dpwm.qsf b/dpwm/dpwm.qsf new file mode 100644 index 0000000..b93161d --- /dev/null +++ b/dpwm/dpwm.qsf @@ -0,0 +1,77 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +# Date created = 19:55:05 November 03, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# dpwm_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE10F17C8 +set_global_assignment -name TOP_LEVEL_ENTITY dpwm_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:55:05 NOVEMBER 03, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH dpwm_top_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME dpwm_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dpwm_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dpwm_tb -section_id dpwm_tb +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name EDA_TEST_BENCH_NAME dpwm_top_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dpwm_top_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dpwm_top_tb -section_id dpwm_top_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/dpwm_tb.v -section_id dpwm_tb +set_global_assignment -name EDA_TEST_BENCH_FILE rtl/dpwm.v -section_id dpwm_tb +set_global_assignment -name EDA_TEST_BENCH_FILE ip/my_pll.qip -section_id dpwm_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/dpwm_top_tb.v -section_id dpwm_top_tb +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name QIP_FILE ip/my_pll.qip +set_global_assignment -name VERILOG_FILE rtl/dpwm_top.v +set_global_assignment -name VERILOG_FILE testbench/dpwm_top_tb.v +set_global_assignment -name VERILOG_FILE rtl/dpwm.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/dpwm/dpwm.qws b/dpwm/dpwm.qws new file mode 100644 index 0000000..8b9fe0c Binary files /dev/null and b/dpwm/dpwm.qws differ diff --git a/dpwm/dpwm_assignment_defaults.qdf b/dpwm/dpwm_assignment_defaults.qdf new file mode 100644 index 0000000..2aeb57d --- /dev/null +++ b/dpwm/dpwm_assignment_defaults.qdf @@ -0,0 +1,807 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +# Date created = 19:55:20 November 05, 2018 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY -value "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/dpwm/dpwm_nativelink_simulation.rpt b/dpwm/dpwm_nativelink_simulation.rpt new file mode 100644 index 0000000..f878da7 --- /dev/null +++ b/dpwm/dpwm_nativelink_simulation.rpt @@ -0,0 +1,23 @@ +Info: Start Nativelink Simulation process +Info: NativeLink has detected Verilog design -- Verilog simulation models will be used + +========= EDA Simulation Settings ===================== + +Sim Mode : RTL +Family : cycloneive +Quartus root : d:/intelfpga/18.0/quartus/bin64/ +Quartus sim root : d:/intelfpga/18.0/quartus/eda/sim_lib +Simulation Tool : modelsim-altera +Simulation Language : verilog +Simulation Mode : GUI +Sim Output File : +Sim SDF file : +Sim dir : simulation\modelsim + +======================================================= + +Info: Starting NativeLink simulation with ModelSim-Altera software +Sourced NativeLink script d:/intelfpga/18.0/quartus/common/tcl/internal/nativelink/modelsim.tcl +Warning: File dpwm_run_msim_rtl_verilog.do already exists - backing up current file as dpwm_run_msim_rtl_verilog.do.bak11 +Info: Spawning ModelSim-Altera Simulation software +Info: NativeLink simulation flow was successful diff --git a/dpwm/greybox_tmp/cbx_args.txt b/dpwm/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..bbfb764 --- /dev/null +++ b/dpwm/greybox_tmp/cbx_args.txt @@ -0,0 +1,12 @@ +INTENDED_DEVICE_FAMILY="Cyclone IV E" +enable_bus_hold=FALSE +left_shift_series_termination_control=FALSE +number_of_channels=8 +open_drain_output=FALSE +pseudo_differential_mode=FALSE +use_differential_mode=FALSE +use_oe=FALSE +use_termination_control=FALSE +DEVICE_FAMILY="Cyclone IV E" +datain +dataout diff --git a/dpwm/incremental_db/README b/dpwm/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/dpwm/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.db_info b/dpwm/incremental_db/compiled_partitions/dpwm.db_info new file mode 100644 index 0000000..6ea6d03 --- /dev/null +++ b/dpwm/incremental_db/compiled_partitions/dpwm.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +Version_Index = 469919232 +Creation_Time = Mon Nov 05 19:55:20 2018 diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.ammdb b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.ammdb new file mode 100644 index 0000000..65bf7e0 Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.ammdb differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.cdb b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.cdb new file mode 100644 index 0000000..59a6666 Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.cdb differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.dfp b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.dfp differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.hdb b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.hdb new file mode 100644 index 0000000..8a73fe1 Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.hdb differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.logdb b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.rcfdb b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.rcfdb new file mode 100644 index 0000000..f057f64 Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.cmp.rcfdb differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.cdb b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.cdb new file mode 100644 index 0000000..b6194f6 Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.cdb differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.dpi b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.dpi new file mode 100644 index 0000000..0235670 Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.dpi differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.cdb b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..0c3c961 Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.cdb differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.hb_info b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..79a6d1b Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.hb_info differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.hdb b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..d9f4918 Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.hdb differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.sig b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.sig new file mode 100644 index 0000000..8061115 --- /dev/null +++ b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +7e275d7c03b7db58cdb79615cd50a481 \ No newline at end of file diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hdb b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hdb new file mode 100644 index 0000000..d5adb99 Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.hdb differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.kpt b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.kpt new file mode 100644 index 0000000..a519adf Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.root_partition.map.kpt differ diff --git a/dpwm/incremental_db/compiled_partitions/dpwm.rrp.hdb b/dpwm/incremental_db/compiled_partitions/dpwm.rrp.hdb new file mode 100644 index 0000000..a4931c9 Binary files /dev/null and b/dpwm/incremental_db/compiled_partitions/dpwm.rrp.hdb differ diff --git a/dpwm/ip/delay.qip b/dpwm/ip/delay.qip new file mode 100644 index 0000000..2d79130 --- /dev/null +++ b/dpwm/ip/delay.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTIOBUF" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "delay.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "delay_bb.v"] diff --git a/dpwm/ip/delay.v b/dpwm/ip/delay.v new file mode 100644 index 0000000..2c24694 --- /dev/null +++ b/dpwm/ip/delay.v @@ -0,0 +1,130 @@ +// megafunction wizard: %ALTIOBUF% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altiobuf_out + +// ============================================================ +// File Name: delay.v +// Megafunction Name(s): +// altiobuf_out +// +// Simulation Library Files(s): +// cycloneive +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Standard Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +//altiobuf_out CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone IV E" ENABLE_BUS_HOLD="FALSE" LEFT_SHIFT_SERIES_TERMINATION_CONTROL="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="FALSE" USE_DIFFERENTIAL_MODE="FALSE" USE_OE="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout +//VERSION_BEGIN 18.0 cbx_altiobuf_out 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ VERSION_END +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + +//synthesis_resources = cycloneive_io_obuf 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module delay_iobuf_out_40t + ( + datain, + dataout) ; + input [0:0] datain; + output [0:0] dataout; + + wire [0:0] wire_obufa_o; + wire [0:0] oe_w; + + cycloneive_io_obuf obufa_0 + ( + .i(datain), + .o(wire_obufa_o[0:0]), + .obar(), + .oe(oe_w) + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .seriesterminationcontrol({16{1'b0}}) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + // synopsys translate_off + , + .devoe(1'b1) + // synopsys translate_on + ); + defparam + obufa_0.bus_hold = "false", + obufa_0.open_drain_output = "false", + obufa_0.lpm_type = "cycloneive_io_obuf"; + assign + dataout = wire_obufa_o, + oe_w = 1'b1; +endmodule //delay_iobuf_out_40t +//VALID FILE + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module delay ( + datain, + dataout); + + input [0:0] datain; + output [0:0] dataout; + + wire [0:0] sub_wire0; + wire [0:0] dataout = sub_wire0[0:0]; + + delay_iobuf_out_40t delay_iobuf_out_40t_component ( + .datain (datain), + .dataout (sub_wire0)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE" +// Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE" +// Retrieval info: CONSTANT: number_of_channels NUMERIC "1" +// Retrieval info: CONSTANT: open_drain_output STRING "FALSE" +// Retrieval info: CONSTANT: pseudo_differential_mode STRING "FALSE" +// Retrieval info: CONSTANT: use_differential_mode STRING "FALSE" +// Retrieval info: CONSTANT: use_oe STRING "FALSE" +// Retrieval info: CONSTANT: use_termination_control STRING "FALSE" +// Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]" +// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]" +// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0 +// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL delay.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay_bb.v TRUE +// Retrieval info: LIB_FILE: cycloneive diff --git a/dpwm/ip/delay_bb.v b/dpwm/ip/delay_bb.v new file mode 100644 index 0000000..a1a4979 --- /dev/null +++ b/dpwm/ip/delay_bb.v @@ -0,0 +1,68 @@ +// megafunction wizard: %ALTIOBUF%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altiobuf_out + +// ============================================================ +// File Name: delay.v +// Megafunction Name(s): +// altiobuf_out +// +// Simulation Library Files(s): +// cycloneive +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Standard Edition +// ************************************************************ + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module delay ( + datain, + dataout)/* synthesis synthesis_clearbox = 1 */; + + input [0:0] datain; + output [0:0] dataout; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE" +// Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE" +// Retrieval info: CONSTANT: number_of_channels NUMERIC "1" +// Retrieval info: CONSTANT: open_drain_output STRING "FALSE" +// Retrieval info: CONSTANT: pseudo_differential_mode STRING "FALSE" +// Retrieval info: CONSTANT: use_differential_mode STRING "FALSE" +// Retrieval info: CONSTANT: use_oe STRING "FALSE" +// Retrieval info: CONSTANT: use_termination_control STRING "FALSE" +// Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]" +// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]" +// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0 +// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL delay.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL delay_bb.v TRUE +// Retrieval info: LIB_FILE: cycloneive diff --git a/dpwm/ip/my_pll.ppf b/dpwm/ip/my_pll.ppf new file mode 100644 index 0000000..70fdbbc --- /dev/null +++ b/dpwm/ip/my_pll.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/dpwm/ip/my_pll.qip b/dpwm/ip/my_pll.qip new file mode 100644 index 0000000..bcfd32c --- /dev/null +++ b/dpwm/ip/my_pll.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "my_pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "my_pll_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "my_pll.ppf"] diff --git a/dpwm/ip/my_pll.v b/dpwm/ip/my_pll.v new file mode 100644 index 0000000..fadfcdf --- /dev/null +++ b/dpwm/ip/my_pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: my_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Standard Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module my_pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [0:0] sub_wire2 = 1'h0; + wire [4:0] sub_wire3; + wire sub_wire5; + wire sub_wire0 = inclk0; + wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; + wire [0:0] sub_wire4 = sub_wire3[0:0]; + wire c0 = sub_wire4; + wire locked = sub_wire5; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire1), + .clk (sub_wire3), + .locked (sub_wire5), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 5, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=my_pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "250.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "250.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "my_pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/dpwm/ip/my_pll_bb.v b/dpwm/ip/my_pll_bb.v new file mode 100644 index 0000000..f137ae5 --- /dev/null +++ b/dpwm/ip/my_pll_bb.v @@ -0,0 +1,210 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: my_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Standard Edition +// ************************************************************ + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module my_pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "250.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "250.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "my_pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/dpwm/output_files/dpwm.asm.rpt b/dpwm/output_files/dpwm.asm.rpt new file mode 100644 index 0000000..163ad17 --- /dev/null +++ b/dpwm/output_files/dpwm.asm.rpt @@ -0,0 +1,91 @@ +Assembler report for dpwm +Mon Nov 05 21:21:13 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: F:/Code/FPGA/reserve/dpwm/output_files/dpwm.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon Nov 05 21:21:13 2018 ; +; Revision Name ; dpwm ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-------------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------------+ +; File Name ; ++-------------------------------------------------+ +; F:/Code/FPGA/reserve/dpwm/output_files/dpwm.sof ; ++-------------------------------------------------+ + + ++---------------------------------------------------------------------------+ +; Assembler Device Options: F:/Code/FPGA/reserve/dpwm/output_files/dpwm.sof ; ++----------------+----------------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------------+ +; JTAG usercode ; 0x0008B7A3 ; +; Checksum ; 0x0008B7A3 ; ++----------------+----------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + Info: Processing started: Mon Nov 05 21:21:11 2018 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off dpwm -c dpwm +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4693 megabytes + Info: Processing ended: Mon Nov 05 21:21:13 2018 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/dpwm/output_files/dpwm.done b/dpwm/output_files/dpwm.done new file mode 100644 index 0000000..851978e --- /dev/null +++ b/dpwm/output_files/dpwm.done @@ -0,0 +1 @@ +Mon Nov 05 21:25:30 2018 diff --git a/dpwm/output_files/dpwm.eda.rpt b/dpwm/output_files/dpwm.eda.rpt new file mode 100644 index 0000000..be6f6be --- /dev/null +++ b/dpwm/output_files/dpwm.eda.rpt @@ -0,0 +1,108 @@ +EDA Netlist Writer report for dpwm +Mon Nov 05 21:21:20 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Mon Nov 05 21:21:20 2018 ; +; Revision Name ; dpwm ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------+ +; Simulation Generated Files ; ++-----------------------------------------------------------------------------+ +; Generated Files ; ++-----------------------------------------------------------------------------+ +; F:/Code/FPGA/reserve/dpwm/simulation/modelsim/dpwm_8_1200mv_85c_slow.vo ; +; F:/Code/FPGA/reserve/dpwm/simulation/modelsim/dpwm_8_1200mv_0c_slow.vo ; +; F:/Code/FPGA/reserve/dpwm/simulation/modelsim/dpwm_min_1200mv_0c_fast.vo ; +; F:/Code/FPGA/reserve/dpwm/simulation/modelsim/dpwm.vo ; +; F:/Code/FPGA/reserve/dpwm/simulation/modelsim/dpwm_8_1200mv_85c_v_slow.sdo ; +; F:/Code/FPGA/reserve/dpwm/simulation/modelsim/dpwm_8_1200mv_0c_v_slow.sdo ; +; F:/Code/FPGA/reserve/dpwm/simulation/modelsim/dpwm_min_1200mv_0c_v_fast.sdo ; +; F:/Code/FPGA/reserve/dpwm/simulation/modelsim/dpwm_v.sdo ; ++-----------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + Info: Processing started: Mon Nov 05 21:21:19 2018 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off dpwm -c dpwm +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file dpwm_8_1200mv_85c_slow.vo in folder "F:/Code/FPGA/reserve/dpwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_8_1200mv_0c_slow.vo in folder "F:/Code/FPGA/reserve/dpwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_min_1200mv_0c_fast.vo in folder "F:/Code/FPGA/reserve/dpwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm.vo in folder "F:/Code/FPGA/reserve/dpwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_8_1200mv_85c_v_slow.sdo in folder "F:/Code/FPGA/reserve/dpwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_8_1200mv_0c_v_slow.sdo in folder "F:/Code/FPGA/reserve/dpwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_min_1200mv_0c_v_fast.sdo in folder "F:/Code/FPGA/reserve/dpwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_v.sdo in folder "F:/Code/FPGA/reserve/dpwm/simulation/modelsim/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4661 megabytes + Info: Processing ended: Mon Nov 05 21:21:20 2018 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/dpwm/output_files/dpwm.fit.rpt b/dpwm/output_files/dpwm.fit.rpt new file mode 100644 index 0000000..9582e02 --- /dev/null +++ b/dpwm/output_files/dpwm.fit.rpt @@ -0,0 +1,1158 @@ +Fitter report for dpwm +Mon Nov 05 21:21:09 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. PLL Summary + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Control Signals + 22. Global & Other Fast Signals + 23. Routing Usage Summary + 24. LAB Logic Elements + 25. LAB-wide Signals + 26. LAB Signals Sourced + 27. LAB Signals Sourced Out + 28. LAB Distinct Inputs + 29. I/O Rules Summary + 30. I/O Rules Details + 31. I/O Rules Matrix + 32. Fitter Device Options + 33. Operating Settings and Conditions + 34. Fitter Messages + 35. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Mon Nov 05 21:21:09 2018 ; +; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ; +; Revision Name ; dpwm ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Total logic elements ; 29 / 10,320 ( < 1 % ) ; +; Total combinational functions ; 29 / 10,320 ( < 1 % ) ; +; Dedicated logic registers ; 11 / 10,320 ( < 1 % ) ; +; Total registers ; 11 ; +; Total pins ; 19 / 180 ( 11 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; Total PLLs ; 1 / 2 ( 50 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP4CE10F17C8 ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Logic Cell Insertion - Logic Duplication ; On ; Auto ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.2% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 92 ) ; 0.00 % ( 0 / 92 ) ; 0.00 % ( 0 / 92 ) ; +; -- Achieved ; 0.00 % ( 0 / 92 ) ; 0.00 % ( 0 / 92 ) ; 0.00 % ( 0 / 92 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 81 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 11 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in F:/Code/FPGA/reserve/dpwm/output_files/dpwm.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 29 / 10,320 ( < 1 % ) ; +; -- Combinational with no register ; 18 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 11 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 8 ; +; -- <=2 input functions ; 21 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 16 ; +; -- arithmetic mode ; 13 ; +; ; ; +; Total registers* ; 11 / 11,172 ( < 1 % ) ; +; -- Dedicated logic registers ; 11 / 10,320 ( < 1 % ) ; +; -- I/O registers ; 0 / 852 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 5 / 645 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 19 / 180 ( 11 % ) ; +; -- Clock pins ; 3 / 3 ( 100 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; M9Ks ; 0 / 46 ( 0 % ) ; +; Total block memory bits ; 0 / 423,936 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; PLLs ; 1 / 2 ( 50 % ) ; +; Global signals ; 3 ; +; -- Global clocks ; 3 / 10 ( 30 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ; +; Peak interconnect usage (total/H/V) ; 0.1% / 0.0% / 0.2% ; +; Maximum fan-out ; 10 ; +; Highest non-global fan-out ; 3 ; +; Total fan-out ; 118 ; +; Average fan-out ; 1.28 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 29 / 10320 ( < 1 % ) ; 0 / 10320 ( 0 % ) ; +; -- Combinational with no register ; 18 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 11 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 0 ; 0 ; +; -- 3 input functions ; 8 ; 0 ; +; -- <=2 input functions ; 21 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 16 ; 0 ; +; -- arithmetic mode ; 13 ; 0 ; +; ; ; ; +; Total registers ; 11 ; 0 ; +; -- Dedicated logic registers ; 11 / 10320 ( < 1 % ) ; 0 / 10320 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 5 / 645 ( < 1 % ) ; 0 / 645 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 19 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; 0 / 46 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; PLL ; 0 / 2 ( 0 % ) ; 1 / 2 ( 50 % ) ; +; Clock control block ; 3 / 12 ( 25 % ) ; 0 / 12 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 2 ; 2 ; +; -- Registered Input Connections ; 1 ; 0 ; +; -- Output Connections ; 2 ; 2 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 112 ; 10 ; +; -- Registered Connections ; 16 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 4 ; +; -- hard_block:auto_generated_inst ; 4 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 10 ; 2 ; +; -- Output Ports ; 9 ; 1 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; clk ; E1 ; 1 ; 0 ; 11 ; 7 ; 11 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; dpid[0] ; J14 ; 5 ; 34 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; dpid[1] ; J12 ; 5 ; 34 ; 11 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; dpid[2] ; J15 ; 5 ; 34 ; 10 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; dpid[3] ; J16 ; 5 ; 34 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; dpid[4] ; J13 ; 5 ; 34 ; 11 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; dpid[5] ; K15 ; 5 ; 34 ; 9 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; dpid[6] ; E15 ; 6 ; 34 ; 12 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; dpid[7] ; E16 ; 6 ; 34 ; 12 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; rst_n ; M2 ; 2 ; 0 ; 11 ; 14 ; 2 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; ++---------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; delay_out[0] ; G16 ; 6 ; 34 ; 17 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; delay_out[1] ; G15 ; 6 ; 34 ; 17 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; delay_out[2] ; F13 ; 6 ; 34 ; 17 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; delay_out[3] ; F15 ; 6 ; 34 ; 18 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; delay_out[4] ; A10 ; 7 ; 21 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; delay_out[5] ; B3 ; 8 ; 3 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; delay_out[6] ; A14 ; 7 ; 28 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; delay_out[7] ; R10 ; 4 ; 21 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; pwm_out ; K16 ; 5 ; 34 ; 9 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; C1 ; DIFFIO_L1n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; D2 ; DIFFIO_L2p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; F4 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; H1 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; H2 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; H5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; J3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; J16 ; DIFFIO_R7n, DEV_OE ; Use as regular IO ; dpid[3] ; Dual Purpose Pin ; +; J15 ; DIFFIO_R7p, DEV_CLRn ; Use as regular IO ; dpid[2] ; Dual Purpose Pin ; +; H14 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; H13 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; H12 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; G16 ; DIFFIO_R4n, INIT_DONE ; Use as regular IO ; delay_out[0] ; Dual Purpose Pin ; +; G15 ; DIFFIO_R4p, CRC_ERROR ; Use as regular IO ; delay_out[1] ; Dual Purpose Pin ; +; F16 ; DIFFIO_R3n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; +; F15 ; DIFFIO_R3p, CLKUSR ; Use as regular IO ; delay_out[3] ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1 ; 5 / 17 ( 29 % ) ; 2.5V ; -- ; +; 2 ; 1 / 19 ( 5 % ) ; 2.5V ; -- ; +; 3 ; 0 / 26 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 1 / 27 ( 4 % ) ; 2.5V ; -- ; +; 5 ; 7 / 25 ( 28 % ) ; 2.5V ; -- ; +; 6 ; 7 / 14 ( 50 % ) ; 2.5V ; -- ; +; 7 ; 2 / 26 ( 8 % ) ; 2.5V ; -- ; +; 8 ; 1 / 26 ( 4 % ) ; 2.5V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A2 ; 194 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 200 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 196 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 192 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 188 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 183 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 177 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 175 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 168 ; 7 ; delay_out[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A11 ; 161 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 159 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 153 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 155 ; 7 ; delay_out[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A15 ; 167 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 201 ; 8 ; delay_out[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B4 ; 197 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 195 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 189 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 184 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 178 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; 176 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B10 ; 169 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 162 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 160 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; 154 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; 156 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B16 ; 141 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; C2 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C3 ; 202 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 187 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C7 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C8 ; 179 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 172 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C11 ; 163 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C14 ; 149 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 147 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C16 ; 146 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; D3 ; 203 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D4 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D5 ; 198 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 199 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D8 ; 180 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 173 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 151 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 152 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; D14 ; 150 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 144 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D16 ; 143 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 24 ; 1 ; clk ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E5 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E6 ; 191 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; 190 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; 181 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 174 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 158 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 157 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E15 ; 128 ; 6 ; dpid[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E16 ; 127 ; 6 ; dpid[7] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F1 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; F4 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; F5 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; 185 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F7 ; 186 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 182 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 165 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 164 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 166 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; 138 ; 6 ; delay_out[2] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F14 ; 142 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; F15 ; 140 ; 6 ; delay_out[3] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F16 ; 139 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G1 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 10 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G11 ; 145 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G12 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G12 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; 137 ; 6 ; delay_out[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G16 ; 136 ; 6 ; delay_out[0] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H1 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H2 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H3 ; 19 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; H4 ; 18 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; H5 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H12 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; H13 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; H14 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J1 ; 28 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; 27 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J3 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 21 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; J5 ; 20 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; J6 ; 29 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J11 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J12 ; 123 ; 5 ; dpid[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J13 ; 124 ; 5 ; dpid[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J14 ; 122 ; 5 ; dpid[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J15 ; 121 ; 5 ; dpid[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J16 ; 120 ; 5 ; dpid[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K1 ; 33 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 32 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K5 ; 39 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 30 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K8 ; 60 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; 76 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K10 ; 87 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K11 ; 110 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K12 ; 105 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K15 ; 119 ; 5 ; dpid[5] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K16 ; 118 ; 5 ; pwm_out ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L1 ; 35 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 34 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; 36 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; L4 ; 40 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L5 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L6 ; 31 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L7 ; 65 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L8 ; 68 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L9 ; 77 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L10 ; 88 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L11 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L12 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L13 ; 114 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L14 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; L15 ; 116 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; 115 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 26 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M2 ; 25 ; 2 ; rst_n ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; 57 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M7 ; 59 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M8 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M9 ; 78 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M10 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M11 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M12 ; 103 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M15 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M16 ; 125 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 38 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 37 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 45 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N4 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N5 ; 55 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N6 ; 56 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N9 ; 79 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N12 ; 101 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N13 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N14 ; 106 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 112 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; 111 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P4 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; P7 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 71 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P9 ; 89 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P11 ; 90 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P14 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P15 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 108 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; 47 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R4 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R5 ; 61 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R6 ; 63 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R7 ; 66 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R8 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R9 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 80 ; 4 ; delay_out[7] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R11 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 85 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 91 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; 109 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T2 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T3 ; 48 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T4 ; 54 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T5 ; 62 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T6 ; 64 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T7 ; 67 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T8 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 75 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T10 ; 81 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T11 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 86 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; 92 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T14 ; 95 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T15 ; 96 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++----------------------------------------------------------------------------------------------------------+ +; PLL Summary ; ++-------------------------------+--------------------------------------------------------------------------+ +; Name ; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|pll1 ; ++-------------------------------+--------------------------------------------------------------------------+ +; SDC pin name ; my_pll|altpll_component|auto_generated|pll1 ; +; PLL mode ; No compensation ; +; Compensate clock ; -- ; +; Compensated input/output pins ; -- ; +; Switchover type ; -- ; +; Input frequency 0 ; 50.0 MHz ; +; Input frequency 1 ; -- ; +; Nominal PFD frequency ; 50.0 MHz ; +; Nominal VCO frequency ; 600.0 MHz ; +; VCO post scale K counter ; 2 ; +; VCO frequency control ; Auto ; +; VCO phase shift step ; 208 ps ; +; VCO multiply ; -- ; +; VCO divide ; -- ; +; Freq min lock ; 25.0 MHz ; +; Freq max lock ; 54.18 MHz ; +; M VCO Tap ; 0 ; +; M Initial ; 1 ; +; M value ; 12 ; +; N value ; 1 ; +; Charge pump current ; setting 1 ; +; Loop filter resistance ; setting 27 ; +; Loop filter capacitance ; setting 0 ; +; Bandwidth ; 680 kHz to 980 kHz ; +; Bandwidth type ; Medium ; +; Real time reconfigurable ; Off ; +; Scan chain MIF file ; -- ; +; Preserve PLL counter order ; Off ; +; PLL location ; PLL_1 ; +; Inclk0 signal ; clk ; +; Inclk1 signal ; -- ; +; Inclk0 signal type ; Dedicated Pin ; +; Inclk1 signal type ; -- ; ++-------------------------------+--------------------------------------------------------------------------+ + + ++----------------------------------------------+ +; I/O Assignment Warnings ; ++--------------+-------------------------------+ +; Pin Name ; Reason ; ++--------------+-------------------------------+ +; delay_out[0] ; Incomplete set of assignments ; +; delay_out[1] ; Incomplete set of assignments ; +; delay_out[2] ; Incomplete set of assignments ; +; delay_out[3] ; Incomplete set of assignments ; +; delay_out[4] ; Incomplete set of assignments ; +; delay_out[5] ; Incomplete set of assignments ; +; delay_out[6] ; Incomplete set of assignments ; +; delay_out[7] ; Incomplete set of assignments ; +; pwm_out ; Incomplete set of assignments ; +; clk ; Incomplete set of assignments ; +; dpid[7] ; Incomplete set of assignments ; +; dpid[6] ; Incomplete set of assignments ; +; dpid[5] ; Incomplete set of assignments ; +; dpid[4] ; Incomplete set of assignments ; +; dpid[3] ; Incomplete set of assignments ; +; dpid[2] ; Incomplete set of assignments ; +; dpid[1] ; Incomplete set of assignments ; +; dpid[0] ; Incomplete set of assignments ; +; rst_n ; Incomplete set of assignments ; +; delay_out[0] ; Missing location assignment ; +; delay_out[1] ; Missing location assignment ; +; delay_out[2] ; Missing location assignment ; +; delay_out[3] ; Missing location assignment ; +; delay_out[4] ; Missing location assignment ; +; delay_out[5] ; Missing location assignment ; +; delay_out[6] ; Missing location assignment ; +; delay_out[7] ; Missing location assignment ; +; pwm_out ; Missing location assignment ; +; clk ; Missing location assignment ; +; dpid[7] ; Missing location assignment ; +; dpid[6] ; Missing location assignment ; +; dpid[5] ; Missing location assignment ; +; dpid[4] ; Missing location assignment ; +; dpid[3] ; Missing location assignment ; +; dpid[2] ; Missing location assignment ; +; dpid[1] ; Missing location assignment ; +; dpid[0] ; Missing location assignment ; +; rst_n ; Missing location assignment ; ++--------------+-------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------+----------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------+----------------+--------------+ +; |dpwm_top ; 29 (0) ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; 18 (0) ; 0 (0) ; 11 (0) ; |dpwm_top ; dpwm_top ; work ; +; |dpwm:dpwm| ; 27 (27) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 (17) ; 0 (0) ; 10 (10) ; |dpwm_top|dpwm:dpwm ; dpwm ; work ; +; |my_pll:my_pll| ; 2 (0) ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 1 (0) ; |dpwm_top|my_pll:my_pll ; my_pll ; work ; +; |altpll:altpll_component| ; 2 (0) ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 1 (0) ; |dpwm_top|my_pll:my_pll|altpll:altpll_component ; altpll ; work ; +; |my_pll_altpll1:auto_generated| ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; |dpwm_top|my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated ; my_pll_altpll1 ; work ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------+----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++--------------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++--------------+----------+---------------+---------------+-----------------------+-----+------+ +; delay_out[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; delay_out[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; delay_out[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; delay_out[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; delay_out[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; delay_out[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; delay_out[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; delay_out[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; pwm_out ; Output ; -- ; -- ; -- ; -- ; -- ; +; clk ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; dpid[7] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; dpid[6] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; dpid[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; dpid[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; dpid[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; dpid[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; dpid[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; dpid[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; rst_n ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; ++--------------+----------+---------------+---------------+-----------------------+-----+------+ + + ++-------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-------------------------------+-------------------+---------+ +; clk ; ; ; +; dpid[7] ; ; ; +; dpid[6] ; ; ; +; dpid[5] ; ; ; +; - dpwm:dpwm|LessThan0~11 ; 0 ; 6 ; +; dpid[4] ; ; ; +; - dpwm:dpwm|LessThan0~9 ; 0 ; 6 ; +; dpid[3] ; ; ; +; - dpwm:dpwm|LessThan0~7 ; 1 ; 6 ; +; dpid[2] ; ; ; +; - dpwm:dpwm|LessThan0~5 ; 1 ; 6 ; +; dpid[1] ; ; ; +; - dpwm:dpwm|LessThan0~3 ; 0 ; 6 ; +; dpid[0] ; ; ; +; - dpwm:dpwm|LessThan0~1 ; 0 ; 6 ; +; rst_n ; ; ; ++-------------------------------+-------------------+---------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++--------------------------------------------------------------------------------------+------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++--------------------------------------------------------------------------------------+------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; clk ; PIN_E1 ; 2 ; Clock ; no ; -- ; -- ; -- ; +; clk ; PIN_E1 ; 10 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; +; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|locked ; LCCOMB_X1_Y4_N14 ; 8 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ; +; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|wire_pll1_locked ; PLL_1 ; 2 ; Clock ; no ; -- ; -- ; -- ; +; rst_n ; PIN_M2 ; 2 ; Async. clear ; yes ; Global Clock ; GCLK4 ; -- ; ++--------------------------------------------------------------------------------------+------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++----------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; clk ; PIN_E1 ; 10 ; 1 ; Global Clock ; GCLK2 ; -- ; +; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|locked ; LCCOMB_X1_Y4_N14 ; 8 ; 0 ; Global Clock ; GCLK1 ; -- ; +; rst_n ; PIN_M2 ; 2 ; 0 ; Global Clock ; GCLK4 ; -- ; ++----------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+-----------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+-----------------------+ +; Block interconnects ; 29 / 32,401 ( < 1 % ) ; +; C16 interconnects ; 0 / 1,326 ( 0 % ) ; +; C4 interconnects ; 12 / 21,816 ( < 1 % ) ; +; Direct links ; 14 / 32,401 ( < 1 % ) ; +; Global clocks ; 3 / 10 ( 30 % ) ; +; Local interconnects ; 16 / 10,320 ( < 1 % ) ; +; R24 interconnects ; 0 / 1,289 ( 0 % ) ; +; R4 interconnects ; 4 / 28,186 ( < 1 % ) ; ++-----------------------+-----------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 5.80) ; Number of LABs (Total = 5) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++--------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 5) ; ++------------------------------------+-----------------------------+ +; 1 Async. clear ; 2 ; +; 1 Clock ; 3 ; ++------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 6.60) ; Number of LABs (Total = 5) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 1.80) ; Number of LABs (Total = 5) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 3 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 3.20) ; Number of LABs (Total = 5) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 2 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 9 ; 0 ; 0 ; 10 ; 0 ; 9 ; 10 ; 0 ; 0 ; 0 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 10 ; 19 ; 19 ; 9 ; 19 ; 10 ; 9 ; 19 ; 19 ; 19 ; 10 ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 19 ; 19 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; delay_out[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; delay_out[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; delay_out[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; delay_out[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; delay_out[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; delay_out[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; delay_out[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; delay_out[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; pwm_out ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; clk ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; dpid[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; dpid[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; dpid[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; dpid[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; dpid[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; dpid[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; dpid[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; dpid[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; rst_n ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 C ; +; High Junction Temperature ; 85 C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device EP4CE10F17C8 for design "dpwm" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (15090): Changed operation mode of PLL "my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|pll1" to No Compensation File: F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v Line: 50 +Info (15535): Implemented PLL "my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|pll1" as Cyclone IV E PLL type File: F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v Line: 50 +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE6F17C8 is compatible + Info (176445): Device EP4CE15F17C8 is compatible + Info (176445): Device EP4CE22F17C8 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 19 pins of 19 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Critical Warning (332012): Synopsys Design Constraints File file not found: 'dpwm.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v Line: 11 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 +Info (176353): Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v Line: 12 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info (176353): Automatically promoted node my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|locked File: F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v Line: 39 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 17 (unused VREF, 2.5V VCCIO, 8 input, 9 output, 0 bidirectional) + Info (176212): I/O standards used: 2.5 V. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (144001): Generated suppressed messages file F:/Code/FPGA/reserve/dpwm/output_files/dpwm.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 5562 megabytes + Info: Processing ended: Mon Nov 05 21:21:09 2018 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:08 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in F:/Code/FPGA/reserve/dpwm/output_files/dpwm.fit.smsg. + + diff --git a/dpwm/output_files/dpwm.fit.smsg b/dpwm/output_files/dpwm.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/dpwm/output_files/dpwm.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/dpwm/output_files/dpwm.fit.summary b/dpwm/output_files/dpwm.fit.summary new file mode 100644 index 0000000..2764ddc --- /dev/null +++ b/dpwm/output_files/dpwm.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon Nov 05 21:21:09 2018 +Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Standard Edition +Revision Name : dpwm +Top-level Entity Name : dpwm_top +Family : Cyclone IV E +Device : EP4CE10F17C8 +Timing Models : Final +Total logic elements : 29 / 10,320 ( < 1 % ) + Total combinational functions : 29 / 10,320 ( < 1 % ) + Dedicated logic registers : 11 / 10,320 ( < 1 % ) +Total registers : 11 +Total pins : 19 / 180 ( 11 % ) +Total virtual pins : 0 +Total memory bits : 0 / 423,936 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 46 ( 0 % ) +Total PLLs : 1 / 2 ( 50 % ) diff --git a/dpwm/output_files/dpwm.flow.rpt b/dpwm/output_files/dpwm.flow.rpt new file mode 100644 index 0000000..cf41109 --- /dev/null +++ b/dpwm/output_files/dpwm.flow.rpt @@ -0,0 +1,147 @@ +Flow report for dpwm +Mon Nov 05 21:21:20 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Mon Nov 05 21:21:20 2018 ; +; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ; +; Revision Name ; dpwm ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Total logic elements ; 29 / 10,320 ( < 1 % ) ; +; Total combinational functions ; 29 / 10,320 ( < 1 % ) ; +; Dedicated logic registers ; 11 / 10,320 ( < 1 % ) ; +; Total registers ; 11 ; +; Total pins ; 19 / 180 ( 11 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; Total PLLs ; 1 / 2 ( 50 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 11/05/2018 21:20:43 ; +; Main task ; Compilation ; +; Revision Name ; dpwm ; ++-------------------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++----------------------------------------------+----------------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++----------------------------------------------+----------------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 93383153531551.154142404319612 ; -- ; -- ; -- ; +; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; dpwm_top_tb ; +; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; dpwm_tb ; +; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; dpwm_top_tb ; -- ; -- ; eda_simulation ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; +; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ; +; EDA_TEST_BENCH_FILE ; testbench/dpwm_top_tb.v ; -- ; -- ; dpwm_top_tb ; +; EDA_TEST_BENCH_FILE ; testbench/dpwm_tb.v ; -- ; -- ; dpwm_tb ; +; EDA_TEST_BENCH_FILE ; rtl/dpwm.v ; -- ; -- ; dpwm_tb ; +; EDA_TEST_BENCH_FILE ; ip/my_pll.qip ; -- ; -- ; dpwm_tb ; +; EDA_TEST_BENCH_MODULE_NAME ; dpwm_top_tb ; -- ; -- ; dpwm_top_tb ; +; EDA_TEST_BENCH_MODULE_NAME ; dpwm_tb ; -- ; -- ; dpwm_tb ; +; EDA_TEST_BENCH_NAME ; dpwm_tb ; -- ; -- ; eda_simulation ; +; EDA_TEST_BENCH_NAME ; dpwm_top_tb ; -- ; -- ; eda_simulation ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; ip/my_pll_bb.v ; -- ; -- ; -- ; +; MISC_FILE ; ip/my_pll.ppf ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; dpwm_top ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; dpwm_top ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; dpwm_top ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; On ; Auto ; -- ; -- ; +; TOP_LEVEL_ENTITY ; dpwm_top ; dpwm ; -- ; -- ; ++----------------------------------------------+----------------------------------------+---------------+-------------+----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:19 ; 1.0 ; 4790 MB ; 00:00:43 ; +; Fitter ; 00:00:06 ; 1.0 ; 5562 MB ; 00:00:08 ; +; Assembler ; 00:00:02 ; 1.0 ; 4693 MB ; 00:00:02 ; +; Timing Analyzer ; 00:00:02 ; 1.0 ; 4776 MB ; 00:00:03 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4658 MB ; 00:00:02 ; +; Total ; 00:00:30 ; -- ; -- ; 00:00:58 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Timing Analyzer ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; ++----------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off dpwm -c dpwm +quartus_fit --read_settings_files=off --write_settings_files=off dpwm -c dpwm +quartus_asm --read_settings_files=off --write_settings_files=off dpwm -c dpwm +quartus_sta dpwm -c dpwm +quartus_eda --read_settings_files=off --write_settings_files=off dpwm -c dpwm + + + diff --git a/dpwm/output_files/dpwm.jdi b/dpwm/output_files/dpwm.jdi new file mode 100644 index 0000000..db0c25f --- /dev/null +++ b/dpwm/output_files/dpwm.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/dpwm/output_files/dpwm.map.rpt b/dpwm/output_files/dpwm.map.rpt new file mode 100644 index 0000000..e1b9559 --- /dev/null +++ b/dpwm/output_files/dpwm.map.rpt @@ -0,0 +1,829 @@ +Analysis & Synthesis report for dpwm +Mon Nov 05 21:21:01 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis IP Cores Summary + 9. General Register Statistics + 10. Source assignments for dpwm:dpwm + 11. Parameter Settings for User Entity Instance: my_pll:my_pll|altpll:altpll_component + 12. altpll Parameter Settings by Entity Instance + 13. Post-Synthesis Netlist Statistics for Top Partition + 14. Elapsed Time Per Partition + 15. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Nov 05 21:21:01 2018 ; +; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ; +; Revision Name ; dpwm ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; +; Total logic elements ; 29 ; +; Total combinational functions ; 28 ; +; Dedicated logic registers ; 11 ; +; Total registers ; 11 ; +; Total pins ; 19 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 1 ; ++------------------------------------+-------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP4CE10F17C8 ; ; +; Top-level entity name ; dpwm_top ; dpwm ; +; Family name ; Cyclone IV E ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.0% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+ +; ip/my_pll.v ; yes ; User Wizard-Generated File ; F:/Code/FPGA/reserve/dpwm/ip/my_pll.v ; ; +; rtl/dpwm_top.v ; yes ; User Verilog HDL File ; F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v ; ; +; rtl/dpwm.v ; yes ; User Verilog HDL File ; F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v ; ; +; altpll.tdf ; yes ; Megafunction ; d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf ; ; +; aglobal180.inc ; yes ; Megafunction ; d:/intelfpga/18.0/quartus/libraries/megafunctions/aglobal180.inc ; ; +; stratix_pll.inc ; yes ; Megafunction ; d:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_pll.inc ; ; +; stratixii_pll.inc ; yes ; Megafunction ; d:/intelfpga/18.0/quartus/libraries/megafunctions/stratixii_pll.inc ; ; +; cycloneii_pll.inc ; yes ; Megafunction ; d:/intelfpga/18.0/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; +; db/my_pll_altpll1.v ; yes ; Auto-Generated Megafunction ; F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v ; ; ++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+ + + ++---------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-----------+ +; Resource ; Usage ; ++---------------------------------------------+-----------+ +; Estimated Total logic elements ; 29 ; +; ; ; +; Total combinational functions ; 28 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 0 ; +; -- 3 input functions ; 8 ; +; -- <=2 input functions ; 20 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 15 ; +; -- arithmetic mode ; 13 ; +; ; ; +; Total registers ; 11 ; +; -- Dedicated logic registers ; 11 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 19 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Total PLLs ; 1 ; +; -- PLLs ; 1 ; +; ; ; +; Maximum fan-out node ; clk~input ; +; Maximum fan-out ; 11 ; +; Total fan-out ; 109 ; +; Average fan-out ; 1.40 ; ++---------------------------------------------+-----------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------+----------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------+----------------+--------------+ +; |dpwm_top ; 28 (0) ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; |dpwm_top ; dpwm_top ; work ; +; |dpwm:dpwm| ; 27 (27) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dpwm_top|dpwm:dpwm ; dpwm ; work ; +; |my_pll:my_pll| ; 1 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dpwm_top|my_pll:my_pll ; my_pll ; work ; +; |altpll:altpll_component| ; 1 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dpwm_top|my_pll:my_pll|altpll:altpll_component ; altpll ; work ; +; |my_pll_altpll1:auto_generated| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dpwm_top|my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated ; my_pll_altpll1 ; work ; ++------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------+----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+-------------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+-------------------------+-----------------+ +; Altera ; ALTPLL ; 18.0 ; N/A ; N/A ; |dpwm_top|my_pll:my_pll ; ip/my_pll.v ; ++--------+--------------+---------+--------------+--------------+-------------------------+-----------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 11 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 9 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++---------------------------------------------------+ +; Source assignments for dpwm:dpwm ; ++------------------------------+-------+------+-----+ +; Assignment ; Value ; From ; To ; ++------------------------------+-------+------+-----+ +; IGNORE_LCELL_BUFFERS ; off ; - ; de1 ; +; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; de1 ; +; IGNORE_LCELL_BUFFERS ; off ; - ; de2 ; +; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; de2 ; +; IGNORE_LCELL_BUFFERS ; off ; - ; de3 ; +; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; de3 ; +; IGNORE_LCELL_BUFFERS ; off ; - ; de4 ; +; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; de4 ; +; IGNORE_LCELL_BUFFERS ; off ; - ; de5 ; +; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; de5 ; +; IGNORE_LCELL_BUFFERS ; off ; - ; de6 ; +; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; de6 ; +; IGNORE_LCELL_BUFFERS ; off ; - ; de7 ; +; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; de7 ; ++------------------------------+-------+------+-----+ + + ++------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: my_pll:my_pll|altpll:altpll_component ; ++-------------------------------+--------------------------+-------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+--------------------------+-------------------------+ +; OPERATION_MODE ; NORMAL ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; LPM_HINT ; CBX_MODULE_PREFIX=my_pll ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 1 ; Untyped ; +; CLK1_MULTIPLY_BY ; 1 ; Untyped ; +; CLK0_MULTIPLY_BY ; 5 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 1 ; Untyped ; +; CLK1_DIVIDE_BY ; 1 ; Untyped ; +; CLK0_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Untyped ; +; CLK1_DUTY_CYCLE ; 50 ; Untyped ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK2 ; PORT_UNUSED ; Untyped ; +; PORT_CLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_USED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_USED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; my_pll_altpll1 ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+--------------------------+-------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------+ +; altpll Parameter Settings by Entity Instance ; ++-------------------------------+---------------------------------------+ +; Name ; Value ; ++-------------------------------+---------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; my_pll:my_pll|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 20000 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; ++-------------------------------+---------------------------------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 19 ; +; cycloneiii_ff ; 11 ; +; CLR ; 9 ; +; plain ; 2 ; +; cycloneiii_lcell_comb ; 29 ; +; arith ; 13 ; +; 2 data inputs ; 5 ; +; 3 data inputs ; 8 ; +; normal ; 16 ; +; 0 data inputs ; 1 ; +; 1 data inputs ; 12 ; +; 2 data inputs ; 3 ; +; cycloneiii_pll ; 1 ; +; ; ; +; Max LUT depth ; 10.60 ; +; Average LUT depth ; 8.16 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + Info: Processing started: Mon Nov 05 21:20:42 2018 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dpwm -c dpwm +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file ip/my_pll.v + Info (12023): Found entity 1: my_pll File: F:/Code/FPGA/reserve/dpwm/ip/my_pll.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file rtl/dpwm_top.v + Info (12023): Found entity 1: dpwm_top File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file testbench/dpwm_top_tb.v + Info (12023): Found entity 1: dpwm_top_tb File: F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v Line: 5 +Info (12021): Found 1 design units, including 1 entities, in source file rtl/dpwm.v + Info (12023): Found entity 1: dpwm File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 1 +Warning (10227): Verilog HDL Port Declaration warning at dpwm.v(30): data type declaration for "delay_out" declares packed dimensions but the port declaration declaration does not File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 30 +Info (10499): HDL info at dpwm.v(28): see declaration for object "delay_out" File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 28 +Info (12127): Elaborating entity "dpwm_top" for the top level hierarchy +Info (12128): Elaborating entity "my_pll" for hierarchy "my_pll:my_pll" File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v Line: 30 +Info (12128): Elaborating entity "altpll" for hierarchy "my_pll:my_pll|altpll:altpll_component" File: F:/Code/FPGA/reserve/dpwm/ip/my_pll.v Line: 103 +Info (12130): Elaborated megafunction instantiation "my_pll:my_pll|altpll:altpll_component" File: F:/Code/FPGA/reserve/dpwm/ip/my_pll.v Line: 103 +Info (12133): Instantiated megafunction "my_pll:my_pll|altpll:altpll_component" with the following parameter: File: F:/Code/FPGA/reserve/dpwm/ip/my_pll.v Line: 103 + Info (12134): Parameter "bandwidth_type" = "AUTO" + Info (12134): Parameter "clk0_divide_by" = "1" + Info (12134): Parameter "clk0_duty_cycle" = "50" + Info (12134): Parameter "clk0_multiply_by" = "5" + Info (12134): Parameter "clk0_phase_shift" = "0" + Info (12134): Parameter "compensate_clock" = "CLK0" + Info (12134): Parameter "inclk0_input_frequency" = "20000" + Info (12134): Parameter "intended_device_family" = "Cyclone IV E" + Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=my_pll" + Info (12134): Parameter "lpm_type" = "altpll" + Info (12134): Parameter "operation_mode" = "NORMAL" + Info (12134): Parameter "pll_type" = "AUTO" + Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" + Info (12134): Parameter "port_areset" = "PORT_USED" + Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" + Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" + Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" + Info (12134): Parameter "port_fbin" = "PORT_UNUSED" + Info (12134): Parameter "port_inclk0" = "PORT_USED" + Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_locked" = "PORT_USED" + Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" + Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" + Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" + Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" + Info (12134): Parameter "port_pllena" = "PORT_UNUSED" + Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" + Info (12134): Parameter "port_scandata" = "PORT_UNUSED" + Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" + Info (12134): Parameter "port_scandone" = "PORT_UNUSED" + Info (12134): Parameter "port_scanread" = "PORT_UNUSED" + Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" + Info (12134): Parameter "port_clk0" = "PORT_USED" + Info (12134): Parameter "port_clk1" = "PORT_UNUSED" + Info (12134): Parameter "port_clk2" = "PORT_UNUSED" + Info (12134): Parameter "port_clk3" = "PORT_UNUSED" + Info (12134): Parameter "port_clk4" = "PORT_UNUSED" + Info (12134): Parameter "port_clk5" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" + Info (12134): Parameter "self_reset_on_loss_lock" = "OFF" + Info (12134): Parameter "width_clock" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/my_pll_altpll1.v + Info (12023): Found entity 1: my_pll_altpll1 File: F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v Line: 30 +Info (12128): Elaborating entity "my_pll_altpll1" for hierarchy "my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated" File: d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf Line: 897 +Info (12128): Elaborating entity "dpwm" for hierarchy "dpwm:dpwm" File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v Line: 39 +Warning (10036): Verilog HDL or VHDL warning at dpwm.v(37): object "is_zero" assigned a value but never read File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 37 +Warning (14284): Synthesized away the following node(s): + Warning (14285): Synthesized away the following LCELL buffer node(s): + Warning (14320): Synthesized away node "de1" + Warning (14320): Synthesized away node "de2" + Warning (14320): Synthesized away node "de3" + Warning (14320): Synthesized away node "de3~ " + Warning (14320): Synthesized away node "de2~ " + Warning (14320): Synthesized away node "de1~ " + Warning (14320): Synthesized away node "de0" +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "delay_out[4]" is stuck at GND File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v Line: 15 + Warning (13410): Pin "delay_out[5]" is stuck at GND File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v Line: 15 + Warning (13410): Pin "delay_out[6]" is stuck at GND File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v Line: 15 + Warning (13410): Pin "delay_out[7]" is stuck at GND File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v Line: 15 +Info (286030): Timing-Driven Synthesis is running +Info (17016): Found the following redundant logic cells in design + Info (17048): Logic cell "dpwm:dpwm|de7" File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 42 + Info (17048): Logic cell "dpwm:dpwm|de6" File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 42 + Info (17048): Logic cell "dpwm:dpwm|de5" File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 42 + Info (17048): Logic cell "dpwm:dpwm|de4" File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 42 + Info (17048): Logic cell "dpwm:dpwm|delay0" File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 46 + Info (17048): Logic cell "dpwm:dpwm|delay1" File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 47 + Info (17048): Logic cell "dpwm:dpwm|delay2" File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 48 + Info (17048): Logic cell "dpwm:dpwm|delay3" File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 49 +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL +Warning (15897): PLL "my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|pll1" has parameter compensate_clock set to clock0 but port CLK[0] is not connected File: F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v Line: 50 +Warning (15899): PLL "my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected File: F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v Line: 50 +Info (21057): Implemented 56 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 10 input pins + Info (21059): Implemented 9 output pins + Info (21061): Implemented 36 logic cells + Info (21065): Implemented 1 PLLs +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 19 warnings + Info: Peak virtual memory: 4790 megabytes + Info: Processing ended: Mon Nov 05 21:21:01 2018 + Info: Elapsed time: 00:00:19 + Info: Total CPU time (on all processors): 00:00:43 + + diff --git a/dpwm/output_files/dpwm.map.smsg b/dpwm/output_files/dpwm.map.smsg new file mode 100644 index 0000000..654e9b3 --- /dev/null +++ b/dpwm/output_files/dpwm.map.smsg @@ -0,0 +1 @@ +Warning (10268): Verilog HDL information at dpwm.v(40): always construct contains both blocking and non-blocking assignments File: F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v Line: 40 diff --git a/dpwm/output_files/dpwm.map.summary b/dpwm/output_files/dpwm.map.summary new file mode 100644 index 0000000..383fcd2 --- /dev/null +++ b/dpwm/output_files/dpwm.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon Nov 05 21:21:01 2018 +Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Standard Edition +Revision Name : dpwm +Top-level Entity Name : dpwm_top +Family : Cyclone IV E +Total logic elements : 29 + Total combinational functions : 28 + Dedicated logic registers : 11 +Total registers : 11 +Total pins : 19 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 1 diff --git a/dpwm/output_files/dpwm.pin b/dpwm/output_files/dpwm.pin new file mode 100644 index 0000000..a9c5655 --- /dev/null +++ b/dpwm/output_files/dpwm.pin @@ -0,0 +1,326 @@ + -- Copyright (C) 2018 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +CHIP "dpwm" ASSIGNED TO AN: EP4CE10F17C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +VCCIO8 : A1 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 : +delay_out[4] : A10 : output : 2.5 V : : 7 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +delay_out[6] : A14 : output : 2.5 V : : 7 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +VCCIO7 : A16 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 1 : +GND : B2 : gnd : : : : +delay_out[5] : B3 : output : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +GND : B15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +VCCIO8 : C4 : power : : 2.5V : 8 : +GND : C5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +VCCIO8 : C7 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +VCCIO7 : C10 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 : +GND : C12 : gnd : : : : +VCCIO7 : C13 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 : +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +GND : D7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 7 : +GND : D10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 : +VCCD_PLL2 : D13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 6 : +clk : E1 : input : 2.5 V : : 1 : N +GND : E2 : gnd : : : : +VCCIO1 : E3 : power : : 2.5V : 1 : +GND : E4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 : +GNDA2 : E12 : gnd : : : : +GND : E13 : gnd : : : : +VCCIO6 : E14 : power : : 2.5V : 6 : +dpid[6] : E15 : input : 2.5 V : : 6 : N +dpid[7] : E16 : input : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 : +nSTATUS : F4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 7 : +VCCA2 : F12 : power : : 2.5V : : +delay_out[2] : F13 : output : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 : +delay_out[3] : F15 : output : 2.5 V : : 6 : N +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 : +VCCIO1 : G3 : power : : 2.5V : 1 : +GND : G4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 : +VCCINT : G6 : power : : 1.2V : : +VCCINT : G7 : power : : 1.2V : : +VCCINT : G8 : power : : 1.2V : : +VCCINT : G9 : power : : 1.2V : : +VCCINT : G10 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 6 : +MSEL2 : G12 : : : : 6 : +GND : G13 : gnd : : : : +VCCIO6 : G14 : power : : 2.5V : 6 : +delay_out[1] : G15 : output : 2.5 V : : 6 : N +delay_out[0] : G16 : output : 2.5 V : : 6 : N +~ALTERA_DCLK~ : H1 : output : 2.5 V : : 1 : N +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V : : 1 : N +TCK : H3 : input : : : 1 : +TDI : H4 : input : : : 1 : +nCONFIG : H5 : : : : 1 : +VCCINT : H6 : power : : 1.2V : : +GND : H7 : gnd : : : : +GND : H8 : gnd : : : : +GND : H9 : gnd : : : : +GND : H10 : gnd : : : : +VCCINT : H11 : power : : 1.2V : : +MSEL1 : H12 : : : : 6 : +MSEL0 : H13 : : : : 6 : +CONF_DONE : H14 : : : : 6 : +GND : H15 : gnd : : : : +GND : H16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 2 : +nCE : J3 : : : : 1 : +TDO : J4 : output : : : 1 : +TMS : J5 : input : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 2 : +GND : J7 : gnd : : : : +GND : J8 : gnd : : : : +GND : J9 : gnd : : : : +GND : J10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 5 : +dpid[1] : J12 : input : 2.5 V : : 5 : N +dpid[4] : J13 : input : 2.5 V : : 5 : N +dpid[0] : J14 : input : 2.5 V : : 5 : N +dpid[2] : J15 : input : 2.5 V : : 5 : N +dpid[3] : J16 : input : 2.5 V : : 5 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 2 : +VCCIO2 : K3 : power : : 2.5V : 2 : +GND : K4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 2 : +VCCINT : K7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 5 : +GND : K13 : gnd : : : : +VCCIO5 : K14 : power : : 2.5V : 5 : +dpid[5] : K15 : input : 2.5 V : : 5 : N +pwm_out : K16 : output : 2.5 V : : 5 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 2 : +VCCA1 : L5 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L12 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 5 : +GND+ : M1 : : : : 2 : +rst_n : M2 : input : 2.5 V : : 2 : N +VCCIO2 : M3 : power : : 2.5V : 2 : +GND : M4 : gnd : : : : +GNDA1 : M5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M12 : : : : 5 : +GND : M13 : gnd : : : : +VCCIO5 : M14 : power : : 2.5V : 5 : +GND+ : M15 : : : : 5 : +GND+ : M16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 3 : +VCCD_PLL1 : N4 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 3 : +GND : N7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 4 : +GND : N10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3 : +VCCIO3 : P4 : power : : 2.5V : 3 : +GND : P5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 3 : +VCCIO3 : P7 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 4 : +VCCIO4 : P10 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 4 : +GND : P12 : gnd : : : : +VCCIO4 : P13 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +GND : R2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 4 : +delay_out[7] : R10 : output : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : +GND : R15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 5 : +VCCIO3 : T1 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 : +VCCIO4 : T16 : power : : 2.5V : 4 : diff --git a/dpwm/output_files/dpwm.sld b/dpwm/output_files/dpwm.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/dpwm/output_files/dpwm.sld @@ -0,0 +1 @@ + diff --git a/dpwm/output_files/dpwm.sof b/dpwm/output_files/dpwm.sof new file mode 100644 index 0000000..31052e6 Binary files /dev/null and b/dpwm/output_files/dpwm.sof differ diff --git a/dpwm/output_files/dpwm.sta.rpt b/dpwm/output_files/dpwm.sta.rpt new file mode 100644 index 0000000..cbbdccd --- /dev/null +++ b/dpwm/output_files/dpwm.sta.rpt @@ -0,0 +1,863 @@ +Timing Analyzer report for dpwm +Mon Nov 05 21:21:17 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Slow 1200mV 85C Model Setup: 'clk' + 13. Slow 1200mV 85C Model Hold: 'clk' + 14. Slow 1200mV 85C Model Metastability Summary + 15. Slow 1200mV 0C Model Fmax Summary + 16. Slow 1200mV 0C Model Setup Summary + 17. Slow 1200mV 0C Model Hold Summary + 18. Slow 1200mV 0C Model Recovery Summary + 19. Slow 1200mV 0C Model Removal Summary + 20. Slow 1200mV 0C Model Minimum Pulse Width Summary + 21. Slow 1200mV 0C Model Setup: 'clk' + 22. Slow 1200mV 0C Model Hold: 'clk' + 23. Slow 1200mV 0C Model Metastability Summary + 24. Fast 1200mV 0C Model Setup Summary + 25. Fast 1200mV 0C Model Hold Summary + 26. Fast 1200mV 0C Model Recovery Summary + 27. Fast 1200mV 0C Model Removal Summary + 28. Fast 1200mV 0C Model Minimum Pulse Width Summary + 29. Fast 1200mV 0C Model Setup: 'clk' + 30. Fast 1200mV 0C Model Hold: 'clk' + 31. Fast 1200mV 0C Model Metastability Summary + 32. Multicorner Timing Analysis Summary + 33. Board Trace Model Assignments + 34. Input Transition Times + 35. Signal Integrity Metrics (Slow 1200mv 0c Model) + 36. Signal Integrity Metrics (Slow 1200mv 85c Model) + 37. Signal Integrity Metrics (Fast 1200mv 0c Model) + 38. Setup Transfers + 39. Hold Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths Summary + 43. Clock Status Summary + 44. Unconstrained Input Ports + 45. Unconstrained Output Ports + 46. Unconstrained Input Ports + 47. Unconstrained Output Ports + 48. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+---------------------------------------------------------+ +; Quartus Prime Version ; Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; dpwm ; +; Device Family ; Cyclone IV E ; +; Device Name ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+---------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.3% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+------------+---------------------------------------------------------------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+---------------------------------------------------------------+ +; 416.84 MHz ; 250.0 MHz ; clk ; limit due to minimum period restriction (max I/O toggle rate) ; ++------------+-----------------+------------+---------------------------------------------------------------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++-------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++-------+--------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+--------------------+ +; clk ; -1.399 ; -8.279 ; ++-------+--------+--------------------+ + + ++------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++-------+-------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+--------------------+ +; clk ; 0.465 ; 0.000 ; ++-------+-------+--------------------+ + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++-------+--------+----------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+----------------------------------+ +; clk ; -3.000 ; -17.870 ; ++-------+--------+----------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'clk' ; ++--------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; -1.399 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.081 ; 2.319 ; +; -1.253 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.081 ; 2.173 ; +; -1.229 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.149 ; +; -1.223 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.081 ; 2.143 ; +; -1.164 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.084 ; +; -1.134 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.081 ; 2.054 ; +; -1.107 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 1.000 ; -0.081 ; 2.027 ; +; -1.093 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.081 ; 2.013 ; +; -1.083 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.081 ; 2.003 ; +; -1.077 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.081 ; 1.997 ; +; -1.047 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.081 ; 1.967 ; +; -1.018 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.081 ; 1.938 ; +; -1.018 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.081 ; 1.938 ; +; -0.988 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.081 ; 1.908 ; +; -0.988 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.081 ; 1.908 ; +; -0.947 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.081 ; 1.867 ; +; -0.931 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 1.000 ; -0.081 ; 1.851 ; +; -0.928 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.081 ; 1.848 ; +; -0.901 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.393 ; 2.295 ; +; -0.901 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.081 ; 1.821 ; +; -0.901 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.081 ; 1.821 ; +; -0.836 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.393 ; 2.230 ; +; -0.808 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|bit_high_syn ; clk ; clk ; 1.000 ; -0.574 ; 1.235 ; +; -0.765 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.393 ; 2.159 ; +; -0.690 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.393 ; 2.084 ; +; -0.600 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.393 ; 1.994 ; +; -0.543 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.393 ; 1.937 ; +; -0.499 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 1.000 ; -0.081 ; 1.419 ; +; -0.453 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.393 ; 1.847 ; +; -0.362 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 1.000 ; -0.081 ; 1.282 ; +; -0.344 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.081 ; 1.264 ; +; -0.343 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.081 ; 1.263 ; +; -0.319 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.081 ; 1.239 ; +; -0.319 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 1.000 ; -0.081 ; 1.239 ; +; -0.318 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.081 ; 1.238 ; +; -0.156 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; -0.100 ; 1.057 ; +; 0.015 ; dpwm:dpwm|bit_high_syn ; dpwm:dpwm|n_bit_high_syn ; clk ; clk ; 1.000 ; -0.081 ; 0.905 ; +; 0.062 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[0] ; clk ; clk ; 1.000 ; -0.081 ; 0.858 ; ++--------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'clk' ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; 0.465 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[0] ; clk ; clk ; 0.000 ; 0.081 ; 0.758 ; +; 0.491 ; dpwm:dpwm|bit_high_syn ; dpwm:dpwm|n_bit_high_syn ; clk ; clk ; 0.000 ; 0.081 ; 0.784 ; +; 0.595 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.574 ; 1.381 ; +; 0.612 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.574 ; 1.398 ; +; 0.660 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.100 ; 0.972 ; +; 0.734 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.027 ; +; 0.735 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.028 ; +; 0.735 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.028 ; +; 0.735 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 0.000 ; 0.081 ; 1.028 ; +; 0.736 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.081 ; 1.029 ; +; 0.736 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.574 ; 1.522 ; +; 0.753 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.574 ; 1.539 ; +; 0.781 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 0.000 ; 0.081 ; 1.074 ; +; 0.876 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.574 ; 1.662 ; +; 0.920 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.574 ; 1.706 ; +; 0.947 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 0.000 ; 0.081 ; 1.240 ; +; 1.089 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.382 ; +; 1.089 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.081 ; 1.382 ; +; 1.090 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.574 ; 1.876 ; +; 1.096 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.389 ; +; 1.097 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.390 ; +; 1.106 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.399 ; +; 1.124 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 0.000 ; 0.081 ; 1.417 ; +; 1.133 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.081 ; 1.426 ; +; 1.220 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.513 ; +; 1.220 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.513 ; +; 1.229 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.522 ; +; 1.237 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.530 ; +; 1.264 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.557 ; +; 1.273 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.566 ; +; 1.280 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 0.000 ; 0.081 ; 1.573 ; +; 1.303 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.081 ; 1.596 ; +; 1.347 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|bit_high_syn ; clk ; clk ; 0.000 ; -0.393 ; 1.166 ; +; 1.360 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.653 ; +; 1.404 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.697 ; +; 1.420 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.713 ; +; 1.443 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.736 ; +; 1.560 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.853 ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++-----------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+------------+---------------------------------------------------------------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+---------------------------------------------------------------+ +; 456.41 MHz ; 250.0 MHz ; clk ; limit due to minimum period restriction (max I/O toggle rate) ; ++------------+-----------------+------------+---------------------------------------------------------------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++-------+--------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-------------------+ +; clk ; -1.191 ; -6.874 ; ++-------+--------+-------------------+ + + ++-----------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++-------+-------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+-------------------+ +; clk ; 0.417 ; 0.000 ; ++-------+-------+-------------------+ + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++-------+--------+---------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------------------------+ +; clk ; -3.000 ; -17.870 ; ++-------+--------+---------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'clk' ; ++--------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; -1.191 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.072 ; 2.121 ; +; -1.065 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.072 ; 1.995 ; +; -1.026 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.072 ; 1.956 ; +; -1.011 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.941 ; +; -0.941 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.072 ; 1.871 ; +; -0.939 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 1.000 ; -0.072 ; 1.869 ; +; -0.902 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.832 ; +; -0.900 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.072 ; 1.830 ; +; -0.885 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.072 ; 1.815 ; +; -0.874 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.072 ; 1.804 ; +; -0.858 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.788 ; +; -0.815 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.072 ; 1.745 ; +; -0.814 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.072 ; 1.744 ; +; -0.776 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.072 ; 1.706 ; +; -0.775 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.705 ; +; -0.759 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 1.000 ; -0.072 ; 1.689 ; +; -0.748 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.072 ; 1.678 ; +; -0.732 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.072 ; 1.662 ; +; -0.732 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.072 ; 1.662 ; +; -0.731 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.661 ; +; -0.704 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.376 ; 2.082 ; +; -0.702 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|bit_high_syn ; clk ; clk ; 1.000 ; -0.539 ; 1.165 ; +; -0.619 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.376 ; 1.997 ; +; -0.552 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.376 ; 1.930 ; +; -0.492 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.376 ; 1.870 ; +; -0.410 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.376 ; 1.788 ; +; -0.365 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.376 ; 1.743 ; +; -0.347 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 1.000 ; -0.072 ; 1.277 ; +; -0.283 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.376 ; 1.661 ; +; -0.228 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 1.000 ; -0.072 ; 1.158 ; +; -0.212 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.072 ; 1.142 ; +; -0.211 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.072 ; 1.141 ; +; -0.192 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 1.000 ; -0.072 ; 1.122 ; +; -0.191 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.072 ; 1.121 ; +; -0.190 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.072 ; 1.120 ; +; -0.072 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; -0.091 ; 0.983 ; +; 0.107 ; dpwm:dpwm|bit_high_syn ; dpwm:dpwm|n_bit_high_syn ; clk ; clk ; 1.000 ; -0.072 ; 0.823 ; +; 0.160 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[0] ; clk ; clk ; 1.000 ; -0.072 ; 0.770 ; ++--------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'clk' ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; 0.417 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[0] ; clk ; clk ; 0.000 ; 0.072 ; 0.684 ; +; 0.455 ; dpwm:dpwm|bit_high_syn ; dpwm:dpwm|n_bit_high_syn ; clk ; clk ; 0.000 ; 0.072 ; 0.722 ; +; 0.541 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.539 ; 1.275 ; +; 0.551 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.539 ; 1.285 ; +; 0.595 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.091 ; 0.881 ; +; 0.664 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.539 ; 1.398 ; +; 0.673 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.539 ; 1.407 ; +; 0.684 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.072 ; 0.951 ; +; 0.684 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.072 ; 0.951 ; +; 0.684 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.072 ; 0.951 ; +; 0.685 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.072 ; 0.952 ; +; 0.685 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 0.000 ; 0.072 ; 0.952 ; +; 0.728 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 0.000 ; 0.072 ; 0.995 ; +; 0.786 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.539 ; 1.520 ; +; 0.820 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.539 ; 1.554 ; +; 0.844 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 0.000 ; 0.072 ; 1.111 ; +; 0.994 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.539 ; 1.728 ; +; 1.003 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.270 ; +; 1.003 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.072 ; 1.270 ; +; 1.009 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.072 ; 1.276 ; +; 1.009 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.072 ; 1.276 ; +; 1.018 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.072 ; 1.285 ; +; 1.027 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 0.000 ; 0.072 ; 1.294 ; +; 1.043 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.072 ; 1.310 ; +; 1.102 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.369 ; +; 1.103 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.072 ; 1.370 ; +; 1.125 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.392 ; +; 1.131 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.072 ; 1.398 ; +; 1.148 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 0.000 ; 0.072 ; 1.415 ; +; 1.149 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.072 ; 1.416 ; +; 1.165 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.072 ; 1.432 ; +; 1.217 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.072 ; 1.484 ; +; 1.225 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.492 ; +; 1.246 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|bit_high_syn ; clk ; clk ; 0.000 ; -0.376 ; 1.065 ; +; 1.270 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.072 ; 1.537 ; +; 1.271 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.538 ; +; 1.339 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.072 ; 1.606 ; +; 1.392 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.659 ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++-------+-------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+--------------------+ +; clk ; 0.003 ; 0.000 ; ++-------+-------+--------------------+ + + ++-----------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++-------+-------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+-------------------+ +; clk ; 0.193 ; 0.000 ; ++-------+-------+-------------------+ + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++-------+--------+---------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------------------------+ +; clk ; -3.000 ; -13.675 ; ++-------+--------+---------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'clk' ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; 0.003 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.947 ; +; 0.032 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.037 ; 0.918 ; +; 0.057 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.893 ; +; 0.058 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.892 ; +; 0.061 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.037 ; 0.889 ; +; 0.071 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.037 ; 0.879 ; +; 0.097 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.037 ; 0.853 ; +; 0.100 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.037 ; 0.850 ; +; 0.125 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.825 ; +; 0.125 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.037 ; 0.825 ; +; 0.126 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.037 ; 0.824 ; +; 0.129 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.037 ; 0.821 ; +; 0.129 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.037 ; 0.821 ; +; 0.138 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.812 ; +; 0.139 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 1.000 ; -0.037 ; 0.811 ; +; 0.156 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.155 ; 0.986 ; +; 0.165 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.037 ; 0.785 ; +; 0.178 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.037 ; 0.772 ; +; 0.185 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.155 ; 0.957 ; +; 0.194 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 1.000 ; -0.037 ; 0.756 ; +; 0.206 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.744 ; +; 0.206 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.037 ; 0.744 ; +; 0.221 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.155 ; 0.921 ; +; 0.230 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|bit_high_syn ; clk ; clk ; 1.000 ; -0.236 ; 0.521 ; +; 0.253 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.155 ; 0.889 ; +; 0.302 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.155 ; 0.840 ; +; 0.321 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.155 ; 0.821 ; +; 0.335 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 1.000 ; -0.037 ; 0.615 ; +; 0.369 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; 0.155 ; 0.773 ; +; 0.401 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 1.000 ; -0.037 ; 0.549 ; +; 0.412 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 1.000 ; -0.037 ; 0.538 ; +; 0.413 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 1.000 ; -0.037 ; 0.537 ; +; 0.422 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 1.000 ; -0.037 ; 0.528 ; +; 0.422 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 1.000 ; -0.037 ; 0.528 ; +; 0.422 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 1.000 ; -0.037 ; 0.528 ; +; 0.490 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 1.000 ; -0.044 ; 0.453 ; +; 0.575 ; dpwm:dpwm|bit_high_syn ; dpwm:dpwm|n_bit_high_syn ; clk ; clk ; 1.000 ; -0.037 ; 0.375 ; +; 0.591 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[0] ; clk ; clk ; 1.000 ; -0.037 ; 0.359 ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'clk' ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ +; 0.193 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[0] ; clk ; clk ; 0.000 ; 0.037 ; 0.314 ; +; 0.201 ; dpwm:dpwm|bit_high_syn ; dpwm:dpwm|n_bit_high_syn ; clk ; clk ; 0.000 ; 0.037 ; 0.322 ; +; 0.241 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.236 ; 0.561 ; +; 0.253 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.044 ; 0.381 ; +; 0.254 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.236 ; 0.574 ; +; 0.291 ; dpwm:dpwm|out_8bit[6] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.412 ; +; 0.292 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.413 ; +; 0.292 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.413 ; +; 0.292 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.037 ; 0.413 ; +; 0.292 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 0.000 ; 0.037 ; 0.413 ; +; 0.308 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.236 ; 0.628 ; +; 0.309 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 0.000 ; 0.037 ; 0.430 ; +; 0.320 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.236 ; 0.640 ; +; 0.362 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[1] ; clk ; clk ; 0.000 ; 0.037 ; 0.483 ; +; 0.374 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.236 ; 0.694 ; +; 0.398 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.236 ; 0.718 ; +; 0.441 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.562 ; +; 0.441 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.037 ; 0.562 ; +; 0.450 ; dpwm:dpwm|out_8bit[5] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.571 ; +; 0.450 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.571 ; +; 0.450 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[7] ; clk ; clk ; 0.000 ; 0.236 ; 0.770 ; +; 0.453 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.574 ; +; 0.462 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 0.000 ; 0.037 ; 0.583 ; +; 0.465 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.037 ; 0.586 ; +; 0.504 ; dpwm:dpwm|out_8bit[4] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.625 ; +; 0.504 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.625 ; +; 0.507 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.628 ; +; 0.514 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[2] ; clk ; clk ; 0.000 ; 0.037 ; 0.635 ; +; 0.516 ; dpwm:dpwm|out_8bit[3] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.637 ; +; 0.517 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[3] ; clk ; clk ; 0.000 ; 0.037 ; 0.638 ; +; 0.526 ; dpwm:dpwm|out_8bit[7] ; dpwm:dpwm|bit_high_syn ; clk ; clk ; 0.000 ; -0.155 ; 0.455 ; +; 0.528 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.649 ; +; 0.531 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.652 ; +; 0.570 ; dpwm:dpwm|out_8bit[2] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.691 ; +; 0.580 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[4] ; clk ; clk ; 0.000 ; 0.037 ; 0.701 ; +; 0.583 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[5] ; clk ; clk ; 0.000 ; 0.037 ; 0.704 ; +; 0.594 ; dpwm:dpwm|out_8bit[0] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.715 ; +; 0.646 ; dpwm:dpwm|out_8bit[1] ; dpwm:dpwm|out_8bit[6] ; clk ; clk ; 0.000 ; 0.037 ; 0.767 ; ++-------+------------------------+--------------------------+--------------+-------------+--------------+------------+------------+ + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+--------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+--------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -1.399 ; 0.193 ; N/A ; N/A ; -3.000 ; +; clk ; -1.399 ; 0.193 ; N/A ; N/A ; -3.000 ; +; Design-wide TNS ; -8.279 ; 0.0 ; 0.0 ; 0.0 ; -17.87 ; +; clk ; -8.279 ; 0.000 ; N/A ; N/A ; -17.870 ; ++------------------+--------+-------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; delay_out[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; delay_out[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; delay_out[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; delay_out[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; delay_out[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; delay_out[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; delay_out[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; delay_out[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; pwm_out ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; clk ; 2.5 V ; 2000 ps ; 2000 ps ; +; dpid[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; dpid[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; dpid[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; dpid[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; dpid[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; dpid[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; dpid[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; dpid[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; rst_n ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; delay_out[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; delay_out[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; delay_out[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.38 V ; -0.0073 V ; 0.097 V ; 0.018 V ; 4.24e-10 s ; 3.65e-10 s ; No ; Yes ; 2.32 V ; 2.07e-09 V ; 2.38 V ; -0.0073 V ; 0.097 V ; 0.018 V ; 4.24e-10 s ; 3.65e-10 s ; No ; Yes ; +; delay_out[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; delay_out[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; delay_out[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; delay_out[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; delay_out[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; pwm_out ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; delay_out[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; delay_out[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; delay_out[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.35 V ; -0.00834 V ; 0.127 V ; 0.035 V ; 4.7e-10 s ; 4.64e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.35 V ; -0.00834 V ; 0.127 V ; 0.035 V ; 4.7e-10 s ; 4.64e-10 s ; Yes ; Yes ; +; delay_out[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; delay_out[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; delay_out[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; delay_out[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; delay_out[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; pwm_out ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; delay_out[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; delay_out[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; delay_out[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; delay_out[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; delay_out[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; delay_out[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; delay_out[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; delay_out[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; pwm_out ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk ; clk ; 38 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk ; clk ; 38 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 9 ; 9 ; +; Unconstrained Input Port Paths ; 33 ; 33 ; +; Unconstrained Output Ports ; 5 ; 5 ; +; Unconstrained Output Port Paths ; 66 ; 66 ; ++---------------------------------+-------+------+ + + ++-------------------------------------+ +; Clock Status Summary ; ++--------+-------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++--------+-------+------+-------------+ +; clk ; clk ; Base ; Constrained ; ++--------+-------+------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; dpid[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++--------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++--------------+---------------------------------------------------------------------------------------+ +; delay_out[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; delay_out[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; delay_out[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; delay_out[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; pwm_out ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++--------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; dpid[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; dpid[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++--------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++--------------+---------------------------------------------------------------------------------------+ +; delay_out[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; delay_out[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; delay_out[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; delay_out[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; pwm_out ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++--------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + Info: Processing started: Mon Nov 05 21:21:15 2018 +Info: Command: quartus_sta dpwm -c dpwm +Info: qsta_default_script.tcl version: #2 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'dpwm.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name clk clk +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -1.399 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -1.399 -8.279 clk +Info (332146): Worst-case hold slack is 0.465 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.465 0.000 clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -3.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -3.000 -17.870 clk +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -1.191 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -1.191 -6.874 clk +Info (332146): Worst-case hold slack is 0.417 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.417 0.000 clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -3.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -3.000 -17.870 clk +Info: Analyzing Fast 1200mV 0C Model +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info (332146): Worst-case setup slack is 0.003 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.003 0.000 clk +Info (332146): Worst-case hold slack is 0.193 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.193 0.000 clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case minimum pulse width slack is -3.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -3.000 -13.675 clk +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 4776 megabytes + Info: Processing ended: Mon Nov 05 21:21:17 2018 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/dpwm/output_files/dpwm.sta.summary b/dpwm/output_files/dpwm.sta.summary new file mode 100644 index 0000000..6f1bacc --- /dev/null +++ b/dpwm/output_files/dpwm.sta.summary @@ -0,0 +1,41 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1200mV 85C Model Setup 'clk' +Slack : -1.399 +TNS : -8.279 + +Type : Slow 1200mV 85C Model Hold 'clk' +Slack : 0.465 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk' +Slack : -3.000 +TNS : -17.870 + +Type : Slow 1200mV 0C Model Setup 'clk' +Slack : -1.191 +TNS : -6.874 + +Type : Slow 1200mV 0C Model Hold 'clk' +Slack : 0.417 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk' +Slack : -3.000 +TNS : -17.870 + +Type : Fast 1200mV 0C Model Setup 'clk' +Slack : 0.003 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'clk' +Slack : 0.193 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk' +Slack : -3.000 +TNS : -13.675 + +------------------------------------------------------------ diff --git a/dpwm/rtl/clk_mux.v b/dpwm/rtl/clk_mux.v new file mode 100644 index 0000000..07e0fc5 --- /dev/null +++ b/dpwm/rtl/clk_mux.v @@ -0,0 +1,26 @@ +module clk_mux( + + rst_n, + clk_0, + clk_180, + sel_clk, + clk_out +); + + input clk_0; + input clk_180; + input sel_clk; + output reg clk_out; + input rst_n; + + always @ (posedge clk_0 or posedge clk_180 or negedge rst_n) + if(!rst_n) + clk_out <= 1'b0; + else + case(sel_clk) + 0:clk_out <= clk_0; + 1:clk_out <= clk_180; + endcase + +endmodule + diff --git a/dpwm/rtl/clk_mux.v.bak b/dpwm/rtl/clk_mux.v.bak new file mode 100644 index 0000000..5901754 --- /dev/null +++ b/dpwm/rtl/clk_mux.v.bak @@ -0,0 +1,26 @@ +module clk_mux( + + rst_n, + clk_0, + clk_180, + sel_clk, + clk_out, +); + + input clk_0, + input clk_180, + input sel_clk, + output clk_out, + input rst_n, + + always @ (posedge clk_0 or posedge clk_180 or negedge rst_n) + if(!rst_n) + clk_out <= 1'b0; + else + case(sel_clk) + 0:clk_out <= clk_0; + 1:clk_out <= clk_180; + endcase + +endmodule + diff --git a/dpwm/rtl/dpwm.v b/dpwm/rtl/dpwm.v new file mode 100644 index 0000000..64daccc --- /dev/null +++ b/dpwm/rtl/dpwm.v @@ -0,0 +1,110 @@ +module dpwm( + + clk, + clk_0, + rst_n, + pwm_crl, + delay_out, + pwm_out + + +); + + input clk; + input clk_0; + input rst_n; + input [7:0] pwm_crl; + + output pwm_out; + + reg n_next7; + reg bit_high_syn; + reg n_bit_high_syn; + + reg [7:0] out_8bit; + + wire [7:0] cnt_8; + + output delay_out; + + wire [7:0] delay_out/* synthesis keep="1" */; + + reg and_a,and_b,clear_delay_line; + + wire out_c; + + reg is_high/* synthesis preserve = 1 */; + reg is_zero; + + and (pwm_out,n_bit_high_syn,bit_high_syn); + and (out_c,and_a,and_b); + + wire de0,de1,de2,de3,de4,de5,de6,de7/* synthesis keep = 1 */; + + assign delay_out = {de0,de1,de2,de3,de4,de5,de6,de7}; + + lcell delay0 /* synthesis keep="1" */ (is_high,de7); + lcell delay1 /* synthesis keep="1" */ (de7, de6); + lcell delay2 /* synthesis keep="1" */ (de6, de5); + lcell delay3 /* synthesis keep="1" */ (de5, de4); + lcell delay4 /* synthesis keep="1" */ (de4, de3); + lcell delay5 /* synthesis keep="1" */ (de3, de2); + lcell delay6 /* synthesis keep="1" */ (de2, de1); + lcell delay7 /* synthesis keep="1" */ (de1, de0); + + + assign cnt_8 = out_8bit + 8'd1; + + + always @ (*) + if(cnt_8 >= pwm_crl) + is_high <= 1'b1; + else + is_high <= 1'b0; + + //always @ (posedge clk_0) + + + + + always @ (posedge clk or negedge rst_n) + if(!rst_n) + out_8bit <= 8'b0; + else + out_8bit <= out_8bit + 1'b1; + + always @ (*) + n_next7 = ~out_8bit[7]; + + always @(posedge clk) + begin + bit_high_syn <= n_next7; + n_bit_high_syn <= ~bit_high_syn; + end + + always @ (*) begin + if(out_8bit < 8'b1111_1111) + and_a = 1'b1; + else + and_a = 1'b0; + if(out_8bit >= pwm_crl) + and_b = 1'b1; + else + and_b = 1'b0; + end + + always @(posedge clk) begin + if(cnt_8 == 8'd0) + is_zero <= 1'b1; + else + is_zero <= 1'b0; + + end + + + + + + +endmodule + diff --git a/dpwm/rtl/dpwm.v.bak b/dpwm/rtl/dpwm.v.bak new file mode 100644 index 0000000..68ae602 --- /dev/null +++ b/dpwm/rtl/dpwm.v.bak @@ -0,0 +1 @@ +module \ No newline at end of file diff --git a/dpwm/rtl/dpwm001.v b/dpwm/rtl/dpwm001.v new file mode 100644 index 0000000..00a383f --- /dev/null +++ b/dpwm/rtl/dpwm001.v @@ -0,0 +1,73 @@ +module dpwm( + + clk_0, + rst_n, + control, + pwm_out + +); + + input clk_0; + input rst_n; + input [13:0] control; + + output reg pwm_out; + + wire set_pwm,rst_pwm; + + wire [10:0] new_duty; + + reg [9:0] cnt; + reg [7:0] shakenum; + reg clk_out; + + + wire [2:0] shake_ctr; + wire [10:0] cat_duty; + + + + assign shake_ctr = control[2:0]; + assign cat_duty = control[13:3]; + + assign set_pwm = (cnt == 1'b0) ? 1'b1:1'b0; + assign rst_pwm = (cnt == new_duty) ? 1'b1:1'b0; + + assign new_duty = shakenum + cat_duty; + + + always @(posedge clk_0 or negedge rst_n) + if(!rst_n) + cnt <= 1'b0; + else if(cnt == 10'd749) + cnt <= 1'b0; + else + cnt <= cnt + 1'b1; + + + always @ (*) + case(shake_ctr) + 3'd0: shakenum <= 8'b0000_0000; + 3'd1: shakenum <= 8'b0000_0001; + 3'd2: shakenum <= 8'b0001_0001; + 3'd3: shakenum <= 8'b0010_0101; + 3'd4: shakenum <= 8'b0101_0101; + 3'd5: shakenum <= 8'b0101_1011; + 3'd6: shakenum <= 8'b0111_0111; + 3'd7: shakenum <= 8'b0111_1111; + endcase + + always @(*) + begin + case({set_pwm,rst_pwm}) + 2'b00:pwm_out<=pwm_out; + 2'b01:pwm_out<=1'b0; + 2'b10:pwm_out<=1'b1; + 2'b11:pwm_out<=1'bx; + endcase + end + + + +endmodule + diff --git a/dpwm/rtl/dpwm_top.v b/dpwm/rtl/dpwm_top.v new file mode 100644 index 0000000..5a88d18 --- /dev/null +++ b/dpwm/rtl/dpwm_top.v @@ -0,0 +1,43 @@ +module dpwm_top( + + clk, + rst_n, + dpid, + delay_out, + pwm_out + +); + + input clk; + input rst_n; + input [7:0] dpid; + output pwm_out; + output [7:0] delay_out; + +// wire clk_0; +// wire areset; +// wire locked; + + +// assign areset = ~rst_n; + + +// my_pll my_pll ( +// .areset(areset), +// .inclk0(clk), +// .c0(clk_0), +// .locked(locked) +// ); + + dpwm dpwm( + .clk(clk), + .clk_0(clk), + .rst_n(rst_n), + .pwm_crl(dpid), + .delay_out(delay_out), + .pwm_out(pwm_out) + ); + + +endmodule + diff --git a/dpwm/rtl/dpwm_top.v.bak b/dpwm/rtl/dpwm_top.v.bak new file mode 100644 index 0000000..f2581cd --- /dev/null +++ b/dpwm/rtl/dpwm_top.v.bak @@ -0,0 +1,9 @@ +module dpwm_top( + + + +); + + +endmodule + diff --git a/dpwm/rtl/jk_trigger.v b/dpwm/rtl/jk_trigger.v new file mode 100644 index 0000000..f25bff4 --- /dev/null +++ b/dpwm/rtl/jk_trigger.v @@ -0,0 +1,26 @@ +module jk_trigger( + + j, + k, + q +); + + input j; + input k; + + + + output reg q; + + always @(*) + begin + case({j,k}) + 2'b00:q<=q; + 2'b01:q<=1'b0; + 2'b10:q<=1'b1; + 2'b11:q<=1'bx; + endcase + end + +endmodule + diff --git a/dpwm/rtl/jk_trigger.v.bak b/dpwm/rtl/jk_trigger.v.bak new file mode 100644 index 0000000..3b7d394 --- /dev/null +++ b/dpwm/rtl/jk_trigger.v.bak @@ -0,0 +1,35 @@ +module jk_trigger( + + j, + k, + clk, + rst_n, + set, + q +); + + input j; + input k; + input clk; + input rst_n; + input set; + output reg q; + + always @(posedge clk or negedge rst_n or negedge set) + if(!rst_n) begin + q <= 1'b0; + end + else if(!set) + q<= 1'b1; + else begin + case({j,k}) + 2'b00:q<=q; + 2'b01:q<=1'b0; + 2'b10:q<=1'b1; + 2'b11:q<=~q; + endcase + + end + +endmodule + diff --git a/dpwm/rtl/pwm_prt.v b/dpwm/rtl/pwm_prt.v new file mode 100644 index 0000000..f85360d --- /dev/null +++ b/dpwm/rtl/pwm_prt.v @@ -0,0 +1,39 @@ +module pwm_prt( + + clk_0, + clk_180, + rst_pwm, + set_pwm, + sel_clk, + pwm_out + +); + input clk_0,clk_180; + input rst_pwm; + input set_pwm; + input sel_clk; + + output reg pwm_out; + + reg clk_out; + + wire r; + + and (r,clk_out,rst_pwm); + + always @ (posedge clk_0 or posedge clk_180) + case(sel_clk) + 0: clk_out = clk_0; + 1: clk_out = clk_180; + endcase + + always @(*) + begin + case({set_pwm,r}) + 2'b00:pwm_out<=pwm_out; + 2'b01:pwm_out<=1'b0; + 2'b10:pwm_out<=1'b1; + 2'b11:pwm_out<=1'bx; + endcase + end +endmodule diff --git a/dpwm/rtl/pwm_prt.v.bak b/dpwm/rtl/pwm_prt.v.bak new file mode 100644 index 0000000..0dec998 --- /dev/null +++ b/dpwm/rtl/pwm_prt.v.bak @@ -0,0 +1,25 @@ +module pwm_prt( + + clk_in, + rst_pwm, + set_pwm, + + pwm_out + +); + input clk_in; + input rst_pwm; + input set_pwm; + + output pwm_out; + + and() + + jk_trigger jk_trigger( + + .j(), + .k(), + .q() +); + +endmodule diff --git a/dpwm/rtl/shake.v b/dpwm/rtl/shake.v new file mode 100644 index 0000000..dc0ce25 --- /dev/null +++ b/dpwm/rtl/shake.v @@ -0,0 +1,49 @@ +module shake( + + clk, + rst_n, + control, + new_duty +); + + input clk; + input rst_n; + input [13:0] control; + + output reg [10:0] new_duty; + + reg [7:0] shakenum; + + reg [7:0] cnt; + + always @ (posedge clk or negedge rst_n) + if(!rst_n) + cnt <= 0; + else if(cnt >=249) + cnt <= 0; + else + cnt <= cnt + 1'b1; + + always @ (posedge clk or negedge rst_n) + if(!rst_n) + new_duty <= 0; + else if(cnt >=249) + new_duty <= shakenum + control[13:3]; + + always @ (posedge clk or negedge rst_n) + if(!rst_n) + shakenum <= 0; + else if(cnt >=249) + case(control[2:0]) + 0: shakenum <= 8'b0000_0000; + 1: shakenum <= 8'b0000_0001; + 2: shakenum <= 8'b0001_0001; + 3: shakenum <= 8'b0010_0101; + 4: shakenum <= 8'b0101_0101; + 5: shakenum <= 8'b0101_1011; + 6: shakenum <= 8'b0111_0111; + 7: shakenum <= 8'b0111_1111; + endcase + + +endmodule diff --git a/dpwm/rtl/shake.v.bak b/dpwm/rtl/shake.v.bak new file mode 100644 index 0000000..f669aa6 --- /dev/null +++ b/dpwm/rtl/shake.v.bak @@ -0,0 +1,40 @@ +module my_shake( + + clk, + rst_n, + + control, + + new_duty + + +); + + input clk; + input rst_n; + input [10:0] control; + + + input shake_counter + + output new_duty; + + reg shake_num; + + always @ (posedge clk or negedge rst_n) + if(!rst_n) + shake_num <= 0; + else + case(control[2:0]) + 0: shakenum <= 8'b0000_0000; + 1: shakenum <= 8'b0000_0001; + 2: shakenum <= 8'b0001_0001; + 3: shakenum <= 8'b0010_0101; + 4: shakenum <= 8'b0101_0101; + 5: shakenum <= 8'b0101_1011; + 6: shakenum <= 8'b0111_0111; + 7: shakenum <= 8'b0111_1111; + endcase + + +endmodule diff --git a/dpwm/simulation/modelsim/dpwm.sft b/dpwm/simulation/modelsim/dpwm.sft new file mode 100644 index 0000000..16129cb --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim-Altera (Verilog)" +set corner_file_list { + {{"Slow -8 1.2V 85 Model"} {dpwm_8_1200mv_85c_slow.vo dpwm_8_1200mv_85c_v_slow.sdo}} + {{"Slow -8 1.2V 0 Model"} {dpwm_8_1200mv_0c_slow.vo dpwm_8_1200mv_0c_v_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {dpwm_min_1200mv_0c_fast.vo dpwm_min_1200mv_0c_v_fast.sdo}} +} diff --git a/dpwm/simulation/modelsim/dpwm.vo b/dpwm/simulation/modelsim/dpwm.vo new file mode 100644 index 0000000..fc0c8d6 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm.vo @@ -0,0 +1,1224 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" + +// DATE "11/05/2018 21:21:20" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module dpwm_top ( + clk, + rst_n, + dpid, + delay_out, + pwm_out); +input clk; +input rst_n; +input [7:0] dpid; +output [7:0] delay_out; +output pwm_out; + +// Design Ports Information +// delay_out[0] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[1] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[2] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[3] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[4] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[5] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[6] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[7] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default +// pwm_out => Location: PIN_K16, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// dpid[7] => Location: PIN_E16, I/O Standard: 2.5 V, Current Strength: Default +// dpid[6] => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[5] => Location: PIN_K15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[4] => Location: PIN_J13, I/O Standard: 2.5 V, Current Strength: Default +// dpid[3] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default +// dpid[2] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[1] => Location: PIN_J12, I/O Standard: 2.5 V, Current Strength: Default +// dpid[0] => Location: PIN_J14, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("dpwm_v.sdo"); +// synopsys translate_on + +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \clk~input_o ; +wire \clk~inputclkctrl_outclk ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \my_pll|altpll_component|auto_generated|locked~combout ; +wire \my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ; +wire \dpwm|out_8bit[0]~0_combout ; +wire \dpwm|Add0~0_combout ; +wire \dpwm|Add0~1 ; +wire \dpwm|Add0~2_combout ; +wire \dpwm|Add0~3 ; +wire \dpwm|Add0~4_combout ; +wire \dpwm|Add0~5 ; +wire \dpwm|Add0~6_combout ; +wire \dpwm|Add0~7 ; +wire \dpwm|Add0~8_combout ; +wire \dpwm|Add0~9 ; +wire \dpwm|Add0~10_combout ; +wire \dpwm|Add0~11 ; +wire \dpwm|Add0~12_combout ; +wire \dpid[7]~input_o ; +wire \dpid[6]~input_o ; +wire \dpid[5]~input_o ; +wire \dpid[4]~input_o ; +wire \dpid[3]~input_o ; +wire \dpid[2]~input_o ; +wire \dpid[1]~input_o ; +wire \dpid[0]~input_o ; +wire \dpwm|LessThan0~1_cout ; +wire \dpwm|LessThan0~3_cout ; +wire \dpwm|LessThan0~5_cout ; +wire \dpwm|LessThan0~7_cout ; +wire \dpwm|LessThan0~9_cout ; +wire \dpwm|LessThan0~11_cout ; +wire \dpwm|LessThan0~13_cout ; +wire \dpwm|LessThan0~14_combout ; +wire \dpwm|delay0~combout ; +wire \dpwm|de7~combout ; +wire \dpwm|delay1~combout ; +wire \dpwm|de6~combout ; +wire \dpwm|delay2~combout ; +wire \dpwm|de5~combout ; +wire \dpwm|delay3~combout ; +wire \dpwm|de4~combout ; +wire \dpwm|bit_high_syn~0_combout ; +wire \dpwm|bit_high_syn~q ; +wire \dpwm|n_bit_high_syn~0_combout ; +wire \dpwm|n_bit_high_syn~q ; +wire \dpwm|pwm_out~combout ; +wire [4:0] \my_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \dpwm|out_8bit ; + +wire [4:0] \my_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X34_Y17_N23 +cycloneive_io_obuf \delay_out[0]~output ( + .i(\dpwm|de7~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[0]), + .obar()); +// synopsys translate_off +defparam \delay_out[0]~output .bus_hold = "false"; +defparam \delay_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N16 +cycloneive_io_obuf \delay_out[1]~output ( + .i(\dpwm|de6~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[1]), + .obar()); +// synopsys translate_off +defparam \delay_out[1]~output .bus_hold = "false"; +defparam \delay_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N2 +cycloneive_io_obuf \delay_out[2]~output ( + .i(\dpwm|de5~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[2]), + .obar()); +// synopsys translate_off +defparam \delay_out[2]~output .bus_hold = "false"; +defparam \delay_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y18_N16 +cycloneive_io_obuf \delay_out[3]~output ( + .i(\dpwm|de4~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[3]), + .obar()); +// synopsys translate_off +defparam \delay_out[3]~output .bus_hold = "false"; +defparam \delay_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X21_Y24_N9 +cycloneive_io_obuf \delay_out[4]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[4]), + .obar()); +// synopsys translate_off +defparam \delay_out[4]~output .bus_hold = "false"; +defparam \delay_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y24_N23 +cycloneive_io_obuf \delay_out[5]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[5]), + .obar()); +// synopsys translate_off +defparam \delay_out[5]~output .bus_hold = "false"; +defparam \delay_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y24_N2 +cycloneive_io_obuf \delay_out[6]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[6]), + .obar()); +// synopsys translate_off +defparam \delay_out[6]~output .bus_hold = "false"; +defparam \delay_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X21_Y0_N9 +cycloneive_io_obuf \delay_out[7]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[7]), + .obar()); +// synopsys translate_off +defparam \delay_out[7]~output .bus_hold = "false"; +defparam \delay_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y9_N16 +cycloneive_io_obuf \pwm_out~output ( + .i(\dpwm|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out), + .obar()); +// synopsys translate_off +defparam \pwm_out~output .bus_hold = "false"; +defparam \pwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk~inputclkctrl .clock_type = "global clock"; +defparam \clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \my_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\my_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \my_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \my_pll|altpll_component|auto_generated|pll1 .m = 12; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .operation_mode = "no compensation"; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \my_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \my_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X1_Y4_N28 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y4_N29 +dffeas \my_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y4_N14 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|locked ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|locked~combout = (!\my_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\my_pll|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|locked~combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked .lut_mask = 16'h0FFF; +defparam \my_pll|altpll_component|auto_generated|locked .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G1 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|locked~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|locked~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X33_Y12_N31 +dffeas \dpwm|out_8bit[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~12_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[7] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N16 +cycloneive_lcell_comb \dpwm|out_8bit[0]~0 ( +// Equation(s): +// \dpwm|out_8bit[0]~0_combout = !\dpwm|out_8bit [0] + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|out_8bit [0]), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|out_8bit[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|out_8bit[0]~0 .lut_mask = 16'h0F0F; +defparam \dpwm|out_8bit[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y12_N17 +dffeas \dpwm|out_8bit[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|out_8bit[0]~0_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[0] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N18 +cycloneive_lcell_comb \dpwm|Add0~0 ( +// Equation(s): +// \dpwm|Add0~0_combout = (\dpwm|out_8bit [1] & (\dpwm|out_8bit [0] $ (VCC))) # (!\dpwm|out_8bit [1] & (\dpwm|out_8bit [0] & VCC)) +// \dpwm|Add0~1 = CARRY((\dpwm|out_8bit [1] & \dpwm|out_8bit [0])) + + .dataa(\dpwm|out_8bit [1]), + .datab(\dpwm|out_8bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm|Add0~0_combout ), + .cout(\dpwm|Add0~1 )); +// synopsys translate_off +defparam \dpwm|Add0~0 .lut_mask = 16'h6688; +defparam \dpwm|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y12_N19 +dffeas \dpwm|out_8bit[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~0_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[1] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N20 +cycloneive_lcell_comb \dpwm|Add0~2 ( +// Equation(s): +// \dpwm|Add0~2_combout = (\dpwm|out_8bit [2] & (!\dpwm|Add0~1 )) # (!\dpwm|out_8bit [2] & ((\dpwm|Add0~1 ) # (GND))) +// \dpwm|Add0~3 = CARRY((!\dpwm|Add0~1 ) # (!\dpwm|out_8bit [2])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~1 ), + .combout(\dpwm|Add0~2_combout ), + .cout(\dpwm|Add0~3 )); +// synopsys translate_off +defparam \dpwm|Add0~2 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N21 +dffeas \dpwm|out_8bit[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~2_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[2] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N22 +cycloneive_lcell_comb \dpwm|Add0~4 ( +// Equation(s): +// \dpwm|Add0~4_combout = (\dpwm|out_8bit [3] & (\dpwm|Add0~3 $ (GND))) # (!\dpwm|out_8bit [3] & (!\dpwm|Add0~3 & VCC)) +// \dpwm|Add0~5 = CARRY((\dpwm|out_8bit [3] & !\dpwm|Add0~3 )) + + .dataa(\dpwm|out_8bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~3 ), + .combout(\dpwm|Add0~4_combout ), + .cout(\dpwm|Add0~5 )); +// synopsys translate_off +defparam \dpwm|Add0~4 .lut_mask = 16'hA50A; +defparam \dpwm|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N23 +dffeas \dpwm|out_8bit[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~4_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[3] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N24 +cycloneive_lcell_comb \dpwm|Add0~6 ( +// Equation(s): +// \dpwm|Add0~6_combout = (\dpwm|out_8bit [4] & (!\dpwm|Add0~5 )) # (!\dpwm|out_8bit [4] & ((\dpwm|Add0~5 ) # (GND))) +// \dpwm|Add0~7 = CARRY((!\dpwm|Add0~5 ) # (!\dpwm|out_8bit [4])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~5 ), + .combout(\dpwm|Add0~6_combout ), + .cout(\dpwm|Add0~7 )); +// synopsys translate_off +defparam \dpwm|Add0~6 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N25 +dffeas \dpwm|out_8bit[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~6_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[4] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N26 +cycloneive_lcell_comb \dpwm|Add0~8 ( +// Equation(s): +// \dpwm|Add0~8_combout = (\dpwm|out_8bit [5] & (\dpwm|Add0~7 $ (GND))) # (!\dpwm|out_8bit [5] & (!\dpwm|Add0~7 & VCC)) +// \dpwm|Add0~9 = CARRY((\dpwm|out_8bit [5] & !\dpwm|Add0~7 )) + + .dataa(\dpwm|out_8bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~7 ), + .combout(\dpwm|Add0~8_combout ), + .cout(\dpwm|Add0~9 )); +// synopsys translate_off +defparam \dpwm|Add0~8 .lut_mask = 16'hA50A; +defparam \dpwm|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N27 +dffeas \dpwm|out_8bit[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~8_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[5] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N28 +cycloneive_lcell_comb \dpwm|Add0~10 ( +// Equation(s): +// \dpwm|Add0~10_combout = (\dpwm|out_8bit [6] & (!\dpwm|Add0~9 )) # (!\dpwm|out_8bit [6] & ((\dpwm|Add0~9 ) # (GND))) +// \dpwm|Add0~11 = CARRY((!\dpwm|Add0~9 ) # (!\dpwm|out_8bit [6])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~9 ), + .combout(\dpwm|Add0~10_combout ), + .cout(\dpwm|Add0~11 )); +// synopsys translate_off +defparam \dpwm|Add0~10 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N29 +dffeas \dpwm|out_8bit[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~10_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[6] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N30 +cycloneive_lcell_comb \dpwm|Add0~12 ( +// Equation(s): +// \dpwm|Add0~12_combout = \dpwm|Add0~11 $ (!\dpwm|out_8bit [7]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|out_8bit [7]), + .cin(\dpwm|Add0~11 ), + .combout(\dpwm|Add0~12_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|Add0~12 .lut_mask = 16'hF00F; +defparam \dpwm|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y12_N8 +cycloneive_io_ibuf \dpid[7]~input ( + .i(dpid[7]), + .ibar(gnd), + .o(\dpid[7]~input_o )); +// synopsys translate_off +defparam \dpid[7]~input .bus_hold = "false"; +defparam \dpid[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y12_N1 +cycloneive_io_ibuf \dpid[6]~input ( + .i(dpid[6]), + .ibar(gnd), + .o(\dpid[6]~input_o )); +// synopsys translate_off +defparam \dpid[6]~input .bus_hold = "false"; +defparam \dpid[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y9_N8 +cycloneive_io_ibuf \dpid[5]~input ( + .i(dpid[5]), + .ibar(gnd), + .o(\dpid[5]~input_o )); +// synopsys translate_off +defparam \dpid[5]~input .bus_hold = "false"; +defparam \dpid[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N1 +cycloneive_io_ibuf \dpid[4]~input ( + .i(dpid[4]), + .ibar(gnd), + .o(\dpid[4]~input_o )); +// synopsys translate_off +defparam \dpid[4]~input .bus_hold = "false"; +defparam \dpid[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y9_N1 +cycloneive_io_ibuf \dpid[3]~input ( + .i(dpid[3]), + .ibar(gnd), + .o(\dpid[3]~input_o )); +// synopsys translate_off +defparam \dpid[3]~input .bus_hold = "false"; +defparam \dpid[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N8 +cycloneive_io_ibuf \dpid[2]~input ( + .i(dpid[2]), + .ibar(gnd), + .o(\dpid[2]~input_o )); +// synopsys translate_off +defparam \dpid[2]~input .bus_hold = "false"; +defparam \dpid[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N8 +cycloneive_io_ibuf \dpid[1]~input ( + .i(dpid[1]), + .ibar(gnd), + .o(\dpid[1]~input_o )); +// synopsys translate_off +defparam \dpid[1]~input .bus_hold = "false"; +defparam \dpid[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N1 +cycloneive_io_ibuf \dpid[0]~input ( + .i(dpid[0]), + .ibar(gnd), + .o(\dpid[0]~input_o )); +// synopsys translate_off +defparam \dpid[0]~input .bus_hold = "false"; +defparam \dpid[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N0 +cycloneive_lcell_comb \dpwm|LessThan0~1 ( +// Equation(s): +// \dpwm|LessThan0~1_cout = CARRY((\dpwm|out_8bit [0] & \dpid[0]~input_o )) + + .dataa(\dpwm|out_8bit [0]), + .datab(\dpid[0]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\dpwm|LessThan0~1_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~1 .lut_mask = 16'h0088; +defparam \dpwm|LessThan0~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N2 +cycloneive_lcell_comb \dpwm|LessThan0~3 ( +// Equation(s): +// \dpwm|LessThan0~3_cout = CARRY((\dpid[1]~input_o & (\dpwm|Add0~0_combout & !\dpwm|LessThan0~1_cout )) # (!\dpid[1]~input_o & ((\dpwm|Add0~0_combout ) # (!\dpwm|LessThan0~1_cout )))) + + .dataa(\dpid[1]~input_o ), + .datab(\dpwm|Add0~0_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~1_cout ), + .combout(), + .cout(\dpwm|LessThan0~3_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~3 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N4 +cycloneive_lcell_comb \dpwm|LessThan0~5 ( +// Equation(s): +// \dpwm|LessThan0~5_cout = CARRY((\dpwm|Add0~2_combout & (\dpid[2]~input_o & !\dpwm|LessThan0~3_cout )) # (!\dpwm|Add0~2_combout & ((\dpid[2]~input_o ) # (!\dpwm|LessThan0~3_cout )))) + + .dataa(\dpwm|Add0~2_combout ), + .datab(\dpid[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~3_cout ), + .combout(), + .cout(\dpwm|LessThan0~5_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~5 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N6 +cycloneive_lcell_comb \dpwm|LessThan0~7 ( +// Equation(s): +// \dpwm|LessThan0~7_cout = CARRY((\dpid[3]~input_o & (\dpwm|Add0~4_combout & !\dpwm|LessThan0~5_cout )) # (!\dpid[3]~input_o & ((\dpwm|Add0~4_combout ) # (!\dpwm|LessThan0~5_cout )))) + + .dataa(\dpid[3]~input_o ), + .datab(\dpwm|Add0~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~5_cout ), + .combout(), + .cout(\dpwm|LessThan0~7_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~7 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N8 +cycloneive_lcell_comb \dpwm|LessThan0~9 ( +// Equation(s): +// \dpwm|LessThan0~9_cout = CARRY((\dpwm|Add0~6_combout & (\dpid[4]~input_o & !\dpwm|LessThan0~7_cout )) # (!\dpwm|Add0~6_combout & ((\dpid[4]~input_o ) # (!\dpwm|LessThan0~7_cout )))) + + .dataa(\dpwm|Add0~6_combout ), + .datab(\dpid[4]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~7_cout ), + .combout(), + .cout(\dpwm|LessThan0~9_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~9 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N10 +cycloneive_lcell_comb \dpwm|LessThan0~11 ( +// Equation(s): +// \dpwm|LessThan0~11_cout = CARRY((\dpid[5]~input_o & (\dpwm|Add0~8_combout & !\dpwm|LessThan0~9_cout )) # (!\dpid[5]~input_o & ((\dpwm|Add0~8_combout ) # (!\dpwm|LessThan0~9_cout )))) + + .dataa(\dpid[5]~input_o ), + .datab(\dpwm|Add0~8_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~9_cout ), + .combout(), + .cout(\dpwm|LessThan0~11_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~11 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N12 +cycloneive_lcell_comb \dpwm|LessThan0~13 ( +// Equation(s): +// \dpwm|LessThan0~13_cout = CARRY((\dpwm|Add0~10_combout & (\dpid[6]~input_o & !\dpwm|LessThan0~11_cout )) # (!\dpwm|Add0~10_combout & ((\dpid[6]~input_o ) # (!\dpwm|LessThan0~11_cout )))) + + .dataa(\dpwm|Add0~10_combout ), + .datab(\dpid[6]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~11_cout ), + .combout(), + .cout(\dpwm|LessThan0~13_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~13 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N14 +cycloneive_lcell_comb \dpwm|LessThan0~14 ( +// Equation(s): +// \dpwm|LessThan0~14_combout = (\dpwm|Add0~12_combout & (\dpwm|LessThan0~13_cout & \dpid[7]~input_o )) # (!\dpwm|Add0~12_combout & ((\dpwm|LessThan0~13_cout ) # (\dpid[7]~input_o ))) + + .dataa(\dpwm|Add0~12_combout ), + .datab(gnd), + .datac(gnd), + .datad(\dpid[7]~input_o ), + .cin(\dpwm|LessThan0~13_cout ), + .combout(\dpwm|LessThan0~14_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|LessThan0~14 .lut_mask = 16'hF550; +defparam \dpwm|LessThan0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N10 +cycloneive_lcell_comb \dpwm|delay0 ( +// Equation(s): +// \dpwm|delay0~combout = LCELL(!\dpwm|LessThan0~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|LessThan0~14_combout ), + .cin(gnd), + .combout(\dpwm|delay0~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay0 .lut_mask = 16'h00FF; +defparam \dpwm|delay0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N4 +cycloneive_lcell_comb \dpwm|de7 ( +// Equation(s): +// \dpwm|de7~combout = LCELL(\dpwm|delay0~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay0~combout ), + .cin(gnd), + .combout(\dpwm|de7~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de7 .lut_mask = 16'hFF00; +defparam \dpwm|de7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N12 +cycloneive_lcell_comb \dpwm|delay1 ( +// Equation(s): +// \dpwm|delay1~combout = LCELL(\dpwm|de7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|de7~combout ), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|delay1~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay1 .lut_mask = 16'hF0F0; +defparam \dpwm|delay1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N2 +cycloneive_lcell_comb \dpwm|de6 ( +// Equation(s): +// \dpwm|de6~combout = LCELL(\dpwm|delay1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay1~combout ), + .cin(gnd), + .combout(\dpwm|de6~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de6 .lut_mask = 16'hFF00; +defparam \dpwm|de6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N18 +cycloneive_lcell_comb \dpwm|delay2 ( +// Equation(s): +// \dpwm|delay2~combout = LCELL(\dpwm|de6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|de6~combout ), + .cin(gnd), + .combout(\dpwm|delay2~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay2 .lut_mask = 16'hFF00; +defparam \dpwm|delay2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N28 +cycloneive_lcell_comb \dpwm|de5 ( +// Equation(s): +// \dpwm|de5~combout = LCELL(\dpwm|delay2~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay2~combout ), + .cin(gnd), + .combout(\dpwm|de5~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de5 .lut_mask = 16'hFF00; +defparam \dpwm|de5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N0 +cycloneive_lcell_comb \dpwm|delay3 ( +// Equation(s): +// \dpwm|delay3~combout = LCELL(\dpwm|de5~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|de5~combout ), + .cin(gnd), + .combout(\dpwm|delay3~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay3 .lut_mask = 16'hFF00; +defparam \dpwm|delay3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y18_N4 +cycloneive_lcell_comb \dpwm|de4 ( +// Equation(s): +// \dpwm|de4~combout = LCELL(\dpwm|delay3~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay3~combout ), + .cin(gnd), + .combout(\dpwm|de4~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de4 .lut_mask = 16'hFF00; +defparam \dpwm|de4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \dpwm|bit_high_syn~0 ( +// Equation(s): +// \dpwm|bit_high_syn~0_combout = !\dpwm|out_8bit [7] + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|out_8bit [7]), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|bit_high_syn~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|bit_high_syn~0 .lut_mask = 16'h0F0F; +defparam \dpwm|bit_high_syn~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N29 +dffeas \dpwm|bit_high_syn ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|bit_high_syn~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|bit_high_syn~q ), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|bit_high_syn .is_wysiwyg = "true"; +defparam \dpwm|bit_high_syn .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \dpwm|n_bit_high_syn~0 ( +// Equation(s): +// \dpwm|n_bit_high_syn~0_combout = !\dpwm|bit_high_syn~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|bit_high_syn~q ), + .cin(gnd), + .combout(\dpwm|n_bit_high_syn~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|n_bit_high_syn~0 .lut_mask = 16'h00FF; +defparam \dpwm|n_bit_high_syn~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N19 +dffeas \dpwm|n_bit_high_syn ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|n_bit_high_syn~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|n_bit_high_syn~q ), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|n_bit_high_syn .is_wysiwyg = "true"; +defparam \dpwm|n_bit_high_syn .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \dpwm|pwm_out ( +// Equation(s): +// \dpwm|pwm_out~combout = (\dpwm|n_bit_high_syn~q & \dpwm|bit_high_syn~q ) + + .dataa(gnd), + .datab(\dpwm|n_bit_high_syn~q ), + .datac(gnd), + .datad(\dpwm|bit_high_syn~q ), + .cin(gnd), + .combout(\dpwm|pwm_out~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|pwm_out .lut_mask = 16'hCC00; +defparam \dpwm|pwm_out .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/dpwm/simulation/modelsim/dpwm_8_1200mv_0c_slow.vo b/dpwm/simulation/modelsim/dpwm_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..36e6d3d --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_8_1200mv_0c_slow.vo @@ -0,0 +1,1224 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" + +// DATE "11/05/2018 21:21:20" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module dpwm_top ( + clk, + rst_n, + dpid, + delay_out, + pwm_out); +input clk; +input rst_n; +input [7:0] dpid; +output [7:0] delay_out; +output pwm_out; + +// Design Ports Information +// delay_out[0] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[1] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[2] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[3] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[4] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[5] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[6] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[7] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default +// pwm_out => Location: PIN_K16, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// dpid[7] => Location: PIN_E16, I/O Standard: 2.5 V, Current Strength: Default +// dpid[6] => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[5] => Location: PIN_K15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[4] => Location: PIN_J13, I/O Standard: 2.5 V, Current Strength: Default +// dpid[3] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default +// dpid[2] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[1] => Location: PIN_J12, I/O Standard: 2.5 V, Current Strength: Default +// dpid[0] => Location: PIN_J14, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("dpwm_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \clk~input_o ; +wire \clk~inputclkctrl_outclk ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \my_pll|altpll_component|auto_generated|locked~combout ; +wire \my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ; +wire \dpwm|out_8bit[0]~0_combout ; +wire \dpwm|Add0~0_combout ; +wire \dpwm|Add0~1 ; +wire \dpwm|Add0~2_combout ; +wire \dpwm|Add0~3 ; +wire \dpwm|Add0~4_combout ; +wire \dpwm|Add0~5 ; +wire \dpwm|Add0~6_combout ; +wire \dpwm|Add0~7 ; +wire \dpwm|Add0~8_combout ; +wire \dpwm|Add0~9 ; +wire \dpwm|Add0~10_combout ; +wire \dpwm|Add0~11 ; +wire \dpwm|Add0~12_combout ; +wire \dpid[7]~input_o ; +wire \dpid[6]~input_o ; +wire \dpid[5]~input_o ; +wire \dpid[4]~input_o ; +wire \dpid[3]~input_o ; +wire \dpid[2]~input_o ; +wire \dpid[1]~input_o ; +wire \dpid[0]~input_o ; +wire \dpwm|LessThan0~1_cout ; +wire \dpwm|LessThan0~3_cout ; +wire \dpwm|LessThan0~5_cout ; +wire \dpwm|LessThan0~7_cout ; +wire \dpwm|LessThan0~9_cout ; +wire \dpwm|LessThan0~11_cout ; +wire \dpwm|LessThan0~13_cout ; +wire \dpwm|LessThan0~14_combout ; +wire \dpwm|delay0~combout ; +wire \dpwm|de7~combout ; +wire \dpwm|delay1~combout ; +wire \dpwm|de6~combout ; +wire \dpwm|delay2~combout ; +wire \dpwm|de5~combout ; +wire \dpwm|delay3~combout ; +wire \dpwm|de4~combout ; +wire \dpwm|bit_high_syn~0_combout ; +wire \dpwm|bit_high_syn~q ; +wire \dpwm|n_bit_high_syn~0_combout ; +wire \dpwm|n_bit_high_syn~q ; +wire \dpwm|pwm_out~combout ; +wire [4:0] \my_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \dpwm|out_8bit ; + +wire [4:0] \my_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X34_Y17_N23 +cycloneive_io_obuf \delay_out[0]~output ( + .i(\dpwm|de7~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[0]), + .obar()); +// synopsys translate_off +defparam \delay_out[0]~output .bus_hold = "false"; +defparam \delay_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N16 +cycloneive_io_obuf \delay_out[1]~output ( + .i(\dpwm|de6~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[1]), + .obar()); +// synopsys translate_off +defparam \delay_out[1]~output .bus_hold = "false"; +defparam \delay_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N2 +cycloneive_io_obuf \delay_out[2]~output ( + .i(\dpwm|de5~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[2]), + .obar()); +// synopsys translate_off +defparam \delay_out[2]~output .bus_hold = "false"; +defparam \delay_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y18_N16 +cycloneive_io_obuf \delay_out[3]~output ( + .i(\dpwm|de4~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[3]), + .obar()); +// synopsys translate_off +defparam \delay_out[3]~output .bus_hold = "false"; +defparam \delay_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X21_Y24_N9 +cycloneive_io_obuf \delay_out[4]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[4]), + .obar()); +// synopsys translate_off +defparam \delay_out[4]~output .bus_hold = "false"; +defparam \delay_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y24_N23 +cycloneive_io_obuf \delay_out[5]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[5]), + .obar()); +// synopsys translate_off +defparam \delay_out[5]~output .bus_hold = "false"; +defparam \delay_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y24_N2 +cycloneive_io_obuf \delay_out[6]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[6]), + .obar()); +// synopsys translate_off +defparam \delay_out[6]~output .bus_hold = "false"; +defparam \delay_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X21_Y0_N9 +cycloneive_io_obuf \delay_out[7]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[7]), + .obar()); +// synopsys translate_off +defparam \delay_out[7]~output .bus_hold = "false"; +defparam \delay_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y9_N16 +cycloneive_io_obuf \pwm_out~output ( + .i(\dpwm|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out), + .obar()); +// synopsys translate_off +defparam \pwm_out~output .bus_hold = "false"; +defparam \pwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk~inputclkctrl .clock_type = "global clock"; +defparam \clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \my_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\my_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \my_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \my_pll|altpll_component|auto_generated|pll1 .m = 12; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .operation_mode = "no compensation"; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \my_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \my_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X1_Y4_N28 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y4_N29 +dffeas \my_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y4_N14 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|locked ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|locked~combout = (!\my_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\my_pll|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|locked~combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked .lut_mask = 16'h0FFF; +defparam \my_pll|altpll_component|auto_generated|locked .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G1 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|locked~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|locked~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X33_Y12_N31 +dffeas \dpwm|out_8bit[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~12_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[7] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N16 +cycloneive_lcell_comb \dpwm|out_8bit[0]~0 ( +// Equation(s): +// \dpwm|out_8bit[0]~0_combout = !\dpwm|out_8bit [0] + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|out_8bit [0]), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|out_8bit[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|out_8bit[0]~0 .lut_mask = 16'h0F0F; +defparam \dpwm|out_8bit[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y12_N17 +dffeas \dpwm|out_8bit[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|out_8bit[0]~0_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[0] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N18 +cycloneive_lcell_comb \dpwm|Add0~0 ( +// Equation(s): +// \dpwm|Add0~0_combout = (\dpwm|out_8bit [1] & (\dpwm|out_8bit [0] $ (VCC))) # (!\dpwm|out_8bit [1] & (\dpwm|out_8bit [0] & VCC)) +// \dpwm|Add0~1 = CARRY((\dpwm|out_8bit [1] & \dpwm|out_8bit [0])) + + .dataa(\dpwm|out_8bit [1]), + .datab(\dpwm|out_8bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm|Add0~0_combout ), + .cout(\dpwm|Add0~1 )); +// synopsys translate_off +defparam \dpwm|Add0~0 .lut_mask = 16'h6688; +defparam \dpwm|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y12_N19 +dffeas \dpwm|out_8bit[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~0_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[1] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N20 +cycloneive_lcell_comb \dpwm|Add0~2 ( +// Equation(s): +// \dpwm|Add0~2_combout = (\dpwm|out_8bit [2] & (!\dpwm|Add0~1 )) # (!\dpwm|out_8bit [2] & ((\dpwm|Add0~1 ) # (GND))) +// \dpwm|Add0~3 = CARRY((!\dpwm|Add0~1 ) # (!\dpwm|out_8bit [2])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~1 ), + .combout(\dpwm|Add0~2_combout ), + .cout(\dpwm|Add0~3 )); +// synopsys translate_off +defparam \dpwm|Add0~2 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N21 +dffeas \dpwm|out_8bit[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~2_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[2] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N22 +cycloneive_lcell_comb \dpwm|Add0~4 ( +// Equation(s): +// \dpwm|Add0~4_combout = (\dpwm|out_8bit [3] & (\dpwm|Add0~3 $ (GND))) # (!\dpwm|out_8bit [3] & (!\dpwm|Add0~3 & VCC)) +// \dpwm|Add0~5 = CARRY((\dpwm|out_8bit [3] & !\dpwm|Add0~3 )) + + .dataa(\dpwm|out_8bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~3 ), + .combout(\dpwm|Add0~4_combout ), + .cout(\dpwm|Add0~5 )); +// synopsys translate_off +defparam \dpwm|Add0~4 .lut_mask = 16'hA50A; +defparam \dpwm|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N23 +dffeas \dpwm|out_8bit[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~4_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[3] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N24 +cycloneive_lcell_comb \dpwm|Add0~6 ( +// Equation(s): +// \dpwm|Add0~6_combout = (\dpwm|out_8bit [4] & (!\dpwm|Add0~5 )) # (!\dpwm|out_8bit [4] & ((\dpwm|Add0~5 ) # (GND))) +// \dpwm|Add0~7 = CARRY((!\dpwm|Add0~5 ) # (!\dpwm|out_8bit [4])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~5 ), + .combout(\dpwm|Add0~6_combout ), + .cout(\dpwm|Add0~7 )); +// synopsys translate_off +defparam \dpwm|Add0~6 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N25 +dffeas \dpwm|out_8bit[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~6_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[4] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N26 +cycloneive_lcell_comb \dpwm|Add0~8 ( +// Equation(s): +// \dpwm|Add0~8_combout = (\dpwm|out_8bit [5] & (\dpwm|Add0~7 $ (GND))) # (!\dpwm|out_8bit [5] & (!\dpwm|Add0~7 & VCC)) +// \dpwm|Add0~9 = CARRY((\dpwm|out_8bit [5] & !\dpwm|Add0~7 )) + + .dataa(\dpwm|out_8bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~7 ), + .combout(\dpwm|Add0~8_combout ), + .cout(\dpwm|Add0~9 )); +// synopsys translate_off +defparam \dpwm|Add0~8 .lut_mask = 16'hA50A; +defparam \dpwm|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N27 +dffeas \dpwm|out_8bit[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~8_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[5] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N28 +cycloneive_lcell_comb \dpwm|Add0~10 ( +// Equation(s): +// \dpwm|Add0~10_combout = (\dpwm|out_8bit [6] & (!\dpwm|Add0~9 )) # (!\dpwm|out_8bit [6] & ((\dpwm|Add0~9 ) # (GND))) +// \dpwm|Add0~11 = CARRY((!\dpwm|Add0~9 ) # (!\dpwm|out_8bit [6])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~9 ), + .combout(\dpwm|Add0~10_combout ), + .cout(\dpwm|Add0~11 )); +// synopsys translate_off +defparam \dpwm|Add0~10 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N29 +dffeas \dpwm|out_8bit[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~10_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[6] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N30 +cycloneive_lcell_comb \dpwm|Add0~12 ( +// Equation(s): +// \dpwm|Add0~12_combout = \dpwm|Add0~11 $ (!\dpwm|out_8bit [7]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|out_8bit [7]), + .cin(\dpwm|Add0~11 ), + .combout(\dpwm|Add0~12_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|Add0~12 .lut_mask = 16'hF00F; +defparam \dpwm|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y12_N8 +cycloneive_io_ibuf \dpid[7]~input ( + .i(dpid[7]), + .ibar(gnd), + .o(\dpid[7]~input_o )); +// synopsys translate_off +defparam \dpid[7]~input .bus_hold = "false"; +defparam \dpid[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y12_N1 +cycloneive_io_ibuf \dpid[6]~input ( + .i(dpid[6]), + .ibar(gnd), + .o(\dpid[6]~input_o )); +// synopsys translate_off +defparam \dpid[6]~input .bus_hold = "false"; +defparam \dpid[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y9_N8 +cycloneive_io_ibuf \dpid[5]~input ( + .i(dpid[5]), + .ibar(gnd), + .o(\dpid[5]~input_o )); +// synopsys translate_off +defparam \dpid[5]~input .bus_hold = "false"; +defparam \dpid[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N1 +cycloneive_io_ibuf \dpid[4]~input ( + .i(dpid[4]), + .ibar(gnd), + .o(\dpid[4]~input_o )); +// synopsys translate_off +defparam \dpid[4]~input .bus_hold = "false"; +defparam \dpid[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y9_N1 +cycloneive_io_ibuf \dpid[3]~input ( + .i(dpid[3]), + .ibar(gnd), + .o(\dpid[3]~input_o )); +// synopsys translate_off +defparam \dpid[3]~input .bus_hold = "false"; +defparam \dpid[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N8 +cycloneive_io_ibuf \dpid[2]~input ( + .i(dpid[2]), + .ibar(gnd), + .o(\dpid[2]~input_o )); +// synopsys translate_off +defparam \dpid[2]~input .bus_hold = "false"; +defparam \dpid[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N8 +cycloneive_io_ibuf \dpid[1]~input ( + .i(dpid[1]), + .ibar(gnd), + .o(\dpid[1]~input_o )); +// synopsys translate_off +defparam \dpid[1]~input .bus_hold = "false"; +defparam \dpid[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N1 +cycloneive_io_ibuf \dpid[0]~input ( + .i(dpid[0]), + .ibar(gnd), + .o(\dpid[0]~input_o )); +// synopsys translate_off +defparam \dpid[0]~input .bus_hold = "false"; +defparam \dpid[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N0 +cycloneive_lcell_comb \dpwm|LessThan0~1 ( +// Equation(s): +// \dpwm|LessThan0~1_cout = CARRY((\dpwm|out_8bit [0] & \dpid[0]~input_o )) + + .dataa(\dpwm|out_8bit [0]), + .datab(\dpid[0]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\dpwm|LessThan0~1_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~1 .lut_mask = 16'h0088; +defparam \dpwm|LessThan0~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N2 +cycloneive_lcell_comb \dpwm|LessThan0~3 ( +// Equation(s): +// \dpwm|LessThan0~3_cout = CARRY((\dpid[1]~input_o & (\dpwm|Add0~0_combout & !\dpwm|LessThan0~1_cout )) # (!\dpid[1]~input_o & ((\dpwm|Add0~0_combout ) # (!\dpwm|LessThan0~1_cout )))) + + .dataa(\dpid[1]~input_o ), + .datab(\dpwm|Add0~0_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~1_cout ), + .combout(), + .cout(\dpwm|LessThan0~3_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~3 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N4 +cycloneive_lcell_comb \dpwm|LessThan0~5 ( +// Equation(s): +// \dpwm|LessThan0~5_cout = CARRY((\dpwm|Add0~2_combout & (\dpid[2]~input_o & !\dpwm|LessThan0~3_cout )) # (!\dpwm|Add0~2_combout & ((\dpid[2]~input_o ) # (!\dpwm|LessThan0~3_cout )))) + + .dataa(\dpwm|Add0~2_combout ), + .datab(\dpid[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~3_cout ), + .combout(), + .cout(\dpwm|LessThan0~5_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~5 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N6 +cycloneive_lcell_comb \dpwm|LessThan0~7 ( +// Equation(s): +// \dpwm|LessThan0~7_cout = CARRY((\dpid[3]~input_o & (\dpwm|Add0~4_combout & !\dpwm|LessThan0~5_cout )) # (!\dpid[3]~input_o & ((\dpwm|Add0~4_combout ) # (!\dpwm|LessThan0~5_cout )))) + + .dataa(\dpid[3]~input_o ), + .datab(\dpwm|Add0~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~5_cout ), + .combout(), + .cout(\dpwm|LessThan0~7_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~7 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N8 +cycloneive_lcell_comb \dpwm|LessThan0~9 ( +// Equation(s): +// \dpwm|LessThan0~9_cout = CARRY((\dpwm|Add0~6_combout & (\dpid[4]~input_o & !\dpwm|LessThan0~7_cout )) # (!\dpwm|Add0~6_combout & ((\dpid[4]~input_o ) # (!\dpwm|LessThan0~7_cout )))) + + .dataa(\dpwm|Add0~6_combout ), + .datab(\dpid[4]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~7_cout ), + .combout(), + .cout(\dpwm|LessThan0~9_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~9 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N10 +cycloneive_lcell_comb \dpwm|LessThan0~11 ( +// Equation(s): +// \dpwm|LessThan0~11_cout = CARRY((\dpid[5]~input_o & (\dpwm|Add0~8_combout & !\dpwm|LessThan0~9_cout )) # (!\dpid[5]~input_o & ((\dpwm|Add0~8_combout ) # (!\dpwm|LessThan0~9_cout )))) + + .dataa(\dpid[5]~input_o ), + .datab(\dpwm|Add0~8_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~9_cout ), + .combout(), + .cout(\dpwm|LessThan0~11_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~11 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N12 +cycloneive_lcell_comb \dpwm|LessThan0~13 ( +// Equation(s): +// \dpwm|LessThan0~13_cout = CARRY((\dpwm|Add0~10_combout & (\dpid[6]~input_o & !\dpwm|LessThan0~11_cout )) # (!\dpwm|Add0~10_combout & ((\dpid[6]~input_o ) # (!\dpwm|LessThan0~11_cout )))) + + .dataa(\dpwm|Add0~10_combout ), + .datab(\dpid[6]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~11_cout ), + .combout(), + .cout(\dpwm|LessThan0~13_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~13 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N14 +cycloneive_lcell_comb \dpwm|LessThan0~14 ( +// Equation(s): +// \dpwm|LessThan0~14_combout = (\dpwm|Add0~12_combout & (\dpwm|LessThan0~13_cout & \dpid[7]~input_o )) # (!\dpwm|Add0~12_combout & ((\dpwm|LessThan0~13_cout ) # (\dpid[7]~input_o ))) + + .dataa(\dpwm|Add0~12_combout ), + .datab(gnd), + .datac(gnd), + .datad(\dpid[7]~input_o ), + .cin(\dpwm|LessThan0~13_cout ), + .combout(\dpwm|LessThan0~14_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|LessThan0~14 .lut_mask = 16'hF550; +defparam \dpwm|LessThan0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N10 +cycloneive_lcell_comb \dpwm|delay0 ( +// Equation(s): +// \dpwm|delay0~combout = LCELL(!\dpwm|LessThan0~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|LessThan0~14_combout ), + .cin(gnd), + .combout(\dpwm|delay0~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay0 .lut_mask = 16'h00FF; +defparam \dpwm|delay0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N4 +cycloneive_lcell_comb \dpwm|de7 ( +// Equation(s): +// \dpwm|de7~combout = LCELL(\dpwm|delay0~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay0~combout ), + .cin(gnd), + .combout(\dpwm|de7~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de7 .lut_mask = 16'hFF00; +defparam \dpwm|de7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N12 +cycloneive_lcell_comb \dpwm|delay1 ( +// Equation(s): +// \dpwm|delay1~combout = LCELL(\dpwm|de7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|de7~combout ), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|delay1~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay1 .lut_mask = 16'hF0F0; +defparam \dpwm|delay1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N2 +cycloneive_lcell_comb \dpwm|de6 ( +// Equation(s): +// \dpwm|de6~combout = LCELL(\dpwm|delay1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay1~combout ), + .cin(gnd), + .combout(\dpwm|de6~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de6 .lut_mask = 16'hFF00; +defparam \dpwm|de6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N18 +cycloneive_lcell_comb \dpwm|delay2 ( +// Equation(s): +// \dpwm|delay2~combout = LCELL(\dpwm|de6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|de6~combout ), + .cin(gnd), + .combout(\dpwm|delay2~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay2 .lut_mask = 16'hFF00; +defparam \dpwm|delay2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N28 +cycloneive_lcell_comb \dpwm|de5 ( +// Equation(s): +// \dpwm|de5~combout = LCELL(\dpwm|delay2~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay2~combout ), + .cin(gnd), + .combout(\dpwm|de5~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de5 .lut_mask = 16'hFF00; +defparam \dpwm|de5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N0 +cycloneive_lcell_comb \dpwm|delay3 ( +// Equation(s): +// \dpwm|delay3~combout = LCELL(\dpwm|de5~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|de5~combout ), + .cin(gnd), + .combout(\dpwm|delay3~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay3 .lut_mask = 16'hFF00; +defparam \dpwm|delay3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y18_N4 +cycloneive_lcell_comb \dpwm|de4 ( +// Equation(s): +// \dpwm|de4~combout = LCELL(\dpwm|delay3~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay3~combout ), + .cin(gnd), + .combout(\dpwm|de4~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de4 .lut_mask = 16'hFF00; +defparam \dpwm|de4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \dpwm|bit_high_syn~0 ( +// Equation(s): +// \dpwm|bit_high_syn~0_combout = !\dpwm|out_8bit [7] + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|out_8bit [7]), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|bit_high_syn~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|bit_high_syn~0 .lut_mask = 16'h0F0F; +defparam \dpwm|bit_high_syn~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N29 +dffeas \dpwm|bit_high_syn ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|bit_high_syn~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|bit_high_syn~q ), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|bit_high_syn .is_wysiwyg = "true"; +defparam \dpwm|bit_high_syn .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \dpwm|n_bit_high_syn~0 ( +// Equation(s): +// \dpwm|n_bit_high_syn~0_combout = !\dpwm|bit_high_syn~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|bit_high_syn~q ), + .cin(gnd), + .combout(\dpwm|n_bit_high_syn~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|n_bit_high_syn~0 .lut_mask = 16'h00FF; +defparam \dpwm|n_bit_high_syn~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N19 +dffeas \dpwm|n_bit_high_syn ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|n_bit_high_syn~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|n_bit_high_syn~q ), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|n_bit_high_syn .is_wysiwyg = "true"; +defparam \dpwm|n_bit_high_syn .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \dpwm|pwm_out ( +// Equation(s): +// \dpwm|pwm_out~combout = (\dpwm|n_bit_high_syn~q & \dpwm|bit_high_syn~q ) + + .dataa(gnd), + .datab(\dpwm|n_bit_high_syn~q ), + .datac(gnd), + .datad(\dpwm|bit_high_syn~q ), + .cin(gnd), + .combout(\dpwm|pwm_out~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|pwm_out .lut_mask = 16'hCC00; +defparam \dpwm|pwm_out .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/dpwm/simulation/modelsim/dpwm_8_1200mv_0c_v_slow.sdo b/dpwm/simulation/modelsim/dpwm_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..5657e6f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,720 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "dpwm_top") + (DATE "11/05/2018 21:21:20") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (442:442:442) (373:373:373)) + (IOPATH i o (2800:2800:2800) (2762:2762:2762)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (441:441:441) (372:372:372)) + (IOPATH i o (2790:2790:2790) (2752:2752:2752)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (444:444:444) (377:377:377)) + (IOPATH i o (2697:2697:2697) (2676:2676:2676)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (421:421:421) (348:348:348)) + (IOPATH i o (2800:2800:2800) (2762:2762:2762)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (1001:1001:1001) (816:816:816)) + (IOPATH i o (2800:2800:2800) (2762:2762:2762)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (194:194:194) (190:190:190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (758:758:758) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (194:194:194) (190:190:190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (1180:1180:1180) (1180:1180:1180)) + (PORT inclk[0] (2058:2058:2058) (2058:2058:2058)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1491:1491:1491) (1697:1697:1697)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1527:1527:1527) (1456:1456:1456)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked) + (DELAY + (ABSOLUTE + (PORT datac (844:844:844) (1025:1025:1025)) + (PORT datad (277:277:277) (331:331:331)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1486:1486:1486) (1349:1349:1349)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1916:1916:1916) (1909:1909:1909)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1483:1483:1483) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|out_8bit\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1449:1449:1449) (1490:1490:1490)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1483:1483:1483) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (524:524:524) (511:511:511)) + (PORT datab (337:337:337) (392:392:392)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1449:1449:1449) (1490:1490:1490)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1483:1483:1483) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT datab (315:315:315) (369:369:369)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1449:1449:1449) (1490:1490:1490)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1483:1483:1483) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (376:376:376)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1449:1449:1449) (1490:1490:1490)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1483:1483:1483) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (314:314:314) (368:368:368)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1449:1449:1449) (1490:1490:1490)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1483:1483:1483) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (375:375:375)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1449:1449:1449) (1490:1490:1490)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1483:1483:1483) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (314:314:314) (367:367:367)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1449:1449:1449) (1490:1490:1490)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1483:1483:1483) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datad (486:486:486) (472:472:472)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (758:758:758) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (718:718:718) (743:743:743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (708:708:708) (733:733:733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (718:718:718) (743:743:743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (718:718:718) (743:743:743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (534:534:534)) + (PORT datab (3056:3056:3056) (3143:3143:3143)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (3026:3026:3026) (3137:3137:3137)) + (PORT datab (740:740:740) (583:583:583)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (417:417:417)) + (PORT datab (3046:3046:3046) (3131:3131:3131)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (3317:3317:3317) (3327:3327:3327)) + (PORT datab (474:474:474) (408:408:408)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (415:415:415)) + (PORT datab (3045:3045:3045) (3130:3130:3130)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (3031:3031:3031) (3139:3139:3139)) + (PORT datab (473:473:473) (413:413:413)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (415:415:415)) + (PORT datab (409:409:409) (532:532:532)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (281:281:281)) + (PORT datad (364:364:364) (468:468:468)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay0) + (DELAY + (ABSOLUTE + (PORT datad (1191:1191:1191) (1017:1017:1017)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de7) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (233:233:233)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay1) + (DELAY + (ABSOLUTE + (PORT datac (246:246:246) (262:262:262)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de6) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (233:233:233)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay2) + (DELAY + (ABSOLUTE + (PORT datad (249:249:249) (257:257:257)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de5) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (233:233:233)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay3) + (DELAY + (ABSOLUTE + (PORT datad (251:251:251) (260:260:260)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de4) + (DELAY + (ABSOLUTE + (PORT datad (439:439:439) (376:376:376)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|bit_high_syn\~0) + (DELAY + (ABSOLUTE + (PORT datac (542:542:542) (518:518:518)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|bit_high_syn) + (DELAY + (ABSOLUTE + (PORT clk (1449:1449:1449) (1490:1490:1490)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|n_bit_high_syn\~0) + (DELAY + (ABSOLUTE + (PORT datad (284:284:284) (342:342:342)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|n_bit_high_syn) + (DELAY + (ABSOLUTE + (PORT clk (1449:1449:1449) (1490:1490:1490)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|pwm_out) + (DELAY + (ABSOLUTE + (PORT datab (317:317:317) (372:372:372)) + (PORT datad (284:284:284) (342:342:342)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) +) diff --git a/dpwm/simulation/modelsim/dpwm_8_1200mv_85c_slow.vo b/dpwm/simulation/modelsim/dpwm_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..b835253 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_8_1200mv_85c_slow.vo @@ -0,0 +1,1224 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" + +// DATE "11/05/2018 21:21:20" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module dpwm_top ( + clk, + rst_n, + dpid, + delay_out, + pwm_out); +input clk; +input rst_n; +input [7:0] dpid; +output [7:0] delay_out; +output pwm_out; + +// Design Ports Information +// delay_out[0] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[1] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[2] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[3] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[4] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[5] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[6] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[7] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default +// pwm_out => Location: PIN_K16, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// dpid[7] => Location: PIN_E16, I/O Standard: 2.5 V, Current Strength: Default +// dpid[6] => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[5] => Location: PIN_K15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[4] => Location: PIN_J13, I/O Standard: 2.5 V, Current Strength: Default +// dpid[3] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default +// dpid[2] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[1] => Location: PIN_J12, I/O Standard: 2.5 V, Current Strength: Default +// dpid[0] => Location: PIN_J14, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("dpwm_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \clk~input_o ; +wire \clk~inputclkctrl_outclk ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \my_pll|altpll_component|auto_generated|locked~combout ; +wire \my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ; +wire \dpwm|out_8bit[0]~0_combout ; +wire \dpwm|Add0~0_combout ; +wire \dpwm|Add0~1 ; +wire \dpwm|Add0~2_combout ; +wire \dpwm|Add0~3 ; +wire \dpwm|Add0~4_combout ; +wire \dpwm|Add0~5 ; +wire \dpwm|Add0~6_combout ; +wire \dpwm|Add0~7 ; +wire \dpwm|Add0~8_combout ; +wire \dpwm|Add0~9 ; +wire \dpwm|Add0~10_combout ; +wire \dpwm|Add0~11 ; +wire \dpwm|Add0~12_combout ; +wire \dpid[7]~input_o ; +wire \dpid[6]~input_o ; +wire \dpid[5]~input_o ; +wire \dpid[4]~input_o ; +wire \dpid[3]~input_o ; +wire \dpid[2]~input_o ; +wire \dpid[1]~input_o ; +wire \dpid[0]~input_o ; +wire \dpwm|LessThan0~1_cout ; +wire \dpwm|LessThan0~3_cout ; +wire \dpwm|LessThan0~5_cout ; +wire \dpwm|LessThan0~7_cout ; +wire \dpwm|LessThan0~9_cout ; +wire \dpwm|LessThan0~11_cout ; +wire \dpwm|LessThan0~13_cout ; +wire \dpwm|LessThan0~14_combout ; +wire \dpwm|delay0~combout ; +wire \dpwm|de7~combout ; +wire \dpwm|delay1~combout ; +wire \dpwm|de6~combout ; +wire \dpwm|delay2~combout ; +wire \dpwm|de5~combout ; +wire \dpwm|delay3~combout ; +wire \dpwm|de4~combout ; +wire \dpwm|bit_high_syn~0_combout ; +wire \dpwm|bit_high_syn~q ; +wire \dpwm|n_bit_high_syn~0_combout ; +wire \dpwm|n_bit_high_syn~q ; +wire \dpwm|pwm_out~combout ; +wire [4:0] \my_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \dpwm|out_8bit ; + +wire [4:0] \my_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X34_Y17_N23 +cycloneive_io_obuf \delay_out[0]~output ( + .i(\dpwm|de7~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[0]), + .obar()); +// synopsys translate_off +defparam \delay_out[0]~output .bus_hold = "false"; +defparam \delay_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N16 +cycloneive_io_obuf \delay_out[1]~output ( + .i(\dpwm|de6~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[1]), + .obar()); +// synopsys translate_off +defparam \delay_out[1]~output .bus_hold = "false"; +defparam \delay_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N2 +cycloneive_io_obuf \delay_out[2]~output ( + .i(\dpwm|de5~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[2]), + .obar()); +// synopsys translate_off +defparam \delay_out[2]~output .bus_hold = "false"; +defparam \delay_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y18_N16 +cycloneive_io_obuf \delay_out[3]~output ( + .i(\dpwm|de4~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[3]), + .obar()); +// synopsys translate_off +defparam \delay_out[3]~output .bus_hold = "false"; +defparam \delay_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X21_Y24_N9 +cycloneive_io_obuf \delay_out[4]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[4]), + .obar()); +// synopsys translate_off +defparam \delay_out[4]~output .bus_hold = "false"; +defparam \delay_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y24_N23 +cycloneive_io_obuf \delay_out[5]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[5]), + .obar()); +// synopsys translate_off +defparam \delay_out[5]~output .bus_hold = "false"; +defparam \delay_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y24_N2 +cycloneive_io_obuf \delay_out[6]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[6]), + .obar()); +// synopsys translate_off +defparam \delay_out[6]~output .bus_hold = "false"; +defparam \delay_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X21_Y0_N9 +cycloneive_io_obuf \delay_out[7]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[7]), + .obar()); +// synopsys translate_off +defparam \delay_out[7]~output .bus_hold = "false"; +defparam \delay_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y9_N16 +cycloneive_io_obuf \pwm_out~output ( + .i(\dpwm|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out), + .obar()); +// synopsys translate_off +defparam \pwm_out~output .bus_hold = "false"; +defparam \pwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk~inputclkctrl .clock_type = "global clock"; +defparam \clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \my_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\my_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \my_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \my_pll|altpll_component|auto_generated|pll1 .m = 12; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .operation_mode = "no compensation"; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \my_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \my_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X1_Y4_N28 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y4_N29 +dffeas \my_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y4_N14 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|locked ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|locked~combout = (!\my_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\my_pll|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|locked~combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked .lut_mask = 16'h0FFF; +defparam \my_pll|altpll_component|auto_generated|locked .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G1 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|locked~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|locked~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X33_Y12_N31 +dffeas \dpwm|out_8bit[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~12_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[7] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N16 +cycloneive_lcell_comb \dpwm|out_8bit[0]~0 ( +// Equation(s): +// \dpwm|out_8bit[0]~0_combout = !\dpwm|out_8bit [0] + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|out_8bit [0]), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|out_8bit[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|out_8bit[0]~0 .lut_mask = 16'h0F0F; +defparam \dpwm|out_8bit[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y12_N17 +dffeas \dpwm|out_8bit[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|out_8bit[0]~0_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[0] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N18 +cycloneive_lcell_comb \dpwm|Add0~0 ( +// Equation(s): +// \dpwm|Add0~0_combout = (\dpwm|out_8bit [1] & (\dpwm|out_8bit [0] $ (VCC))) # (!\dpwm|out_8bit [1] & (\dpwm|out_8bit [0] & VCC)) +// \dpwm|Add0~1 = CARRY((\dpwm|out_8bit [1] & \dpwm|out_8bit [0])) + + .dataa(\dpwm|out_8bit [1]), + .datab(\dpwm|out_8bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm|Add0~0_combout ), + .cout(\dpwm|Add0~1 )); +// synopsys translate_off +defparam \dpwm|Add0~0 .lut_mask = 16'h6688; +defparam \dpwm|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y12_N19 +dffeas \dpwm|out_8bit[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~0_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[1] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N20 +cycloneive_lcell_comb \dpwm|Add0~2 ( +// Equation(s): +// \dpwm|Add0~2_combout = (\dpwm|out_8bit [2] & (!\dpwm|Add0~1 )) # (!\dpwm|out_8bit [2] & ((\dpwm|Add0~1 ) # (GND))) +// \dpwm|Add0~3 = CARRY((!\dpwm|Add0~1 ) # (!\dpwm|out_8bit [2])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~1 ), + .combout(\dpwm|Add0~2_combout ), + .cout(\dpwm|Add0~3 )); +// synopsys translate_off +defparam \dpwm|Add0~2 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N21 +dffeas \dpwm|out_8bit[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~2_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[2] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N22 +cycloneive_lcell_comb \dpwm|Add0~4 ( +// Equation(s): +// \dpwm|Add0~4_combout = (\dpwm|out_8bit [3] & (\dpwm|Add0~3 $ (GND))) # (!\dpwm|out_8bit [3] & (!\dpwm|Add0~3 & VCC)) +// \dpwm|Add0~5 = CARRY((\dpwm|out_8bit [3] & !\dpwm|Add0~3 )) + + .dataa(\dpwm|out_8bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~3 ), + .combout(\dpwm|Add0~4_combout ), + .cout(\dpwm|Add0~5 )); +// synopsys translate_off +defparam \dpwm|Add0~4 .lut_mask = 16'hA50A; +defparam \dpwm|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N23 +dffeas \dpwm|out_8bit[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~4_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[3] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N24 +cycloneive_lcell_comb \dpwm|Add0~6 ( +// Equation(s): +// \dpwm|Add0~6_combout = (\dpwm|out_8bit [4] & (!\dpwm|Add0~5 )) # (!\dpwm|out_8bit [4] & ((\dpwm|Add0~5 ) # (GND))) +// \dpwm|Add0~7 = CARRY((!\dpwm|Add0~5 ) # (!\dpwm|out_8bit [4])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~5 ), + .combout(\dpwm|Add0~6_combout ), + .cout(\dpwm|Add0~7 )); +// synopsys translate_off +defparam \dpwm|Add0~6 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N25 +dffeas \dpwm|out_8bit[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~6_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[4] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N26 +cycloneive_lcell_comb \dpwm|Add0~8 ( +// Equation(s): +// \dpwm|Add0~8_combout = (\dpwm|out_8bit [5] & (\dpwm|Add0~7 $ (GND))) # (!\dpwm|out_8bit [5] & (!\dpwm|Add0~7 & VCC)) +// \dpwm|Add0~9 = CARRY((\dpwm|out_8bit [5] & !\dpwm|Add0~7 )) + + .dataa(\dpwm|out_8bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~7 ), + .combout(\dpwm|Add0~8_combout ), + .cout(\dpwm|Add0~9 )); +// synopsys translate_off +defparam \dpwm|Add0~8 .lut_mask = 16'hA50A; +defparam \dpwm|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N27 +dffeas \dpwm|out_8bit[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~8_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[5] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N28 +cycloneive_lcell_comb \dpwm|Add0~10 ( +// Equation(s): +// \dpwm|Add0~10_combout = (\dpwm|out_8bit [6] & (!\dpwm|Add0~9 )) # (!\dpwm|out_8bit [6] & ((\dpwm|Add0~9 ) # (GND))) +// \dpwm|Add0~11 = CARRY((!\dpwm|Add0~9 ) # (!\dpwm|out_8bit [6])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~9 ), + .combout(\dpwm|Add0~10_combout ), + .cout(\dpwm|Add0~11 )); +// synopsys translate_off +defparam \dpwm|Add0~10 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N29 +dffeas \dpwm|out_8bit[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~10_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[6] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N30 +cycloneive_lcell_comb \dpwm|Add0~12 ( +// Equation(s): +// \dpwm|Add0~12_combout = \dpwm|Add0~11 $ (!\dpwm|out_8bit [7]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|out_8bit [7]), + .cin(\dpwm|Add0~11 ), + .combout(\dpwm|Add0~12_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|Add0~12 .lut_mask = 16'hF00F; +defparam \dpwm|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y12_N8 +cycloneive_io_ibuf \dpid[7]~input ( + .i(dpid[7]), + .ibar(gnd), + .o(\dpid[7]~input_o )); +// synopsys translate_off +defparam \dpid[7]~input .bus_hold = "false"; +defparam \dpid[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y12_N1 +cycloneive_io_ibuf \dpid[6]~input ( + .i(dpid[6]), + .ibar(gnd), + .o(\dpid[6]~input_o )); +// synopsys translate_off +defparam \dpid[6]~input .bus_hold = "false"; +defparam \dpid[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y9_N8 +cycloneive_io_ibuf \dpid[5]~input ( + .i(dpid[5]), + .ibar(gnd), + .o(\dpid[5]~input_o )); +// synopsys translate_off +defparam \dpid[5]~input .bus_hold = "false"; +defparam \dpid[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N1 +cycloneive_io_ibuf \dpid[4]~input ( + .i(dpid[4]), + .ibar(gnd), + .o(\dpid[4]~input_o )); +// synopsys translate_off +defparam \dpid[4]~input .bus_hold = "false"; +defparam \dpid[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y9_N1 +cycloneive_io_ibuf \dpid[3]~input ( + .i(dpid[3]), + .ibar(gnd), + .o(\dpid[3]~input_o )); +// synopsys translate_off +defparam \dpid[3]~input .bus_hold = "false"; +defparam \dpid[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N8 +cycloneive_io_ibuf \dpid[2]~input ( + .i(dpid[2]), + .ibar(gnd), + .o(\dpid[2]~input_o )); +// synopsys translate_off +defparam \dpid[2]~input .bus_hold = "false"; +defparam \dpid[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N8 +cycloneive_io_ibuf \dpid[1]~input ( + .i(dpid[1]), + .ibar(gnd), + .o(\dpid[1]~input_o )); +// synopsys translate_off +defparam \dpid[1]~input .bus_hold = "false"; +defparam \dpid[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N1 +cycloneive_io_ibuf \dpid[0]~input ( + .i(dpid[0]), + .ibar(gnd), + .o(\dpid[0]~input_o )); +// synopsys translate_off +defparam \dpid[0]~input .bus_hold = "false"; +defparam \dpid[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N0 +cycloneive_lcell_comb \dpwm|LessThan0~1 ( +// Equation(s): +// \dpwm|LessThan0~1_cout = CARRY((\dpwm|out_8bit [0] & \dpid[0]~input_o )) + + .dataa(\dpwm|out_8bit [0]), + .datab(\dpid[0]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\dpwm|LessThan0~1_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~1 .lut_mask = 16'h0088; +defparam \dpwm|LessThan0~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N2 +cycloneive_lcell_comb \dpwm|LessThan0~3 ( +// Equation(s): +// \dpwm|LessThan0~3_cout = CARRY((\dpid[1]~input_o & (\dpwm|Add0~0_combout & !\dpwm|LessThan0~1_cout )) # (!\dpid[1]~input_o & ((\dpwm|Add0~0_combout ) # (!\dpwm|LessThan0~1_cout )))) + + .dataa(\dpid[1]~input_o ), + .datab(\dpwm|Add0~0_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~1_cout ), + .combout(), + .cout(\dpwm|LessThan0~3_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~3 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N4 +cycloneive_lcell_comb \dpwm|LessThan0~5 ( +// Equation(s): +// \dpwm|LessThan0~5_cout = CARRY((\dpwm|Add0~2_combout & (\dpid[2]~input_o & !\dpwm|LessThan0~3_cout )) # (!\dpwm|Add0~2_combout & ((\dpid[2]~input_o ) # (!\dpwm|LessThan0~3_cout )))) + + .dataa(\dpwm|Add0~2_combout ), + .datab(\dpid[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~3_cout ), + .combout(), + .cout(\dpwm|LessThan0~5_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~5 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N6 +cycloneive_lcell_comb \dpwm|LessThan0~7 ( +// Equation(s): +// \dpwm|LessThan0~7_cout = CARRY((\dpid[3]~input_o & (\dpwm|Add0~4_combout & !\dpwm|LessThan0~5_cout )) # (!\dpid[3]~input_o & ((\dpwm|Add0~4_combout ) # (!\dpwm|LessThan0~5_cout )))) + + .dataa(\dpid[3]~input_o ), + .datab(\dpwm|Add0~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~5_cout ), + .combout(), + .cout(\dpwm|LessThan0~7_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~7 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N8 +cycloneive_lcell_comb \dpwm|LessThan0~9 ( +// Equation(s): +// \dpwm|LessThan0~9_cout = CARRY((\dpwm|Add0~6_combout & (\dpid[4]~input_o & !\dpwm|LessThan0~7_cout )) # (!\dpwm|Add0~6_combout & ((\dpid[4]~input_o ) # (!\dpwm|LessThan0~7_cout )))) + + .dataa(\dpwm|Add0~6_combout ), + .datab(\dpid[4]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~7_cout ), + .combout(), + .cout(\dpwm|LessThan0~9_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~9 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N10 +cycloneive_lcell_comb \dpwm|LessThan0~11 ( +// Equation(s): +// \dpwm|LessThan0~11_cout = CARRY((\dpid[5]~input_o & (\dpwm|Add0~8_combout & !\dpwm|LessThan0~9_cout )) # (!\dpid[5]~input_o & ((\dpwm|Add0~8_combout ) # (!\dpwm|LessThan0~9_cout )))) + + .dataa(\dpid[5]~input_o ), + .datab(\dpwm|Add0~8_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~9_cout ), + .combout(), + .cout(\dpwm|LessThan0~11_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~11 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N12 +cycloneive_lcell_comb \dpwm|LessThan0~13 ( +// Equation(s): +// \dpwm|LessThan0~13_cout = CARRY((\dpwm|Add0~10_combout & (\dpid[6]~input_o & !\dpwm|LessThan0~11_cout )) # (!\dpwm|Add0~10_combout & ((\dpid[6]~input_o ) # (!\dpwm|LessThan0~11_cout )))) + + .dataa(\dpwm|Add0~10_combout ), + .datab(\dpid[6]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~11_cout ), + .combout(), + .cout(\dpwm|LessThan0~13_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~13 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N14 +cycloneive_lcell_comb \dpwm|LessThan0~14 ( +// Equation(s): +// \dpwm|LessThan0~14_combout = (\dpwm|Add0~12_combout & (\dpwm|LessThan0~13_cout & \dpid[7]~input_o )) # (!\dpwm|Add0~12_combout & ((\dpwm|LessThan0~13_cout ) # (\dpid[7]~input_o ))) + + .dataa(\dpwm|Add0~12_combout ), + .datab(gnd), + .datac(gnd), + .datad(\dpid[7]~input_o ), + .cin(\dpwm|LessThan0~13_cout ), + .combout(\dpwm|LessThan0~14_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|LessThan0~14 .lut_mask = 16'hF550; +defparam \dpwm|LessThan0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N10 +cycloneive_lcell_comb \dpwm|delay0 ( +// Equation(s): +// \dpwm|delay0~combout = LCELL(!\dpwm|LessThan0~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|LessThan0~14_combout ), + .cin(gnd), + .combout(\dpwm|delay0~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay0 .lut_mask = 16'h00FF; +defparam \dpwm|delay0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N4 +cycloneive_lcell_comb \dpwm|de7 ( +// Equation(s): +// \dpwm|de7~combout = LCELL(\dpwm|delay0~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay0~combout ), + .cin(gnd), + .combout(\dpwm|de7~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de7 .lut_mask = 16'hFF00; +defparam \dpwm|de7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N12 +cycloneive_lcell_comb \dpwm|delay1 ( +// Equation(s): +// \dpwm|delay1~combout = LCELL(\dpwm|de7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|de7~combout ), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|delay1~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay1 .lut_mask = 16'hF0F0; +defparam \dpwm|delay1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N2 +cycloneive_lcell_comb \dpwm|de6 ( +// Equation(s): +// \dpwm|de6~combout = LCELL(\dpwm|delay1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay1~combout ), + .cin(gnd), + .combout(\dpwm|de6~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de6 .lut_mask = 16'hFF00; +defparam \dpwm|de6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N18 +cycloneive_lcell_comb \dpwm|delay2 ( +// Equation(s): +// \dpwm|delay2~combout = LCELL(\dpwm|de6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|de6~combout ), + .cin(gnd), + .combout(\dpwm|delay2~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay2 .lut_mask = 16'hFF00; +defparam \dpwm|delay2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N28 +cycloneive_lcell_comb \dpwm|de5 ( +// Equation(s): +// \dpwm|de5~combout = LCELL(\dpwm|delay2~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay2~combout ), + .cin(gnd), + .combout(\dpwm|de5~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de5 .lut_mask = 16'hFF00; +defparam \dpwm|de5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N0 +cycloneive_lcell_comb \dpwm|delay3 ( +// Equation(s): +// \dpwm|delay3~combout = LCELL(\dpwm|de5~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|de5~combout ), + .cin(gnd), + .combout(\dpwm|delay3~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay3 .lut_mask = 16'hFF00; +defparam \dpwm|delay3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y18_N4 +cycloneive_lcell_comb \dpwm|de4 ( +// Equation(s): +// \dpwm|de4~combout = LCELL(\dpwm|delay3~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay3~combout ), + .cin(gnd), + .combout(\dpwm|de4~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de4 .lut_mask = 16'hFF00; +defparam \dpwm|de4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \dpwm|bit_high_syn~0 ( +// Equation(s): +// \dpwm|bit_high_syn~0_combout = !\dpwm|out_8bit [7] + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|out_8bit [7]), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|bit_high_syn~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|bit_high_syn~0 .lut_mask = 16'h0F0F; +defparam \dpwm|bit_high_syn~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N29 +dffeas \dpwm|bit_high_syn ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|bit_high_syn~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|bit_high_syn~q ), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|bit_high_syn .is_wysiwyg = "true"; +defparam \dpwm|bit_high_syn .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \dpwm|n_bit_high_syn~0 ( +// Equation(s): +// \dpwm|n_bit_high_syn~0_combout = !\dpwm|bit_high_syn~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|bit_high_syn~q ), + .cin(gnd), + .combout(\dpwm|n_bit_high_syn~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|n_bit_high_syn~0 .lut_mask = 16'h00FF; +defparam \dpwm|n_bit_high_syn~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N19 +dffeas \dpwm|n_bit_high_syn ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|n_bit_high_syn~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|n_bit_high_syn~q ), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|n_bit_high_syn .is_wysiwyg = "true"; +defparam \dpwm|n_bit_high_syn .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \dpwm|pwm_out ( +// Equation(s): +// \dpwm|pwm_out~combout = (\dpwm|n_bit_high_syn~q & \dpwm|bit_high_syn~q ) + + .dataa(gnd), + .datab(\dpwm|n_bit_high_syn~q ), + .datac(gnd), + .datad(\dpwm|bit_high_syn~q ), + .cin(gnd), + .combout(\dpwm|pwm_out~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|pwm_out .lut_mask = 16'hCC00; +defparam \dpwm|pwm_out .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/dpwm/simulation/modelsim/dpwm_8_1200mv_85c_v_slow.sdo b/dpwm/simulation/modelsim/dpwm_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..f61993d --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,720 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "dpwm_top") + (DATE "11/05/2018 21:21:20") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (462:462:462) (417:417:417)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (461:461:461) (415:415:415)) + (IOPATH i o (3128:3128:3128) (3105:3105:3105)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (464:464:464) (421:421:421)) + (IOPATH i o (3048:3048:3048) (3009:3009:3009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (435:435:435) (390:390:390)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (1024:1024:1024) (914:914:914)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (1327:1327:1327) (1327:1327:1327)) + (PORT inclk[0] (2336:2336:2336) (2336:2336:2336)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1773:1773:1773)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked) + (DELAY + (ABSOLUTE + (PORT datac (946:946:946) (1049:1049:1049)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1559:1559:1559) (1485:1485:1485)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (2108:2108:2108) (2121:2121:2121)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|out_8bit\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (571:571:571)) + (PORT datab (357:357:357) (433:433:433)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (406:406:406)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (416:416:416)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (330:330:330) (406:406:406)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (415:415:415)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (330:330:330) (405:405:405)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datad (499:499:499) (529:529:529)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (726:726:726) (772:772:772)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (597:597:597)) + (PORT datab (3456:3456:3456) (3658:3658:3658)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (3425:3425:3425) (3653:3653:3653)) + (PORT datab (741:741:741) (656:656:656)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (469:469:469)) + (PORT datab (3446:3446:3446) (3646:3646:3646)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (3711:3711:3711) (3875:3875:3875)) + (PORT datab (476:476:476) (458:458:458)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (467:467:467)) + (PORT datab (3445:3445:3445) (3646:3646:3646)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (3428:3428:3428) (3654:3654:3654)) + (PORT datab (480:480:480) (462:462:462)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (467:467:467)) + (PORT datab (468:468:468) (537:537:537)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datad (416:416:416) (475:475:475)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay0) + (DELAY + (ABSOLUTE + (PORT datad (1228:1228:1228) (1135:1135:1135)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de7) + (DELAY + (ABSOLUTE + (PORT datad (236:236:236) (255:255:255)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay1) + (DELAY + (ABSOLUTE + (PORT datac (262:262:262) (287:287:287)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de6) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (255:255:255)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay2) + (DELAY + (ABSOLUTE + (PORT datad (264:264:264) (282:282:282)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de5) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (255:255:255)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay3) + (DELAY + (ABSOLUTE + (PORT datad (267:267:267) (284:284:284)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de4) + (DELAY + (ABSOLUTE + (PORT datad (443:443:443) (424:424:424)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|bit_high_syn\~0) + (DELAY + (ABSOLUTE + (PORT datac (554:554:554) (580:580:580)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|bit_high_syn) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|n_bit_high_syn\~0) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (377:377:377)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|n_bit_high_syn) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|pwm_out) + (DELAY + (ABSOLUTE + (PORT datab (333:333:333) (410:410:410)) + (PORT datad (303:303:303) (376:376:376)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) +) diff --git a/dpwm/simulation/modelsim/dpwm_8_1200mv_85c_v_slow.sdo_typ.csd b/dpwm/simulation/modelsim/dpwm_8_1200mv_85c_v_slow.sdo_typ.csd new file mode 100644 index 0000000..a069354 Binary files /dev/null and b/dpwm/simulation/modelsim/dpwm_8_1200mv_85c_v_slow.sdo_typ.csd differ diff --git a/dpwm/simulation/modelsim/dpwm_min_1200mv_0c_fast.vo b/dpwm/simulation/modelsim/dpwm_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..4f441dc --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_min_1200mv_0c_fast.vo @@ -0,0 +1,1224 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" + +// DATE "11/05/2018 21:21:20" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module dpwm_top ( + clk, + rst_n, + dpid, + delay_out, + pwm_out); +input clk; +input rst_n; +input [7:0] dpid; +output [7:0] delay_out; +output pwm_out; + +// Design Ports Information +// delay_out[0] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[1] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[2] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[3] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[4] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[5] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[6] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// delay_out[7] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default +// pwm_out => Location: PIN_K16, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// dpid[7] => Location: PIN_E16, I/O Standard: 2.5 V, Current Strength: Default +// dpid[6] => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[5] => Location: PIN_K15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[4] => Location: PIN_J13, I/O Standard: 2.5 V, Current Strength: Default +// dpid[3] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default +// dpid[2] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default +// dpid[1] => Location: PIN_J12, I/O Standard: 2.5 V, Current Strength: Default +// dpid[0] => Location: PIN_J14, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("dpwm_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \clk~input_o ; +wire \clk~inputclkctrl_outclk ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \my_pll|altpll_component|auto_generated|locked~combout ; +wire \my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ; +wire \dpwm|out_8bit[0]~0_combout ; +wire \dpwm|Add0~0_combout ; +wire \dpwm|Add0~1 ; +wire \dpwm|Add0~2_combout ; +wire \dpwm|Add0~3 ; +wire \dpwm|Add0~4_combout ; +wire \dpwm|Add0~5 ; +wire \dpwm|Add0~6_combout ; +wire \dpwm|Add0~7 ; +wire \dpwm|Add0~8_combout ; +wire \dpwm|Add0~9 ; +wire \dpwm|Add0~10_combout ; +wire \dpwm|Add0~11 ; +wire \dpwm|Add0~12_combout ; +wire \dpid[7]~input_o ; +wire \dpid[6]~input_o ; +wire \dpid[5]~input_o ; +wire \dpid[4]~input_o ; +wire \dpid[3]~input_o ; +wire \dpid[2]~input_o ; +wire \dpid[1]~input_o ; +wire \dpid[0]~input_o ; +wire \dpwm|LessThan0~1_cout ; +wire \dpwm|LessThan0~3_cout ; +wire \dpwm|LessThan0~5_cout ; +wire \dpwm|LessThan0~7_cout ; +wire \dpwm|LessThan0~9_cout ; +wire \dpwm|LessThan0~11_cout ; +wire \dpwm|LessThan0~13_cout ; +wire \dpwm|LessThan0~14_combout ; +wire \dpwm|delay0~combout ; +wire \dpwm|de7~combout ; +wire \dpwm|delay1~combout ; +wire \dpwm|de6~combout ; +wire \dpwm|delay2~combout ; +wire \dpwm|de5~combout ; +wire \dpwm|delay3~combout ; +wire \dpwm|de4~combout ; +wire \dpwm|bit_high_syn~0_combout ; +wire \dpwm|bit_high_syn~q ; +wire \dpwm|n_bit_high_syn~0_combout ; +wire \dpwm|n_bit_high_syn~q ; +wire \dpwm|pwm_out~combout ; +wire [4:0] \my_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \dpwm|out_8bit ; + +wire [4:0] \my_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X34_Y17_N23 +cycloneive_io_obuf \delay_out[0]~output ( + .i(\dpwm|de7~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[0]), + .obar()); +// synopsys translate_off +defparam \delay_out[0]~output .bus_hold = "false"; +defparam \delay_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N16 +cycloneive_io_obuf \delay_out[1]~output ( + .i(\dpwm|de6~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[1]), + .obar()); +// synopsys translate_off +defparam \delay_out[1]~output .bus_hold = "false"; +defparam \delay_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N2 +cycloneive_io_obuf \delay_out[2]~output ( + .i(\dpwm|de5~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[2]), + .obar()); +// synopsys translate_off +defparam \delay_out[2]~output .bus_hold = "false"; +defparam \delay_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y18_N16 +cycloneive_io_obuf \delay_out[3]~output ( + .i(\dpwm|de4~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[3]), + .obar()); +// synopsys translate_off +defparam \delay_out[3]~output .bus_hold = "false"; +defparam \delay_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X21_Y24_N9 +cycloneive_io_obuf \delay_out[4]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[4]), + .obar()); +// synopsys translate_off +defparam \delay_out[4]~output .bus_hold = "false"; +defparam \delay_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y24_N23 +cycloneive_io_obuf \delay_out[5]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[5]), + .obar()); +// synopsys translate_off +defparam \delay_out[5]~output .bus_hold = "false"; +defparam \delay_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y24_N2 +cycloneive_io_obuf \delay_out[6]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[6]), + .obar()); +// synopsys translate_off +defparam \delay_out[6]~output .bus_hold = "false"; +defparam \delay_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X21_Y0_N9 +cycloneive_io_obuf \delay_out[7]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(delay_out[7]), + .obar()); +// synopsys translate_off +defparam \delay_out[7]~output .bus_hold = "false"; +defparam \delay_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y9_N16 +cycloneive_io_obuf \pwm_out~output ( + .i(\dpwm|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out), + .obar()); +// synopsys translate_off +defparam \pwm_out~output .bus_hold = "false"; +defparam \pwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk~inputclkctrl .clock_type = "global clock"; +defparam \clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \my_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\my_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \my_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \my_pll|altpll_component|auto_generated|pll1 .m = 12; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .operation_mode = "no compensation"; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \my_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \my_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X1_Y4_N28 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y4_N29 +dffeas \my_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y4_N14 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|locked ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|locked~combout = (!\my_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\my_pll|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|locked~combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked .lut_mask = 16'h0FFF; +defparam \my_pll|altpll_component|auto_generated|locked .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G1 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|locked~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|locked~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X33_Y12_N31 +dffeas \dpwm|out_8bit[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~12_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[7] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N16 +cycloneive_lcell_comb \dpwm|out_8bit[0]~0 ( +// Equation(s): +// \dpwm|out_8bit[0]~0_combout = !\dpwm|out_8bit [0] + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|out_8bit [0]), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|out_8bit[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|out_8bit[0]~0 .lut_mask = 16'h0F0F; +defparam \dpwm|out_8bit[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y12_N17 +dffeas \dpwm|out_8bit[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|out_8bit[0]~0_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[0] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N18 +cycloneive_lcell_comb \dpwm|Add0~0 ( +// Equation(s): +// \dpwm|Add0~0_combout = (\dpwm|out_8bit [1] & (\dpwm|out_8bit [0] $ (VCC))) # (!\dpwm|out_8bit [1] & (\dpwm|out_8bit [0] & VCC)) +// \dpwm|Add0~1 = CARRY((\dpwm|out_8bit [1] & \dpwm|out_8bit [0])) + + .dataa(\dpwm|out_8bit [1]), + .datab(\dpwm|out_8bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm|Add0~0_combout ), + .cout(\dpwm|Add0~1 )); +// synopsys translate_off +defparam \dpwm|Add0~0 .lut_mask = 16'h6688; +defparam \dpwm|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y12_N19 +dffeas \dpwm|out_8bit[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~0_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[1] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N20 +cycloneive_lcell_comb \dpwm|Add0~2 ( +// Equation(s): +// \dpwm|Add0~2_combout = (\dpwm|out_8bit [2] & (!\dpwm|Add0~1 )) # (!\dpwm|out_8bit [2] & ((\dpwm|Add0~1 ) # (GND))) +// \dpwm|Add0~3 = CARRY((!\dpwm|Add0~1 ) # (!\dpwm|out_8bit [2])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~1 ), + .combout(\dpwm|Add0~2_combout ), + .cout(\dpwm|Add0~3 )); +// synopsys translate_off +defparam \dpwm|Add0~2 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N21 +dffeas \dpwm|out_8bit[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~2_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[2] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N22 +cycloneive_lcell_comb \dpwm|Add0~4 ( +// Equation(s): +// \dpwm|Add0~4_combout = (\dpwm|out_8bit [3] & (\dpwm|Add0~3 $ (GND))) # (!\dpwm|out_8bit [3] & (!\dpwm|Add0~3 & VCC)) +// \dpwm|Add0~5 = CARRY((\dpwm|out_8bit [3] & !\dpwm|Add0~3 )) + + .dataa(\dpwm|out_8bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~3 ), + .combout(\dpwm|Add0~4_combout ), + .cout(\dpwm|Add0~5 )); +// synopsys translate_off +defparam \dpwm|Add0~4 .lut_mask = 16'hA50A; +defparam \dpwm|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N23 +dffeas \dpwm|out_8bit[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~4_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[3] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N24 +cycloneive_lcell_comb \dpwm|Add0~6 ( +// Equation(s): +// \dpwm|Add0~6_combout = (\dpwm|out_8bit [4] & (!\dpwm|Add0~5 )) # (!\dpwm|out_8bit [4] & ((\dpwm|Add0~5 ) # (GND))) +// \dpwm|Add0~7 = CARRY((!\dpwm|Add0~5 ) # (!\dpwm|out_8bit [4])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~5 ), + .combout(\dpwm|Add0~6_combout ), + .cout(\dpwm|Add0~7 )); +// synopsys translate_off +defparam \dpwm|Add0~6 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N25 +dffeas \dpwm|out_8bit[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~6_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[4] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N26 +cycloneive_lcell_comb \dpwm|Add0~8 ( +// Equation(s): +// \dpwm|Add0~8_combout = (\dpwm|out_8bit [5] & (\dpwm|Add0~7 $ (GND))) # (!\dpwm|out_8bit [5] & (!\dpwm|Add0~7 & VCC)) +// \dpwm|Add0~9 = CARRY((\dpwm|out_8bit [5] & !\dpwm|Add0~7 )) + + .dataa(\dpwm|out_8bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~7 ), + .combout(\dpwm|Add0~8_combout ), + .cout(\dpwm|Add0~9 )); +// synopsys translate_off +defparam \dpwm|Add0~8 .lut_mask = 16'hA50A; +defparam \dpwm|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N27 +dffeas \dpwm|out_8bit[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~8_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[5] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N28 +cycloneive_lcell_comb \dpwm|Add0~10 ( +// Equation(s): +// \dpwm|Add0~10_combout = (\dpwm|out_8bit [6] & (!\dpwm|Add0~9 )) # (!\dpwm|out_8bit [6] & ((\dpwm|Add0~9 ) # (GND))) +// \dpwm|Add0~11 = CARRY((!\dpwm|Add0~9 ) # (!\dpwm|out_8bit [6])) + + .dataa(gnd), + .datab(\dpwm|out_8bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|Add0~9 ), + .combout(\dpwm|Add0~10_combout ), + .cout(\dpwm|Add0~11 )); +// synopsys translate_off +defparam \dpwm|Add0~10 .lut_mask = 16'h3C3F; +defparam \dpwm|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y12_N29 +dffeas \dpwm|out_8bit[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|Add0~10_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|out_8bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|out_8bit[6] .is_wysiwyg = "true"; +defparam \dpwm|out_8bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N30 +cycloneive_lcell_comb \dpwm|Add0~12 ( +// Equation(s): +// \dpwm|Add0~12_combout = \dpwm|Add0~11 $ (!\dpwm|out_8bit [7]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|out_8bit [7]), + .cin(\dpwm|Add0~11 ), + .combout(\dpwm|Add0~12_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|Add0~12 .lut_mask = 16'hF00F; +defparam \dpwm|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y12_N8 +cycloneive_io_ibuf \dpid[7]~input ( + .i(dpid[7]), + .ibar(gnd), + .o(\dpid[7]~input_o )); +// synopsys translate_off +defparam \dpid[7]~input .bus_hold = "false"; +defparam \dpid[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y12_N1 +cycloneive_io_ibuf \dpid[6]~input ( + .i(dpid[6]), + .ibar(gnd), + .o(\dpid[6]~input_o )); +// synopsys translate_off +defparam \dpid[6]~input .bus_hold = "false"; +defparam \dpid[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y9_N8 +cycloneive_io_ibuf \dpid[5]~input ( + .i(dpid[5]), + .ibar(gnd), + .o(\dpid[5]~input_o )); +// synopsys translate_off +defparam \dpid[5]~input .bus_hold = "false"; +defparam \dpid[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N1 +cycloneive_io_ibuf \dpid[4]~input ( + .i(dpid[4]), + .ibar(gnd), + .o(\dpid[4]~input_o )); +// synopsys translate_off +defparam \dpid[4]~input .bus_hold = "false"; +defparam \dpid[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y9_N1 +cycloneive_io_ibuf \dpid[3]~input ( + .i(dpid[3]), + .ibar(gnd), + .o(\dpid[3]~input_o )); +// synopsys translate_off +defparam \dpid[3]~input .bus_hold = "false"; +defparam \dpid[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N8 +cycloneive_io_ibuf \dpid[2]~input ( + .i(dpid[2]), + .ibar(gnd), + .o(\dpid[2]~input_o )); +// synopsys translate_off +defparam \dpid[2]~input .bus_hold = "false"; +defparam \dpid[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N8 +cycloneive_io_ibuf \dpid[1]~input ( + .i(dpid[1]), + .ibar(gnd), + .o(\dpid[1]~input_o )); +// synopsys translate_off +defparam \dpid[1]~input .bus_hold = "false"; +defparam \dpid[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N1 +cycloneive_io_ibuf \dpid[0]~input ( + .i(dpid[0]), + .ibar(gnd), + .o(\dpid[0]~input_o )); +// synopsys translate_off +defparam \dpid[0]~input .bus_hold = "false"; +defparam \dpid[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N0 +cycloneive_lcell_comb \dpwm|LessThan0~1 ( +// Equation(s): +// \dpwm|LessThan0~1_cout = CARRY((\dpwm|out_8bit [0] & \dpid[0]~input_o )) + + .dataa(\dpwm|out_8bit [0]), + .datab(\dpid[0]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\dpwm|LessThan0~1_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~1 .lut_mask = 16'h0088; +defparam \dpwm|LessThan0~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N2 +cycloneive_lcell_comb \dpwm|LessThan0~3 ( +// Equation(s): +// \dpwm|LessThan0~3_cout = CARRY((\dpid[1]~input_o & (\dpwm|Add0~0_combout & !\dpwm|LessThan0~1_cout )) # (!\dpid[1]~input_o & ((\dpwm|Add0~0_combout ) # (!\dpwm|LessThan0~1_cout )))) + + .dataa(\dpid[1]~input_o ), + .datab(\dpwm|Add0~0_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~1_cout ), + .combout(), + .cout(\dpwm|LessThan0~3_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~3 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N4 +cycloneive_lcell_comb \dpwm|LessThan0~5 ( +// Equation(s): +// \dpwm|LessThan0~5_cout = CARRY((\dpwm|Add0~2_combout & (\dpid[2]~input_o & !\dpwm|LessThan0~3_cout )) # (!\dpwm|Add0~2_combout & ((\dpid[2]~input_o ) # (!\dpwm|LessThan0~3_cout )))) + + .dataa(\dpwm|Add0~2_combout ), + .datab(\dpid[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~3_cout ), + .combout(), + .cout(\dpwm|LessThan0~5_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~5 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N6 +cycloneive_lcell_comb \dpwm|LessThan0~7 ( +// Equation(s): +// \dpwm|LessThan0~7_cout = CARRY((\dpid[3]~input_o & (\dpwm|Add0~4_combout & !\dpwm|LessThan0~5_cout )) # (!\dpid[3]~input_o & ((\dpwm|Add0~4_combout ) # (!\dpwm|LessThan0~5_cout )))) + + .dataa(\dpid[3]~input_o ), + .datab(\dpwm|Add0~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~5_cout ), + .combout(), + .cout(\dpwm|LessThan0~7_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~7 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N8 +cycloneive_lcell_comb \dpwm|LessThan0~9 ( +// Equation(s): +// \dpwm|LessThan0~9_cout = CARRY((\dpwm|Add0~6_combout & (\dpid[4]~input_o & !\dpwm|LessThan0~7_cout )) # (!\dpwm|Add0~6_combout & ((\dpid[4]~input_o ) # (!\dpwm|LessThan0~7_cout )))) + + .dataa(\dpwm|Add0~6_combout ), + .datab(\dpid[4]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~7_cout ), + .combout(), + .cout(\dpwm|LessThan0~9_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~9 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N10 +cycloneive_lcell_comb \dpwm|LessThan0~11 ( +// Equation(s): +// \dpwm|LessThan0~11_cout = CARRY((\dpid[5]~input_o & (\dpwm|Add0~8_combout & !\dpwm|LessThan0~9_cout )) # (!\dpid[5]~input_o & ((\dpwm|Add0~8_combout ) # (!\dpwm|LessThan0~9_cout )))) + + .dataa(\dpid[5]~input_o ), + .datab(\dpwm|Add0~8_combout ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~9_cout ), + .combout(), + .cout(\dpwm|LessThan0~11_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~11 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N12 +cycloneive_lcell_comb \dpwm|LessThan0~13 ( +// Equation(s): +// \dpwm|LessThan0~13_cout = CARRY((\dpwm|Add0~10_combout & (\dpid[6]~input_o & !\dpwm|LessThan0~11_cout )) # (!\dpwm|Add0~10_combout & ((\dpid[6]~input_o ) # (!\dpwm|LessThan0~11_cout )))) + + .dataa(\dpwm|Add0~10_combout ), + .datab(\dpid[6]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\dpwm|LessThan0~11_cout ), + .combout(), + .cout(\dpwm|LessThan0~13_cout )); +// synopsys translate_off +defparam \dpwm|LessThan0~13 .lut_mask = 16'h004D; +defparam \dpwm|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y12_N14 +cycloneive_lcell_comb \dpwm|LessThan0~14 ( +// Equation(s): +// \dpwm|LessThan0~14_combout = (\dpwm|Add0~12_combout & (\dpwm|LessThan0~13_cout & \dpid[7]~input_o )) # (!\dpwm|Add0~12_combout & ((\dpwm|LessThan0~13_cout ) # (\dpid[7]~input_o ))) + + .dataa(\dpwm|Add0~12_combout ), + .datab(gnd), + .datac(gnd), + .datad(\dpid[7]~input_o ), + .cin(\dpwm|LessThan0~13_cout ), + .combout(\dpwm|LessThan0~14_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|LessThan0~14 .lut_mask = 16'hF550; +defparam \dpwm|LessThan0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N10 +cycloneive_lcell_comb \dpwm|delay0 ( +// Equation(s): +// \dpwm|delay0~combout = LCELL(!\dpwm|LessThan0~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|LessThan0~14_combout ), + .cin(gnd), + .combout(\dpwm|delay0~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay0 .lut_mask = 16'h00FF; +defparam \dpwm|delay0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N4 +cycloneive_lcell_comb \dpwm|de7 ( +// Equation(s): +// \dpwm|de7~combout = LCELL(\dpwm|delay0~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay0~combout ), + .cin(gnd), + .combout(\dpwm|de7~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de7 .lut_mask = 16'hFF00; +defparam \dpwm|de7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N12 +cycloneive_lcell_comb \dpwm|delay1 ( +// Equation(s): +// \dpwm|delay1~combout = LCELL(\dpwm|de7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|de7~combout ), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|delay1~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay1 .lut_mask = 16'hF0F0; +defparam \dpwm|delay1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N2 +cycloneive_lcell_comb \dpwm|de6 ( +// Equation(s): +// \dpwm|de6~combout = LCELL(\dpwm|delay1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay1~combout ), + .cin(gnd), + .combout(\dpwm|de6~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de6 .lut_mask = 16'hFF00; +defparam \dpwm|de6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N18 +cycloneive_lcell_comb \dpwm|delay2 ( +// Equation(s): +// \dpwm|delay2~combout = LCELL(\dpwm|de6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|de6~combout ), + .cin(gnd), + .combout(\dpwm|delay2~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay2 .lut_mask = 16'hFF00; +defparam \dpwm|delay2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N28 +cycloneive_lcell_comb \dpwm|de5 ( +// Equation(s): +// \dpwm|de5~combout = LCELL(\dpwm|delay2~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay2~combout ), + .cin(gnd), + .combout(\dpwm|de5~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de5 .lut_mask = 16'hFF00; +defparam \dpwm|de5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y17_N0 +cycloneive_lcell_comb \dpwm|delay3 ( +// Equation(s): +// \dpwm|delay3~combout = LCELL(\dpwm|de5~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|de5~combout ), + .cin(gnd), + .combout(\dpwm|delay3~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|delay3 .lut_mask = 16'hFF00; +defparam \dpwm|delay3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y18_N4 +cycloneive_lcell_comb \dpwm|de4 ( +// Equation(s): +// \dpwm|de4~combout = LCELL(\dpwm|delay3~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|delay3~combout ), + .cin(gnd), + .combout(\dpwm|de4~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|de4 .lut_mask = 16'hFF00; +defparam \dpwm|de4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N28 +cycloneive_lcell_comb \dpwm|bit_high_syn~0 ( +// Equation(s): +// \dpwm|bit_high_syn~0_combout = !\dpwm|out_8bit [7] + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm|out_8bit [7]), + .datad(gnd), + .cin(gnd), + .combout(\dpwm|bit_high_syn~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|bit_high_syn~0 .lut_mask = 16'h0F0F; +defparam \dpwm|bit_high_syn~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N29 +dffeas \dpwm|bit_high_syn ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|bit_high_syn~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|bit_high_syn~q ), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|bit_high_syn .is_wysiwyg = "true"; +defparam \dpwm|bit_high_syn .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N18 +cycloneive_lcell_comb \dpwm|n_bit_high_syn~0 ( +// Equation(s): +// \dpwm|n_bit_high_syn~0_combout = !\dpwm|bit_high_syn~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm|bit_high_syn~q ), + .cin(gnd), + .combout(\dpwm|n_bit_high_syn~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|n_bit_high_syn~0 .lut_mask = 16'h00FF; +defparam \dpwm|n_bit_high_syn~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y12_N19 +dffeas \dpwm|n_bit_high_syn ( + .clk(\clk~inputclkctrl_outclk ), + .d(\dpwm|n_bit_high_syn~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm|n_bit_high_syn~q ), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm|n_bit_high_syn .is_wysiwyg = "true"; +defparam \dpwm|n_bit_high_syn .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y12_N8 +cycloneive_lcell_comb \dpwm|pwm_out ( +// Equation(s): +// \dpwm|pwm_out~combout = (\dpwm|n_bit_high_syn~q & \dpwm|bit_high_syn~q ) + + .dataa(gnd), + .datab(\dpwm|n_bit_high_syn~q ), + .datac(gnd), + .datad(\dpwm|bit_high_syn~q ), + .cin(gnd), + .combout(\dpwm|pwm_out~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm|pwm_out .lut_mask = 16'hCC00; +defparam \dpwm|pwm_out .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/dpwm/simulation/modelsim/dpwm_min_1200mv_0c_v_fast.sdo b/dpwm/simulation/modelsim/dpwm_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..ac0443f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,720 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE10F17C8, +// with speed grade M, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "dpwm_top") + (DATE "11/05/2018 21:21:20") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (166:166:166) (183:183:183)) + (IOPATH i o (1599:1599:1599) (1624:1624:1624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (166:166:166) (182:182:182)) + (IOPATH i o (1589:1589:1589) (1614:1614:1614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (166:166:166) (184:184:184)) + (IOPATH i o (1545:1545:1545) (1550:1550:1550)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (154:154:154) (172:172:172)) + (IOPATH i o (1599:1599:1599) (1624:1624:1624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (395:395:395) (439:439:439)) + (IOPATH i o (1599:1599:1599) (1624:1624:1624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (108:108:108) (89:89:89)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (108:108:108) (89:89:89)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (618:618:618) (618:618:618)) + (PORT inclk[0] (1111:1111:1111) (1111:1111:1111)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (784:784:784) (712:712:712)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (776:776:776) (748:748:748)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked) + (DELAY + (ABSOLUTE + (PORT datac (468:468:468) (401:401:401)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (649:649:649) (715:715:715)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (954:954:954) (999:999:999)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|out_8bit\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (755:755:755) (775:775:775)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (256:256:256)) + (PORT datab (140:140:140) (187:187:187)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (755:755:755) (775:775:775)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT datab (129:129:129) (175:175:175)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (755:755:755) (775:775:775)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (178:178:178)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (755:755:755) (775:775:775)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (128:128:128) (175:175:175)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (755:755:755) (775:775:775)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (179:179:179)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (755:755:755) (775:775:775)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (128:128:128) (175:175:175)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (755:755:755) (775:775:775)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datad (188:188:188) (235:235:235)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (668:668:668)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (658:658:658)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (668:668:668)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (668:668:668)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (267:267:267)) + (PORT datab (1642:1642:1642) (1839:1839:1839)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1624:1624:1624) (1828:1828:1828)) + (PORT datab (259:259:259) (301:301:301)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (214:214:214)) + (PORT datab (1635:1635:1635) (1830:1830:1830)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1740:1740:1740) (1941:1941:1941)) + (PORT datab (173:173:173) (210:210:210)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (1631:1631:1631) (1826:1826:1826)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1631:1631:1631) (1835:1835:1835)) + (PORT datab (171:171:171) (210:210:210)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (213:213:213)) + (PORT datab (222:222:222) (201:201:201)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datad (195:195:195) (182:182:182)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay0) + (DELAY + (ABSOLUTE + (PORT datad (486:486:486) (562:562:562)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de7) + (DELAY + (ABSOLUTE + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay1) + (DELAY + (ABSOLUTE + (PORT datac (101:101:101) (123:123:123)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de6) + (DELAY + (ABSOLUTE + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay2) + (DELAY + (ABSOLUTE + (PORT datad (104:104:104) (121:121:121)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de5) + (DELAY + (ABSOLUTE + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay3) + (DELAY + (ABSOLUTE + (PORT datad (105:105:105) (123:123:123)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de4) + (DELAY + (ABSOLUTE + (PORT datad (163:163:163) (191:191:191)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|bit_high_syn\~0) + (DELAY + (ABSOLUTE + (PORT datac (203:203:203) (259:259:259)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|bit_high_syn) + (DELAY + (ABSOLUTE + (PORT clk (755:755:755) (775:775:775)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|n_bit_high_syn\~0) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|n_bit_high_syn) + (DELAY + (ABSOLUTE + (PORT clk (755:755:755) (775:775:775)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|pwm_out) + (DELAY + (ABSOLUTE + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) +) diff --git a/dpwm/simulation/modelsim/dpwm_modelsim.xrf b/dpwm/simulation/modelsim/dpwm_modelsim.xrf new file mode 100644 index 0000000..b3e4951 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_modelsim.xrf @@ -0,0 +1,82 @@ +vendor_name = ModelSim +source_file = 1, F:/Code/FPGA/reserve/dpwm/ip/my_pll.qip +source_file = 1, F:/Code/FPGA/reserve/dpwm/ip/my_pll.v +source_file = 1, F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v +source_file = 1, F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v +source_file = 1, F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/aglobal180.inc +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_pll.inc +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/stratixii_pll.inc +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/cycloneii_pll.inc +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/cbx.lst +source_file = 1, F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v +design_name = dpwm_top +instance = comp, \delay_out[0]~output , delay_out[0]~output, dpwm_top, 1 +instance = comp, \delay_out[1]~output , delay_out[1]~output, dpwm_top, 1 +instance = comp, \delay_out[2]~output , delay_out[2]~output, dpwm_top, 1 +instance = comp, \delay_out[3]~output , delay_out[3]~output, dpwm_top, 1 +instance = comp, \delay_out[4]~output , delay_out[4]~output, dpwm_top, 1 +instance = comp, \delay_out[5]~output , delay_out[5]~output, dpwm_top, 1 +instance = comp, \delay_out[6]~output , delay_out[6]~output, dpwm_top, 1 +instance = comp, \delay_out[7]~output , delay_out[7]~output, dpwm_top, 1 +instance = comp, \pwm_out~output , pwm_out~output, dpwm_top, 1 +instance = comp, \~ALTERA_DCLK~~obuf , ~ALTERA_DCLK~~obuf, dpwm_top, 1 +instance = comp, \~ALTERA_nCEO~~obuf , ~ALTERA_nCEO~~obuf, dpwm_top, 1 +instance = comp, \clk~input , clk~input, dpwm_top, 1 +instance = comp, \clk~inputclkctrl , clk~inputclkctrl, dpwm_top, 1 +instance = comp, \rst_n~input , rst_n~input, dpwm_top, 1 +instance = comp, \rst_n~inputclkctrl , rst_n~inputclkctrl, dpwm_top, 1 +instance = comp, \my_pll|altpll_component|auto_generated|pll1 , my_pll|altpll_component|auto_generated|pll1, dpwm_top, 1 +instance = comp, \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder , my_pll|altpll_component|auto_generated|pll_lock_sync~feeder, dpwm_top, 1 +instance = comp, \my_pll|altpll_component|auto_generated|pll_lock_sync , my_pll|altpll_component|auto_generated|pll_lock_sync, dpwm_top, 1 +instance = comp, \my_pll|altpll_component|auto_generated|locked , my_pll|altpll_component|auto_generated|locked, dpwm_top, 1 +instance = comp, \my_pll|altpll_component|auto_generated|locked~clkctrl , my_pll|altpll_component|auto_generated|locked~clkctrl, dpwm_top, 1 +instance = comp, \dpwm|out_8bit[7] , dpwm|out_8bit[7], dpwm_top, 1 +instance = comp, \dpwm|out_8bit[0]~0 , dpwm|out_8bit[0]~0, dpwm_top, 1 +instance = comp, \dpwm|out_8bit[0] , dpwm|out_8bit[0], dpwm_top, 1 +instance = comp, \dpwm|Add0~0 , dpwm|Add0~0, dpwm_top, 1 +instance = comp, \dpwm|out_8bit[1] , dpwm|out_8bit[1], dpwm_top, 1 +instance = comp, \dpwm|Add0~2 , dpwm|Add0~2, dpwm_top, 1 +instance = comp, \dpwm|out_8bit[2] , dpwm|out_8bit[2], dpwm_top, 1 +instance = comp, \dpwm|Add0~4 , dpwm|Add0~4, dpwm_top, 1 +instance = comp, \dpwm|out_8bit[3] , dpwm|out_8bit[3], dpwm_top, 1 +instance = comp, \dpwm|Add0~6 , dpwm|Add0~6, dpwm_top, 1 +instance = comp, \dpwm|out_8bit[4] , dpwm|out_8bit[4], dpwm_top, 1 +instance = comp, \dpwm|Add0~8 , dpwm|Add0~8, dpwm_top, 1 +instance = comp, \dpwm|out_8bit[5] , dpwm|out_8bit[5], dpwm_top, 1 +instance = comp, \dpwm|Add0~10 , dpwm|Add0~10, dpwm_top, 1 +instance = comp, \dpwm|out_8bit[6] , dpwm|out_8bit[6], dpwm_top, 1 +instance = comp, \dpwm|Add0~12 , dpwm|Add0~12, dpwm_top, 1 +instance = comp, \dpid[7]~input , dpid[7]~input, dpwm_top, 1 +instance = comp, \dpid[6]~input , dpid[6]~input, dpwm_top, 1 +instance = comp, \dpid[5]~input , dpid[5]~input, dpwm_top, 1 +instance = comp, \dpid[4]~input , dpid[4]~input, dpwm_top, 1 +instance = comp, \dpid[3]~input , dpid[3]~input, dpwm_top, 1 +instance = comp, \dpid[2]~input , dpid[2]~input, dpwm_top, 1 +instance = comp, \dpid[1]~input , dpid[1]~input, dpwm_top, 1 +instance = comp, \dpid[0]~input , dpid[0]~input, dpwm_top, 1 +instance = comp, \dpwm|LessThan0~1 , dpwm|LessThan0~1, dpwm_top, 1 +instance = comp, \dpwm|LessThan0~3 , dpwm|LessThan0~3, dpwm_top, 1 +instance = comp, \dpwm|LessThan0~5 , dpwm|LessThan0~5, dpwm_top, 1 +instance = comp, \dpwm|LessThan0~7 , dpwm|LessThan0~7, dpwm_top, 1 +instance = comp, \dpwm|LessThan0~9 , dpwm|LessThan0~9, dpwm_top, 1 +instance = comp, \dpwm|LessThan0~11 , dpwm|LessThan0~11, dpwm_top, 1 +instance = comp, \dpwm|LessThan0~13 , dpwm|LessThan0~13, dpwm_top, 1 +instance = comp, \dpwm|LessThan0~14 , dpwm|LessThan0~14, dpwm_top, 1 +instance = comp, \dpwm|delay0 , dpwm|delay0, dpwm_top, 1 +instance = comp, \dpwm|de7 , dpwm|de7, dpwm_top, 1 +instance = comp, \dpwm|delay1 , dpwm|delay1, dpwm_top, 1 +instance = comp, \dpwm|de6 , dpwm|de6, dpwm_top, 1 +instance = comp, \dpwm|delay2 , dpwm|delay2, dpwm_top, 1 +instance = comp, \dpwm|de5 , dpwm|de5, dpwm_top, 1 +instance = comp, \dpwm|delay3 , dpwm|delay3, dpwm_top, 1 +instance = comp, \dpwm|de4 , dpwm|de4, dpwm_top, 1 +instance = comp, \dpwm|bit_high_syn~0 , dpwm|bit_high_syn~0, dpwm_top, 1 +instance = comp, \dpwm|bit_high_syn , dpwm|bit_high_syn, dpwm_top, 1 +instance = comp, \dpwm|n_bit_high_syn~0 , dpwm|n_bit_high_syn~0, dpwm_top, 1 +instance = comp, \dpwm|n_bit_high_syn , dpwm|n_bit_high_syn, dpwm_top, 1 +instance = comp, \dpwm|pwm_out , dpwm|pwm_out, dpwm_top, 1 +instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, dpwm_top, 1 +instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, dpwm_top, 1 +instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, dpwm_top, 1 diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak1 b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak1 new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak1 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak10 b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak10 new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak10 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak11 b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak11 new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak11 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak2 b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak2 new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak2 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak3 b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak3 new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak3 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak4 b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak4 new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak4 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak5 b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak5 new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak5 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak6 b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak6 new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak6 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak7 b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak7 new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak7 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak8 b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak8 new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak8 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak9 b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak9 new file mode 100644 index 0000000..345959f --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_gate_verilog.do.bak9 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do new file mode 100644 index 0000000..135c822 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak new file mode 100644 index 0000000..d2ebebc --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak1 b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak1 new file mode 100644 index 0000000..1fede35 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak1 @@ -0,0 +1,18 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak10 b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak10 new file mode 100644 index 0000000..27a1619 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak10 @@ -0,0 +1,24 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/jk_trigger.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/clk_mux.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/pwm_prt.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak11 b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak11 new file mode 100644 index 0000000..135c822 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak11 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak2 b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak2 new file mode 100644 index 0000000..911eb9d --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak2 @@ -0,0 +1,19 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_tb.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak3 b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak3 new file mode 100644 index 0000000..911eb9d --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak3 @@ -0,0 +1,19 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_tb.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak4 b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak4 new file mode 100644 index 0000000..517e1d5 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak4 @@ -0,0 +1,22 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/jk_trigger.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_tb.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak5 b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak5 new file mode 100644 index 0000000..e5fe881 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak5 @@ -0,0 +1,21 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/jk_trigger.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak6 b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak6 new file mode 100644 index 0000000..e5fe881 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak6 @@ -0,0 +1,21 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/jk_trigger.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak7 b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak7 new file mode 100644 index 0000000..27a1619 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak7 @@ -0,0 +1,24 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/jk_trigger.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/clk_mux.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/pwm_prt.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak8 b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak8 new file mode 100644 index 0000000..27a1619 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak8 @@ -0,0 +1,24 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/jk_trigger.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/clk_mux.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/pwm_prt.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak9 b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak9 new file mode 100644 index 0000000..27a1619 --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_run_msim_rtl_verilog.do.bak9 @@ -0,0 +1,24 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/jk_trigger.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/clk_mux.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/pwm_prt.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm/simulation/modelsim/dpwm_v.sdo b/dpwm/simulation/modelsim/dpwm_v.sdo new file mode 100644 index 0000000..f61993d --- /dev/null +++ b/dpwm/simulation/modelsim/dpwm_v.sdo @@ -0,0 +1,720 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "dpwm_top") + (DATE "11/05/2018 21:21:20") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (462:462:462) (417:417:417)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (461:461:461) (415:415:415)) + (IOPATH i o (3128:3128:3128) (3105:3105:3105)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (464:464:464) (421:421:421)) + (IOPATH i o (3048:3048:3048) (3009:3009:3009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE delay_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (435:435:435) (390:390:390)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (1024:1024:1024) (914:914:914)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (1327:1327:1327) (1327:1327:1327)) + (PORT inclk[0] (2336:2336:2336) (2336:2336:2336)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1773:1773:1773)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked) + (DELAY + (ABSOLUTE + (PORT datac (946:946:946) (1049:1049:1049)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1559:1559:1559) (1485:1485:1485)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (2108:2108:2108) (2121:2121:2121)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|out_8bit\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (571:571:571)) + (PORT datab (357:357:357) (433:433:433)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (406:406:406)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (416:416:416)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (330:330:330) (406:406:406)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (415:415:415)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (330:330:330) (405:405:405)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|out_8bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1649:1649:1649) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datad (499:499:499) (529:529:529)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (726:726:726) (772:772:772)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE dpid\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (597:597:597)) + (PORT datab (3456:3456:3456) (3658:3658:3658)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (3425:3425:3425) (3653:3653:3653)) + (PORT datab (741:741:741) (656:656:656)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (469:469:469)) + (PORT datab (3446:3446:3446) (3646:3646:3646)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (3711:3711:3711) (3875:3875:3875)) + (PORT datab (476:476:476) (458:458:458)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (467:467:467)) + (PORT datab (3445:3445:3445) (3646:3646:3646)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (3428:3428:3428) (3654:3654:3654)) + (PORT datab (480:480:480) (462:462:462)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (467:467:467)) + (PORT datab (468:468:468) (537:537:537)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|LessThan0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datad (416:416:416) (475:475:475)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay0) + (DELAY + (ABSOLUTE + (PORT datad (1228:1228:1228) (1135:1135:1135)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de7) + (DELAY + (ABSOLUTE + (PORT datad (236:236:236) (255:255:255)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay1) + (DELAY + (ABSOLUTE + (PORT datac (262:262:262) (287:287:287)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de6) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (255:255:255)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay2) + (DELAY + (ABSOLUTE + (PORT datad (264:264:264) (282:282:282)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de5) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (255:255:255)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|delay3) + (DELAY + (ABSOLUTE + (PORT datad (267:267:267) (284:284:284)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|de4) + (DELAY + (ABSOLUTE + (PORT datad (443:443:443) (424:424:424)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|bit_high_syn\~0) + (DELAY + (ABSOLUTE + (PORT datac (554:554:554) (580:580:580)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|bit_high_syn) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|n_bit_high_syn\~0) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (377:377:377)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm\|n_bit_high_syn) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1648:1648:1648)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm\|pwm_out) + (DELAY + (ABSOLUTE + (PORT datab (333:333:333) (410:410:410)) + (PORT datad (303:303:303) (376:376:376)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) +) diff --git a/dpwm/simulation/modelsim/gate_work/_info b/dpwm/simulation/modelsim/gate_work/_info new file mode 100644 index 0000000..862c812 --- /dev/null +++ b/dpwm/simulation/modelsim/gate_work/_info @@ -0,0 +1,54 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dF:/Code/FPGA/reserve/dpwm/simulation/modelsim +vdpwm_top +Z1 !s110 1541425119 +!i10b 1 +!s100 kmDN29:m`JMo_KV7H9l^LOSWQ2g:dI[Yo`Zh3 +R2 +R0 +w1541425070 +8F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v +FF:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v +L0 5 +R3 +r1 +!s85 0 +31 +R4 +!s107 F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+F:/Code/FPGA/reserve/dpwm/testbench|F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v| +!i113 1 +R5 +!s92 -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench +R6 diff --git a/dpwm/simulation/modelsim/gate_work/_lib.qdb b/dpwm/simulation/modelsim/gate_work/_lib.qdb new file mode 100644 index 0000000..0cae056 Binary files /dev/null and b/dpwm/simulation/modelsim/gate_work/_lib.qdb differ diff --git a/dpwm/simulation/modelsim/gate_work/_lib1_0.qdb b/dpwm/simulation/modelsim/gate_work/_lib1_0.qdb new file mode 100644 index 0000000..c4d0c65 Binary files /dev/null and b/dpwm/simulation/modelsim/gate_work/_lib1_0.qdb differ diff --git a/dpwm/simulation/modelsim/gate_work/_lib1_0.qpg b/dpwm/simulation/modelsim/gate_work/_lib1_0.qpg new file mode 100644 index 0000000..6fced8e Binary files /dev/null and b/dpwm/simulation/modelsim/gate_work/_lib1_0.qpg differ diff --git a/dpwm/simulation/modelsim/gate_work/_lib1_0.qtl b/dpwm/simulation/modelsim/gate_work/_lib1_0.qtl new file mode 100644 index 0000000..f9ce833 Binary files /dev/null and b/dpwm/simulation/modelsim/gate_work/_lib1_0.qtl differ diff --git a/dpwm/simulation/modelsim/gate_work/_vmake b/dpwm/simulation/modelsim/gate_work/_vmake new file mode 100644 index 0000000..37aa36a --- /dev/null +++ b/dpwm/simulation/modelsim/gate_work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/dpwm/simulation/modelsim/modelsim.ini b/dpwm/simulation/modelsim/modelsim.ini new file mode 100644 index 0000000..29480d4 --- /dev/null +++ b/dpwm/simulation/modelsim/modelsim.ini @@ -0,0 +1,324 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +work = rtl_work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/dpwm/simulation/modelsim/msim_transcript b/dpwm/simulation/modelsim/msim_transcript new file mode 100644 index 0000000..90e053f --- /dev/null +++ b/dpwm/simulation/modelsim/msim_transcript @@ -0,0 +1,83 @@ +# Reading D:/intelFPGA/18.0/modelsim_ase/tcl/vsim/pref.tcl +# do dpwm_run_msim_rtl_verilog.do +# if {[file exists rtl_work]} { +# vdel -lib rtl_work -all +# } +# vlib rtl_work +# vmap work rtl_work +# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 +# vmap work rtl_work +# Copying D:/intelFPGA/18.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini +# Modifying modelsim.ini +# +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip {F:/Code/FPGA/reserve/dpwm/ip/my_pll.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 21:44:39 on Nov 05,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/dpwm/ip" F:/Code/FPGA/reserve/dpwm/ip/my_pll.v +# -- Compiling module my_pll +# +# Top level modules: +# my_pll +# End time: 21:44:39 on Nov 05,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 21:44:40 on Nov 05,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/dpwm/rtl" F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v +# -- Compiling module dpwm_top +# +# Top level modules: +# dpwm_top +# End time: 21:44:40 on Nov 05,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl {F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 21:44:40 on Nov 05,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/dpwm/rtl" F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v +# -- Compiling module dpwm +# +# Top level modules: +# dpwm +# End time: 21:44:41 on Nov 05,2018, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db {F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 21:44:41 on Nov 05,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/dpwm/db" F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v +# -- Compiling module my_pll_altpll1 +# +# Top level modules: +# my_pll_altpll1 +# End time: 21:44:41 on Nov 05,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench {F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 21:44:41 on Nov 05,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/dpwm/testbench" F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v +# -- Compiling module dpwm_top_tb +# +# Top level modules: +# dpwm_top_tb +# End time: 21:44:41 on Nov 05,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# +# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb +# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=""+acc"" dpwm_top_tb +# Start time: 21:44:42 on Nov 05,2018 +# Loading work.dpwm_top_tb +# Loading work.dpwm_top +# Loading work.dpwm +# Loading altera_mf_ver.lcell +# +# add wave * +# view structure +# .main_pane.structure.interior.cs.body.struct +# view signals +# .main_pane.objects.interior.cs.body.tree +# run -all +# ** Note: $stop : F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v(43) +# Time: 50004 ns Iteration: 0 Instance: /dpwm_top_tb +# Break in Module dpwm_top_tb at F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v line 43 +# End time: 21:45:30 on Nov 05,2018, Elapsed time: 0:00:48 +# Errors: 0, Warnings: 0 diff --git a/dpwm/simulation/modelsim/my_pll.qip b/dpwm/simulation/modelsim/my_pll.qip new file mode 100644 index 0000000..bcfd32c --- /dev/null +++ b/dpwm/simulation/modelsim/my_pll.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "my_pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "my_pll_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "my_pll.ppf"] diff --git a/dpwm/simulation/modelsim/rtl_work/_info b/dpwm/simulation/modelsim/rtl_work/_info new file mode 100644 index 0000000..1a384a4 --- /dev/null +++ b/dpwm/simulation/modelsim/rtl_work/_info @@ -0,0 +1,120 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dF:/Code/FPGA/reserve/dpwm/simulation/modelsim +vdpwm +Z1 !s110 1541425481 +!i10b 1 +!s100 hDm[mBdK79Igk_Va@G^OI1 +IAf9I_?e@l07@2z13Ga_Jm3 +Z2 VDg1SIo80bB@j0V0VzS_@n1 +R0 +w1541425468 +8F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v +FF:/Code/FPGA/reserve/dpwm/rtl/dpwm.v +L0 1 +Z3 OV;L;10.5b;63 +r1 +!s85 0 +31 +Z4 !s108 1541425480.000000 +!s107 F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+F:/Code/FPGA/reserve/dpwm/rtl|F:/Code/FPGA/reserve/dpwm/rtl/dpwm.v| +!i113 1 +Z5 o-vlog01compat -work work +Z6 !s92 -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/rtl +Z7 tCvgOpt 0 +vdpwm_top +!s110 1541425480 +!i10b 1 +!s100 NE9Hn]SBHEGcVCgaNKCZ80 +I=nido;R[jbJKT5iP?o>jA2 +R2 +R0 +w1541424787 +8F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v +FF:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v +L0 1 +R3 +r1 +!s85 0 +31 +R4 +!s107 F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+F:/Code/FPGA/reserve/dpwm/rtl|F:/Code/FPGA/reserve/dpwm/rtl/dpwm_top.v| +!i113 1 +R5 +R6 +R7 +vdpwm_top_tb +R1 +!i10b 1 +!s100 [1acgXloNSf0c]dWzzgLU0 +I8RH8A7@:8>2g:dI[Yo`Zh3 +R2 +R0 +w1541425070 +8F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v +FF:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v +L0 5 +R3 +r1 +!s85 0 +31 +Z8 !s108 1541425481.000000 +!s107 F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+F:/Code/FPGA/reserve/dpwm/testbench|F:/Code/FPGA/reserve/dpwm/testbench/dpwm_top_tb.v| +!i113 1 +R5 +!s92 -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/testbench +R7 +vmy_pll +!s110 1541425479 +!i10b 1 +!s100 Z4GGBOiJ>^d8V1BNSEzO01 +I@hGiCf0B4h@@i39WULYF;1 +R2 +R0 +w1541412130 +8F:/Code/FPGA/reserve/dpwm/ip/my_pll.v +FF:/Code/FPGA/reserve/dpwm/ip/my_pll.v +L0 39 +R3 +r1 +!s85 0 +31 +!s108 1541425479.000000 +!s107 F:/Code/FPGA/reserve/dpwm/ip/my_pll.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+F:/Code/FPGA/reserve/dpwm/ip|F:/Code/FPGA/reserve/dpwm/ip/my_pll.v| +!i113 1 +R5 +!s92 -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/ip +R7 +vmy_pll_altpll1 +R1 +!i10b 1 +!s100 F89kJncA1?mY_Y=;Sc?Mo0 +I>mlM9JbDbnaTa8GRCnRfH3 +R2 +R0 +w1541412170 +8F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v +FF:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v +L0 30 +R3 +r1 +!s85 0 +31 +R8 +!s107 F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+F:/Code/FPGA/reserve/dpwm/db|F:/Code/FPGA/reserve/dpwm/db/my_pll_altpll1.v| +!i113 1 +R5 +!s92 -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm/db +R7 diff --git a/dpwm/simulation/modelsim/rtl_work/_lib.qdb b/dpwm/simulation/modelsim/rtl_work/_lib.qdb new file mode 100644 index 0000000..2c6810d Binary files /dev/null and b/dpwm/simulation/modelsim/rtl_work/_lib.qdb differ diff --git a/dpwm/simulation/modelsim/rtl_work/_lib1_0.qdb b/dpwm/simulation/modelsim/rtl_work/_lib1_0.qdb new file mode 100644 index 0000000..89d1f48 Binary files /dev/null and b/dpwm/simulation/modelsim/rtl_work/_lib1_0.qdb differ diff --git a/dpwm/simulation/modelsim/rtl_work/_lib1_0.qpg b/dpwm/simulation/modelsim/rtl_work/_lib1_0.qpg new file mode 100644 index 0000000..5991905 Binary files /dev/null and b/dpwm/simulation/modelsim/rtl_work/_lib1_0.qpg differ diff --git a/dpwm/simulation/modelsim/rtl_work/_lib1_0.qtl b/dpwm/simulation/modelsim/rtl_work/_lib1_0.qtl new file mode 100644 index 0000000..f9917c1 Binary files /dev/null and b/dpwm/simulation/modelsim/rtl_work/_lib1_0.qtl differ diff --git a/dpwm/simulation/modelsim/rtl_work/_vmake b/dpwm/simulation/modelsim/rtl_work/_vmake new file mode 100644 index 0000000..37aa36a --- /dev/null +++ b/dpwm/simulation/modelsim/rtl_work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/dpwm/simulation/modelsim/tcl_stacktrace.txt b/dpwm/simulation/modelsim/tcl_stacktrace.txt new file mode 100644 index 0000000..77acdd3 --- /dev/null +++ b/dpwm/simulation/modelsim/tcl_stacktrace.txt @@ -0,0 +1,13 @@ +Mon Nov 05 21:40:34 CST 2018 +Trace back: can't read "itk_component(label)": no such element in array + while executing +"$itk_component(label) configure -wraplength $_LAYOUT_TABLE($pos-wrap)" + (method "::iwidgets::Labeledframe::_positionLabel" body line 21) + invoked from within +"::.main_pane.wave.interior.cs.body.pw.wf.sig_dlg.nb.canvas.notebook.cs.page2.cs.format_frame _positionLabel now" + (in namespace inscope "::iwidgets::Labeledframe" script line 1) + invoked from within +"namespace inscope ::iwidgets::Labeledframe {::.main_pane.wave.interior.cs.body.pw.wf.sig_dlg.nb.canvas.notebook.cs.page2.cs.format_frame _positionLabe..." + ("after" script) + <2:D:/intelFPGA/18.0/modelsim_ase/win32aloem/tk8.5/bgerror.tcl:92: ::tkerror {can't read "itk_component(label)": no such element in array} + <1:eval:1: ::tk::dialog::error::bgerror {can't read "itk_component(label)": no such element in array} diff --git a/dpwm/simulation/modelsim/vsim.wlf b/dpwm/simulation/modelsim/vsim.wlf new file mode 100644 index 0000000..4782480 Binary files /dev/null and b/dpwm/simulation/modelsim/vsim.wlf differ diff --git a/dpwm/testbench/dpwm_tb.v b/dpwm/testbench/dpwm_tb.v new file mode 100644 index 0000000..065c72d --- /dev/null +++ b/dpwm/testbench/dpwm_tb.v @@ -0,0 +1,59 @@ +`timescale 1ns/1ns + +`define clk_period 20 + +module dpwm_tb; + +//source define + + +//probe define + reg clk; + reg sel; + reg rst_n; + wire out; + wire clk_0; + wire clk_180; + +//instant user module + +my_pll my_pll ( + .areset(rst_n), + .inclk0(clk), + .c0(clk_0), + .c1(clk_180), + .locked() + ); + +dpwm dpwm( + + .clk_0(clk_0), + .rst_n(rst_n), + .duty(duty), + + .set_pwm(set_pwm), + .rst_pwm(rst_pwm) + +); + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + //integer i; + + initial begin + rst_n = 1; + sel = 0; + #(`clk_period*20) + #3; + rst_n = 0; + + #200; + sel = 1; + #200; + + $stop; + end + +endmodule diff --git a/dpwm/testbench/dpwm_tb.v.bak b/dpwm/testbench/dpwm_tb.v.bak new file mode 100644 index 0000000..deffd23 --- /dev/null +++ b/dpwm/testbench/dpwm_tb.v.bak @@ -0,0 +1,52 @@ +`timescale 1ns/1ns + +`define clk_period 20 + +module dpwm_tb; + +//source define + + +//probe define + reg clk; + reg clk_0; + reg clk_180; + reg sel; + reg rst_n; + wire out; + +//instant user module + +my_pll my_pll ( + .areset(rst_n), + .inclk0(clk), + .c0(clk_0), + .c1(clk_180), + .locked() + ); + +dpwm dpwm( + + .clk_0(clk_0), + .clk_180(clk_180), + .sel(sel), + .out(out) +); + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + //integer i; + + initial begin + rst_n = 0; + #(`clk_period*20) + #3; + rst_n = 1; + + + $stop; + end + +endmodule diff --git a/dpwm/testbench/dpwm_top_tb.v b/dpwm/testbench/dpwm_top_tb.v new file mode 100644 index 0000000..f6e4dca --- /dev/null +++ b/dpwm/testbench/dpwm_top_tb.v @@ -0,0 +1,46 @@ +`timescale 1ps/1ps + +`define clk_period 20 + +module dpwm_top_tb; + +//source define + reg clk; + reg rst_n; + reg [7:0] dpid; + wire pwm_out; + wire [7:0] delay_out; + +//probe define + + +//instant user module +dpwm_top dpwm_top( + + .clk(clk), + .rst_n(rst_n), + .dpid(dpid), + .delay_out(delay_out), + .pwm_out(pwm_out) + ); + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + integer i; + + initial begin + rst_n = 0; + #(`clk_period * 200); + rst_n = 1; + + for(i=10;i<20;i=i+1) begin + dpid = i; + #5000000; + end + + $stop; + end + +endmodule diff --git a/dpwm/testbench/dpwm_top_tb.v.bak b/dpwm/testbench/dpwm_top_tb.v.bak new file mode 100644 index 0000000..ad1a428 --- /dev/null +++ b/dpwm/testbench/dpwm_top_tb.v.bak @@ -0,0 +1,29 @@ +`timescale 1ns/1ns + +`define clk_period 20 + +module dpwm_top_tb; + +//source define + + +//probe define + + +//instant user module + + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + integer i; + + initial begin + + + + $stop; + end + +endmodule diff --git a/dpwm_shake/.qsys_edit/filters.xml b/dpwm_shake/.qsys_edit/filters.xml new file mode 100644 index 0000000..d287b06 --- /dev/null +++ b/dpwm_shake/.qsys_edit/filters.xml @@ -0,0 +1,2 @@ + + diff --git a/dpwm_shake/.qsys_edit/preferences.xml b/dpwm_shake/.qsys_edit/preferences.xml new file mode 100644 index 0000000..58d766f --- /dev/null +++ b/dpwm_shake/.qsys_edit/preferences.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/dpwm_shake/PLLJ_PLLSPE_INFO.txt b/dpwm_shake/PLLJ_PLLSPE_INFO.txt new file mode 100644 index 0000000..722e928 --- /dev/null +++ b/dpwm_shake/PLLJ_PLLSPE_INFO.txt @@ -0,0 +1,5 @@ +PLL_Name pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated|pll1 +PLLJITTER 30 +PLLSPEmax 84 +PLLSPEmin -53 + diff --git a/dpwm_shake/db/.cmp.kpt b/dpwm_shake/db/.cmp.kpt new file mode 100644 index 0000000..4384bdc Binary files /dev/null and b/dpwm_shake/db/.cmp.kpt differ diff --git a/dpwm_shake/db/.ipregen.qmsg b/dpwm_shake/db/.ipregen.qmsg new file mode 100644 index 0000000..5d5f305 --- /dev/null +++ b/dpwm_shake/db/.ipregen.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IIPMAN_IPRGEN_BACKUP_FILE" "ip/pwm_pll.v ip/pwm_pll.BAK.v " "Backing up file \"ip/pwm_pll.v\" to \"ip/pwm_pll.BAK.v\"" { } { } 0 11902 "Backing up file \"%1!s!\" to \"%2!s!\"" 0 0 "Shell" 0 -1 1544266140973 ""} +{ "Info" "IIPMAN_IPRGEN_START" "ALTPLL ip/pwm_pll.v " "Started upgrading IP component ALTPLL with file \"ip/pwm_pll.v\"" { } { } 0 11837 "Started upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1544266140974 ""} +{ "Info" "IIPMAN_IPRGEN_SUCCESSFUL" "ALTPLL ip/pwm_pll.v " "Completed upgrading IP component ALTPLL with file \"ip/pwm_pll.v\"" { } { } 0 11131 "Completed upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1544266142850 ""} +{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "d:/intelfpga/18.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl " "Evaluation of Tcl script d:/intelfpga/18.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful" { } { } 0 23030 "Evaluation of Tcl script %1!s! was successful" 0 0 "Shell" 0 -1 1544266142870 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Shell 0 s 0 s Quartus Prime " "Quartus Prime Shell was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4905 " "Peak virtual memory: 4905 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544266142870 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:49:02 2018 " "Processing ended: Sat Dec 08 18:49:02 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544266142870 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544266142870 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:31 " "Total CPU time (on all processors): 00:00:31" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544266142870 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1544266142870 ""} diff --git a/dpwm_shake/db/dpwm_shake.(0).cnf.cdb b/dpwm_shake/db/dpwm_shake.(0).cnf.cdb new file mode 100644 index 0000000..76b42ef Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.(0).cnf.cdb differ diff --git a/dpwm_shake/db/dpwm_shake.(0).cnf.hdb b/dpwm_shake/db/dpwm_shake.(0).cnf.hdb new file mode 100644 index 0000000..09e009c Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.(0).cnf.hdb differ diff --git a/dpwm_shake/db/dpwm_shake.(1).cnf.cdb b/dpwm_shake/db/dpwm_shake.(1).cnf.cdb new file mode 100644 index 0000000..63d6ce4 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.(1).cnf.cdb differ diff --git a/dpwm_shake/db/dpwm_shake.(1).cnf.hdb b/dpwm_shake/db/dpwm_shake.(1).cnf.hdb new file mode 100644 index 0000000..afb346a Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.(1).cnf.hdb differ diff --git a/dpwm_shake/db/dpwm_shake.(2).cnf.cdb b/dpwm_shake/db/dpwm_shake.(2).cnf.cdb new file mode 100644 index 0000000..95d5791 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.(2).cnf.cdb differ diff --git a/dpwm_shake/db/dpwm_shake.(2).cnf.hdb b/dpwm_shake/db/dpwm_shake.(2).cnf.hdb new file mode 100644 index 0000000..6ceec8f Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.(2).cnf.hdb differ diff --git a/dpwm_shake/db/dpwm_shake.(3).cnf.cdb b/dpwm_shake/db/dpwm_shake.(3).cnf.cdb new file mode 100644 index 0000000..cb1500b Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.(3).cnf.cdb differ diff --git a/dpwm_shake/db/dpwm_shake.(3).cnf.hdb b/dpwm_shake/db/dpwm_shake.(3).cnf.hdb new file mode 100644 index 0000000..00fafc7 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.(3).cnf.hdb differ diff --git a/dpwm_shake/db/dpwm_shake.(4).cnf.cdb b/dpwm_shake/db/dpwm_shake.(4).cnf.cdb new file mode 100644 index 0000000..5d21195 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.(4).cnf.cdb differ diff --git a/dpwm_shake/db/dpwm_shake.(4).cnf.hdb b/dpwm_shake/db/dpwm_shake.(4).cnf.hdb new file mode 100644 index 0000000..ef039f0 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.(4).cnf.hdb differ diff --git a/dpwm_shake/db/dpwm_shake.asm.qmsg b/dpwm_shake/db/dpwm_shake.asm.qmsg new file mode 100644 index 0000000..a9d10da --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544266271780 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544266271793 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 18:51:11 2018 " "Processing started: Sat Dec 08 18:51:11 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544266271793 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1544266271793 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off dpwm_shake -c dpwm_shake " "Command: quartus_asm --read_settings_files=off --write_settings_files=off dpwm_shake -c dpwm_shake" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1544266271793 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1544266272307 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1544266272714 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1544266272748 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4696 " "Peak virtual memory: 4696 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544266272915 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:51:12 2018 " "Processing ended: Sat Dec 08 18:51:12 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544266272915 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544266272915 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544266272915 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1544266272915 ""} diff --git a/dpwm_shake/db/dpwm_shake.asm.rdb b/dpwm_shake/db/dpwm_shake.asm.rdb new file mode 100644 index 0000000..7043c7d Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.asm.rdb differ diff --git a/dpwm_shake/db/dpwm_shake.asm_labs.ddb b/dpwm_shake/db/dpwm_shake.asm_labs.ddb new file mode 100644 index 0000000..d1ec1b1 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.asm_labs.ddb differ diff --git a/dpwm_shake/db/dpwm_shake.cmp.bpm b/dpwm_shake/db/dpwm_shake.cmp.bpm new file mode 100644 index 0000000..e5e2b41 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.cmp.bpm differ diff --git a/dpwm_shake/db/dpwm_shake.cmp.cdb b/dpwm_shake/db/dpwm_shake.cmp.cdb new file mode 100644 index 0000000..a73149e Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.cmp.cdb differ diff --git a/dpwm_shake/db/dpwm_shake.cmp.hdb b/dpwm_shake/db/dpwm_shake.cmp.hdb new file mode 100644 index 0000000..9c39329 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.cmp.hdb differ diff --git a/dpwm_shake/db/dpwm_shake.cmp.idb b/dpwm_shake/db/dpwm_shake.cmp.idb new file mode 100644 index 0000000..39fcae1 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.cmp.idb differ diff --git a/dpwm_shake/db/dpwm_shake.cmp.logdb b/dpwm_shake/db/dpwm_shake.cmp.logdb new file mode 100644 index 0000000..708fa47 --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.cmp.logdb @@ -0,0 +1,59 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;17;0;0;17;17;0;2;0;0;15;0;2;15;0;0;0;2;0;0;0;0;0;17;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,17;17;17;17;17;0;17;17;0;0;17;15;17;17;2;17;15;2;17;17;17;15;17;17;17;17;17;0;17;17, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,pwm_out,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,pwm_out_n,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,rst_n,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,clk,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,control[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21, diff --git a/dpwm_shake/db/dpwm_shake.cmp.rdb b/dpwm_shake/db/dpwm_shake.cmp.rdb new file mode 100644 index 0000000..2c84573 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.cmp.rdb differ diff --git a/dpwm_shake/db/dpwm_shake.cmp_merge.kpt b/dpwm_shake/db/dpwm_shake.cmp_merge.kpt new file mode 100644 index 0000000..31ee9df Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.cmp_merge.kpt differ diff --git a/dpwm_shake/db/dpwm_shake.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/dpwm_shake/db/dpwm_shake.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd new file mode 100644 index 0000000..d24bd1b Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd differ diff --git a/dpwm_shake/db/dpwm_shake.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd b/dpwm_shake/db/dpwm_shake.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd new file mode 100644 index 0000000..87b0f3a Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd differ diff --git a/dpwm_shake/db/dpwm_shake.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd b/dpwm_shake/db/dpwm_shake.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd new file mode 100644 index 0000000..5116cf6 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd differ diff --git a/dpwm_shake/db/dpwm_shake.db_info b/dpwm_shake/db/dpwm_shake.db_info new file mode 100644 index 0000000..9c45acf --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Version_Index = 486699264 +Creation_Time = Sat Dec 08 18:48:02 2018 diff --git a/dpwm_shake/db/dpwm_shake.eda.qmsg b/dpwm_shake/db/dpwm_shake.eda.qmsg new file mode 100644 index 0000000..e4d60ff --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.eda.qmsg @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544266277854 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544266277867 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 18:51:17 2018 " "Processing started: Sat Dec 08 18:51:17 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544266277867 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1544266277867 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off dpwm_shake -c dpwm_shake " "Command: quartus_eda --read_settings_files=off --write_settings_files=off dpwm_shake -c dpwm_shake" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1544266277867 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1544266278521 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_shake_8_1200mv_85c_slow.vo F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/ simulation " "Generated file dpwm_shake_8_1200mv_85c_slow.vo in folder \"F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544266278707 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_shake_8_1200mv_0c_slow.vo F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/ simulation " "Generated file dpwm_shake_8_1200mv_0c_slow.vo in folder \"F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544266278741 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_shake_min_1200mv_0c_fast.vo F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/ simulation " "Generated file dpwm_shake_min_1200mv_0c_fast.vo in folder \"F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544266278792 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_shake.vo F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/ simulation " "Generated file dpwm_shake.vo in folder \"F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544266278822 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_shake_8_1200mv_85c_v_slow.sdo F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/ simulation " "Generated file dpwm_shake_8_1200mv_85c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544266278855 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_shake_8_1200mv_0c_v_slow.sdo F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/ simulation " "Generated file dpwm_shake_8_1200mv_0c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544266278879 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_shake_min_1200mv_0c_v_fast.sdo F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/ simulation " "Generated file dpwm_shake_min_1200mv_0c_v_fast.sdo in folder \"F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544266278902 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "dpwm_shake_v.sdo F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/ simulation " "Generated file dpwm_shake_v.sdo in folder \"F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544266278925 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4664 " "Peak virtual memory: 4664 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544266278970 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:51:18 2018 " "Processing ended: Sat Dec 08 18:51:18 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544266278970 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544266278970 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544266278970 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1544266278970 ""} diff --git a/dpwm_shake/db/dpwm_shake.fit.qmsg b/dpwm_shake/db/dpwm_shake.fit.qmsg new file mode 100644 index 0000000..7dec63f --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.fit.qmsg @@ -0,0 +1,52 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1544266265102 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1544266265103 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "dpwm_shake EP4CE10F17C8 " "Selected device EP4CE10F17C8 for design \"dpwm_shake\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1544266265143 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1544266265222 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1544266265222 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|wire_pll1_clk\[0\] 49 10 0 0 " "Implementing clock multiplication of 49, clock division of 10, and phase shift of 0 degrees (0 ps) for pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pwm_pll_altpll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v" 50 -1 0 } } { "" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 78 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1544266265280 ""} } { { "db/pwm_pll_altpll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v" 50 -1 0 } } { "" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 78 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1544266265280 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1544266265377 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Device EP4CE6F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1544266265609 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1544266265609 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1544266265609 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1544266265609 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 205 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544266265627 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 207 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544266265627 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 209 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544266265627 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 211 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544266265627 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 213 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544266265627 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1544266265627 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1544266265632 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "17 17 " "No exact pin location assignment(s) for 17 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1544266265920 ""} +{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "The Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1544266266161 ""} +{ "Info" "ISTA_SDC_FOUND" "dpwm_shake.out.sdc " "Reading SDC File: 'dpwm_shake.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1544266266162 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "dpwm_shake:dpwm_shake\|cnt\[0\] " "Node: dpwm_shake:dpwm_shake\|cnt\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch dpwm_shake:dpwm_shake\|pwm_out dpwm_shake:dpwm_shake\|cnt\[0\] " "Latch dpwm_shake:dpwm_shake\|pwm_out is being clocked by dpwm_shake:dpwm_shake\|cnt\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1544266266165 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1544266266165 "|dpwm_top|dpwm_shake:dpwm_shake|cnt[0]"} +{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000 " "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1544266266166 ""} } { } 0 332056 "%1!s!" 0 0 "Fitter" 0 -1 1544266266166 ""} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk_0 (Rise) clk_0 (Rise) setup and hold " "From clk_0 (Rise) to clk_0 (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1544266266167 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1544266266167 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1544266266168 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1544266266168 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1544266266168 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 4.500 clk_0 " " 4.500 clk_0" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1544266266168 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1544266266168 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1) " "Automatically promoted node pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} } { { "db/pwm_pll_altpll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v" 92 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 78 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1544266266185 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "rst_all " "Destination node rst_all" { } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 21 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 99 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~0 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~0" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 156 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~1 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~1" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 157 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|shakenum~2 " "Destination node dpwm_shake:dpwm_shake\|shakenum~2" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 25 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 165 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~2 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~2" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 166 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~3 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~3" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 167 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~4 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~4" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 168 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~5 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~5" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 169 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~6 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~6" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 170 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|cat_duty~7 " "Destination node dpwm_shake:dpwm_shake\|cat_duty~7" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 32 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 171 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266185 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1544266266185 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1544266266185 ""} } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 12 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 182 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1544266266185 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_all " "Automatically promoted node rst_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1544266266186 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|shakenum~0 " "Destination node dpwm_shake:dpwm_shake\|shakenum~0" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 25 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 158 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266186 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "dpwm_shake:dpwm_shake\|shakenum~1 " "Destination node dpwm_shake:dpwm_shake\|shakenum~1" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 25 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 164 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1544266266186 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1544266266186 ""} } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 21 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 0 { 0 ""} 0 99 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1544266266186 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1544266266392 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1544266266392 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1544266266393 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1544266266393 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1544266266394 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1544266266394 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1544266266394 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1544266266394 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1544266266395 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1544266266395 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1544266266395 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "15 unused 2.5V 13 2 0 " "Number of I/O pins in group: 15 (unused VREF, 2.5V VCCIO, 13 input, 2 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1544266266397 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1544266266397 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1544266266397 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 12 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 18 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 26 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 27 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 25 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 13 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 26 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 26 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544266266398 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1544266266398 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1544266266398 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544266266420 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1544266266433 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1544266266965 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544266267020 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1544266267038 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1544266267805 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544266267805 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1544266268067 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11" { } { { "loc" "" { Generic "F:/Code/FPGA/reserve/dpwm_shake/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11"} { { 12 { 0 ""} 0 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1544266268527 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1544266268527 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1544266268752 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1544266268752 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1544266268752 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544266268755 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.16 " "Total time spent on timing analysis during the Fitter is 0.16 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1544266268892 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1544266268899 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1544266269038 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1544266269038 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1544266269184 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544266269558 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/Code/FPGA/reserve/dpwm_shake/output_files/dpwm_shake.fit.smsg " "Generated suppressed messages file F:/Code/FPGA/reserve/dpwm_shake/output_files/dpwm_shake.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1544266269897 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 9 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5560 " "Peak virtual memory: 5560 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544266270259 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:51:10 2018 " "Processing ended: Sat Dec 08 18:51:10 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544266270259 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544266270259 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544266270259 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1544266270259 ""} diff --git a/dpwm_shake/db/dpwm_shake.hier_info b/dpwm_shake/db/dpwm_shake.hier_info new file mode 100644 index 0000000..7e61ee3 --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.hier_info @@ -0,0 +1,199 @@ +|dpwm_top +clk => clk.IN2 +rst_n => rst_all.IN1 +rst_n => areset.IN1 +control[0] => control[0].IN1 +control[1] => control[1].IN1 +control[2] => control[2].IN1 +control[3] => control[3].IN1 +control[4] => control[4].IN1 +control[5] => control[5].IN1 +control[6] => control[6].IN1 +control[7] => control[7].IN1 +control[8] => control[8].IN1 +control[9] => control[9].IN1 +control[10] => control[10].IN1 +control[11] => control[11].IN1 +control[12] => control[12].IN1 +pwm_out << dpwm_shake:dpwm_shake.pwm_out +pwm_out_n << dpwm_shake:dpwm_shake.pwm_out_n + + +|dpwm_top|pwm_pll:pwm_pll +areset => areset.IN1 +inclk0 => sub_wire1[0].IN1 +c0 <= altpll:altpll_component.clk +locked <= altpll:altpll_component.locked + + +|dpwm_top|pwm_pll:pwm_pll|altpll:altpll_component +inclk[0] => pwm_pll_altpll:auto_generated.inclk[0] +inclk[1] => pwm_pll_altpll:auto_generated.inclk[1] +fbin => ~NO_FANOUT~ +pllena => ~NO_FANOUT~ +clkswitch => ~NO_FANOUT~ +areset => pwm_pll_altpll:auto_generated.areset +pfdena => ~NO_FANOUT~ +clkena[0] => ~NO_FANOUT~ +clkena[1] => ~NO_FANOUT~ +clkena[2] => ~NO_FANOUT~ +clkena[3] => ~NO_FANOUT~ +clkena[4] => ~NO_FANOUT~ +clkena[5] => ~NO_FANOUT~ +extclkena[0] => ~NO_FANOUT~ +extclkena[1] => ~NO_FANOUT~ +extclkena[2] => ~NO_FANOUT~ +extclkena[3] => ~NO_FANOUT~ +scanclk => ~NO_FANOUT~ +scanclkena => ~NO_FANOUT~ +scanaclr => ~NO_FANOUT~ +scanread => ~NO_FANOUT~ +scanwrite => ~NO_FANOUT~ +scandata => ~NO_FANOUT~ +phasecounterselect[0] => ~NO_FANOUT~ +phasecounterselect[1] => ~NO_FANOUT~ +phasecounterselect[2] => ~NO_FANOUT~ +phasecounterselect[3] => ~NO_FANOUT~ +phaseupdown => ~NO_FANOUT~ +phasestep => ~NO_FANOUT~ +configupdate => ~NO_FANOUT~ +fbmimicbidir <> +clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE +clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE +clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE +clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE +clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE +extclk[0] <= +extclk[1] <= +extclk[2] <= +extclk[3] <= +clkbad[0] <= +clkbad[1] <= +enable1 <= +enable0 <= +activeclock <= +clkloss <= +locked <= pwm_pll_altpll:auto_generated.locked +scandataout <= +scandone <= +sclkout0 <= +sclkout1 <= +phasedone <= +vcooverrange <= +vcounderrange <= +fbout <= +fref <= +icdrclk <= + + +|dpwm_top|pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated +areset => pll_lock_sync.ACLR +areset => pll1.ARESET +clk[0] <= pll1.CLK +clk[1] <= pll1.CLK1 +clk[2] <= pll1.CLK2 +clk[3] <= pll1.CLK3 +clk[4] <= pll1.CLK4 +inclk[0] => pll1.CLK +inclk[1] => pll1.CLK1 +locked <= locked.DB_MAX_OUTPUT_PORT_TYPE + + +|dpwm_top|dpwm_shake:dpwm_shake +clk => ~NO_FANOUT~ +clk_0 => shakenum[0].CLK +clk_0 => shakenum[1].CLK +clk_0 => shakenum[2].CLK +clk_0 => shakenum[3].CLK +clk_0 => new_duty[0].CLK +clk_0 => new_duty[1].CLK +clk_0 => new_duty[2].CLK +clk_0 => new_duty[3].CLK +clk_0 => new_duty[4].CLK +clk_0 => new_duty[5].CLK +clk_0 => new_duty[6].CLK +clk_0 => new_duty[7].CLK +clk_0 => new_duty[8].CLK +clk_0 => new_duty[9].CLK +clk_0 => new_duty[10].CLK +clk_0 => shake_count[0].CLK +clk_0 => shake_count[1].CLK +clk_0 => cnt[0].CLK +clk_0 => cnt[1].CLK +clk_0 => cnt[2].CLK +clk_0 => cnt[3].CLK +clk_0 => cnt[4].CLK +clk_0 => cnt[5].CLK +clk_0 => cnt[6].CLK +clk_0 => cnt[7].CLK +clk_0 => cnt[8].CLK +clk_0 => cnt[9].CLK +clk_0 => cnt[10].CLK +clk_0 => shake_ctr[0].CLK +clk_0 => shake_ctr[1].CLK +clk_0 => cat_duty[0].CLK +clk_0 => cat_duty[1].CLK +clk_0 => cat_duty[2].CLK +clk_0 => cat_duty[3].CLK +clk_0 => cat_duty[4].CLK +clk_0 => cat_duty[5].CLK +clk_0 => cat_duty[6].CLK +clk_0 => cat_duty[7].CLK +clk_0 => cat_duty[8].CLK +clk_0 => cat_duty[9].CLK +clk_0 => cat_duty[10].CLK +clk_0 => cat_duty[11].CLK +rst_n => cat_duty.OUTPUTSELECT +rst_n => cat_duty.OUTPUTSELECT +rst_n => cat_duty.OUTPUTSELECT +rst_n => cat_duty.OUTPUTSELECT +rst_n => cat_duty.OUTPUTSELECT +rst_n => cat_duty.OUTPUTSELECT +rst_n => cat_duty.OUTPUTSELECT +rst_n => cat_duty.OUTPUTSELECT +rst_n => cat_duty.OUTPUTSELECT +rst_n => cat_duty.OUTPUTSELECT +rst_n => cat_duty.OUTPUTSELECT +rst_n => shake_ctr.OUTPUTSELECT +rst_n => shake_ctr.OUTPUTSELECT +rst_n => cnt[0].ACLR +rst_n => cnt[1].ACLR +rst_n => cnt[2].ACLR +rst_n => cnt[3].ACLR +rst_n => cnt[4].ACLR +rst_n => cnt[5].ACLR +rst_n => cnt[6].ACLR +rst_n => cnt[7].ACLR +rst_n => cnt[8].ACLR +rst_n => cnt[9].ACLR +rst_n => cnt[10].ACLR +rst_n => shakenum.OUTPUTSELECT +rst_n => shakenum.OUTPUTSELECT +rst_n => shakenum.OUTPUTSELECT +rst_n => shake_count[0].ACLR +rst_n => shake_count[1].ACLR +control[0] => shake_ctr.DATAA +control[1] => shake_ctr.DATAA +control[2] => cat_duty.DATAA +control[3] => cat_duty.DATAA +control[4] => cat_duty.DATAA +control[5] => cat_duty.DATAA +control[6] => cat_duty.DATAA +control[7] => cat_duty.DATAA +control[8] => cat_duty.DATAA +control[9] => cat_duty.DATAA +control[10] => cat_duty.DATAA +control[11] => cat_duty.DATAA +control[12] => cat_duty.DATAA +dead_zone[0] => ~NO_FANOUT~ +dead_zone[1] => ~NO_FANOUT~ +dead_zone[2] => ~NO_FANOUT~ +dead_zone[3] => ~NO_FANOUT~ +dead_zone[4] => ~NO_FANOUT~ +dead_zone[5] => ~NO_FANOUT~ +dead_zone[6] => ~NO_FANOUT~ +dead_zone[7] => ~NO_FANOUT~ +pwm_out <= pwm_out$latch.DB_MAX_OUTPUT_PORT_TYPE +pwm_out_n <= pwm_out$latch.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/dpwm_shake/db/dpwm_shake.hif b/dpwm_shake/db/dpwm_shake.hif new file mode 100644 index 0000000..8bdb464 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.hif differ diff --git a/dpwm_shake/db/dpwm_shake.lpc.html b/dpwm_shake/db/dpwm_shake.lpc.html new file mode 100644 index 0000000..fe52428 --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.lpc.html @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
dpwm_shake24818288800000
pwm_pll|altpll_component|auto_generated3000600000000
pwm_pll2000200000000
diff --git a/dpwm_shake/db/dpwm_shake.lpc.rdb b/dpwm_shake/db/dpwm_shake.lpc.rdb new file mode 100644 index 0000000..64a168f Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.lpc.rdb differ diff --git a/dpwm_shake/db/dpwm_shake.lpc.txt b/dpwm_shake/db/dpwm_shake.lpc.txt new file mode 100644 index 0000000..247e791 --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.lpc.txt @@ -0,0 +1,9 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; dpwm_shake ; 24 ; 8 ; 1 ; 8 ; 2 ; 8 ; 8 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; pwm_pll|altpll_component|auto_generated ; 3 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; pwm_pll ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/dpwm_shake/db/dpwm_shake.map.ammdb b/dpwm_shake/db/dpwm_shake.map.ammdb new file mode 100644 index 0000000..73f234e Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.map.ammdb differ diff --git a/dpwm_shake/db/dpwm_shake.map.bpm b/dpwm_shake/db/dpwm_shake.map.bpm new file mode 100644 index 0000000..4769749 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.map.bpm differ diff --git a/dpwm_shake/db/dpwm_shake.map.cdb b/dpwm_shake/db/dpwm_shake.map.cdb new file mode 100644 index 0000000..775c8ea Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.map.cdb differ diff --git a/dpwm_shake/db/dpwm_shake.map.hdb b/dpwm_shake/db/dpwm_shake.map.hdb new file mode 100644 index 0000000..8677092 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.map.hdb differ diff --git a/dpwm_shake/db/dpwm_shake.map.kpt b/dpwm_shake/db/dpwm_shake.map.kpt new file mode 100644 index 0000000..f223db2 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.map.kpt differ diff --git a/dpwm_shake/db/dpwm_shake.map.logdb b/dpwm_shake/db/dpwm_shake.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/dpwm_shake/db/dpwm_shake.map.qmsg b/dpwm_shake/db/dpwm_shake.map.qmsg new file mode 100644 index 0000000..8098dbb --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.map.qmsg @@ -0,0 +1,29 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544266248630 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544266248645 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 18:50:48 2018 " "Processing started: Sat Dec 08 18:50:48 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544266248645 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266248645 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dpwm_shake -c dpwm_shake " "Command: quartus_map --read_settings_files=on --write_settings_files=off dpwm_shake -c dpwm_shake" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266248645 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1544266249209 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1544266249209 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/dpwm_shake.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/dpwm_shake.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm_shake " "Found entity 1: dpwm_shake" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544266261536 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266261536 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ip/pwm_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file ip/pwm_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm_pll " "Found entity 1: pwm_pll" { } { { "ip/pwm_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544266261541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266261541 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/dpwm_top.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/dpwm_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm_top " "Found entity 1: dpwm_top" { } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544266261544 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266261544 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "simulation/dpwm_top_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file simulation/dpwm_top_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm_top_tb " "Found entity 1: dpwm_top_tb" { } { { "simulation/dpwm_top_tb.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544266261549 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266261549 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "dpwm_top " "Elaborating entity \"dpwm_top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1544266261603 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm_pll pwm_pll:pwm_pll " "Elaborating entity \"pwm_pll\" for hierarchy \"pwm_pll:pwm_pll\"" { } { { "rtl/dpwm_top.v" "pwm_pll" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 31 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266261614 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pwm_pll:pwm_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"pwm_pll:pwm_pll\|altpll:altpll_component\"" { } { { "ip/pwm_pll.v" "altpll_component" { Text "F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v" 103 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266261676 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "pwm_pll:pwm_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"pwm_pll:pwm_pll\|altpll:altpll_component\"" { } { { "ip/pwm_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v" 103 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266261678 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pwm_pll:pwm_pll\|altpll:altpll_component " "Instantiated megafunction \"pwm_pll:pwm_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 10 " "Parameter \"clk0_divide_by\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 49 " "Parameter \"clk0_multiply_by\" = \"49\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pwm_pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pwm_pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Parameter \"port_areset\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Parameter \"port_clk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock ON " "Parameter \"self_reset_on_loss_lock\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266261678 ""} } { { "ip/pwm_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v" 103 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1544266261678 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pwm_pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pwm_pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm_pll_altpll " "Found entity 1: pwm_pll_altpll" { } { { "db/pwm_pll_altpll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544266261755 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266261755 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm_pll_altpll pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated " "Elaborating entity \"pwm_pll_altpll\" for hierarchy \"pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266261756 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpwm_shake dpwm_shake:dpwm_shake " "Elaborating entity \"dpwm_shake\" for hierarchy \"dpwm_shake:dpwm_shake\"" { } { { "rtl/dpwm_top.v" "dpwm_shake" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 42 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266261760 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tmp_q_n dpwm_shake.v(34) " "Verilog HDL or VHDL warning at dpwm_shake.v(34): object \"tmp_q_n\" assigned a value but never read" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 34 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1544266261761 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 11 dpwm_shake.v(78) " "Verilog HDL assignment warning at dpwm_shake.v(78): truncated value with size 12 to match size of target (11)" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 78 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1544266261761 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 11 dpwm_shake.v(79) " "Verilog HDL assignment warning at dpwm_shake.v(79): truncated value with size 12 to match size of target (11)" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 79 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1544266261761 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 11 dpwm_shake.v(80) " "Verilog HDL assignment warning at dpwm_shake.v(80): truncated value with size 12 to match size of target (11)" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 80 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1544266261762 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 11 dpwm_shake.v(81) " "Verilog HDL assignment warning at dpwm_shake.v(81): truncated value with size 12 to match size of target (11)" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 81 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1544266261762 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "pwm_out dpwm_shake.v(47) " "Inferred latch for \"pwm_out\" at dpwm_shake.v(47)" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 47 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266261762 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1544266262197 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "dpwm_shake:dpwm_shake\|pwm_out " "Latch dpwm_shake:dpwm_shake\|pwm_out has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA dpwm_shake:dpwm_shake\|cnt\[0\] " "Ports D and ENA on the latch are fed by the same signal dpwm_shake:dpwm_shake\|cnt\[0\]" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 68 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1544266262205 ""} } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 19 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1544266262205 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1544266262304 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1544266262840 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266262840 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "80 " "Implemented 80 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Implemented 15 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1544266262884 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1544266262884 ""} { "Info" "ICUT_CUT_TM_LCELLS" "62 " "Implemented 62 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1544266262884 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1544266262884 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1544266262884 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4792 " "Peak virtual memory: 4792 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544266262901 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:51:02 2018 " "Processing ended: Sat Dec 08 18:51:02 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544266262901 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544266262901 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:29 " "Total CPU time (on all processors): 00:00:29" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544266262901 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266262901 ""} diff --git a/dpwm_shake/db/dpwm_shake.map.rdb b/dpwm_shake/db/dpwm_shake.map.rdb new file mode 100644 index 0000000..1f1a34f Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.map.rdb differ diff --git a/dpwm_shake/db/dpwm_shake.map_bb.cdb b/dpwm_shake/db/dpwm_shake.map_bb.cdb new file mode 100644 index 0000000..0b8ca32 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.map_bb.cdb differ diff --git a/dpwm_shake/db/dpwm_shake.map_bb.hdb b/dpwm_shake/db/dpwm_shake.map_bb.hdb new file mode 100644 index 0000000..dcc27da Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.map_bb.hdb differ diff --git a/dpwm_shake/db/dpwm_shake.map_bb.logdb b/dpwm_shake/db/dpwm_shake.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/dpwm_shake/db/dpwm_shake.pre_map.hdb b/dpwm_shake/db/dpwm_shake.pre_map.hdb new file mode 100644 index 0000000..8cb54e9 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.pre_map.hdb differ diff --git a/dpwm_shake/db/dpwm_shake.root_partition.map.reg_db.cdb b/dpwm_shake/db/dpwm_shake.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..0faf844 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.root_partition.map.reg_db.cdb differ diff --git a/dpwm_shake/db/dpwm_shake.routing.rdb b/dpwm_shake/db/dpwm_shake.routing.rdb new file mode 100644 index 0000000..2a5b6a0 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.routing.rdb differ diff --git a/dpwm_shake/db/dpwm_shake.rtlv.hdb b/dpwm_shake/db/dpwm_shake.rtlv.hdb new file mode 100644 index 0000000..6733e11 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.rtlv.hdb differ diff --git a/dpwm_shake/db/dpwm_shake.rtlv_sg.cdb b/dpwm_shake/db/dpwm_shake.rtlv_sg.cdb new file mode 100644 index 0000000..c1b4064 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.rtlv_sg.cdb differ diff --git a/dpwm_shake/db/dpwm_shake.rtlv_sg_swap.cdb b/dpwm_shake/db/dpwm_shake.rtlv_sg_swap.cdb new file mode 100644 index 0000000..d7666d8 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.rtlv_sg_swap.cdb differ diff --git a/dpwm_shake/db/dpwm_shake.sld_design_entry.sci b/dpwm_shake/db/dpwm_shake.sld_design_entry.sci new file mode 100644 index 0000000..0cf4f27 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.sld_design_entry.sci differ diff --git a/dpwm_shake/db/dpwm_shake.sld_design_entry_dsc.sci b/dpwm_shake/db/dpwm_shake.sld_design_entry_dsc.sci new file mode 100644 index 0000000..0cf4f27 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.sld_design_entry_dsc.sci differ diff --git a/dpwm_shake/db/dpwm_shake.smart_action.txt b/dpwm_shake/db/dpwm_shake.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/dpwm_shake/db/dpwm_shake.sta.qmsg b/dpwm_shake/db/dpwm_shake.sta.qmsg new file mode 100644 index 0000000..2551d19 --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.sta.qmsg @@ -0,0 +1,43 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544266274661 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544266274675 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 18:51:14 2018 " "Processing started: Sat Dec 08 18:51:14 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544266274675 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1544266274675 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta dpwm_shake -c dpwm_shake " "Command: quartus_sta dpwm_shake -c dpwm_shake" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1544266274675 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1544266274878 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1544266275089 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1544266275089 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275170 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275171 ""} +{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "The Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Timing Analyzer" 0 -1 1544266275346 ""} +{ "Info" "ISTA_SDC_FOUND" "dpwm_shake.out.sdc " "Reading SDC File: 'dpwm_shake.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1544266275361 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "dpwm_shake:dpwm_shake\|cnt\[0\] " "Node: dpwm_shake:dpwm_shake\|cnt\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch dpwm_shake:dpwm_shake\|pwm_out dpwm_shake:dpwm_shake\|cnt\[0\] " "Latch dpwm_shake:dpwm_shake\|pwm_out is being clocked by dpwm_shake:dpwm_shake\|cnt\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1544266275366 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1544266275366 "|dpwm_top|dpwm_shake:dpwm_shake|cnt[0]"} +{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000 " "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1544266275367 ""} } { } 0 332056 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544266275367 ""} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk_0 (Rise) clk_0 (Rise) setup and hold " "From clk_0 (Rise) to clk_0 (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1544266275367 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1544266275367 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1544266275368 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1544266275377 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.467 " "Worst-case setup slack is 0.467" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275403 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.467 0.000 clk_0 " " 0.467 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275403 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275403 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.452 " "Worst-case hold slack is 0.452" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275406 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 clk_0 " " 0.452 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275406 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275406 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275410 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275413 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.945 " "Worst-case minimum pulse width slack is 1.945" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.945 0.000 clk_0 " " 1.945 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275415 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275415 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1544266275452 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1544266275474 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1544266275704 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "dpwm_shake:dpwm_shake\|cnt\[0\] " "Node: dpwm_shake:dpwm_shake\|cnt\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch dpwm_shake:dpwm_shake\|pwm_out dpwm_shake:dpwm_shake\|cnt\[0\] " "Latch dpwm_shake:dpwm_shake\|pwm_out is being clocked by dpwm_shake:dpwm_shake\|cnt\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1544266275763 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1544266275763 "|dpwm_top|dpwm_shake:dpwm_shake|cnt[0]"} +{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000 " "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1544266275764 ""} } { } 0 332056 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544266275764 ""} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk_0 (Rise) clk_0 (Rise) setup and hold " "From clk_0 (Rise) to clk_0 (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1544266275764 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1544266275764 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.812 " "Worst-case setup slack is 0.812" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275774 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275774 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.812 0.000 clk_0 " " 0.812 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275774 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275774 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.401 " "Worst-case hold slack is 0.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275779 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 clk_0 " " 0.401 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275779 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275779 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275783 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275787 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 1.920 " "Worst-case minimum pulse width slack is 1.920" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275790 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.920 0.000 clk_0 " " 1.920 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275790 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275790 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1544266275818 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "dpwm_shake:dpwm_shake\|cnt\[0\] " "Node: dpwm_shake:dpwm_shake\|cnt\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch dpwm_shake:dpwm_shake\|pwm_out dpwm_shake:dpwm_shake\|cnt\[0\] " "Latch dpwm_shake:dpwm_shake\|pwm_out is being clocked by dpwm_shake:dpwm_shake\|cnt\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1544266275941 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1544266275941 "|dpwm_top|dpwm_shake:dpwm_shake|cnt[0]"} +{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000 " "Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] does not match the period requirement: 20.000" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1544266275941 ""} } { } 0 332056 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544266275941 ""} +{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "clk_0 (Rise) clk_0 (Rise) setup and hold " "From clk_0 (Rise) to clk_0 (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1544266275941 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1544266275941 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.748 " "Worst-case setup slack is 2.748" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.748 0.000 clk_0 " " 2.748 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275945 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275945 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.186 " "Worst-case hold slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275949 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275949 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 clk_0 " " 0.186 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275949 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275949 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275954 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544266275957 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 2.025 " "Worst-case minimum pulse width slack is 2.025" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275960 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.025 0.000 clk_0 " " 2.025 0.000 clk_0 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544266275960 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544266275960 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1544266276369 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1544266276379 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 17 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4776 " "Peak virtual memory: 4776 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544266276427 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:51:16 2018 " "Processing ended: Sat Dec 08 18:51:16 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544266276427 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544266276427 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544266276427 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1544266276427 ""} diff --git a/dpwm_shake/db/dpwm_shake.sta.rdb b/dpwm_shake/db/dpwm_shake.sta.rdb new file mode 100644 index 0000000..01b7597 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.sta.rdb differ diff --git a/dpwm_shake/db/dpwm_shake.sta_cmp.8_slow_1200mv_85c.tdb b/dpwm_shake/db/dpwm_shake.sta_cmp.8_slow_1200mv_85c.tdb new file mode 100644 index 0000000..6751f1c Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.sta_cmp.8_slow_1200mv_85c.tdb differ diff --git a/dpwm_shake/db/dpwm_shake.tis_db_list.ddb b/dpwm_shake/db/dpwm_shake.tis_db_list.ddb new file mode 100644 index 0000000..7dc5f0b Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.tis_db_list.ddb differ diff --git a/dpwm_shake/db/dpwm_shake.tiscmp.fast_1200mv_0c.ddb b/dpwm_shake/db/dpwm_shake.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..7377b15 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.tiscmp.fast_1200mv_0c.ddb differ diff --git a/dpwm_shake/db/dpwm_shake.tiscmp.fastest_slow_1200mv_0c.ddb b/dpwm_shake/db/dpwm_shake.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..5796d52 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/dpwm_shake/db/dpwm_shake.tiscmp.fastest_slow_1200mv_85c.ddb b/dpwm_shake/db/dpwm_shake.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..e9f6347 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/dpwm_shake/db/dpwm_shake.tiscmp.slow_1200mv_0c.ddb b/dpwm_shake/db/dpwm_shake.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..f2cef05 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.tiscmp.slow_1200mv_0c.ddb differ diff --git a/dpwm_shake/db/dpwm_shake.tiscmp.slow_1200mv_85c.ddb b/dpwm_shake/db/dpwm_shake.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..7293758 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.tiscmp.slow_1200mv_85c.ddb differ diff --git a/dpwm_shake/db/dpwm_shake.tmw_info b/dpwm_shake/db/dpwm_shake.tmw_info new file mode 100644 index 0000000..5560c41 --- /dev/null +++ b/dpwm_shake/db/dpwm_shake.tmw_info @@ -0,0 +1,7 @@ +start_full_compilation:s:00:00:32 +start_analysis_synthesis:s:00:00:16-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:07-start_full_compilation +start_assembler:s:00:00:03-start_full_compilation +start_timing_analyzer:s:00:00:04-start_full_compilation +start_eda_netlist_writer:s:00:00:02-start_full_compilation diff --git a/dpwm_shake/db/dpwm_shake.vpr.ammdb b/dpwm_shake/db/dpwm_shake.vpr.ammdb new file mode 100644 index 0000000..f56d3d6 Binary files /dev/null and b/dpwm_shake/db/dpwm_shake.vpr.ammdb differ diff --git a/dpwm_shake/db/dpwm_shake_partition_pins.json b/dpwm_shake/db/dpwm_shake_partition_pins.json new file mode 100644 index 0000000..63db70d --- /dev/null +++ b/dpwm_shake/db/dpwm_shake_partition_pins.json @@ -0,0 +1,73 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "pwm_out", + "strict" : false + }, + { + "name" : "pwm_out_n", + "strict" : false + }, + { + "name" : "rst_n", + "strict" : false + }, + { + "name" : "control[3]", + "strict" : false + }, + { + "name" : "control[2]", + "strict" : false + }, + { + "name" : "control[5]", + "strict" : false + }, + { + "name" : "control[4]", + "strict" : false + }, + { + "name" : "control[7]", + "strict" : false + }, + { + "name" : "control[6]", + "strict" : false + }, + { + "name" : "control[9]", + "strict" : false + }, + { + "name" : "control[8]", + "strict" : false + }, + { + "name" : "control[11]", + "strict" : false + }, + { + "name" : "control[10]", + "strict" : false + }, + { + "name" : "control[12]", + "strict" : false + }, + { + "name" : "control[0]", + "strict" : false + }, + { + "name" : "control[1]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/dpwm_shake/db/prev_cmp_dpwm_shake.qmsg b/dpwm_shake/db/prev_cmp_dpwm_shake.qmsg new file mode 100644 index 0000000..cc46a2b --- /dev/null +++ b/dpwm_shake/db/prev_cmp_dpwm_shake.qmsg @@ -0,0 +1,29 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544266215078 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544266215090 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 18:50:14 2018 " "Processing started: Sat Dec 08 18:50:14 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544266215090 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266215090 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dpwm_shake -c dpwm_shake " "Command: quartus_map --read_settings_files=on --write_settings_files=off dpwm_shake -c dpwm_shake" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266215090 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1544266215622 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1544266215622 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/dpwm_shake.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/dpwm_shake.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm_shake " "Found entity 1: dpwm_shake" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544266228016 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266228016 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ip/pwm_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file ip/pwm_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm_pll " "Found entity 1: pwm_pll" { } { { "ip/pwm_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544266228020 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266228020 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/dpwm_top.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/dpwm_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm_top " "Found entity 1: dpwm_top" { } { { "rtl/dpwm_top.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544266228023 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266228023 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "simulation/dpwm_top_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file simulation/dpwm_top_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpwm_top_tb " "Found entity 1: dpwm_top_tb" { } { { "simulation/dpwm_top_tb.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544266228056 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266228056 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "dpwm_top " "Elaborating entity \"dpwm_top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1544266228100 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm_pll pwm_pll:pwm_pll " "Elaborating entity \"pwm_pll\" for hierarchy \"pwm_pll:pwm_pll\"" { } { { "rtl/dpwm_top.v" "pwm_pll" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 31 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266228127 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pwm_pll:pwm_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"pwm_pll:pwm_pll\|altpll:altpll_component\"" { } { { "ip/pwm_pll.v" "altpll_component" { Text "F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v" 103 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266228215 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "pwm_pll:pwm_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"pwm_pll:pwm_pll\|altpll:altpll_component\"" { } { { "ip/pwm_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v" 103 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266228231 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pwm_pll:pwm_pll\|altpll:altpll_component " "Instantiated megafunction \"pwm_pll:pwm_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 10 " "Parameter \"clk0_divide_by\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 49 " "Parameter \"clk0_multiply_by\" = \"49\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pwm_pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pwm_pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Parameter \"port_areset\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Parameter \"port_clk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock ON " "Parameter \"self_reset_on_loss_lock\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544266228231 ""} } { { "ip/pwm_pll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v" 103 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1544266228231 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pwm_pll_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pwm_pll_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm_pll_altpll " "Found entity 1: pwm_pll_altpll" { } { { "db/pwm_pll_altpll.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544266228298 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266228298 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm_pll_altpll pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated " "Elaborating entity \"pwm_pll_altpll\" for hierarchy \"pwm_pll:pwm_pll\|altpll:altpll_component\|pwm_pll_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266228299 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpwm_shake dpwm_shake:dpwm_shake " "Elaborating entity \"dpwm_shake\" for hierarchy \"dpwm_shake:dpwm_shake\"" { } { { "rtl/dpwm_top.v" "dpwm_shake" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v" 42 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266228321 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "tmp_q_n dpwm_shake.v(34) " "Verilog HDL or VHDL warning at dpwm_shake.v(34): object \"tmp_q_n\" assigned a value but never read" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 34 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1544266228321 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 11 dpwm_shake.v(78) " "Verilog HDL assignment warning at dpwm_shake.v(78): truncated value with size 12 to match size of target (11)" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 78 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1544266228322 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 11 dpwm_shake.v(79) " "Verilog HDL assignment warning at dpwm_shake.v(79): truncated value with size 12 to match size of target (11)" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 79 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1544266228322 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 11 dpwm_shake.v(80) " "Verilog HDL assignment warning at dpwm_shake.v(80): truncated value with size 12 to match size of target (11)" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 80 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1544266228322 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 11 dpwm_shake.v(81) " "Verilog HDL assignment warning at dpwm_shake.v(81): truncated value with size 12 to match size of target (11)" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 81 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1544266228322 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "pwm_out dpwm_shake.v(47) " "Inferred latch for \"pwm_out\" at dpwm_shake.v(47)" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 47 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266228323 "|dpwm_top|dpwm_shake:dpwm_shake"} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1544266228833 ""} +{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "dpwm_shake:dpwm_shake\|pwm_out " "Latch dpwm_shake:dpwm_shake\|pwm_out has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA dpwm_shake:dpwm_shake\|cnt\[0\] " "Ports D and ENA on the latch are fed by the same signal dpwm_shake:dpwm_shake\|cnt\[0\]" { } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 68 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1544266228853 ""} } { { "rtl/dpwm_shake.v" "" { Text "F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v" 19 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1544266228853 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1544266228951 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1544266229512 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544266229512 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "80 " "Implemented 80 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Implemented 15 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1544266229559 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1544266229559 ""} { "Info" "ICUT_CUT_TM_LCELLS" "62 " "Implemented 62 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1544266229559 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1544266229559 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1544266229559 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4790 " "Peak virtual memory: 4790 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544266229575 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:50:29 2018 " "Processing ended: Sat Dec 08 18:50:29 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544266229575 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544266229575 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:30 " "Total CPU time (on all processors): 00:00:30" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544266229575 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1544266229575 ""} diff --git a/dpwm_shake/db/pwm_pll_altpll.v b/dpwm_shake/db/pwm_pll_altpll.v new file mode 100644 index 0000000..fb09478 --- /dev/null +++ b/dpwm_shake/db/pwm_pll_altpll.v @@ -0,0 +1,109 @@ +//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=10 clk0_duty_cycle=50 clk0_multiply_by=49 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=pwm_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="ON" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +//VERSION_BEGIN 18.1 cbx_altclkbuf 2018:09:12:13:04:24:SJ cbx_altiobuf_bidir 2018:09:12:13:04:24:SJ cbx_altiobuf_in 2018:09:12:13:04:24:SJ cbx_altiobuf_out 2018:09:12:13:04:24:SJ cbx_altpll 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END +//CBXI_INSTANCE_NAME="dpwm_top_pwm_pll_pwm_pll_altpll_altpll_component" +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + + +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + + +//synthesis_resources = cycloneive_pll 1 reg 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *) +module pwm_pll_altpll + ( + areset, + clk, + inclk, + locked) /* synthesis synthesis_clearbox=1 */; + input areset; + output [4:0] clk; + input [1:0] inclk; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; + tri0 [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + reg pll_lock_sync; + wire [4:0] wire_pll1_clk; + wire wire_pll1_fbout; + wire wire_pll1_locked; + + // synopsys translate_off + initial + pll_lock_sync = 0; + // synopsys translate_on + always @ ( posedge wire_pll1_locked or posedge areset) + if (areset == 1'b1) pll_lock_sync <= 1'b0; + else pll_lock_sync <= 1'b1; + cycloneive_pll pll1 + ( + .activeclock(), + .areset(areset), + .clk(wire_pll1_clk), + .clkbad(), + .fbin(wire_pll1_fbout), + .fbout(wire_pll1_fbout), + .inclk(inclk), + .locked(wire_pll1_locked), + .phasedone(), + .scandataout(), + .scandone(), + .vcooverrange(), + .vcounderrange() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .clkswitch(1'b0), + .configupdate(1'b0), + .pfdena(1'b1), + .phasecounterselect({3{1'b0}}), + .phasestep(1'b0), + .phaseupdown(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + defparam + pll1.bandwidth_type = "auto", + pll1.clk0_divide_by = 10, + pll1.clk0_duty_cycle = 50, + pll1.clk0_multiply_by = 49, + pll1.clk0_phase_shift = "0", + pll1.compensate_clock = "clk0", + pll1.inclk0_input_frequency = 20000, + pll1.operation_mode = "normal", + pll1.pll_type = "auto", + pll1.self_reset_on_loss_lock = "on", + pll1.lpm_type = "cycloneive_pll"; + assign + clk = {wire_pll1_clk[4:0]}, + locked = (wire_pll1_locked & pll_lock_sync); +endmodule //pwm_pll_altpll +//VALID FILE diff --git a/dpwm_shake/dpwm_shake.ipregen.rpt b/dpwm_shake/dpwm_shake.ipregen.rpt new file mode 100644 index 0000000..56cbcb2 --- /dev/null +++ b/dpwm_shake/dpwm_shake.ipregen.rpt @@ -0,0 +1,68 @@ +IP Upgrade report for dpwm_shake +Sat Dec 08 18:49:02 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. IP Upgrade Summary + 3. Successfully Upgraded IP Components + 4. IP Upgrade Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------+ +; IP Upgrade Summary ; ++------------------------------+-------------------------------------------------+ +; IP Components Upgrade Status ; Passed - Sat Dec 08 18:49:02 2018 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; dpwm_shake ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; ++------------------------------+-------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Successfully Upgraded IP Components ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ +; Entity Name ; Component Name ; Version ; Original Source File ; Generation File Path ; New Source File ; Message ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ +; pwm_pll ; ALTPLL ; 18.0 ; ip/pwm_pll.qip ; ip/pwm_pll.v ; ip/pwm_pll.qip ; ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ + + ++---------------------+ +; IP Upgrade Messages ; ++---------------------+ +Info (11902): Backing up file "ip/pwm_pll.v" to "ip/pwm_pll.BAK.v" +Info (11837): Started upgrading IP component ALTPLL with file "ip/pwm_pll.v" +Info (11131): Completed upgrading IP component ALTPLL with file "ip/pwm_pll.v" +Info (23030): Evaluation of Tcl script d:/intelfpga/18.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful +Info: Quartus Prime Shell was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4905 megabytes + Info: Processing ended: Sat Dec 08 18:49:02 2018 + Info: Elapsed time: 00:00:16 + Info: Total CPU time (on all processors): 00:00:31 + + diff --git a/dpwm_shake/dpwm_shake.out.sdc b/dpwm_shake/dpwm_shake.out.sdc new file mode 100644 index 0000000..3484d98 --- /dev/null +++ b/dpwm_shake/dpwm_shake.out.sdc @@ -0,0 +1,108 @@ +## Generated SDC file "dpwm_shake.out.sdc" + +## Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, the Altera Quartus II License Agreement, +## the Altera MegaCore Function License Agreement, or other +## applicable license agreement, including, without limitation, +## that your use is for the sole purpose of programming logic +## devices manufactured by Altera and sold by Altera or its +## authorized distributors. Please refer to the applicable +## agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 15.0.0 Build 145 04/22/2015 SJ Full Version" + +## DATE "Wed Nov 07 17:04:12 2018" + +## +## DEVICE "EP4CE10F17C8" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clk_0} -period 4.500 -waveform { 0.000 2.250 } [get_nets {pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/dpwm_shake/dpwm_shake.qpf b/dpwm_shake/dpwm_shake.qpf new file mode 100644 index 0000000..7bf9620 --- /dev/null +++ b/dpwm_shake/dpwm_shake.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +# Date created = 18:54:05 November 06, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.0" +DATE = "18:54:05 November 06, 2018" + +# Revisions + +PROJECT_REVISION = "dpwm_shake" diff --git a/dpwm_shake/dpwm_shake.qsf b/dpwm_shake/dpwm_shake.qsf new file mode 100644 index 0000000..85ad8c7 --- /dev/null +++ b/dpwm_shake/dpwm_shake.qsf @@ -0,0 +1,71 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +# Date created = 18:54:05 November 06, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# dpwm_shake_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE10F17C8 +set_global_assignment -name TOP_LEVEL_ENTITY dpwm_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:54:05 NOVEMBER 06, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH dpwm_top_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME dpwm_top_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dpwm_top_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dpwm_top_tb -section_id dpwm_top_tb +set_global_assignment -name EDA_TEST_BENCH_FILE simulation/dpwm_top_tb.v -section_id dpwm_top_tb +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VERILOG_FILE rtl/dpwm_shake.v +set_global_assignment -name QIP_FILE ip/pwm_pll.qip +set_global_assignment -name VERILOG_FILE rtl/dpwm_top.v +set_global_assignment -name VERILOG_FILE simulation/dpwm_top_tb.v +set_global_assignment -name SDC_FILE dpwm_shake.out.sdc +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/dpwm_shake/dpwm_shake.qws b/dpwm_shake/dpwm_shake.qws new file mode 100644 index 0000000..1feb218 Binary files /dev/null and b/dpwm_shake/dpwm_shake.qws differ diff --git a/dpwm_shake/dpwm_shake_assignment_defaults.qdf b/dpwm_shake/dpwm_shake_assignment_defaults.qdf new file mode 100644 index 0000000..4b34d12 --- /dev/null +++ b/dpwm_shake/dpwm_shake_assignment_defaults.qdf @@ -0,0 +1,807 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +# Date created = 17:10:31 November 07, 2018 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY -value "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/dpwm_shake/dpwm_shake_nativelink_simulation.rpt b/dpwm_shake/dpwm_shake_nativelink_simulation.rpt new file mode 100644 index 0000000..b17ff0c --- /dev/null +++ b/dpwm_shake/dpwm_shake_nativelink_simulation.rpt @@ -0,0 +1,16 @@ +Info: Start Nativelink Simulation process +Error: Run Analysis and Elaboration successfully before starting RTL NativeLink Simulation +Analysis and Synthesis should be completed successfully before starting RTL NativeLink Simulation +Error: NativeLink simulation flow was NOT successful + + + +================The following additional information is provided to help identify the cause of error while running nativelink scripts================= +Nativelink TCL script failed with errorCode: 1 +Nativelink TCL script failed with errorInfo: 1 + invoked from within +"if ![qmap_successfully_completed] { + nl_postmsg error "Error: Run Analysis and Elaboration successfully before starting RTL NativeLink Simu..." + (procedure "run_eda_simulation_tool" line 232) + invoked from within +"run_eda_simulation_tool eda_opts_hash" diff --git a/dpwm_shake/greybox_tmp/cbx_args.txt b/dpwm_shake/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..3e64375 --- /dev/null +++ b/dpwm_shake/greybox_tmp/cbx_args.txt @@ -0,0 +1,11 @@ +LPM_DIRECTION=UP +LPM_PORT_UPDOWN=PORT_UNUSED +LPM_TYPE=LPM_COUNTER +LPM_WIDTH=8 +DEVICE_FAMILY="Cyclone IV E" +cin +clock +data +sload +cout +q diff --git a/dpwm_shake/incremental_db/README b/dpwm_shake/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/dpwm_shake/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.db_info b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.db_info new file mode 100644 index 0000000..9c45acf --- /dev/null +++ b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Version_Index = 486699264 +Creation_Time = Sat Dec 08 18:48:02 2018 diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.ammdb b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.ammdb new file mode 100644 index 0000000..ee94ec8 Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.ammdb differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.cdb b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.cdb new file mode 100644 index 0000000..b9ec581 Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.cdb differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.dfp b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.dfp differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.hdb b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.hdb new file mode 100644 index 0000000..5928411 Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.hdb differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.logdb b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.rcfdb b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.rcfdb new file mode 100644 index 0000000..ff31ddc Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.cmp.rcfdb differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.cdb b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.cdb new file mode 100644 index 0000000..732689e Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.cdb differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.dpi b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.dpi new file mode 100644 index 0000000..43c4e63 Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.dpi differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.cdb b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..1dd24a6 Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.cdb differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.hb_info b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..eee968e Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.hb_info differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.hdb b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..4f89f17 Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.hdb differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.sig b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.sig new file mode 100644 index 0000000..ba0709d --- /dev/null +++ b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +1697d03df553b4bbb97cf230b0cfe43e \ No newline at end of file diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hdb b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hdb new file mode 100644 index 0000000..56f6246 Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.hdb differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.kpt b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.kpt new file mode 100644 index 0000000..b74498d Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.root_partition.map.kpt differ diff --git a/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.rrp.hdb b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.rrp.hdb new file mode 100644 index 0000000..c7f042d Binary files /dev/null and b/dpwm_shake/incremental_db/compiled_partitions/dpwm_shake.rrp.hdb differ diff --git a/dpwm_shake/ip/pwm_pll.ppf b/dpwm_shake/ip/pwm_pll.ppf new file mode 100644 index 0000000..13e30b6 --- /dev/null +++ b/dpwm_shake/ip/pwm_pll.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/dpwm_shake/ip/pwm_pll.qip b/dpwm_shake/ip/pwm_pll.qip new file mode 100644 index 0000000..0a4f71f --- /dev/null +++ b/dpwm_shake/ip/pwm_pll.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pwm_pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pwm_pll_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pwm_pll.ppf"] diff --git a/dpwm_shake/ip/pwm_pll.v b/dpwm_shake/ip/pwm_pll.v new file mode 100644 index 0000000..9b6bf4e --- /dev/null +++ b/dpwm_shake/ip/pwm_pll.v @@ -0,0 +1,319 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pwm_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Standard Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pwm_pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [0:0] sub_wire2 = 1'h0; + wire [4:0] sub_wire3; + wire sub_wire5; + wire sub_wire0 = inclk0; + wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; + wire [0:0] sub_wire4 = sub_wire3[0:0]; + wire c0 = sub_wire4; + wire locked = sub_wire5; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire1), + .clk (sub_wire3), + .locked (sub_wire5), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 10, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 49, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pwm_pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "ON", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "245.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "245.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pwm_pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "49" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll_bb.v TRUE +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/dpwm_shake/ip/pwm_pll_bb.v b/dpwm_shake/ip/pwm_pll_bb.v new file mode 100644 index 0000000..0067445 --- /dev/null +++ b/dpwm_shake/ip/pwm_pll_bb.v @@ -0,0 +1,209 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pwm_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Standard Edition +// ************************************************************ + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module pwm_pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "245.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "245.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pwm_pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "49" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pwm_pll_bb.v TRUE +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/dpwm_shake/output_files/dpwm_shake.asm.rpt b/dpwm_shake/output_files/dpwm_shake.asm.rpt new file mode 100644 index 0000000..764b0c5 --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.asm.rpt @@ -0,0 +1,91 @@ +Assembler report for dpwm_shake +Sat Dec 08 18:51:12 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: F:/Code/FPGA/reserve/dpwm_shake/output_files/dpwm_shake.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Dec 08 18:51:12 2018 ; +; Revision Name ; dpwm_shake ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-------------------------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------------------------+ +; File Name ; ++-------------------------------------------------------------+ +; F:/Code/FPGA/reserve/dpwm_shake/output_files/dpwm_shake.sof ; ++-------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Assembler Device Options: F:/Code/FPGA/reserve/dpwm_shake/output_files/dpwm_shake.sof ; ++----------------+----------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------------------------+ +; JTAG usercode ; 0x0008FD08 ; +; Checksum ; 0x0008FD08 ; ++----------------+----------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Sat Dec 08 18:51:11 2018 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off dpwm_shake -c dpwm_shake +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4696 megabytes + Info: Processing ended: Sat Dec 08 18:51:12 2018 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/dpwm_shake/output_files/dpwm_shake.done b/dpwm_shake/output_files/dpwm_shake.done new file mode 100644 index 0000000..bd7df02 --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.done @@ -0,0 +1 @@ +Sat Dec 08 18:51:19 2018 diff --git a/dpwm_shake/output_files/dpwm_shake.eda.rpt b/dpwm_shake/output_files/dpwm_shake.eda.rpt new file mode 100644 index 0000000..08edb7d --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.eda.rpt @@ -0,0 +1,108 @@ +EDA Netlist Writer report for dpwm_shake +Sat Dec 08 18:51:18 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Sat Dec 08 18:51:18 2018 ; +; Revision Name ; dpwm_shake ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++-----------------------------------------------------------------------------------------+ +; Generated Files ; ++-----------------------------------------------------------------------------------------+ +; F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_85c_slow.vo ; +; F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_0c_slow.vo ; +; F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/dpwm_shake_min_1200mv_0c_fast.vo ; +; F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/dpwm_shake.vo ; +; F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_85c_v_slow.sdo ; +; F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_0c_v_slow.sdo ; +; F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/dpwm_shake_min_1200mv_0c_v_fast.sdo ; +; F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/dpwm_shake_v.sdo ; ++-----------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Sat Dec 08 18:51:17 2018 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off dpwm_shake -c dpwm_shake +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file dpwm_shake_8_1200mv_85c_slow.vo in folder "F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_shake_8_1200mv_0c_slow.vo in folder "F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_shake_min_1200mv_0c_fast.vo in folder "F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_shake.vo in folder "F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_shake_8_1200mv_85c_v_slow.sdo in folder "F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_shake_8_1200mv_0c_v_slow.sdo in folder "F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_shake_min_1200mv_0c_v_fast.sdo in folder "F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file dpwm_shake_v.sdo in folder "F:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4664 megabytes + Info: Processing ended: Sat Dec 08 18:51:18 2018 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/dpwm_shake/output_files/dpwm_shake.fit.rpt b/dpwm_shake/output_files/dpwm_shake.fit.rpt new file mode 100644 index 0000000..50ada2d --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.fit.rpt @@ -0,0 +1,1264 @@ +Fitter report for dpwm_shake +Sat Dec 08 18:51:09 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. PLL Summary + 17. PLL Usage + 18. I/O Assignment Warnings + 19. Fitter Resource Utilization by Entity + 20. Delay Chain Summary + 21. Pad To Core Delay Chain Fanout + 22. Control Signals + 23. Global & Other Fast Signals + 24. Routing Usage Summary + 25. LAB Logic Elements + 26. LAB-wide Signals + 27. LAB Signals Sourced + 28. LAB Signals Sourced Out + 29. LAB Distinct Inputs + 30. I/O Rules Summary + 31. I/O Rules Details + 32. I/O Rules Matrix + 33. Fitter Device Options + 34. Operating Settings and Conditions + 35. Estimated Delay Added for Hold Timing Summary + 36. Estimated Delay Added for Hold Timing Details + 37. Fitter Messages + 38. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Sat Dec 08 18:51:09 2018 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; dpwm_shake ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Total logic elements ; 62 / 10,320 ( < 1 % ) ; +; Total combinational functions ; 62 / 10,320 ( < 1 % ) ; +; Dedicated logic registers ; 41 / 10,320 ( < 1 % ) ; +; Total registers ; 41 ; +; Total pins ; 17 / 180 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; Total PLLs ; 1 / 2 ( 50 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP4CE10F17C8 ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.4% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 151 ) ; 0.00 % ( 0 / 151 ) ; 0.00 % ( 0 / 151 ) ; +; -- Achieved ; 0.00 % ( 0 / 151 ) ; 0.00 % ( 0 / 151 ) ; 0.00 % ( 0 / 151 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 139 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 12 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in F:/Code/FPGA/reserve/dpwm_shake/output_files/dpwm_shake.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 62 / 10,320 ( < 1 % ) ; +; -- Combinational with no register ; 21 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 41 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 30 ; +; -- 3 input functions ; 10 ; +; -- <=2 input functions ; 22 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 43 ; +; -- arithmetic mode ; 19 ; +; ; ; +; Total registers* ; 41 / 11,172 ( < 1 % ) ; +; -- Dedicated logic registers ; 41 / 10,320 ( < 1 % ) ; +; -- I/O registers ; 0 / 852 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 5 / 645 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 17 / 180 ( 9 % ) ; +; -- Clock pins ; 2 / 3 ( 67 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; M9Ks ; 0 / 46 ( 0 % ) ; +; Total block memory bits ; 0 / 423,936 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; PLLs ; 1 / 2 ( 50 % ) ; +; Global signals ; 3 ; +; -- Global clocks ; 3 / 10 ( 30 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ; +; Peak interconnect usage (total/H/V) ; 0.6% / 0.7% / 0.4% ; +; Maximum fan-out ; 40 ; +; Highest non-global fan-out ; 16 ; +; Total fan-out ; 337 ; +; Average fan-out ; 2.23 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 62 / 10320 ( < 1 % ) ; 0 / 10320 ( 0 % ) ; +; -- Combinational with no register ; 21 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 41 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 30 ; 0 ; +; -- 3 input functions ; 10 ; 0 ; +; -- <=2 input functions ; 22 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 43 ; 0 ; +; -- arithmetic mode ; 19 ; 0 ; +; ; ; ; +; Total registers ; 41 ; 0 ; +; -- Dedicated logic registers ; 41 / 10320 ( < 1 % ) ; 0 / 10320 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 5 / 645 ( < 1 % ) ; 0 / 645 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 17 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; 0 / 46 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; PLL ; 0 / 2 ( 0 % ) ; 1 / 2 ( 50 % ) ; +; Clock control block ; 2 / 12 ( 16 % ) ; 1 / 12 ( 8 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 56 ; 2 ; +; -- Registered Input Connections ; 41 ; 0 ; +; -- Output Connections ; 2 ; 56 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 330 ; 65 ; +; -- Registered Connections ; 152 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 58 ; +; -- hard_block:auto_generated_inst ; 58 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 15 ; 2 ; +; -- Output Ports ; 2 ; 2 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; clk ; E1 ; 1 ; 0 ; 11 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[0] ; L6 ; 2 ; 0 ; 9 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[10] ; L4 ; 2 ; 0 ; 6 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[11] ; J1 ; 2 ; 0 ; 10 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[12] ; J2 ; 2 ; 0 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[1] ; K2 ; 2 ; 0 ; 8 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[2] ; K6 ; 2 ; 0 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[3] ; M1 ; 2 ; 0 ; 11 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[4] ; N2 ; 2 ; 0 ; 7 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[5] ; L1 ; 2 ; 0 ; 8 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[6] ; G2 ; 1 ; 0 ; 18 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[7] ; L3 ; 2 ; 0 ; 7 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[8] ; J6 ; 2 ; 0 ; 10 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; control[9] ; N1 ; 2 ; 0 ; 7 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; rst_n ; M2 ; 2 ; 0 ; 11 ; 14 ; 17 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; pwm_out ; K1 ; 2 ; 0 ; 8 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; pwm_out_n ; L2 ; 2 ; 0 ; 8 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; C1 ; DIFFIO_L1n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; D2 ; DIFFIO_L2p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; F4 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; H1 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; H2 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; H5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; J3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; H14 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; H13 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; H12 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; F16 ; DIFFIO_R3n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 6 / 17 ( 35 % ) ; 2.5V ; -- ; +; 2 ; 15 / 19 ( 79 % ) ; 2.5V ; -- ; +; 3 ; 0 / 26 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 27 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 25 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 1 / 14 ( 7 % ) ; 2.5V ; -- ; +; 7 ; 0 / 26 ( 0 % ) ; 2.5V ; -- ; +; 8 ; 0 / 26 ( 0 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A2 ; 194 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 200 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 196 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 192 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 188 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 183 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 177 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 175 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A10 ; 168 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 161 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 159 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 153 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 155 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 167 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 201 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 197 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 195 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 189 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 184 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 178 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; 176 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B10 ; 169 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 162 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 160 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; 154 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; 156 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B16 ; 141 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; C2 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C3 ; 202 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 187 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C7 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C8 ; 179 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C9 ; 172 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C11 ; 163 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C14 ; 149 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 147 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C16 ; 146 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; D3 ; 203 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D4 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D5 ; 198 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 199 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D8 ; 180 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D9 ; 173 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 151 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 152 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; D14 ; 150 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 144 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D16 ; 143 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 24 ; 1 ; clk ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E5 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E6 ; 191 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; 190 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; 181 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 174 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 158 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 157 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E15 ; 128 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; E16 ; 127 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; F1 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; F4 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; F5 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; 185 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F7 ; 186 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F8 ; 182 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F9 ; 165 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 164 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 166 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; 138 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F14 ; 142 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; F15 ; 140 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F16 ; 139 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G1 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 13 ; 1 ; control[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 10 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G11 ; 145 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G12 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G12 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; 137 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G16 ; 136 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H2 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H3 ; 19 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; H4 ; 18 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; H5 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H12 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; H13 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; H14 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J1 ; 28 ; 2 ; control[11] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J2 ; 27 ; 2 ; control[12] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J3 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 21 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; J5 ; 20 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; J6 ; 29 ; 2 ; control[8] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J11 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J12 ; 123 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J13 ; 124 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J14 ; 122 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 121 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; 120 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 33 ; 2 ; pwm_out ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K2 ; 32 ; 2 ; control[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K5 ; 39 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 30 ; 2 ; control[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; K7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K8 ; 60 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; 76 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K10 ; 87 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K11 ; 110 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K12 ; 105 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K15 ; 119 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; 118 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 35 ; 2 ; control[5] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L2 ; 34 ; 2 ; pwm_out_n ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L3 ; 36 ; 2 ; control[7] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L4 ; 40 ; 2 ; control[10] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L5 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L6 ; 31 ; 2 ; control[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L7 ; 65 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L8 ; 68 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L9 ; 77 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L10 ; 88 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L11 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L12 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L13 ; 114 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L14 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; L15 ; 116 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; 115 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 26 ; 2 ; control[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M2 ; 25 ; 2 ; rst_n ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; 57 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M7 ; 59 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M8 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M9 ; 78 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M10 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M11 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M12 ; 103 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M15 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M16 ; 125 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 38 ; 2 ; control[9] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N2 ; 37 ; 2 ; control[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N3 ; 45 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N4 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N5 ; 55 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N6 ; 56 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N9 ; 79 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N12 ; 101 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N13 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N14 ; 106 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 112 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; 111 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P4 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; P7 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 71 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P9 ; 89 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P11 ; 90 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P14 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P15 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 108 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; 47 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R4 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R5 ; 61 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R6 ; 63 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R7 ; 66 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R8 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R9 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 80 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 85 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 91 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; 109 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T2 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T3 ; 48 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T4 ; 54 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T5 ; 62 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T6 ; 64 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T7 ; 67 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T8 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 75 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T10 ; 81 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T11 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 86 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; 92 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T14 ; 95 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T15 ; 96 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------------------------------------------------------------------------+ +; PLL Summary ; ++-------------------------------+----------------------------------------------------------------------------+ +; Name ; pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated|pll1 ; ++-------------------------------+----------------------------------------------------------------------------+ +; SDC pin name ; pwm_pll|altpll_component|auto_generated|pll1 ; +; PLL mode ; Normal ; +; Compensate clock ; clock0 ; +; Compensated input/output pins ; -- ; +; Switchover type ; -- ; +; Input frequency 0 ; 50.0 MHz ; +; Input frequency 1 ; -- ; +; Nominal PFD frequency ; 10.0 MHz ; +; Nominal VCO frequency ; 490.0 MHz ; +; VCO post scale K counter ; 2 ; +; VCO frequency control ; Auto ; +; VCO phase shift step ; 255 ps ; +; VCO multiply ; -- ; +; VCO divide ; -- ; +; Freq min lock ; 30.62 MHz ; +; Freq max lock ; 66.35 MHz ; +; M VCO Tap ; 0 ; +; M Initial ; 1 ; +; M value ; 49 ; +; N value ; 5 ; +; Charge pump current ; setting 1 ; +; Loop filter resistance ; setting 19 ; +; Loop filter capacitance ; setting 0 ; +; Bandwidth ; 450 kHz to 560 kHz ; +; Bandwidth type ; Medium ; +; Real time reconfigurable ; Off ; +; Scan chain MIF file ; -- ; +; Preserve PLL counter order ; Off ; +; PLL location ; PLL_1 ; +; Inclk0 signal ; clk ; +; Inclk1 signal ; -- ; +; Inclk0 signal type ; Dedicated Pin ; +; Inclk1 signal type ; -- ; ++-------------------------------+----------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Usage ; ++----------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+ +; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ; ++----------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+ +; pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated|wire_pll1_clk[0] ; clock0 ; 49 ; 10 ; 245.0 MHz ; 0 (0 ps) ; 22.50 (255 ps) ; 50/50 ; C0 ; 2 ; 1/1 Even ; -- ; 1 ; 0 ; pwm_pll|altpll_component|auto_generated|pll1|clk[0] ; ++----------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-----------------------------------------------------+ + + ++---------------------------------------------+ +; I/O Assignment Warnings ; ++-------------+-------------------------------+ +; Pin Name ; Reason ; ++-------------+-------------------------------+ +; pwm_out ; Incomplete set of assignments ; +; pwm_out_n ; Incomplete set of assignments ; +; rst_n ; Incomplete set of assignments ; +; clk ; Incomplete set of assignments ; +; control[3] ; Incomplete set of assignments ; +; control[2] ; Incomplete set of assignments ; +; control[5] ; Incomplete set of assignments ; +; control[4] ; Incomplete set of assignments ; +; control[7] ; Incomplete set of assignments ; +; control[6] ; Incomplete set of assignments ; +; control[9] ; Incomplete set of assignments ; +; control[8] ; Incomplete set of assignments ; +; control[11] ; Incomplete set of assignments ; +; control[10] ; Incomplete set of assignments ; +; control[12] ; Incomplete set of assignments ; +; control[0] ; Incomplete set of assignments ; +; control[1] ; Incomplete set of assignments ; +; pwm_out ; Missing location assignment ; +; pwm_out_n ; Missing location assignment ; +; rst_n ; Missing location assignment ; +; clk ; Missing location assignment ; +; control[3] ; Missing location assignment ; +; control[2] ; Missing location assignment ; +; control[5] ; Missing location assignment ; +; control[4] ; Missing location assignment ; +; control[7] ; Missing location assignment ; +; control[6] ; Missing location assignment ; +; control[9] ; Missing location assignment ; +; control[8] ; Missing location assignment ; +; control[11] ; Missing location assignment ; +; control[10] ; Missing location assignment ; +; control[12] ; Missing location assignment ; +; control[0] ; Missing location assignment ; +; control[1] ; Missing location assignment ; ++-------------+-------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------+----------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------+----------------+--------------+ +; |dpwm_top ; 62 (1) ; 41 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 ; 0 ; 21 (1) ; 0 (0) ; 41 (0) ; |dpwm_top ; dpwm_top ; work ; +; |dpwm_shake:dpwm_shake| ; 60 (60) ; 40 (40) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (20) ; 0 (0) ; 40 (40) ; |dpwm_top|dpwm_shake:dpwm_shake ; dpwm_shake ; work ; +; |pwm_pll:pwm_pll| ; 1 (0) ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (0) ; |dpwm_top|pwm_pll:pwm_pll ; pwm_pll ; work ; +; |altpll:altpll_component| ; 1 (0) ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (0) ; |dpwm_top|pwm_pll:pwm_pll|altpll:altpll_component ; altpll ; work ; +; |pwm_pll_altpll:auto_generated| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |dpwm_top|pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated ; pwm_pll_altpll ; work ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------------------------------------------+----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++-------------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++-------------+----------+---------------+---------------+-----------------------+-----+------+ +; pwm_out ; Output ; -- ; -- ; -- ; -- ; -- ; +; pwm_out_n ; Output ; -- ; -- ; -- ; -- ; -- ; +; rst_n ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; clk ; Input ; -- ; -- ; -- ; -- ; -- ; +; control[3] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; control[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; control[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; control[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; control[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; control[6] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; control[9] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; control[8] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; control[11] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; control[10] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; control[12] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; control[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; control[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; ++-------------+----------+---------------+---------------+-----------------------+-----+------+ + + ++------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++------------------------------------------+-------------------+---------+ +; rst_n ; ; ; +; clk ; ; ; +; control[3] ; ; ; +; control[2] ; ; ; +; - dpwm_shake:dpwm_shake|cat_duty~1 ; 1 ; 6 ; +; control[5] ; ; ; +; - dpwm_shake:dpwm_shake|cat_duty~2 ; 0 ; 6 ; +; control[4] ; ; ; +; - dpwm_shake:dpwm_shake|cat_duty~3 ; 0 ; 6 ; +; control[7] ; ; ; +; - dpwm_shake:dpwm_shake|cat_duty~4 ; 0 ; 6 ; +; control[6] ; ; ; +; - dpwm_shake:dpwm_shake|cat_duty~5 ; 1 ; 6 ; +; control[9] ; ; ; +; - dpwm_shake:dpwm_shake|cat_duty~6 ; 0 ; 6 ; +; control[8] ; ; ; +; - dpwm_shake:dpwm_shake|cat_duty~7 ; 0 ; 6 ; +; control[11] ; ; ; +; - dpwm_shake:dpwm_shake|cat_duty~8 ; 1 ; 6 ; +; control[10] ; ; ; +; - dpwm_shake:dpwm_shake|cat_duty~9 ; 1 ; 6 ; +; control[12] ; ; ; +; - dpwm_shake:dpwm_shake|cat_duty~10 ; 1 ; 6 ; +; control[0] ; ; ; +; - dpwm_shake:dpwm_shake|shake_ctr~0 ; 1 ; 6 ; +; control[1] ; ; ; +; - dpwm_shake:dpwm_shake|shake_ctr~1 ; 0 ; 6 ; ++------------------------------------------+-------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++----------------------------------------------------------------------------------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------------------------------------------------------------------------------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; clk ; PIN_E1 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; dpwm_shake:dpwm_shake|Add2~3 ; LCCOMB_X4_Y11_N12 ; 11 ; Sync. load ; no ; -- ; -- ; -- ; +; dpwm_shake:dpwm_shake|pwm_out~2 ; LCCOMB_X1_Y11_N0 ; 1 ; Latch enable ; no ; -- ; -- ; -- ; +; pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated|wire_pll1_clk[0] ; PLL_1 ; 40 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; +; pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated|wire_pll1_locked ; PLL_1 ; 16 ; Clock ; no ; -- ; -- ; -- ; +; rst_all ; LCCOMB_X4_Y11_N4 ; 13 ; Async. clear ; yes ; Global Clock ; GCLK2 ; -- ; +; rst_n ; PIN_M2 ; 2 ; Async. clear ; yes ; Global Clock ; GCLK4 ; -- ; ++----------------------------------------------------------------------------------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++----------------------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------------------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated|wire_pll1_clk[0] ; PLL_1 ; 40 ; 14 ; Global Clock ; GCLK3 ; -- ; +; rst_all ; LCCOMB_X4_Y11_N4 ; 13 ; 0 ; Global Clock ; GCLK2 ; -- ; +; rst_n ; PIN_M2 ; 2 ; 0 ; Global Clock ; GCLK4 ; -- ; ++----------------------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+-----------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+-----------------------+ +; Block interconnects ; 79 / 32,401 ( < 1 % ) ; +; C16 interconnects ; 0 / 1,326 ( 0 % ) ; +; C4 interconnects ; 23 / 21,816 ( < 1 % ) ; +; Direct links ; 36 / 32,401 ( < 1 % ) ; +; Global clocks ; 3 / 10 ( 30 % ) ; +; Local interconnects ; 37 / 10,320 ( < 1 % ) ; +; R24 interconnects ; 1 / 1,289 ( < 1 % ) ; +; R4 interconnects ; 36 / 28,186 ( < 1 % ) ; ++-----------------------+-----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 12.40) ; Number of LABs (Total = 5) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 1 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 3 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 1.80) ; Number of LABs (Total = 5) ; ++------------------------------------+-----------------------------+ +; 1 Async. clear ; 3 ; +; 1 Clock ; 5 ; +; 1 Sync. load ; 1 ; ++------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 20.60) ; Number of LABs (Total = 5) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 2 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 1 ; +; 28 ; 0 ; +; 29 ; 0 ; +; 30 ; 0 ; +; 31 ; 0 ; +; 32 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 8.60) ; Number of LABs (Total = 5) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 1 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 14.00) ; Number of LABs (Total = 5) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 1 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 0 ; +; 29 ; 0 ; +; 30 ; 0 ; +; 31 ; 0 ; +; 32 ; 0 ; +; 33 ; 0 ; +; 34 ; 0 ; +; 35 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 17 ; 17 ; 0 ; 2 ; 0 ; 0 ; 15 ; 0 ; 2 ; 15 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 17 ; 17 ; 17 ; 17 ; 17 ; 0 ; 17 ; 17 ; 0 ; 0 ; 17 ; 15 ; 17 ; 17 ; 2 ; 17 ; 15 ; 2 ; 17 ; 17 ; 17 ; 15 ; 17 ; 17 ; 17 ; 17 ; 17 ; 0 ; 17 ; 17 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; pwm_out ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; pwm_out_n ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; rst_n ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; clk ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; control[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 C ; +; High Junction Temperature ; 85 C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer. + + ++-----------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++-------------------------------+-------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++-------------------------------+-------------------------------+-------------------+ +; dpwm_shake:dpwm_shake|cnt[10] ; dpwm_shake:dpwm_shake|cnt[10] ; 0.011 ; ++-------------------------------+-------------------------------+-------------------+ +Note: This table only shows the top 1 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device EP4CE10F17C8 for design "dpwm_shake" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (15535): Implemented PLL "pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated|pll1" as Cyclone IV E PLL type File: F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v Line: 50 + Info (15099): Implementing clock multiplication of 49, clock division of 10, and phase shift of 0 degrees (0 ps) for pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated|wire_pll1_clk[0] port File: F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v Line: 50 +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE6F17C8 is compatible + Info (176445): Device EP4CE15F17C8 is compatible + Info (176445): Device EP4CE22F17C8 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 17 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Warning (335093): The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report. +Info (332104): Reading SDC File: 'dpwm_shake.out.sdc' +Warning (332060): Node: dpwm_shake:dpwm_shake|cnt[0] was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch dpwm_shake:dpwm_shake|pwm_out is being clocked by dpwm_shake:dpwm_shake|cnt[0] +Warning (332056): PLL cross checking found inconsistent PLL clock settings: + Warning (332056): Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll|altpll_component|auto_generated|pll1|clk[0] does not match the period requirement: 20.000 +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From clk_0 (Rise) to clk_0 (Rise) (setup and hold) +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 1 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 4.500 clk_0 +Info (176353): Automatically promoted node pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_1) File: F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v Line: 92 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info (176353): Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v Line: 12 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node rst_all File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v Line: 21 + Info (176357): Destination node dpwm_shake:dpwm_shake|cat_duty~0 File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 32 + Info (176357): Destination node dpwm_shake:dpwm_shake|cat_duty~1 File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 32 + Info (176357): Destination node dpwm_shake:dpwm_shake|shakenum~2 File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 25 + Info (176357): Destination node dpwm_shake:dpwm_shake|cat_duty~2 File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 32 + Info (176357): Destination node dpwm_shake:dpwm_shake|cat_duty~3 File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 32 + Info (176357): Destination node dpwm_shake:dpwm_shake|cat_duty~4 File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 32 + Info (176357): Destination node dpwm_shake:dpwm_shake|cat_duty~5 File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 32 + Info (176357): Destination node dpwm_shake:dpwm_shake|cat_duty~6 File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 32 + Info (176357): Destination node dpwm_shake:dpwm_shake|cat_duty~7 File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 32 + Info (176358): Non-global destination nodes limited to 10 nodes +Info (176353): Automatically promoted node rst_all File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v Line: 21 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node dpwm_shake:dpwm_shake|shakenum~0 File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 25 + Info (176357): Destination node dpwm_shake:dpwm_shake|shakenum~1 File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 25 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 15 (unused VREF, 2.5V VCCIO, 13 input, 2 output, 0 bidirectional) + Info (176212): I/O standards used: 2.5 V. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.16 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (144001): Generated suppressed messages file F:/Code/FPGA/reserve/dpwm_shake/output_files/dpwm_shake.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 9 warnings + Info: Peak virtual memory: 5560 megabytes + Info: Processing ended: Sat Dec 08 18:51:10 2018 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:07 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in F:/Code/FPGA/reserve/dpwm_shake/output_files/dpwm_shake.fit.smsg. + + diff --git a/dpwm_shake/output_files/dpwm_shake.fit.smsg b/dpwm_shake/output_files/dpwm_shake.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/dpwm_shake/output_files/dpwm_shake.fit.summary b/dpwm_shake/output_files/dpwm_shake.fit.summary new file mode 100644 index 0000000..40a7ec8 --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Sat Dec 08 18:51:09 2018 +Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Revision Name : dpwm_shake +Top-level Entity Name : dpwm_top +Family : Cyclone IV E +Device : EP4CE10F17C8 +Timing Models : Final +Total logic elements : 62 / 10,320 ( < 1 % ) + Total combinational functions : 62 / 10,320 ( < 1 % ) + Dedicated logic registers : 41 / 10,320 ( < 1 % ) +Total registers : 41 +Total pins : 17 / 180 ( 9 % ) +Total virtual pins : 0 +Total memory bits : 0 / 423,936 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 46 ( 0 % ) +Total PLLs : 1 / 2 ( 50 % ) diff --git a/dpwm_shake/output_files/dpwm_shake.flow.rpt b/dpwm_shake/output_files/dpwm_shake.flow.rpt new file mode 100644 index 0000000..d483d19 --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.flow.rpt @@ -0,0 +1,140 @@ +Flow report for dpwm_shake +Sat Dec 08 18:51:18 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Sat Dec 08 18:51:18 2018 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; dpwm_shake ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Total logic elements ; 62 / 10,320 ( < 1 % ) ; +; Total combinational functions ; 62 / 10,320 ( < 1 % ) ; +; Dedicated logic registers ; 41 / 10,320 ( < 1 % ) ; +; Total registers ; 41 ; +; Total pins ; 17 / 180 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; Total PLLs ; 1 / 2 ( 50 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/08/2018 18:50:49 ; +; Main task ; Compilation ; +; Revision Name ; dpwm_shake ; ++-------------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++--------------------------------------+----------------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++--------------------------------------+----------------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 93383153531551.154426624818644 ; -- ; -- ; -- ; +; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; dpwm_top_tb ; +; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; dpwm_top_tb ; -- ; -- ; eda_simulation ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; +; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ; +; EDA_TEST_BENCH_FILE ; simulation/dpwm_top_tb.v ; -- ; -- ; dpwm_top_tb ; +; EDA_TEST_BENCH_MODULE_NAME ; dpwm_top_tb ; -- ; -- ; dpwm_top_tb ; +; EDA_TEST_BENCH_NAME ; dpwm_top_tb ; -- ; -- ; eda_simulation ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; ip/pwm_pll_bb.v ; -- ; -- ; -- ; +; MISC_FILE ; ip/pwm_pll.ppf ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; dpwm_top ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; dpwm_top ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; dpwm_top ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; TOP_LEVEL_ENTITY ; dpwm_top ; dpwm_shake ; -- ; -- ; ++--------------------------------------+----------------------------------------+---------------+-------------+----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:14 ; 1.0 ; 4792 MB ; 00:00:29 ; +; Fitter ; 00:00:05 ; 1.0 ; 5560 MB ; 00:00:07 ; +; Assembler ; 00:00:01 ; 1.0 ; 4695 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:02 ; 1.0 ; 4776 MB ; 00:00:02 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4664 MB ; 00:00:01 ; +; Total ; 00:00:23 ; -- ; -- ; 00:00:40 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Timing Analyzer ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; ++----------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off dpwm_shake -c dpwm_shake +quartus_fit --read_settings_files=off --write_settings_files=off dpwm_shake -c dpwm_shake +quartus_asm --read_settings_files=off --write_settings_files=off dpwm_shake -c dpwm_shake +quartus_sta dpwm_shake -c dpwm_shake +quartus_eda --read_settings_files=off --write_settings_files=off dpwm_shake -c dpwm_shake + + + diff --git a/dpwm_shake/output_files/dpwm_shake.jdi b/dpwm_shake/output_files/dpwm_shake.jdi new file mode 100644 index 0000000..c19ac11 --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/dpwm_shake/output_files/dpwm_shake.map.rpt b/dpwm_shake/output_files/dpwm_shake.map.rpt new file mode 100644 index 0000000..07b6cd9 --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.map.rpt @@ -0,0 +1,846 @@ +Analysis & Synthesis report for dpwm_shake +Sat Dec 08 18:51:02 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis IP Cores Summary + 9. User-Specified and Inferred Latches + 10. Registers Removed During Synthesis + 11. General Register Statistics + 12. Multiplexer Restructuring Statistics (Restructuring Performed) + 13. Parameter Settings for User Entity Instance: pwm_pll:pwm_pll|altpll:altpll_component + 14. Parameter Settings for User Entity Instance: dpwm_shake:dpwm_shake + 15. altpll Parameter Settings by Entity Instance + 16. Port Connectivity Checks: "dpwm_shake:dpwm_shake" + 17. Post-Synthesis Netlist Statistics for Top Partition + 18. Elapsed Time Per Partition + 19. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sat Dec 08 18:51:02 2018 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; dpwm_shake ; +; Top-level Entity Name ; dpwm_top ; +; Family ; Cyclone IV E ; +; Total logic elements ; 62 ; +; Total combinational functions ; 61 ; +; Dedicated logic registers ; 41 ; +; Total registers ; 41 ; +; Total pins ; 17 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 1 ; ++------------------------------------+-------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP4CE10F17C8 ; ; +; Top-level entity name ; dpwm_top ; dpwm_shake ; +; Family name ; Cyclone IV E ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.0% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+ +; rtl/dpwm_shake.v ; yes ; User Verilog HDL File ; F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v ; ; +; ip/pwm_pll.v ; yes ; User Wizard-Generated File ; F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v ; ; +; rtl/dpwm_top.v ; yes ; User Verilog HDL File ; F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v ; ; +; altpll.tdf ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf ; ; +; aglobal181.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/aglobal181.inc ; ; +; stratix_pll.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/stratix_pll.inc ; ; +; stratixii_pll.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/stratixii_pll.inc ; ; +; cycloneii_pll.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; +; db/pwm_pll_altpll.v ; yes ; Auto-Generated Megafunction ; F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v ; ; ++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------------------------------------------------------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------------------------------------------------------------------------+ +; Estimated Total logic elements ; 62 ; +; ; ; +; Total combinational functions ; 61 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 30 ; +; -- 3 input functions ; 10 ; +; -- <=2 input functions ; 21 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 42 ; +; -- arithmetic mode ; 19 ; +; ; ; +; Total registers ; 41 ; +; -- Dedicated logic registers ; 41 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 17 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Total PLLs ; 1 ; +; -- PLLs ; 1 ; +; ; ; +; Maximum fan-out node ; pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated|wire_pll1_clk[0] ; +; Maximum fan-out ; 57 ; +; Total fan-out ; 328 ; +; Average fan-out ; 2.39 ; ++---------------------------------------------+----------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------+----------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------+----------------+--------------+ +; |dpwm_top ; 61 (1) ; 41 (0) ; 0 ; 0 ; 0 ; 0 ; 17 ; 0 ; |dpwm_top ; dpwm_top ; work ; +; |dpwm_shake:dpwm_shake| ; 60 (60) ; 40 (40) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dpwm_top|dpwm_shake:dpwm_shake ; dpwm_shake ; work ; +; |pwm_pll:pwm_pll| ; 0 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dpwm_top|pwm_pll:pwm_pll ; pwm_pll ; work ; +; |altpll:altpll_component| ; 0 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dpwm_top|pwm_pll:pwm_pll|altpll:altpll_component ; altpll ; work ; +; |pwm_pll_altpll:auto_generated| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |dpwm_top|pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated ; pwm_pll_altpll ; work ; ++------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------+----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+---------------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+---------------------------+-----------------+ +; Altera ; ALTPLL ; 18.1 ; N/A ; N/A ; |dpwm_top|pwm_pll:pwm_pll ; ip/pwm_pll.v ; ++--------+--------------+---------+--------------+--------------+---------------------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------+ +; User-Specified and Inferred Latches ; ++----------------------------------------------------+-------------------------------+------------------------+ +; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ; ++----------------------------------------------------+-------------------------------+------------------------+ +; dpwm_shake:dpwm_shake|pwm_out ; dpwm_shake:dpwm_shake|pwm_out ; yes ; +; Number of user-specified and inferred latches = 1 ; ; ; ++----------------------------------------------------+-------------------------------+------------------------+ +Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations. + + ++--------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------+----------------------------------------+ +; dpwm_shake:dpwm_shake|shakenum[3] ; Stuck at GND due to stuck port data_in ; +; dpwm_shake:dpwm_shake|cat_duty[11] ; Stuck at GND due to stuck port data_in ; +; Total Number of Removed Registers = 2 ; ; ++---------------------------------------+----------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 41 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 11 ; +; Number of registers using Asynchronous Clear ; 14 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ +; 1:1 ; 10 bits ; 0 LEs ; 0 LEs ; 0 LEs ; No ; |dpwm_top|dpwm_shake:dpwm_shake|Add2 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ + + ++--------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: pwm_pll:pwm_pll|altpll:altpll_component ; ++-------------------------------+---------------------------+--------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+---------------------------+--------------------------+ +; OPERATION_MODE ; NORMAL ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; LPM_HINT ; CBX_MODULE_PREFIX=pwm_pll ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; ON ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 1 ; Untyped ; +; CLK1_MULTIPLY_BY ; 1 ; Untyped ; +; CLK0_MULTIPLY_BY ; 49 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 1 ; Untyped ; +; CLK1_DIVIDE_BY ; 1 ; Untyped ; +; CLK0_DIVIDE_BY ; 10 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Untyped ; +; CLK1_DUTY_CYCLE ; 50 ; Untyped ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK2 ; PORT_UNUSED ; Untyped ; +; PORT_CLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_USED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_USED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; pwm_pll_altpll ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+---------------------------+--------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: dpwm_shake:dpwm_shake ; ++----------------+-------------+-------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------------+-------------------------------------+ +; MAX_CNT ; 11111111111 ; Unsigned Binary ; ++----------------+-------------+-------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------+ +; altpll Parameter Settings by Entity Instance ; ++-------------------------------+-----------------------------------------+ +; Name ; Value ; ++-------------------------------+-----------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; pwm_pll:pwm_pll|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 20000 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; ++-------------------------------+-----------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "dpwm_shake:dpwm_shake" ; ++-----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; dead_zone ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (8 bits) it drives. The 24 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ; +; dead_zone[6..0] ; Input ; Info ; Stuck at GND ; +; dead_zone[7] ; Input ; Info ; Stuck at VCC ; ++-----------------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 17 ; +; cycloneiii_ff ; 41 ; +; CLR ; 14 ; +; SLD ; 11 ; +; plain ; 16 ; +; cycloneiii_lcell_comb ; 62 ; +; arith ; 19 ; +; 2 data inputs ; 17 ; +; 3 data inputs ; 2 ; +; normal ; 43 ; +; 1 data inputs ; 4 ; +; 2 data inputs ; 1 ; +; 3 data inputs ; 8 ; +; 4 data inputs ; 30 ; +; cycloneiii_pll ; 1 ; +; ; ; +; Max LUT depth ; 5.00 ; +; Average LUT depth ; 2.67 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Sat Dec 08 18:50:48 2018 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dpwm_shake -c dpwm_shake +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file rtl/dpwm_shake.v + Info (12023): Found entity 1: dpwm_shake File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file ip/pwm_pll.v + Info (12023): Found entity 1: pwm_pll File: F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file rtl/dpwm_top.v + Info (12023): Found entity 1: dpwm_top File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file simulation/dpwm_top_tb.v + Info (12023): Found entity 1: dpwm_top_tb File: F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v Line: 5 +Info (12127): Elaborating entity "dpwm_top" for the top level hierarchy +Info (12128): Elaborating entity "pwm_pll" for hierarchy "pwm_pll:pwm_pll" File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v Line: 31 +Info (12128): Elaborating entity "altpll" for hierarchy "pwm_pll:pwm_pll|altpll:altpll_component" File: F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v Line: 103 +Info (12130): Elaborated megafunction instantiation "pwm_pll:pwm_pll|altpll:altpll_component" File: F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v Line: 103 +Info (12133): Instantiated megafunction "pwm_pll:pwm_pll|altpll:altpll_component" with the following parameter: File: F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v Line: 103 + Info (12134): Parameter "bandwidth_type" = "AUTO" + Info (12134): Parameter "clk0_divide_by" = "10" + Info (12134): Parameter "clk0_duty_cycle" = "50" + Info (12134): Parameter "clk0_multiply_by" = "49" + Info (12134): Parameter "clk0_phase_shift" = "0" + Info (12134): Parameter "compensate_clock" = "CLK0" + Info (12134): Parameter "inclk0_input_frequency" = "20000" + Info (12134): Parameter "intended_device_family" = "Cyclone IV E" + Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pwm_pll" + Info (12134): Parameter "lpm_type" = "altpll" + Info (12134): Parameter "operation_mode" = "NORMAL" + Info (12134): Parameter "pll_type" = "AUTO" + Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" + Info (12134): Parameter "port_areset" = "PORT_USED" + Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" + Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" + Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" + Info (12134): Parameter "port_fbin" = "PORT_UNUSED" + Info (12134): Parameter "port_inclk0" = "PORT_USED" + Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_locked" = "PORT_USED" + Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" + Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" + Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" + Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" + Info (12134): Parameter "port_pllena" = "PORT_UNUSED" + Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" + Info (12134): Parameter "port_scandata" = "PORT_UNUSED" + Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" + Info (12134): Parameter "port_scandone" = "PORT_UNUSED" + Info (12134): Parameter "port_scanread" = "PORT_UNUSED" + Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" + Info (12134): Parameter "port_clk0" = "PORT_USED" + Info (12134): Parameter "port_clk1" = "PORT_UNUSED" + Info (12134): Parameter "port_clk2" = "PORT_UNUSED" + Info (12134): Parameter "port_clk3" = "PORT_UNUSED" + Info (12134): Parameter "port_clk4" = "PORT_UNUSED" + Info (12134): Parameter "port_clk5" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" + Info (12134): Parameter "self_reset_on_loss_lock" = "ON" + Info (12134): Parameter "width_clock" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/pwm_pll_altpll.v + Info (12023): Found entity 1: pwm_pll_altpll File: F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v Line: 30 +Info (12128): Elaborating entity "pwm_pll_altpll" for hierarchy "pwm_pll:pwm_pll|altpll:altpll_component|pwm_pll_altpll:auto_generated" File: d:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf Line: 897 +Info (12128): Elaborating entity "dpwm_shake" for hierarchy "dpwm_shake:dpwm_shake" File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v Line: 42 +Warning (10036): Verilog HDL or VHDL warning at dpwm_shake.v(34): object "tmp_q_n" assigned a value but never read File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 34 +Warning (10230): Verilog HDL assignment warning at dpwm_shake.v(78): truncated value with size 12 to match size of target (11) File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 78 +Warning (10230): Verilog HDL assignment warning at dpwm_shake.v(79): truncated value with size 12 to match size of target (11) File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 79 +Warning (10230): Verilog HDL assignment warning at dpwm_shake.v(80): truncated value with size 12 to match size of target (11) File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 80 +Warning (10230): Verilog HDL assignment warning at dpwm_shake.v(81): truncated value with size 12 to match size of target (11) File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 81 +Info (10041): Inferred latch for "pwm_out" at dpwm_shake.v(47) File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 47 +Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13012): Latch dpwm_shake:dpwm_shake|pwm_out has unsafe behavior File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 19 + Warning (13013): Ports D and ENA on the latch are fed by the same signal dpwm_shake:dpwm_shake|cnt[0] File: F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v Line: 68 +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 80 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 15 input pins + Info (21059): Implemented 2 output pins + Info (21061): Implemented 62 logic cells + Info (21065): Implemented 1 PLLs +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 9 warnings + Info: Peak virtual memory: 4792 megabytes + Info: Processing ended: Sat Dec 08 18:51:02 2018 + Info: Elapsed time: 00:00:14 + Info: Total CPU time (on all processors): 00:00:29 + + diff --git a/dpwm_shake/output_files/dpwm_shake.map.summary b/dpwm_shake/output_files/dpwm_shake.map.summary new file mode 100644 index 0000000..d39f82f --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Sat Dec 08 18:51:02 2018 +Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Revision Name : dpwm_shake +Top-level Entity Name : dpwm_top +Family : Cyclone IV E +Total logic elements : 62 + Total combinational functions : 61 + Dedicated logic registers : 41 +Total registers : 41 +Total pins : 17 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 1 diff --git a/dpwm_shake/output_files/dpwm_shake.pin b/dpwm_shake/output_files/dpwm_shake.pin new file mode 100644 index 0000000..ed7ce9c --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.pin @@ -0,0 +1,326 @@ + -- Copyright (C) 2018 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +CHIP "dpwm_shake" ASSIGNED TO AN: EP4CE10F17C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +VCCIO8 : A1 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +VCCIO7 : A16 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 1 : +GND : B2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +GND : B15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +VCCIO8 : C4 : power : : 2.5V : 8 : +GND : C5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +VCCIO8 : C7 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +VCCIO7 : C10 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 : +GND : C12 : gnd : : : : +VCCIO7 : C13 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 : +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +GND : D7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 7 : +GND : D10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 : +VCCD_PLL2 : D13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 6 : +clk : E1 : input : 2.5 V : : 1 : N +GND : E2 : gnd : : : : +VCCIO1 : E3 : power : : 2.5V : 1 : +GND : E4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 : +GNDA2 : E12 : gnd : : : : +GND : E13 : gnd : : : : +VCCIO6 : E14 : power : : 2.5V : 6 : +GND+ : E15 : : : : 6 : +GND+ : E16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 : +nSTATUS : F4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 7 : +VCCA2 : F12 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 : +control[6] : G2 : input : 2.5 V : : 1 : N +VCCIO1 : G3 : power : : 2.5V : 1 : +GND : G4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 : +VCCINT : G6 : power : : 1.2V : : +VCCINT : G7 : power : : 1.2V : : +VCCINT : G8 : power : : 1.2V : : +VCCINT : G9 : power : : 1.2V : : +VCCINT : G10 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 6 : +MSEL2 : G12 : : : : 6 : +GND : G13 : gnd : : : : +VCCIO6 : G14 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 6 : +~ALTERA_DCLK~ : H1 : output : 2.5 V : : 1 : N +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V : : 1 : N +TCK : H3 : input : : : 1 : +TDI : H4 : input : : : 1 : +nCONFIG : H5 : : : : 1 : +VCCINT : H6 : power : : 1.2V : : +GND : H7 : gnd : : : : +GND : H8 : gnd : : : : +GND : H9 : gnd : : : : +GND : H10 : gnd : : : : +VCCINT : H11 : power : : 1.2V : : +MSEL1 : H12 : : : : 6 : +MSEL0 : H13 : : : : 6 : +CONF_DONE : H14 : : : : 6 : +GND : H15 : gnd : : : : +GND : H16 : gnd : : : : +control[11] : J1 : input : 2.5 V : : 2 : N +control[12] : J2 : input : 2.5 V : : 2 : N +nCE : J3 : : : : 1 : +TDO : J4 : output : : : 1 : +TMS : J5 : input : : : 1 : +control[8] : J6 : input : 2.5 V : : 2 : N +GND : J7 : gnd : : : : +GND : J8 : gnd : : : : +GND : J9 : gnd : : : : +GND : J10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 5 : +pwm_out : K1 : output : 2.5 V : : 2 : N +control[1] : K2 : input : 2.5 V : : 2 : N +VCCIO2 : K3 : power : : 2.5V : 2 : +GND : K4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 : +control[2] : K6 : input : 2.5 V : : 2 : N +VCCINT : K7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 5 : +GND : K13 : gnd : : : : +VCCIO5 : K14 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 5 : +control[5] : L1 : input : 2.5 V : : 2 : N +pwm_out_n : L2 : output : 2.5 V : : 2 : N +control[7] : L3 : input : 2.5 V : : 2 : N +control[10] : L4 : input : 2.5 V : : 2 : N +VCCA1 : L5 : power : : 2.5V : : +control[0] : L6 : input : 2.5 V : : 2 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L12 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 5 : +control[3] : M1 : input : 2.5 V : : 2 : N +rst_n : M2 : input : 2.5 V : : 2 : N +VCCIO2 : M3 : power : : 2.5V : 2 : +GND : M4 : gnd : : : : +GNDA1 : M5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M12 : : : : 5 : +GND : M13 : gnd : : : : +VCCIO5 : M14 : power : : 2.5V : 5 : +GND+ : M15 : : : : 5 : +GND+ : M16 : : : : 5 : +control[9] : N1 : input : 2.5 V : : 2 : N +control[4] : N2 : input : 2.5 V : : 2 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 3 : +VCCD_PLL1 : N4 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 3 : +GND : N7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 4 : +GND : N10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3 : +VCCIO3 : P4 : power : : 2.5V : 3 : +GND : P5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 3 : +VCCIO3 : P7 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 4 : +VCCIO4 : P10 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 4 : +GND : P12 : gnd : : : : +VCCIO4 : P13 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +GND : R2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : +GND : R15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 5 : +VCCIO3 : T1 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 : +VCCIO4 : T16 : power : : 2.5V : 4 : diff --git a/dpwm_shake/output_files/dpwm_shake.sld b/dpwm_shake/output_files/dpwm_shake.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.sld @@ -0,0 +1 @@ + diff --git a/dpwm_shake/output_files/dpwm_shake.sof b/dpwm_shake/output_files/dpwm_shake.sof new file mode 100644 index 0000000..2b0028f Binary files /dev/null and b/dpwm_shake/output_files/dpwm_shake.sof differ diff --git a/dpwm_shake/output_files/dpwm_shake.sta.rpt b/dpwm_shake/output_files/dpwm_shake.sta.rpt new file mode 100644 index 0000000..4e941c4 --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.sta.rpt @@ -0,0 +1,1235 @@ +Timing Analyzer report for dpwm_shake +Sat Dec 08 18:51:16 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1200mV 85C Model Fmax Summary + 7. Timing Closure Recommendations + 8. Slow 1200mV 85C Model Setup Summary + 9. Slow 1200mV 85C Model Hold Summary + 10. Slow 1200mV 85C Model Recovery Summary + 11. Slow 1200mV 85C Model Removal Summary + 12. Slow 1200mV 85C Model Minimum Pulse Width Summary + 13. Slow 1200mV 85C Model Setup: 'clk_0' + 14. Slow 1200mV 85C Model Hold: 'clk_0' + 15. Slow 1200mV 85C Model Metastability Summary + 16. Slow 1200mV 0C Model Fmax Summary + 17. Slow 1200mV 0C Model Setup Summary + 18. Slow 1200mV 0C Model Hold Summary + 19. Slow 1200mV 0C Model Recovery Summary + 20. Slow 1200mV 0C Model Removal Summary + 21. Slow 1200mV 0C Model Minimum Pulse Width Summary + 22. Slow 1200mV 0C Model Setup: 'clk_0' + 23. Slow 1200mV 0C Model Hold: 'clk_0' + 24. Slow 1200mV 0C Model Metastability Summary + 25. Fast 1200mV 0C Model Setup Summary + 26. Fast 1200mV 0C Model Hold Summary + 27. Fast 1200mV 0C Model Recovery Summary + 28. Fast 1200mV 0C Model Removal Summary + 29. Fast 1200mV 0C Model Minimum Pulse Width Summary + 30. Fast 1200mV 0C Model Setup: 'clk_0' + 31. Fast 1200mV 0C Model Hold: 'clk_0' + 32. Fast 1200mV 0C Model Metastability Summary + 33. Multicorner Timing Analysis Summary + 34. Board Trace Model Assignments + 35. Input Transition Times + 36. Signal Integrity Metrics (Slow 1200mv 0c Model) + 37. Signal Integrity Metrics (Slow 1200mv 85c Model) + 38. Signal Integrity Metrics (Fast 1200mv 0c Model) + 39. Setup Transfers + 40. Hold Transfers + 41. Report TCCS + 42. Report RSKM + 43. Unconstrained Paths Summary + 44. Clock Status Summary + 45. Unconstrained Input Ports + 46. Unconstrained Output Ports + 47. Unconstrained Input Ports + 48. Unconstrained Output Ports + 49. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+---------------------------------------------------------+ +; Quartus Prime Version ; Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; dpwm_shake ; +; Device Family ; Cyclone IV E ; +; Device Name ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+---------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.4% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------+ +; SDC File List ; ++--------------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++--------------------+--------+--------------------------+ +; dpwm_shake.out.sdc ; OK ; Sat Dec 08 18:51:15 2018 ; ++--------------------+--------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------------------------------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------------------------------------+ +; clk_0 ; Base ; 4.500 ; 222.22 MHz ; 0.000 ; 2.250 ; ; ; ; ; ; ; ; ; ; ; { pwm_pll|altpll_component|auto_generated|pll1|clk[0] } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------------------------------------------------------+ + + ++--------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 247.95 MHz ; 247.95 MHz ; clk_0 ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++-------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++-------+-------+---------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------------+ +; clk_0 ; 0.467 ; 0.000 ; ++-------+-------+---------------------+ + + ++------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++-------+-------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+--------------------+ +; clk_0 ; 0.452 ; 0.000 ; ++-------+-------+--------------------+ + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++-------+-------+-----------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+-----------------------------------+ +; clk_0 ; 1.945 ; 0.000 ; ++-------+-------+-----------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'clk_0' ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.467 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.973 ; +; 0.485 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.955 ; +; 0.489 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.951 ; +; 0.503 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.937 ; +; 0.617 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.823 ; +; 0.647 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.793 ; +; 0.738 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.702 ; +; 0.759 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.681 ; +; 0.768 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.672 ; +; 0.777 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.663 ; +; 0.927 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.513 ; +; 0.939 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.501 ; +; 0.941 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.499 ; +; 0.951 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.489 ; +; 1.051 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.389 ; +; 1.054 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.827 ; +; 1.055 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.385 ; +; 1.060 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.380 ; +; 1.069 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.371 ; +; 1.072 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.809 ; +; 1.076 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.805 ; +; 1.090 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.791 ; +; 1.127 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.313 ; +; 1.176 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.264 ; +; 1.204 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.677 ; +; 1.222 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.659 ; +; 1.231 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.209 ; +; 1.234 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.647 ; +; 1.236 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.645 ; +; 1.243 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.197 ; +; 1.273 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.167 ; +; 1.325 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.556 ; +; 1.346 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.535 ; +; 1.350 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.531 ; +; 1.352 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.088 ; +; 1.355 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.526 ; +; 1.360 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.579 ; 2.582 ; +; 1.360 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.579 ; 2.582 ; +; 1.364 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.517 ; +; 1.389 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.051 ; +; 1.403 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.037 ; +; 1.403 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.037 ; +; 1.419 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.021 ; +; 1.433 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.007 ; +; 1.433 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 3.007 ; +; 1.441 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.541 ; 2.539 ; +; 1.471 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.410 ; +; 1.500 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 4.500 ; -0.578 ; 2.443 ; +; 1.514 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.367 ; +; 1.526 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.355 ; +; 1.528 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.353 ; +; 1.535 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[2] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.905 ; +; 1.565 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[3] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.875 ; +; 1.567 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.872 ; +; 1.568 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.871 ; +; 1.574 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 4.500 ; 0.396 ; 3.343 ; +; 1.612 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 4.500 ; -0.578 ; 2.331 ; +; 1.617 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.541 ; 2.363 ; +; 1.636 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.804 ; +; 1.642 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.239 ; +; 1.647 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.234 ; +; 1.654 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.786 ; +; 1.682 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.579 ; 2.260 ; +; 1.683 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.579 ; 2.259 ; +; 1.725 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.715 ; +; 1.725 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.715 ; +; 1.733 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.541 ; 2.247 ; +; 1.735 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.541 ; 2.245 ; +; 1.747 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.692 ; +; 1.747 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.692 ; +; 1.758 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 4.500 ; -0.578 ; 2.185 ; +; 1.763 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 3.118 ; +; 1.766 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.673 ; +; 1.767 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.672 ; +; 1.792 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 4.500 ; -0.578 ; 2.151 ; +; 1.816 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.541 ; 2.164 ; +; 1.825 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.615 ; +; 1.833 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.541 ; 2.147 ; +; 1.841 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.599 ; +; 1.841 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.599 ; +; 1.862 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.578 ; +; 1.864 ; dpwm_shake:dpwm_shake|cat_duty[7] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.541 ; 2.116 ; +; 1.887 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.552 ; +; 1.888 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.551 ; +; 1.893 ; dpwm_shake:dpwm_shake|cnt[10] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.546 ; +; 1.894 ; dpwm_shake:dpwm_shake|cnt[10] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.545 ; +; 1.897 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.542 ; +; 1.897 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.082 ; 2.542 ; +; 1.904 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 4.500 ; -0.578 ; 2.039 ; +; 1.911 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.541 ; 2.069 ; +; 1.938 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 4.500 ; -0.578 ; 2.005 ; +; 1.958 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.482 ; +; 1.962 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 4.500 ; -0.578 ; 1.981 ; +; 1.988 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.452 ; +; 1.990 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 2.891 ; +; 1.990 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.360 ; 2.891 ; +; 1.992 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 4.500 ; -0.578 ; 1.951 ; +; 2.002 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.438 ; +; 2.017 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.423 ; +; 2.017 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.081 ; 2.423 ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'clk_0' ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.452 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 0.000 ; 0.082 ; 0.746 ; +; 0.452 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 0.000 ; 0.082 ; 0.746 ; +; 0.643 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.578 ; 1.433 ; +; 0.688 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.000 ; +; 0.690 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.002 ; +; 0.727 ; dpwm_shake:dpwm_shake|cnt[10] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.020 ; +; 0.746 ; dpwm_shake:dpwm_shake|cat_duty[7] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.058 ; +; 0.747 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.059 ; +; 0.749 ; dpwm_shake:dpwm_shake|cat_duty[8] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.061 ; +; 0.750 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.101 ; 1.063 ; +; 0.765 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 0.000 ; 0.082 ; 1.059 ; +; 0.770 ; dpwm_shake:dpwm_shake|cnt[9] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.063 ; +; 0.770 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[2] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.063 ; +; 0.771 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[1] ; clk_0 ; clk_0 ; 0.000 ; 0.101 ; 1.084 ; +; 0.773 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[3] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.066 ; +; 0.779 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.072 ; +; 0.782 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.075 ; +; 0.783 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.578 ; 1.573 ; +; 0.786 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.578 ; 1.576 ; +; 0.795 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.088 ; +; 0.795 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.088 ; +; 0.858 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.541 ; 1.611 ; +; 0.861 ; dpwm_shake:dpwm_shake|cat_duty[6] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.541 ; 1.614 ; +; 0.895 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.541 ; 1.648 ; +; 0.903 ; dpwm_shake:dpwm_shake|cat_duty[6] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.541 ; 1.656 ; +; 0.905 ; dpwm_shake:dpwm_shake|cat_duty[10] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.198 ; +; 0.907 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.200 ; +; 0.917 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.578 ; 1.707 ; +; 0.923 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.578 ; 1.713 ; +; 0.935 ; dpwm_shake:dpwm_shake|cat_duty[6] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.228 ; +; 0.942 ; dpwm_shake:dpwm_shake|cat_duty[9] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.235 ; +; 0.945 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.238 ; +; 0.956 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.541 ; 1.709 ; +; 0.959 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.541 ; 1.712 ; +; 0.974 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 0.000 ; 0.082 ; 1.268 ; +; 0.984 ; dpwm_shake:dpwm_shake|shake_ctr[0] ; dpwm_shake:dpwm_shake|shakenum[0] ; clk_0 ; clk_0 ; 0.000 ; -0.395 ; 0.801 ; +; 0.986 ; dpwm_shake:dpwm_shake|shake_ctr[0] ; dpwm_shake:dpwm_shake|shakenum[1] ; clk_0 ; clk_0 ; 0.000 ; -0.395 ; 0.803 ; +; 1.039 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.578 ; 1.829 ; +; 1.096 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.541 ; 1.849 ; +; 1.099 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.541 ; 1.852 ; +; 1.100 ; dpwm_shake:dpwm_shake|cat_duty[7] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.412 ; +; 1.108 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.420 ; +; 1.113 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[1] ; clk_0 ; clk_0 ; 0.000 ; 0.578 ; 1.903 ; +; 1.125 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[3] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.418 ; +; 1.131 ; dpwm_shake:dpwm_shake|cnt[9] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.424 ; +; 1.134 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.427 ; +; 1.138 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.541 ; 1.891 ; +; 1.143 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.436 ; +; 1.143 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.436 ; +; 1.149 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.442 ; +; 1.149 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.442 ; +; 1.149 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.442 ; +; 1.152 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.445 ; +; 1.175 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.541 ; 1.928 ; +; 1.182 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 1.936 ; +; 1.182 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 1.936 ; +; 1.182 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 1.936 ; +; 1.182 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 1.936 ; +; 1.182 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 1.936 ; +; 1.203 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 1.957 ; +; 1.213 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.525 ; +; 1.220 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 1.974 ; +; 1.222 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.534 ; +; 1.223 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.535 ; +; 1.231 ; dpwm_shake:dpwm_shake|shake_ctr[1] ; dpwm_shake:dpwm_shake|shakenum[2] ; clk_0 ; clk_0 ; 0.000 ; -0.395 ; 1.048 ; +; 1.232 ; dpwm_shake:dpwm_shake|shake_ctr[1] ; dpwm_shake:dpwm_shake|shakenum[1] ; clk_0 ; clk_0 ; 0.000 ; -0.395 ; 1.049 ; +; 1.248 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.560 ; +; 1.256 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.549 ; +; 1.257 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.569 ; +; 1.265 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.558 ; +; 1.274 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.567 ; +; 1.279 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.572 ; +; 1.280 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.573 ; +; 1.280 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.573 ; +; 1.283 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.576 ; +; 1.289 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.582 ; +; 1.289 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.582 ; +; 1.292 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.585 ; +; 1.299 ; dpwm_shake:dpwm_shake|shake_ctr[1] ; dpwm_shake:dpwm_shake|shakenum[0] ; clk_0 ; clk_0 ; 0.000 ; -0.395 ; 1.116 ; +; 1.314 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 2.068 ; +; 1.314 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 2.068 ; +; 1.314 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 2.068 ; +; 1.314 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 2.068 ; +; 1.314 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 2.068 ; +; 1.336 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 0.000 ; 0.082 ; 1.630 ; +; 1.347 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 0.000 ; 0.082 ; 1.641 ; +; 1.353 ; dpwm_shake:dpwm_shake|cat_duty[9] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.646 ; +; 1.354 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.100 ; 1.666 ; +; 1.390 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 2.144 ; +; 1.391 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 2.145 ; +; 1.396 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.689 ; +; 1.405 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.698 ; +; 1.416 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 2.170 ; +; 1.420 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.713 ; +; 1.423 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.716 ; +; 1.423 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.716 ; +; 1.429 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.722 ; +; 1.458 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.751 ; +; 1.461 ; dpwm_shake:dpwm_shake|cat_duty[6] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 0.000 ; 0.081 ; 1.754 ; +; 1.483 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.542 ; 2.237 ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 271.15 MHz ; 271.15 MHz ; clk_0 ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++-------+-------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+--------------------+ +; clk_0 ; 0.812 ; 0.000 ; ++-------+-------+--------------------+ + + ++-----------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++-------+-------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+-------------------+ +; clk_0 ; 0.401 ; 0.000 ; ++-------+-------+-------------------+ + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++-------+-------+----------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+----------------------------------+ +; clk_0 ; 1.920 ; 0.000 ; ++-------+-------+----------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'clk_0' ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.812 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.637 ; +; 0.824 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.625 ; +; 0.851 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.598 ; +; 0.863 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.586 ; +; 0.949 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.500 ; +; 0.988 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.461 ; +; 1.064 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.385 ; +; 1.103 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.346 ; +; 1.103 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.346 ; +; 1.115 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.334 ; +; 1.190 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.259 ; +; 1.202 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.247 ; +; 1.210 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.239 ; +; 1.240 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.209 ; +; 1.327 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.122 ; +; 1.350 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.511 ; +; 1.355 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.094 ; +; 1.355 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.094 ; +; 1.362 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.499 ; +; 1.367 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.082 ; +; 1.375 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.074 ; +; 1.389 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.472 ; +; 1.401 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.460 ; +; 1.442 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 3.007 ; +; 1.462 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.987 ; +; 1.476 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.385 ; +; 1.487 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.374 ; +; 1.488 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.373 ; +; 1.492 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.957 ; +; 1.501 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.948 ; +; 1.526 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.540 ; 2.456 ; +; 1.526 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.335 ; +; 1.527 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.540 ; 2.455 ; +; 1.588 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.861 ; +; 1.602 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.259 ; +; 1.607 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.842 ; +; 1.613 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.248 ; +; 1.627 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.822 ; +; 1.641 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.220 ; +; 1.641 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.220 ; +; 1.653 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.208 ; +; 1.666 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.783 ; +; 1.669 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.780 ; +; 1.694 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.755 ; +; 1.694 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.755 ; +; 1.705 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.744 ; +; 1.708 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.741 ; +; 1.714 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[2] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.735 ; +; 1.728 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.133 ; +; 1.728 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.133 ; +; 1.740 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.121 ; +; 1.753 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[3] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.696 ; +; 1.757 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.502 ; 2.263 ; +; 1.778 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 3.083 ; +; 1.782 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 4.500 ; -0.540 ; 2.200 ; +; 1.784 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 4.500 ; 0.375 ; 3.113 ; +; 1.821 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.540 ; 2.161 ; +; 1.821 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.540 ; 2.161 ; +; 1.865 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 2.996 ; +; 1.893 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 2.968 ; +; 1.895 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.554 ; +; 1.895 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.554 ; +; 1.896 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.553 ; +; 1.897 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.552 ; +; 1.903 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 4.500 ; -0.540 ; 2.079 ; +; 1.922 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.502 ; 2.098 ; +; 1.923 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.526 ; +; 1.935 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.514 ; +; 1.957 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.492 ; +; 1.960 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.489 ; +; 1.980 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 2.881 ; +; 2.006 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.443 ; +; 2.006 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.443 ; +; 2.009 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.502 ; 2.011 ; +; 2.012 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.502 ; 2.008 ; +; 2.014 ; dpwm_shake:dpwm_shake|cnt[10] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.435 ; +; 2.014 ; dpwm_shake:dpwm_shake|cnt[10] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.435 ; +; 2.029 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 4.500 ; -0.540 ; 1.953 ; +; 2.034 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 4.500 ; -0.540 ; 1.948 ; +; 2.041 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.408 ; +; 2.042 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.407 ; +; 2.044 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.405 ; +; 2.047 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.402 ; +; 2.060 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.389 ; +; 2.075 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.502 ; 1.945 ; +; 2.086 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.502 ; 1.934 ; +; 2.121 ; dpwm_shake:dpwm_shake|cat_duty[7] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.502 ; 1.899 ; +; 2.142 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.307 ; +; 2.142 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.307 ; +; 2.155 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.294 ; +; 2.155 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 4.500 ; -0.540 ; 1.827 ; +; 2.160 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 4.500 ; -0.540 ; 1.822 ; +; 2.175 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.274 ; +; 2.177 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.502 ; 1.843 ; +; 2.182 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.267 ; +; 2.201 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 4.500 ; -0.540 ; 1.781 ; +; 2.204 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 2.657 ; +; 2.207 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.339 ; 2.654 ; +; 2.209 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.240 ; +; 2.212 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.073 ; 2.237 ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'clk_0' ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.401 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 0.669 ; +; 0.401 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 0.669 ; +; 0.575 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.540 ; 1.310 ; +; 0.637 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 0.922 ; +; 0.639 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 0.924 ; +; 0.653 ; dpwm_shake:dpwm_shake|cnt[10] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 0.921 ; +; 0.693 ; dpwm_shake:dpwm_shake|cat_duty[7] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 0.978 ; +; 0.693 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.540 ; 1.428 ; +; 0.695 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 0.980 ; +; 0.696 ; dpwm_shake:dpwm_shake|cat_duty[8] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 0.981 ; +; 0.696 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.092 ; 0.983 ; +; 0.699 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.540 ; 1.434 ; +; 0.712 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[2] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 0.980 ; +; 0.712 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 0.980 ; +; 0.714 ; dpwm_shake:dpwm_shake|cnt[9] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 0.982 ; +; 0.720 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[3] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 0.988 ; +; 0.720 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[1] ; clk_0 ; clk_0 ; 0.000 ; 0.092 ; 1.007 ; +; 0.723 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 0.991 ; +; 0.725 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 0.993 ; +; 0.738 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.006 ; +; 0.738 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.006 ; +; 0.750 ; dpwm_shake:dpwm_shake|cat_duty[6] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.447 ; +; 0.805 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.502 ; +; 0.815 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.540 ; 1.550 ; +; 0.816 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.540 ; 1.551 ; +; 0.820 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.517 ; +; 0.835 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.532 ; +; 0.835 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.532 ; +; 0.839 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.107 ; +; 0.848 ; dpwm_shake:dpwm_shake|cat_duty[10] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.116 ; +; 0.851 ; dpwm_shake:dpwm_shake|cat_duty[6] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.548 ; +; 0.861 ; dpwm_shake:dpwm_shake|cat_duty[6] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.129 ; +; 0.864 ; dpwm_shake:dpwm_shake|cat_duty[9] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.132 ; +; 0.868 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.136 ; +; 0.897 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.165 ; +; 0.907 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.540 ; 1.642 ; +; 0.924 ; dpwm_shake:dpwm_shake|shake_ctr[0] ; dpwm_shake:dpwm_shake|shakenum[0] ; clk_0 ; clk_0 ; 0.000 ; -0.375 ; 0.744 ; +; 0.925 ; dpwm_shake:dpwm_shake|shake_ctr[0] ; dpwm_shake:dpwm_shake|shakenum[1] ; clk_0 ; clk_0 ; 0.000 ; -0.375 ; 0.745 ; +; 0.957 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.654 ; +; 0.957 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.654 ; +; 0.961 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[1] ; clk_0 ; clk_0 ; 0.000 ; 0.540 ; 1.696 ; +; 1.013 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 1.298 ; +; 1.017 ; dpwm_shake:dpwm_shake|cat_duty[7] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 1.302 ; +; 1.033 ; dpwm_shake:dpwm_shake|cnt[9] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.301 ; +; 1.034 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[3] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.302 ; +; 1.039 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.307 ; +; 1.044 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.312 ; +; 1.049 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.746 ; +; 1.054 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.322 ; +; 1.057 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.325 ; +; 1.059 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.327 ; +; 1.061 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.758 ; +; 1.062 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.330 ; +; 1.062 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.330 ; +; 1.064 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.761 ; +; 1.077 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.774 ; +; 1.094 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 1.379 ; +; 1.111 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.808 ; +; 1.111 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.808 ; +; 1.111 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.808 ; +; 1.111 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.808 ; +; 1.111 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.808 ; +; 1.120 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 1.405 ; +; 1.122 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 1.407 ; +; 1.130 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.398 ; +; 1.135 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 1.420 ; +; 1.142 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.410 ; +; 1.151 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 1.436 ; +; 1.152 ; dpwm_shake:dpwm_shake|shake_ctr[1] ; dpwm_shake:dpwm_shake|shakenum[2] ; clk_0 ; clk_0 ; 0.000 ; -0.375 ; 0.972 ; +; 1.153 ; dpwm_shake:dpwm_shake|shake_ctr[1] ; dpwm_shake:dpwm_shake|shakenum[1] ; clk_0 ; clk_0 ; 0.000 ; -0.375 ; 0.973 ; +; 1.156 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.424 ; +; 1.160 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.428 ; +; 1.161 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.429 ; +; 1.164 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.432 ; +; 1.176 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.444 ; +; 1.181 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.449 ; +; 1.184 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.452 ; +; 1.184 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.452 ; +; 1.194 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.462 ; +; 1.202 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.470 ; +; 1.213 ; dpwm_shake:dpwm_shake|shake_ctr[1] ; dpwm_shake:dpwm_shake|shakenum[0] ; clk_0 ; clk_0 ; 0.000 ; -0.375 ; 1.033 ; +; 1.218 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.090 ; 1.503 ; +; 1.246 ; dpwm_shake:dpwm_shake|cat_duty[9] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.514 ; +; 1.248 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.945 ; +; 1.248 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.945 ; +; 1.248 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.945 ; +; 1.248 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.945 ; +; 1.248 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.945 ; +; 1.252 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.520 ; +; 1.275 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.972 ; +; 1.278 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.546 ; +; 1.282 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.550 ; +; 1.288 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.556 ; +; 1.290 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.987 ; +; 1.298 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.566 ; +; 1.300 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 1.997 ; +; 1.301 ; dpwm_shake:dpwm_shake|cat_duty[6] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.569 ; +; 1.305 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 2.002 ; +; 1.306 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.073 ; 1.574 ; +; 1.321 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.502 ; 2.018 ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++-------+-------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+--------------------+ +; clk_0 ; 2.748 ; 0.000 ; ++-------+-------+--------------------+ + + ++-----------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++-------+-------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+-------------------+ +; clk_0 ; 0.186 ; 0.000 ; ++-------+-------+-------------------+ + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++-------+-------+----------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+----------------------------------+ +; clk_0 ; 2.025 ; 0.000 ; ++-------+-------+----------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'clk_0' ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; 2.748 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.723 ; +; 2.753 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.718 ; +; 2.812 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.659 ; +; 2.817 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.654 ; +; 2.836 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.635 ; +; 2.884 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.587 ; +; 2.889 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.582 ; +; 2.896 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.575 ; +; 2.939 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.532 ; +; 2.943 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.528 ; +; 2.972 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.499 ; +; 2.996 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.655 ; +; 3.001 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.650 ; +; 3.016 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.455 ; +; 3.020 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.451 ; +; 3.021 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.450 ; +; 3.025 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.446 ; +; 3.060 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.591 ; +; 3.065 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.586 ; +; 3.071 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.399 ; +; 3.075 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.396 ; +; 3.080 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.390 ; +; 3.084 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.567 ; +; 3.100 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.371 ; +; 3.108 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.363 ; +; 3.128 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.523 ; +; 3.132 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.519 ; +; 3.133 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.518 ; +; 3.137 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.514 ; +; 3.144 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.507 ; +; 3.146 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.239 ; 1.122 ; +; 3.146 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.239 ; 1.122 ; +; 3.147 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.324 ; +; 3.148 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.322 ; +; 3.166 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.305 ; +; 3.168 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.303 ; +; 3.177 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.225 ; 1.105 ; +; 3.187 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.464 ; +; 3.191 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.460 ; +; 3.207 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.263 ; +; 3.211 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.260 ; +; 3.212 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.439 ; +; 3.216 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.254 ; +; 3.220 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.431 ; +; 3.221 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.250 ; +; 3.222 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.249 ; +; 3.234 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 4.500 ; -0.238 ; 1.035 ; +; 3.241 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.225 ; 1.041 ; +; 3.241 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.228 ; +; 3.242 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.227 ; +; 3.256 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.215 ; +; 3.259 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.392 ; +; 3.261 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.210 ; +; 3.264 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.387 ; +; 3.269 ; dpwm_shake:dpwm_shake|shakenum[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.382 ; +; 3.270 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 4.500 ; -0.238 ; 0.999 ; +; 3.275 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.195 ; +; 3.284 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[3] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.186 ; +; 3.290 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.239 ; 0.978 ; +; 3.291 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.239 ; 0.977 ; +; 3.302 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.169 ; +; 3.304 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.167 ; +; 3.308 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.161 ; +; 3.309 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.160 ; +; 3.313 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 4.500 ; -0.225 ; 0.969 ; +; 3.315 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.225 ; 0.967 ; +; 3.322 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.147 ; +; 3.322 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.147 ; +; 3.323 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.328 ; +; 3.332 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 4.500 ; 0.156 ; 1.331 ; +; 3.338 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 4.500 ; -0.238 ; 0.931 ; +; 3.343 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[2] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.127 ; +; 3.344 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.127 ; +; 3.345 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.125 ; +; 3.348 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.303 ; +; 3.355 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.225 ; 0.927 ; +; 3.359 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.110 ; +; 3.359 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.110 ; +; 3.370 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 4.500 ; -0.238 ; 0.899 ; +; 3.372 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.097 ; +; 3.373 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.096 ; +; 3.375 ; dpwm_shake:dpwm_shake|cat_duty[7] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.225 ; 0.907 ; +; 3.376 ; dpwm_shake:dpwm_shake|cnt[10] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.093 ; +; 3.377 ; dpwm_shake:dpwm_shake|cnt[10] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 4.500 ; -0.038 ; 1.092 ; +; 3.379 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.225 ; 0.903 ; +; 3.386 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.225 ; 0.896 ; +; 3.395 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.256 ; +; 3.406 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 4.500 ; -0.238 ; 0.863 ; +; 3.408 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.062 ; +; 3.409 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.061 ; +; 3.414 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.237 ; +; 3.416 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; 0.144 ; 1.235 ; +; 3.423 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 4.500 ; -0.238 ; 0.846 ; +; 3.425 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 4.500 ; -0.045 ; 1.037 ; +; 3.425 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.045 ; +; 3.425 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.046 ; +; 3.426 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 4.500 ; -0.036 ; 1.045 ; +; 3.427 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 4.500 ; -0.238 ; 0.842 ; +; 3.429 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 4.500 ; -0.037 ; 1.041 ; +; 3.438 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 4.500 ; -0.238 ; 0.831 ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'clk_0' ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.186 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|shake_count[0] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.307 ; +; 0.264 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.393 ; +; 0.266 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.395 ; +; 0.272 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.238 ; 0.594 ; +; 0.281 ; dpwm_shake:dpwm_shake|cnt[10] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.402 ; +; 0.299 ; dpwm_shake:dpwm_shake|cat_duty[7] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.428 ; +; 0.300 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.429 ; +; 0.301 ; dpwm_shake:dpwm_shake|cat_duty[8] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.430 ; +; 0.301 ; dpwm_shake:dpwm_shake|cnt[8] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.430 ; +; 0.307 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|shake_count[1] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.428 ; +; 0.308 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[2] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.429 ; +; 0.308 ; dpwm_shake:dpwm_shake|cnt[1] ; dpwm_shake:dpwm_shake|cnt[1] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.437 ; +; 0.309 ; dpwm_shake:dpwm_shake|cnt[9] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.430 ; +; 0.310 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[3] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.431 ; +; 0.314 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.435 ; +; 0.315 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.436 ; +; 0.321 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.442 ; +; 0.322 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.443 ; +; 0.333 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.238 ; 0.655 ; +; 0.337 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.238 ; 0.659 ; +; 0.338 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[2] ; clk_0 ; clk_0 ; 0.000 ; 0.036 ; 0.458 ; +; 0.339 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.225 ; 0.648 ; +; 0.342 ; dpwm_shake:dpwm_shake|cat_duty[10] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 0.000 ; 0.036 ; 0.462 ; +; 0.344 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.225 ; 0.653 ; +; 0.346 ; dpwm_shake:dpwm_shake|cat_duty[6] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 0.000 ; 0.036 ; 0.466 ; +; 0.347 ; dpwm_shake:dpwm_shake|cat_duty[9] ; dpwm_shake:dpwm_shake|new_duty[9] ; clk_0 ; clk_0 ; 0.000 ; 0.036 ; 0.467 ; +; 0.349 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 0.000 ; 0.036 ; 0.469 ; +; 0.350 ; dpwm_shake:dpwm_shake|cat_duty[6] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.225 ; 0.659 ; +; 0.353 ; dpwm_shake:dpwm_shake|cat_duty[6] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.225 ; 0.662 ; +; 0.362 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.483 ; +; 0.390 ; dpwm_shake:dpwm_shake|shake_ctr[0] ; dpwm_shake:dpwm_shake|shakenum[0] ; clk_0 ; clk_0 ; 0.000 ; -0.157 ; 0.317 ; +; 0.392 ; dpwm_shake:dpwm_shake|shake_ctr[0] ; dpwm_shake:dpwm_shake|shakenum[1] ; clk_0 ; clk_0 ; 0.000 ; -0.157 ; 0.319 ; +; 0.398 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.238 ; 0.720 ; +; 0.399 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.238 ; 0.721 ; +; 0.402 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.225 ; 0.711 ; +; 0.407 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.225 ; 0.716 ; +; 0.448 ; dpwm_shake:dpwm_shake|cat_duty[7] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.577 ; +; 0.451 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[8] ; clk_0 ; clk_0 ; 0.000 ; 0.238 ; 0.773 ; +; 0.454 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.764 ; +; 0.454 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.764 ; +; 0.454 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.764 ; +; 0.454 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.764 ; +; 0.454 ; dpwm_shake:dpwm_shake|shake_count[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.764 ; +; 0.457 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[3] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.578 ; +; 0.458 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.587 ; +; 0.464 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[1] ; clk_0 ; clk_0 ; 0.000 ; 0.238 ; 0.786 ; +; 0.467 ; dpwm_shake:dpwm_shake|cnt[9] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.588 ; +; 0.468 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.589 ; +; 0.468 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.225 ; 0.777 ; +; 0.470 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.591 ; +; 0.471 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.592 ; +; 0.471 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.225 ; 0.780 ; +; 0.471 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.592 ; +; 0.472 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.593 ; +; 0.473 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.225 ; 0.782 ; +; 0.475 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.596 ; +; 0.476 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.597 ; +; 0.476 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.225 ; 0.785 ; +; 0.485 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.795 ; +; 0.486 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.796 ; +; 0.497 ; dpwm_shake:dpwm_shake|shake_ctr[1] ; dpwm_shake:dpwm_shake|shakenum[2] ; clk_0 ; clk_0 ; 0.000 ; -0.157 ; 0.424 ; +; 0.498 ; dpwm_shake:dpwm_shake|shake_ctr[1] ; dpwm_shake:dpwm_shake|shakenum[1] ; clk_0 ; clk_0 ; 0.000 ; -0.157 ; 0.425 ; +; 0.503 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.632 ; +; 0.506 ; dpwm_shake:dpwm_shake|cat_duty[5] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.635 ; +; 0.508 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.637 ; +; 0.509 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.819 ; +; 0.509 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.819 ; +; 0.509 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.819 ; +; 0.509 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.819 ; +; 0.509 ; dpwm_shake:dpwm_shake|shake_count[1] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.819 ; +; 0.520 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[4] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.641 ; +; 0.521 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.642 ; +; 0.523 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[5] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.644 ; +; 0.523 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[0] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.644 ; +; 0.524 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[7] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.653 ; +; 0.525 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[3] ; clk_0 ; clk_0 ; 0.000 ; 0.036 ; 0.645 ; +; 0.527 ; dpwm_shake:dpwm_shake|cat_duty[4] ; dpwm_shake:dpwm_shake|new_duty[8] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.656 ; +; 0.529 ; dpwm_shake:dpwm_shake|shake_ctr[1] ; dpwm_shake:dpwm_shake|shakenum[0] ; clk_0 ; clk_0 ; 0.000 ; -0.157 ; 0.456 ; +; 0.531 ; dpwm_shake:dpwm_shake|cat_duty[9] ; dpwm_shake:dpwm_shake|new_duty[10] ; clk_0 ; clk_0 ; 0.000 ; 0.036 ; 0.651 ; +; 0.533 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.654 ; +; 0.534 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.655 ; +; 0.536 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.657 ; +; 0.537 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.658 ; +; 0.537 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.658 ; +; 0.539 ; dpwm_shake:dpwm_shake|cnt[7] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.660 ; +; 0.541 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.662 ; +; 0.554 ; dpwm_shake:dpwm_shake|shakenum[1] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.864 ; +; 0.555 ; dpwm_shake:dpwm_shake|shakenum[2] ; dpwm_shake:dpwm_shake|new_duty[4] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.865 ; +; 0.562 ; dpwm_shake:dpwm_shake|cat_duty[0] ; dpwm_shake:dpwm_shake|new_duty[1] ; clk_0 ; clk_0 ; 0.000 ; 0.226 ; 0.872 ; +; 0.571 ; dpwm_shake:dpwm_shake|cat_duty[1] ; dpwm_shake:dpwm_shake|new_duty[5] ; clk_0 ; clk_0 ; 0.000 ; 0.045 ; 0.700 ; +; 0.586 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[6] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.707 ; +; 0.589 ; dpwm_shake:dpwm_shake|cnt[2] ; dpwm_shake:dpwm_shake|cnt[7] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.710 ; +; 0.594 ; dpwm_shake:dpwm_shake|cat_duty[2] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 0.000 ; 0.036 ; 0.714 ; +; 0.599 ; dpwm_shake:dpwm_shake|cat_duty[3] ; dpwm_shake:dpwm_shake|new_duty[6] ; clk_0 ; clk_0 ; 0.000 ; 0.036 ; 0.719 ; +; 0.600 ; dpwm_shake:dpwm_shake|cnt[6] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.721 ; +; 0.602 ; dpwm_shake:dpwm_shake|cnt[4] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.723 ; +; 0.603 ; dpwm_shake:dpwm_shake|cnt[0] ; dpwm_shake:dpwm_shake|cnt[0] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.724 ; +; 0.603 ; dpwm_shake:dpwm_shake|cnt[3] ; dpwm_shake:dpwm_shake|cnt[9] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.724 ; +; 0.604 ; dpwm_shake:dpwm_shake|cnt[5] ; dpwm_shake:dpwm_shake|cnt[10] ; clk_0 ; clk_0 ; 0.000 ; 0.037 ; 0.725 ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 0.467 ; 0.186 ; N/A ; N/A ; 1.920 ; +; clk_0 ; 0.467 ; 0.186 ; N/A ; N/A ; 1.920 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; clk_0 ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ++------------------+-------+-------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; pwm_out ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; pwm_out_n ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; rst_n ; 2.5 V ; 2000 ps ; 2000 ps ; +; clk ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; control[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; pwm_out ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; pwm_out_n ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; pwm_out ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; pwm_out_n ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; pwm_out ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; pwm_out_n ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk_0 ; clk_0 ; 283 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk_0 ; clk_0 ; 283 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 1 ; 1 ; +; Unconstrained Input Ports ; 15 ; 15 ; +; Unconstrained Input Port Paths ; 44 ; 44 ; +; Unconstrained Output Ports ; 2 ; 2 ; +; Unconstrained Output Port Paths ; 2 ; 2 ; ++---------------------------------+-------+------+ + + ++------------------------------------------------------------------------------------+ +; Clock Status Summary ; ++-----------------------------------------------------+-------+------+---------------+ +; Target ; Clock ; Type ; Status ; ++-----------------------------------------------------+-------+------+---------------+ +; dpwm_shake:dpwm_shake|cnt[0] ; ; Base ; Unconstrained ; +; pwm_pll|altpll_component|auto_generated|pll1|clk[0] ; clk_0 ; Base ; Constrained ; ++-----------------------------------------------------+-------+------+---------------+ + + ++----------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++-------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++-------------+--------------------------------------------------------------------------------------+ +; clk ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; pwm_out ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; pwm_out_n ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++-------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++-------------+--------------------------------------------------------------------------------------+ +; clk ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; control[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; pwm_out ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; pwm_out_n ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Sat Dec 08 18:51:14 2018 +Info: Command: quartus_sta dpwm_shake -c dpwm_shake +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Warning (335093): The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report. +Info (332104): Reading SDC File: 'dpwm_shake.out.sdc' +Warning (332060): Node: dpwm_shake:dpwm_shake|cnt[0] was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch dpwm_shake:dpwm_shake|pwm_out is being clocked by dpwm_shake:dpwm_shake|cnt[0] +Warning (332056): PLL cross checking found inconsistent PLL clock settings: + Warning (332056): Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll|altpll_component|auto_generated|pll1|clk[0] does not match the period requirement: 20.000 +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From clk_0 (Rise) to clk_0 (Rise) (setup and hold) +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Info (332146): Worst-case setup slack is 0.467 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.467 0.000 clk_0 +Info (332146): Worst-case hold slack is 0.452 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.452 0.000 clk_0 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 1.945 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 1.945 0.000 clk_0 +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Warning (332060): Node: dpwm_shake:dpwm_shake|cnt[0] was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch dpwm_shake:dpwm_shake|pwm_out is being clocked by dpwm_shake:dpwm_shake|cnt[0] +Warning (332056): PLL cross checking found inconsistent PLL clock settings: + Warning (332056): Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll|altpll_component|auto_generated|pll1|clk[0] does not match the period requirement: 20.000 +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From clk_0 (Rise) to clk_0 (Rise) (setup and hold) +Info (332146): Worst-case setup slack is 0.812 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.812 0.000 clk_0 +Info (332146): Worst-case hold slack is 0.401 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.401 0.000 clk_0 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 1.920 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 1.920 0.000 clk_0 +Info: Analyzing Fast 1200mV 0C Model +Warning (332060): Node: dpwm_shake:dpwm_shake|cnt[0] was determined to be a clock but was found without an associated clock assignment. + Info (13166): Latch dpwm_shake:dpwm_shake|pwm_out is being clocked by dpwm_shake:dpwm_shake|cnt[0] +Warning (332056): PLL cross checking found inconsistent PLL clock settings: + Warning (332056): Clock: clk_0 with period: 4.500 found on PLL node: pwm_pll|altpll_component|auto_generated|pll1|clk[0] does not match the period requirement: 20.000 +Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. + Critical Warning (332169): From clk_0 (Rise) to clk_0 (Rise) (setup and hold) +Info (332146): Worst-case setup slack is 2.748 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 2.748 0.000 clk_0 +Info (332146): Worst-case hold slack is 0.186 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.186 0.000 clk_0 +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 2.025 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 2.025 0.000 clk_0 +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 17 warnings + Info: Peak virtual memory: 4776 megabytes + Info: Processing ended: Sat Dec 08 18:51:16 2018 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/dpwm_shake/output_files/dpwm_shake.sta.summary b/dpwm_shake/output_files/dpwm_shake.sta.summary new file mode 100644 index 0000000..b5d9d14 --- /dev/null +++ b/dpwm_shake/output_files/dpwm_shake.sta.summary @@ -0,0 +1,41 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1200mV 85C Model Setup 'clk_0' +Slack : 0.467 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'clk_0' +Slack : 0.452 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk_0' +Slack : 1.945 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Setup 'clk_0' +Slack : 0.812 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'clk_0' +Slack : 0.401 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk_0' +Slack : 1.920 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Setup 'clk_0' +Slack : 2.748 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'clk_0' +Slack : 0.186 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk_0' +Slack : 2.025 +TNS : 0.000 + +------------------------------------------------------------ diff --git a/dpwm_shake/rtl/dpwm_shake.v b/dpwm_shake/rtl/dpwm_shake.v new file mode 100644 index 0000000..d19dcbb --- /dev/null +++ b/dpwm_shake/rtl/dpwm_shake.v @@ -0,0 +1,97 @@ +module dpwm_shake( + + clk, + clk_0, + rst_n, + control, + dead_zone, + pwm_out, + pwm_out_n +); + + input clk,clk_0; + input rst_n; + + input [12:0] control; + + input [7:0] dead_zone; + + output pwm_out,pwm_out_n; + + wire set_pwm,rst_pwm; + + reg [10:0] cnt,new_duty; + + reg [3:0] shakenum; + + reg [1:0] shake_count; + + + reg [1:0] shake_ctr; + + reg [11:0] cat_duty; + + wire tmp_q,tmp_q_n; + reg shake_add; + reg [7:0] cnt_dead; + + parameter MAX_CNT = 11'h7ff; + + assign set_pwm = (cnt == 11'b0) ? 1'b1:1'b0; + assign rst_pwm = (cnt == new_duty) ? 1'b1:1'b0; + + assign tmp_q = set_pwm & (~rst_pwm); + + assign tmp_q_n = rst_pwm & (~set_pwm); + + assign pwm_out = (set_pwm | rst_pwm) ?tmp_q:pwm_out; + + //assign pwm_out_n = (set_pwm | rst_pwm) ?tmp_q_n:pwm_out_n; + + assign pwm_out_n = ~pwm_out; + + + always @ (posedge clk_0) + if(!rst_n) begin + cat_duty <= 12'd0; + shake_ctr <= 2'd0; + end + else begin + shake_ctr <= control[1:0]; + cat_duty <= control[12:2]; + end + + always @(posedge clk_0 or negedge rst_n) + if(!rst_n) + cnt <= 11'b0; + else + cnt <= cnt + 11'd1; + + always @ (posedge clk_0 or negedge rst_n) + if(!rst_n) + shake_count <= 2'd0; + else if(cnt == MAX_CNT) + shake_count <= shake_count +1'b1; + + always @ (posedge clk_0) begin + case(shake_count) + 0: new_duty <= cat_duty + shakenum[0]; + 1: new_duty <= cat_duty + shakenum[1]; + 2: new_duty <= cat_duty + shakenum[2]; + 3: new_duty <= cat_duty + shakenum[3]; + endcase + end + + always @ (posedge clk_0) + if(!rst_n) begin + shakenum <= 4'd0; + end + else + case(shake_ctr) + 0: shakenum <= 4'b0000; + 1: shakenum <= 4'b0001; + 2: shakenum <= 4'b0101; + 3: shakenum <= 4'b0111; + endcase +endmodule + \ No newline at end of file diff --git a/dpwm_shake/rtl/dpwm_shake.v.bak b/dpwm_shake/rtl/dpwm_shake.v.bak new file mode 100644 index 0000000..5217028 --- /dev/null +++ b/dpwm_shake/rtl/dpwm_shake.v.bak @@ -0,0 +1,64 @@ +module dpwm_shake( + clk_0 + +); + + input clk_0; + input rst_n; + input [13:0] control; + + output reg pwm_out; + + wire set_pwm,rst_pwm; + + wire [10:0] new_duty; + + reg [9:0] cnt; + reg [7:0] shakenum; + reg clk_out; + + + wire [2:0] shake_ctr; + wire [10:0] cat_duty; + + + + assign shake_ctr = control[2:0]; + assign cat_duty = control[13:3]; + + assign set_pwm = (cnt == 1'b0) ? 1'b1:1'b0; + assign rst_pwm = (cnt == new_duty) ? 1'b1:1'b0; + + assign new_duty = shakenum + cat_duty; + + + always @(posedge clk_0 or negedge rst_n) + if(!rst_n) + cnt <= 1'b0; + else if(cnt == 10'd749) + cnt <= 1'b0; + else + cnt <= cnt + 1'b1; + + + always @ (*) + case(shake_ctr) + 3'd0: shakenum <= 8'b0000_0000; + 3'd1: shakenum <= 8'b0000_0001; + 3'd2: shakenum <= 8'b0001_0001; + 3'd3: shakenum <= 8'b0010_0101; + 3'd4: shakenum <= 8'b0101_0101; + 3'd5: shakenum <= 8'b0101_1011; + 3'd6: shakenum <= 8'b0111_0111; + 3'd7: shakenum <= 8'b0111_1111; + endcase + + always @(*) + begin + case({set_pwm,rst_pwm}) + 2'b00:pwm_out<=pwm_out; + 2'b01:pwm_out<=1'b0; + 2'b10:pwm_out<=1'b1; + 2'b11:pwm_out<=1'bx; + endcase + end \ No newline at end of file diff --git a/dpwm_shake/rtl/dpwm_top.v b/dpwm_shake/rtl/dpwm_top.v new file mode 100644 index 0000000..043a8cd --- /dev/null +++ b/dpwm_shake/rtl/dpwm_top.v @@ -0,0 +1,48 @@ +module dpwm_top( + + clk, + rst_n, + control, + pwm_out, + pwm_out_n + +); + + input clk; + input rst_n; + + input [12:0] control; + + output pwm_out,pwm_out_n; + + + wire areset,c0,locked; + + wire rst_all; + + assign rst_all = (locked |rst_n ); + assign areset = ~rst_n; + + pwm_pll pwm_pll( + .areset(areset), + .inclk0(clk), + .c0(c0), + .locked(locked) + ); + + dpwm_shake dpwm_shake( + + .clk(clk), + .clk_0(c0), + .rst_n(rst_all), + .control(control), + .dead_zone(128), + .pwm_out(pwm_out), + .pwm_out_n(pwm_out_n) +); + + + + +endmodule + diff --git a/dpwm_shake/rtl/dpwm_top.v.bak b/dpwm_shake/rtl/dpwm_top.v.bak new file mode 100644 index 0000000..079a22e --- /dev/null +++ b/dpwm_shake/rtl/dpwm_top.v.bak @@ -0,0 +1,50 @@ +module dpwm_top( + + clk, + rst_n, + control, + pwm_out + + +); + + input clk; + input rst_n; + input [13:0] control; + output pwm_out; + + + wire areset,c0,c1,locked; + + wire rst_all; + + assign rst_all = (locked |rst_n ); + assign areset = ~rst_n; + + + + + + pwm_pll pwm_pll( + .areset(areset), + .inclk0(clk), + .c0(c0), + .c1(c1), + .locked(locked) + ); + + dpwm_shake( + + .clk_0(c0), + .clk_90(c1), + .rst_n(rst_all), + .control(control), + .pwm_out(pwm_out) + +); + + + + +endmodule + diff --git a/dpwm_shake/simulation/dpwm_top_tb.v b/dpwm_shake/simulation/dpwm_top_tb.v new file mode 100644 index 0000000..99c6a58 --- /dev/null +++ b/dpwm_shake/simulation/dpwm_top_tb.v @@ -0,0 +1,51 @@ +`timescale 1ns/1ns + +`define clk_period 20 + +module dpwm_top_tb; + +//source define + + reg clk; + reg rst_n; + reg [12:0] control; + wire pwm_out,pwm_out_n; + +//probe define + + +//instant user module +dpwm_top dpwm_top( + + .clk(clk), + .rst_n(rst_n), + .control(control), + .pwm_out(pwm_out), + .pwm_out_n(pwm_out_n) +); + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + integer i; + + initial begin + + rst_n = 0; + control = 1; + #(`clk_period *200); + rst_n =1; + + for(i=128;i<133;i=i+1) + begin + control = i; + + #(`clk_period *10000); + + end + + $stop; + end + +endmodule diff --git a/dpwm_shake/simulation/dpwm_top_tb.v.bak b/dpwm_shake/simulation/dpwm_top_tb.v.bak new file mode 100644 index 0000000..5093210 --- /dev/null +++ b/dpwm_shake/simulation/dpwm_top_tb.v.bak @@ -0,0 +1,51 @@ +`timescale 1ns/1ns + +`define clk_period 20 + +module dpwm_top_tb; + +//source define + + reg clk; + reg rst_n; + reg [13:0] control; + wire pwm_out; + +//probe define + + +//instant user module +dpwm_top dpwm_top( + + .clk(clk), + .rst_n(rst_n), + .control(control), + .pwm_out(pwm_out) + +); + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + integer i; + + initial begin + + rst_n = 0; + control = 1; + #(`clk_period *200); + rst_n =1; + + for(i=128;i<256;i=i+1) + begin + control = i; + + #(`clk_period *800); + + end + + $stop; + end + +endmodule diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake.sft b/dpwm_shake/simulation/modelsim/dpwm_shake.sft new file mode 100644 index 0000000..2f09d59 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim-Altera (Verilog)" +set corner_file_list { + {{"Slow -8 1.2V 85 Model"} {dpwm_shake_8_1200mv_85c_slow.vo dpwm_shake_8_1200mv_85c_v_slow.sdo}} + {{"Slow -8 1.2V 0 Model"} {dpwm_shake_8_1200mv_0c_slow.vo dpwm_shake_8_1200mv_0c_v_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {dpwm_shake_min_1200mv_0c_fast.vo dpwm_shake_min_1200mv_0c_v_fast.sdo}} +} diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake.vo b/dpwm_shake/simulation/modelsim/dpwm_shake.vo new file mode 100644 index 0000000..83b4ff8 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake.vo @@ -0,0 +1,2380 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" + +// DATE "12/08/2018 18:51:18" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module dpwm_top ( + clk, + rst_n, + control, + pwm_out, + pwm_out_n); +input clk; +input rst_n; +input [12:0] control; +output pwm_out; +output pwm_out_n; + +// Design Ports Information +// pwm_out => Location: PIN_K1, I/O Standard: 2.5 V, Current Strength: Default +// pwm_out_n => Location: PIN_L2, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// control[3] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// control[2] => Location: PIN_K6, I/O Standard: 2.5 V, Current Strength: Default +// control[5] => Location: PIN_L1, I/O Standard: 2.5 V, Current Strength: Default +// control[4] => Location: PIN_N2, I/O Standard: 2.5 V, Current Strength: Default +// control[7] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default +// control[6] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// control[9] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +// control[8] => Location: PIN_J6, I/O Standard: 2.5 V, Current Strength: Default +// control[11] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// control[10] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default +// control[12] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// control[0] => Location: PIN_L6, I/O Standard: 2.5 V, Current Strength: Default +// control[1] => Location: PIN_K2, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("dpwm_shake_v.sdo"); +// synopsys translate_on + +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \clk~input_o ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \dpwm_shake|cnt[0]~30_combout ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_all~combout ; +wire \rst_all~clkctrl_outclk ; +wire \dpwm_shake|cnt[1]~10_combout ; +wire \dpwm_shake|cnt[1]~11 ; +wire \dpwm_shake|cnt[2]~12_combout ; +wire \dpwm_shake|cnt[2]~13 ; +wire \dpwm_shake|cnt[3]~14_combout ; +wire \dpwm_shake|Equal0~0_combout ; +wire \dpwm_shake|cnt[3]~15 ; +wire \dpwm_shake|cnt[4]~16_combout ; +wire \dpwm_shake|cnt[4]~17 ; +wire \dpwm_shake|cnt[5]~18_combout ; +wire \dpwm_shake|cnt[5]~19 ; +wire \dpwm_shake|cnt[6]~20_combout ; +wire \dpwm_shake|cnt[6]~21 ; +wire \dpwm_shake|cnt[7]~22_combout ; +wire \dpwm_shake|cnt[7]~23 ; +wire \dpwm_shake|cnt[8]~24_combout ; +wire \dpwm_shake|cnt[8]~25 ; +wire \dpwm_shake|cnt[9]~26_combout ; +wire \dpwm_shake|cnt[9]~27 ; +wire \dpwm_shake|cnt[10]~28_combout ; +wire \dpwm_shake|Equal0~2_combout ; +wire \dpwm_shake|Equal0~1_combout ; +wire \control[3]~input_o ; +wire \dpwm_shake|cat_duty~0_combout ; +wire \dpwm_shake|Equal2~0_combout ; +wire \dpwm_shake|Equal2~1_combout ; +wire \dpwm_shake|Equal2~2_combout ; +wire \dpwm_shake|shake_count[0]~1_combout ; +wire \dpwm_shake|shake_count[1]~0_combout ; +wire \control[2]~input_o ; +wire \dpwm_shake|cat_duty~1_combout ; +wire \control[1]~input_o ; +wire \dpwm_shake|shake_ctr~1_combout ; +wire \dpwm_shake|shakenum~2_combout ; +wire \dpwm_shake|Add2~2_combout ; +wire \control[0]~input_o ; +wire \dpwm_shake|shake_ctr~0_combout ; +wire \dpwm_shake|shakenum~0_combout ; +wire \dpwm_shake|Add2~0_combout ; +wire \dpwm_shake|shakenum~1_combout ; +wire \dpwm_shake|Add2~1_combout ; +wire \dpwm_shake|new_duty[0]~12 ; +wire \dpwm_shake|new_duty[1]~13_combout ; +wire \dpwm_shake|Add2~3_combout ; +wire \dpwm_shake|new_duty[0]~11_combout ; +wire \dpwm_shake|Equal1~0_combout ; +wire \control[9]~input_o ; +wire \dpwm_shake|cat_duty~6_combout ; +wire \control[8]~input_o ; +wire \dpwm_shake|cat_duty~7_combout ; +wire \control[7]~input_o ; +wire \dpwm_shake|cat_duty~4_combout ; +wire \control[6]~input_o ; +wire \dpwm_shake|cat_duty~5_combout ; +wire \control[5]~input_o ; +wire \dpwm_shake|cat_duty~2_combout ; +wire \control[4]~input_o ; +wire \dpwm_shake|cat_duty~3_combout ; +wire \dpwm_shake|new_duty[1]~14 ; +wire \dpwm_shake|new_duty[2]~16 ; +wire \dpwm_shake|new_duty[3]~18 ; +wire \dpwm_shake|new_duty[4]~20 ; +wire \dpwm_shake|new_duty[5]~22 ; +wire \dpwm_shake|new_duty[6]~24 ; +wire \dpwm_shake|new_duty[7]~25_combout ; +wire \dpwm_shake|new_duty[6]~23_combout ; +wire \dpwm_shake|Equal1~3_combout ; +wire \dpwm_shake|new_duty[4]~19_combout ; +wire \dpwm_shake|new_duty[5]~21_combout ; +wire \dpwm_shake|Equal1~2_combout ; +wire \dpwm_shake|new_duty[3]~17_combout ; +wire \dpwm_shake|new_duty[2]~15_combout ; +wire \dpwm_shake|Equal1~1_combout ; +wire \dpwm_shake|Equal1~4_combout ; +wire \control[12]~input_o ; +wire \dpwm_shake|cat_duty~10_combout ; +wire \control[11]~input_o ; +wire \dpwm_shake|cat_duty~8_combout ; +wire \control[10]~input_o ; +wire \dpwm_shake|cat_duty~9_combout ; +wire \dpwm_shake|new_duty[7]~26 ; +wire \dpwm_shake|new_duty[8]~28 ; +wire \dpwm_shake|new_duty[9]~30 ; +wire \dpwm_shake|new_duty[10]~31_combout ; +wire \dpwm_shake|new_duty[8]~27_combout ; +wire \dpwm_shake|new_duty[9]~29_combout ; +wire \dpwm_shake|Equal1~5_combout ; +wire \dpwm_shake|Equal1~6_combout ; +wire \dpwm_shake|tmp_q~combout ; +wire \dpwm_shake|pwm_out~2_combout ; +wire \dpwm_shake|pwm_out~combout ; +wire [10:0] \dpwm_shake|cnt ; +wire [10:0] \dpwm_shake|new_duty ; +wire [1:0] \dpwm_shake|shake_ctr ; +wire [4:0] \pwm_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [11:0] \dpwm_shake|cat_duty ; +wire [3:0] \dpwm_shake|shakenum ; +wire [1:0] \dpwm_shake|shake_count ; + +wire [4:0] \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X0_Y8_N9 +cycloneive_io_obuf \pwm_out~output ( + .i(\dpwm_shake|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out), + .obar()); +// synopsys translate_off +defparam \pwm_out~output .bus_hold = "false"; +defparam \pwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y8_N16 +cycloneive_io_obuf \pwm_out_n~output ( + .i(!\dpwm_shake|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out_n), + .obar()); +// synopsys translate_off +defparam \pwm_out_n~output .bus_hold = "false"; +defparam \pwm_out_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \pwm_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\pwm_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_high = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_low = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 10; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 49; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 19; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m = 49; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .n = 5; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "on"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 255; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneive_clkctrl \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\pwm_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|cnt[0]~30 ( +// Equation(s): +// \dpwm_shake|cnt[0]~30_combout = !\dpwm_shake|cnt [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm_shake|cnt [0]), + .cin(gnd), + .combout(\dpwm_shake|cnt[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cnt[0]~30 .lut_mask = 16'h00FF; +defparam \dpwm_shake|cnt[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y10_N4 +cycloneive_lcell_comb \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y10_N5 +dffeas \pwm_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N4 +cycloneive_lcell_comb rst_all( +// Equation(s): +// \rst_all~combout = (!\rst_n~input_o & ((!\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ))) + + .dataa(\rst_n~input_o ), + .datab(gnd), + .datac(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_all~combout ), + .cout()); +// synopsys translate_off +defparam rst_all.lut_mask = 16'h0555; +defparam rst_all.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \rst_all~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_all~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_all~clkctrl_outclk )); +// synopsys translate_off +defparam \rst_all~clkctrl .clock_type = "global clock"; +defparam \rst_all~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X1_Y11_N31 +dffeas \dpwm_shake|cnt[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\dpwm_shake|cnt[0]~30_combout ), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|cnt[1]~10 ( +// Equation(s): +// \dpwm_shake|cnt[1]~10_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] $ (VCC))) # (!\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] & VCC)) +// \dpwm_shake|cnt[1]~11 = CARRY((\dpwm_shake|cnt [1] & \dpwm_shake|cnt [0])) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm_shake|cnt[1]~10_combout ), + .cout(\dpwm_shake|cnt[1]~11 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[1]~10 .lut_mask = 16'h6688; +defparam \dpwm_shake|cnt[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y11_N11 +dffeas \dpwm_shake|cnt[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|cnt[2]~12 ( +// Equation(s): +// \dpwm_shake|cnt[2]~12_combout = (\dpwm_shake|cnt [2] & (!\dpwm_shake|cnt[1]~11 )) # (!\dpwm_shake|cnt [2] & ((\dpwm_shake|cnt[1]~11 ) # (GND))) +// \dpwm_shake|cnt[2]~13 = CARRY((!\dpwm_shake|cnt[1]~11 ) # (!\dpwm_shake|cnt [2])) + + .dataa(\dpwm_shake|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[1]~11 ), + .combout(\dpwm_shake|cnt[2]~12_combout ), + .cout(\dpwm_shake|cnt[2]~13 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[2]~12 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|cnt[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N13 +dffeas \dpwm_shake|cnt[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|cnt[3]~14 ( +// Equation(s): +// \dpwm_shake|cnt[3]~14_combout = (\dpwm_shake|cnt [3] & (\dpwm_shake|cnt[2]~13 $ (GND))) # (!\dpwm_shake|cnt [3] & (!\dpwm_shake|cnt[2]~13 & VCC)) +// \dpwm_shake|cnt[3]~15 = CARRY((\dpwm_shake|cnt [3] & !\dpwm_shake|cnt[2]~13 )) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[2]~13 ), + .combout(\dpwm_shake|cnt[3]~14_combout ), + .cout(\dpwm_shake|cnt[3]~15 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[3]~14 .lut_mask = 16'hC30C; +defparam \dpwm_shake|cnt[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N15 +dffeas \dpwm_shake|cnt[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|Equal0~0 ( +// Equation(s): +// \dpwm_shake|Equal0~0_combout = (!\dpwm_shake|cnt [1] & (!\dpwm_shake|cnt [3] & (!\dpwm_shake|cnt [0] & !\dpwm_shake|cnt [2]))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [3]), + .datac(\dpwm_shake|cnt [0]), + .datad(\dpwm_shake|cnt [2]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~0 .lut_mask = 16'h0001; +defparam \dpwm_shake|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|cnt[4]~16 ( +// Equation(s): +// \dpwm_shake|cnt[4]~16_combout = (\dpwm_shake|cnt [4] & (!\dpwm_shake|cnt[3]~15 )) # (!\dpwm_shake|cnt [4] & ((\dpwm_shake|cnt[3]~15 ) # (GND))) +// \dpwm_shake|cnt[4]~17 = CARRY((!\dpwm_shake|cnt[3]~15 ) # (!\dpwm_shake|cnt [4])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[3]~15 ), + .combout(\dpwm_shake|cnt[4]~16_combout ), + .cout(\dpwm_shake|cnt[4]~17 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[4]~16 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N17 +dffeas \dpwm_shake|cnt[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|cnt[5]~18 ( +// Equation(s): +// \dpwm_shake|cnt[5]~18_combout = (\dpwm_shake|cnt [5] & (\dpwm_shake|cnt[4]~17 $ (GND))) # (!\dpwm_shake|cnt [5] & (!\dpwm_shake|cnt[4]~17 & VCC)) +// \dpwm_shake|cnt[5]~19 = CARRY((\dpwm_shake|cnt [5] & !\dpwm_shake|cnt[4]~17 )) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[4]~17 ), + .combout(\dpwm_shake|cnt[5]~18_combout ), + .cout(\dpwm_shake|cnt[5]~19 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[5]~18 .lut_mask = 16'hC30C; +defparam \dpwm_shake|cnt[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N19 +dffeas \dpwm_shake|cnt[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|cnt[6]~20 ( +// Equation(s): +// \dpwm_shake|cnt[6]~20_combout = (\dpwm_shake|cnt [6] & (!\dpwm_shake|cnt[5]~19 )) # (!\dpwm_shake|cnt [6] & ((\dpwm_shake|cnt[5]~19 ) # (GND))) +// \dpwm_shake|cnt[6]~21 = CARRY((!\dpwm_shake|cnt[5]~19 ) # (!\dpwm_shake|cnt [6])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[5]~19 ), + .combout(\dpwm_shake|cnt[6]~20_combout ), + .cout(\dpwm_shake|cnt[6]~21 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[6]~20 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N21 +dffeas \dpwm_shake|cnt[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|cnt[7]~22 ( +// Equation(s): +// \dpwm_shake|cnt[7]~22_combout = (\dpwm_shake|cnt [7] & (\dpwm_shake|cnt[6]~21 $ (GND))) # (!\dpwm_shake|cnt [7] & (!\dpwm_shake|cnt[6]~21 & VCC)) +// \dpwm_shake|cnt[7]~23 = CARRY((\dpwm_shake|cnt [7] & !\dpwm_shake|cnt[6]~21 )) + + .dataa(\dpwm_shake|cnt [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[6]~21 ), + .combout(\dpwm_shake|cnt[7]~22_combout ), + .cout(\dpwm_shake|cnt[7]~23 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[7]~22 .lut_mask = 16'hA50A; +defparam \dpwm_shake|cnt[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N23 +dffeas \dpwm_shake|cnt[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|cnt[8]~24 ( +// Equation(s): +// \dpwm_shake|cnt[8]~24_combout = (\dpwm_shake|cnt [8] & (!\dpwm_shake|cnt[7]~23 )) # (!\dpwm_shake|cnt [8] & ((\dpwm_shake|cnt[7]~23 ) # (GND))) +// \dpwm_shake|cnt[8]~25 = CARRY((!\dpwm_shake|cnt[7]~23 ) # (!\dpwm_shake|cnt [8])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[7]~23 ), + .combout(\dpwm_shake|cnt[8]~24_combout ), + .cout(\dpwm_shake|cnt[8]~25 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[8]~24 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[8]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N25 +dffeas \dpwm_shake|cnt[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[8]~24_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cnt[9]~26 ( +// Equation(s): +// \dpwm_shake|cnt[9]~26_combout = (\dpwm_shake|cnt [9] & (\dpwm_shake|cnt[8]~25 $ (GND))) # (!\dpwm_shake|cnt [9] & (!\dpwm_shake|cnt[8]~25 & VCC)) +// \dpwm_shake|cnt[9]~27 = CARRY((\dpwm_shake|cnt [9] & !\dpwm_shake|cnt[8]~25 )) + + .dataa(\dpwm_shake|cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[8]~25 ), + .combout(\dpwm_shake|cnt[9]~26_combout ), + .cout(\dpwm_shake|cnt[9]~27 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[9]~26 .lut_mask = 16'hA50A; +defparam \dpwm_shake|cnt[9]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N27 +dffeas \dpwm_shake|cnt[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[9]~26_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|cnt[10]~28 ( +// Equation(s): +// \dpwm_shake|cnt[10]~28_combout = \dpwm_shake|cnt[9]~27 $ (\dpwm_shake|cnt [10]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm_shake|cnt [10]), + .cin(\dpwm_shake|cnt[9]~27 ), + .combout(\dpwm_shake|cnt[10]~28_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cnt[10]~28 .lut_mask = 16'h0FF0; +defparam \dpwm_shake|cnt[10]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N29 +dffeas \dpwm_shake|cnt[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[10]~28_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|Equal0~2 ( +// Equation(s): +// \dpwm_shake|Equal0~2_combout = (!\dpwm_shake|cnt [8] & (!\dpwm_shake|cnt [9] & !\dpwm_shake|cnt [10])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|cnt [9]), + .datad(\dpwm_shake|cnt [10]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~2 .lut_mask = 16'h0003; +defparam \dpwm_shake|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|Equal0~1 ( +// Equation(s): +// \dpwm_shake|Equal0~1_combout = (!\dpwm_shake|cnt [7] & (!\dpwm_shake|cnt [4] & (!\dpwm_shake|cnt [6] & !\dpwm_shake|cnt [5]))) + + .dataa(\dpwm_shake|cnt [7]), + .datab(\dpwm_shake|cnt [4]), + .datac(\dpwm_shake|cnt [6]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~1 .lut_mask = 16'h0001; +defparam \dpwm_shake|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \control[3]~input ( + .i(control[3]), + .ibar(gnd), + .o(\control[3]~input_o )); +// synopsys translate_off +defparam \control[3]~input .bus_hold = "false"; +defparam \control[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|cat_duty~0 ( +// Equation(s): +// \dpwm_shake|cat_duty~0_combout = (\control[3]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[3]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~0 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N31 +dffeas \dpwm_shake|cat_duty[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|Equal2~0 ( +// Equation(s): +// \dpwm_shake|Equal2~0_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] & (\dpwm_shake|cnt [3] & \dpwm_shake|cnt [2]))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(\dpwm_shake|cnt [3]), + .datad(\dpwm_shake|cnt [2]), + .cin(gnd), + .combout(\dpwm_shake|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~0 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|Equal2~1 ( +// Equation(s): +// \dpwm_shake|Equal2~1_combout = (\dpwm_shake|cnt [4] & (\dpwm_shake|cnt [6] & (\dpwm_shake|cnt [7] & \dpwm_shake|cnt [5]))) + + .dataa(\dpwm_shake|cnt [4]), + .datab(\dpwm_shake|cnt [6]), + .datac(\dpwm_shake|cnt [7]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~1 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|Equal2~2 ( +// Equation(s): +// \dpwm_shake|Equal2~2_combout = (\dpwm_shake|cnt [10] & (\dpwm_shake|cnt [8] & (\dpwm_shake|cnt [9] & \dpwm_shake|Equal2~1_combout ))) + + .dataa(\dpwm_shake|cnt [10]), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|cnt [9]), + .datad(\dpwm_shake|Equal2~1_combout ), + .cin(gnd), + .combout(\dpwm_shake|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~2 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|shake_count[0]~1 ( +// Equation(s): +// \dpwm_shake|shake_count[0]~1_combout = \dpwm_shake|shake_count [0] $ (((\dpwm_shake|Equal2~0_combout & \dpwm_shake|Equal2~2_combout ))) + + .dataa(\dpwm_shake|Equal2~0_combout ), + .datab(gnd), + .datac(\dpwm_shake|shake_count [0]), + .datad(\dpwm_shake|Equal2~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|shake_count[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_count[0]~1 .lut_mask = 16'h5AF0; +defparam \dpwm_shake|shake_count[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N17 +dffeas \dpwm_shake|shake_count[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_count[0]~1_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_count[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|shake_count[1]~0 ( +// Equation(s): +// \dpwm_shake|shake_count[1]~0_combout = \dpwm_shake|shake_count [1] $ (((\dpwm_shake|Equal2~0_combout & (\dpwm_shake|shake_count [0] & \dpwm_shake|Equal2~2_combout )))) + + .dataa(\dpwm_shake|Equal2~0_combout ), + .datab(\dpwm_shake|shake_count [0]), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|Equal2~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|shake_count[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_count[1]~0 .lut_mask = 16'h78F0; +defparam \dpwm_shake|shake_count[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N15 +dffeas \dpwm_shake|shake_count[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_count[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_count[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y9_N1 +cycloneive_io_ibuf \control[2]~input ( + .i(control[2]), + .ibar(gnd), + .o(\control[2]~input_o )); +// synopsys translate_off +defparam \control[2]~input .bus_hold = "false"; +defparam \control[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|cat_duty~1 ( +// Equation(s): +// \dpwm_shake|cat_duty~1_combout = (\control[2]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\control[2]~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~1 .lut_mask = 16'hA8A0; +defparam \dpwm_shake|cat_duty~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N31 +dffeas \dpwm_shake|cat_duty[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \control[1]~input ( + .i(control[1]), + .ibar(gnd), + .o(\control[1]~input_o )); +// synopsys translate_off +defparam \control[1]~input .bus_hold = "false"; +defparam \control[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|shake_ctr~1 ( +// Equation(s): +// \dpwm_shake|shake_ctr~1_combout = (\control[1]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\control[1]~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shake_ctr~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr~1 .lut_mask = 16'hE0A0; +defparam \dpwm_shake|shake_ctr~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N29 +dffeas \dpwm_shake|shake_ctr[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_ctr~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_ctr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_ctr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|shakenum~2 ( +// Equation(s): +// \dpwm_shake|shakenum~2_combout = (\dpwm_shake|shake_ctr [1] & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shakenum~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~2 .lut_mask = 16'hC888; +defparam \dpwm_shake|shakenum~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N25 +dffeas \dpwm_shake|shakenum[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|Add2~2 ( +// Equation(s): +// \dpwm_shake|Add2~2_combout = (\dpwm_shake|shake_count [1] & ((\dpwm_shake|shakenum [2]))) # (!\dpwm_shake|shake_count [1] & (\dpwm_shake|cat_duty [0])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_count [1]), + .datac(\dpwm_shake|cat_duty [0]), + .datad(\dpwm_shake|shakenum [2]), + .cin(gnd), + .combout(\dpwm_shake|Add2~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~2 .lut_mask = 16'hFC30; +defparam \dpwm_shake|Add2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y9_N8 +cycloneive_io_ibuf \control[0]~input ( + .i(control[0]), + .ibar(gnd), + .o(\control[0]~input_o )); +// synopsys translate_off +defparam \control[0]~input .bus_hold = "false"; +defparam \control[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|shake_ctr~0 ( +// Equation(s): +// \dpwm_shake|shake_ctr~0_combout = (\control[0]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\control[0]~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shake_ctr~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr~0 .lut_mask = 16'hE0A0; +defparam \dpwm_shake|shake_ctr~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N7 +dffeas \dpwm_shake|shake_ctr[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_ctr~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_ctr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_ctr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|shakenum~0 ( +// Equation(s): +// \dpwm_shake|shakenum~0_combout = (!\rst_all~combout & ((\dpwm_shake|shake_ctr [1]) # (\dpwm_shake|shake_ctr [0]))) + + .dataa(gnd), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\rst_all~combout ), + .datad(\dpwm_shake|shake_ctr [0]), + .cin(gnd), + .combout(\dpwm_shake|shakenum~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~0 .lut_mask = 16'h0F0C; +defparam \dpwm_shake|shakenum~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N9 +dffeas \dpwm_shake|shakenum[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|Add2~0 ( +// Equation(s): +// \dpwm_shake|Add2~0_combout = (!\dpwm_shake|shake_count [0] & ((\dpwm_shake|shake_count [1] & (\dpwm_shake|cat_duty [0])) # (!\dpwm_shake|shake_count [1] & ((\dpwm_shake|shakenum [0]))))) + + .dataa(\dpwm_shake|cat_duty [0]), + .datab(\dpwm_shake|shakenum [0]), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|shake_count [0]), + .cin(gnd), + .combout(\dpwm_shake|Add2~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~0 .lut_mask = 16'h00AC; +defparam \dpwm_shake|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|shakenum~1 ( +// Equation(s): +// \dpwm_shake|shakenum~1_combout = (\dpwm_shake|shake_ctr [1] & (!\rst_all~combout & \dpwm_shake|shake_ctr [0])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\rst_all~combout ), + .datad(\dpwm_shake|shake_ctr [0]), + .cin(gnd), + .combout(\dpwm_shake|shakenum~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~1 .lut_mask = 16'h0C00; +defparam \dpwm_shake|shakenum~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N21 +dffeas \dpwm_shake|shakenum[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|Add2~1 ( +// Equation(s): +// \dpwm_shake|Add2~1_combout = (\dpwm_shake|Add2~0_combout ) # ((\dpwm_shake|shake_count [0] & \dpwm_shake|shakenum [1])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_count [0]), + .datac(\dpwm_shake|Add2~0_combout ), + .datad(\dpwm_shake|shakenum [1]), + .cin(gnd), + .combout(\dpwm_shake|Add2~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~1 .lut_mask = 16'hFCF0; +defparam \dpwm_shake|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|new_duty[0]~11 ( +// Equation(s): +// \dpwm_shake|new_duty[0]~11_combout = (\dpwm_shake|Add2~2_combout & (\dpwm_shake|Add2~1_combout $ (VCC))) # (!\dpwm_shake|Add2~2_combout & (\dpwm_shake|Add2~1_combout & VCC)) +// \dpwm_shake|new_duty[0]~12 = CARRY((\dpwm_shake|Add2~2_combout & \dpwm_shake|Add2~1_combout )) + + .dataa(\dpwm_shake|Add2~2_combout ), + .datab(\dpwm_shake|Add2~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm_shake|new_duty[0]~11_combout ), + .cout(\dpwm_shake|new_duty[0]~12 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[0]~11 .lut_mask = 16'h6688; +defparam \dpwm_shake|new_duty[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|new_duty[1]~13 ( +// Equation(s): +// \dpwm_shake|new_duty[1]~13_combout = (\dpwm_shake|cat_duty [1] & (!\dpwm_shake|new_duty[0]~12 )) # (!\dpwm_shake|cat_duty [1] & ((\dpwm_shake|new_duty[0]~12 ) # (GND))) +// \dpwm_shake|new_duty[1]~14 = CARRY((!\dpwm_shake|new_duty[0]~12 ) # (!\dpwm_shake|cat_duty [1])) + + .dataa(\dpwm_shake|cat_duty [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[0]~12 ), + .combout(\dpwm_shake|new_duty[1]~13_combout ), + .cout(\dpwm_shake|new_duty[1]~14 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[1]~13 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[1]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|Add2~3 ( +// Equation(s): +// \dpwm_shake|Add2~3_combout = (\dpwm_shake|shake_count [1] & \dpwm_shake|shake_count [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|shake_count [0]), + .cin(gnd), + .combout(\dpwm_shake|Add2~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~3 .lut_mask = 16'hF000; +defparam \dpwm_shake|Add2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N7 +dffeas \dpwm_shake|new_duty[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[1]~13_combout ), + .asdata(\dpwm_shake|cat_duty [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N5 +dffeas \dpwm_shake|new_duty[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[0]~11_combout ), + .asdata(\dpwm_shake|cat_duty [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|Equal1~0 ( +// Equation(s): +// \dpwm_shake|Equal1~0_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|new_duty [1] & (\dpwm_shake|cnt [0] $ (!\dpwm_shake|new_duty [0])))) # (!\dpwm_shake|cnt [1] & (!\dpwm_shake|new_duty [1] & (\dpwm_shake|cnt [0] $ (!\dpwm_shake|new_duty [0])))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(\dpwm_shake|new_duty [1]), + .datad(\dpwm_shake|new_duty [0]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~0 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N22 +cycloneive_io_ibuf \control[9]~input ( + .i(control[9]), + .ibar(gnd), + .o(\control[9]~input_o )); +// synopsys translate_off +defparam \control[9]~input .bus_hold = "false"; +defparam \control[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|cat_duty~6 ( +// Equation(s): +// \dpwm_shake|cat_duty~6_combout = (\control[9]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[9]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~6_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~6 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N3 +dffeas \dpwm_shake|cat_duty[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N22 +cycloneive_io_ibuf \control[8]~input ( + .i(control[8]), + .ibar(gnd), + .o(\control[8]~input_o )); +// synopsys translate_off +defparam \control[8]~input .bus_hold = "false"; +defparam \control[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|cat_duty~7 ( +// Equation(s): +// \dpwm_shake|cat_duty~7_combout = (\control[8]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[8]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~7_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~7 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N1 +dffeas \dpwm_shake|cat_duty[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[6] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N1 +cycloneive_io_ibuf \control[7]~input ( + .i(control[7]), + .ibar(gnd), + .o(\control[7]~input_o )); +// synopsys translate_off +defparam \control[7]~input .bus_hold = "false"; +defparam \control[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cat_duty~4 ( +// Equation(s): +// \dpwm_shake|cat_duty~4_combout = (\control[7]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[7]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~4_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~4 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N27 +dffeas \dpwm_shake|cat_duty[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \control[6]~input ( + .i(control[6]), + .ibar(gnd), + .o(\control[6]~input_o )); +// synopsys translate_off +defparam \control[6]~input .bus_hold = "false"; +defparam \control[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|cat_duty~5 ( +// Equation(s): +// \dpwm_shake|cat_duty~5_combout = (\control[6]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[6]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~5_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~5 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N29 +dffeas \dpwm_shake|cat_duty[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[4] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N22 +cycloneive_io_ibuf \control[5]~input ( + .i(control[5]), + .ibar(gnd), + .o(\control[5]~input_o )); +// synopsys translate_off +defparam \control[5]~input .bus_hold = "false"; +defparam \control[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|cat_duty~2 ( +// Equation(s): +// \dpwm_shake|cat_duty~2_combout = (\control[5]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[5]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~2 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N17 +dffeas \dpwm_shake|cat_duty[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[3] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N15 +cycloneive_io_ibuf \control[4]~input ( + .i(control[4]), + .ibar(gnd), + .o(\control[4]~input_o )); +// synopsys translate_off +defparam \control[4]~input .bus_hold = "false"; +defparam \control[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|cat_duty~3 ( +// Equation(s): +// \dpwm_shake|cat_duty~3_combout = (\control[4]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[4]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~3 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N7 +dffeas \dpwm_shake|cat_duty[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|new_duty[2]~15 ( +// Equation(s): +// \dpwm_shake|new_duty[2]~15_combout = (\dpwm_shake|cat_duty [2] & (\dpwm_shake|new_duty[1]~14 $ (GND))) # (!\dpwm_shake|cat_duty [2] & (!\dpwm_shake|new_duty[1]~14 & VCC)) +// \dpwm_shake|new_duty[2]~16 = CARRY((\dpwm_shake|cat_duty [2] & !\dpwm_shake|new_duty[1]~14 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [2]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[1]~14 ), + .combout(\dpwm_shake|new_duty[2]~15_combout ), + .cout(\dpwm_shake|new_duty[2]~16 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[2]~15 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[2]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|new_duty[3]~17 ( +// Equation(s): +// \dpwm_shake|new_duty[3]~17_combout = (\dpwm_shake|cat_duty [3] & (!\dpwm_shake|new_duty[2]~16 )) # (!\dpwm_shake|cat_duty [3] & ((\dpwm_shake|new_duty[2]~16 ) # (GND))) +// \dpwm_shake|new_duty[3]~18 = CARRY((!\dpwm_shake|new_duty[2]~16 ) # (!\dpwm_shake|cat_duty [3])) + + .dataa(\dpwm_shake|cat_duty [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[2]~16 ), + .combout(\dpwm_shake|new_duty[3]~17_combout ), + .cout(\dpwm_shake|new_duty[3]~18 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[3]~17 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|new_duty[4]~19 ( +// Equation(s): +// \dpwm_shake|new_duty[4]~19_combout = (\dpwm_shake|cat_duty [4] & (\dpwm_shake|new_duty[3]~18 $ (GND))) # (!\dpwm_shake|cat_duty [4] & (!\dpwm_shake|new_duty[3]~18 & VCC)) +// \dpwm_shake|new_duty[4]~20 = CARRY((\dpwm_shake|cat_duty [4] & !\dpwm_shake|new_duty[3]~18 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[3]~18 ), + .combout(\dpwm_shake|new_duty[4]~19_combout ), + .cout(\dpwm_shake|new_duty[4]~20 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[4]~19 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|new_duty[5]~21 ( +// Equation(s): +// \dpwm_shake|new_duty[5]~21_combout = (\dpwm_shake|cat_duty [5] & (!\dpwm_shake|new_duty[4]~20 )) # (!\dpwm_shake|cat_duty [5] & ((\dpwm_shake|new_duty[4]~20 ) # (GND))) +// \dpwm_shake|new_duty[5]~22 = CARRY((!\dpwm_shake|new_duty[4]~20 ) # (!\dpwm_shake|cat_duty [5])) + + .dataa(\dpwm_shake|cat_duty [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[4]~20 ), + .combout(\dpwm_shake|new_duty[5]~21_combout ), + .cout(\dpwm_shake|new_duty[5]~22 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[5]~21 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|new_duty[6]~23 ( +// Equation(s): +// \dpwm_shake|new_duty[6]~23_combout = (\dpwm_shake|cat_duty [6] & (\dpwm_shake|new_duty[5]~22 $ (GND))) # (!\dpwm_shake|cat_duty [6] & (!\dpwm_shake|new_duty[5]~22 & VCC)) +// \dpwm_shake|new_duty[6]~24 = CARRY((\dpwm_shake|cat_duty [6] & !\dpwm_shake|new_duty[5]~22 )) + + .dataa(\dpwm_shake|cat_duty [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[5]~22 ), + .combout(\dpwm_shake|new_duty[6]~23_combout ), + .cout(\dpwm_shake|new_duty[6]~24 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[6]~23 .lut_mask = 16'hA50A; +defparam \dpwm_shake|new_duty[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|new_duty[7]~25 ( +// Equation(s): +// \dpwm_shake|new_duty[7]~25_combout = (\dpwm_shake|cat_duty [7] & (!\dpwm_shake|new_duty[6]~24 )) # (!\dpwm_shake|cat_duty [7] & ((\dpwm_shake|new_duty[6]~24 ) # (GND))) +// \dpwm_shake|new_duty[7]~26 = CARRY((!\dpwm_shake|new_duty[6]~24 ) # (!\dpwm_shake|cat_duty [7])) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [7]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[6]~24 ), + .combout(\dpwm_shake|new_duty[7]~25_combout ), + .cout(\dpwm_shake|new_duty[7]~26 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[7]~25 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|new_duty[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y11_N19 +dffeas \dpwm_shake|new_duty[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[7]~25_combout ), + .asdata(\dpwm_shake|cat_duty [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N17 +dffeas \dpwm_shake|new_duty[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[6]~23_combout ), + .asdata(\dpwm_shake|cat_duty [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|Equal1~3 ( +// Equation(s): +// \dpwm_shake|Equal1~3_combout = (\dpwm_shake|new_duty [7] & (\dpwm_shake|cnt [7] & (\dpwm_shake|cnt [6] $ (!\dpwm_shake|new_duty [6])))) # (!\dpwm_shake|new_duty [7] & (!\dpwm_shake|cnt [7] & (\dpwm_shake|cnt [6] $ (!\dpwm_shake|new_duty [6])))) + + .dataa(\dpwm_shake|new_duty [7]), + .datab(\dpwm_shake|cnt [6]), + .datac(\dpwm_shake|cnt [7]), + .datad(\dpwm_shake|new_duty [6]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~3 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N13 +dffeas \dpwm_shake|new_duty[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[4]~19_combout ), + .asdata(\dpwm_shake|cat_duty [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N15 +dffeas \dpwm_shake|new_duty[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[5]~21_combout ), + .asdata(\dpwm_shake|cat_duty [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|Equal1~2 ( +// Equation(s): +// \dpwm_shake|Equal1~2_combout = (\dpwm_shake|cnt [4] & (\dpwm_shake|new_duty [4] & (\dpwm_shake|new_duty [5] $ (!\dpwm_shake|cnt [5])))) # (!\dpwm_shake|cnt [4] & (!\dpwm_shake|new_duty [4] & (\dpwm_shake|new_duty [5] $ (!\dpwm_shake|cnt [5])))) + + .dataa(\dpwm_shake|cnt [4]), + .datab(\dpwm_shake|new_duty [4]), + .datac(\dpwm_shake|new_duty [5]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~2 .lut_mask = 16'h9009; +defparam \dpwm_shake|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N11 +dffeas \dpwm_shake|new_duty[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[3]~17_combout ), + .asdata(\dpwm_shake|cat_duty [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N9 +dffeas \dpwm_shake|new_duty[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[2]~15_combout ), + .asdata(\dpwm_shake|cat_duty [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|Equal1~1 ( +// Equation(s): +// \dpwm_shake|Equal1~1_combout = (\dpwm_shake|cnt [2] & (\dpwm_shake|new_duty [2] & (\dpwm_shake|new_duty [3] $ (!\dpwm_shake|cnt [3])))) # (!\dpwm_shake|cnt [2] & (!\dpwm_shake|new_duty [2] & (\dpwm_shake|new_duty [3] $ (!\dpwm_shake|cnt [3])))) + + .dataa(\dpwm_shake|cnt [2]), + .datab(\dpwm_shake|new_duty [3]), + .datac(\dpwm_shake|new_duty [2]), + .datad(\dpwm_shake|cnt [3]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~1 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|Equal1~4 ( +// Equation(s): +// \dpwm_shake|Equal1~4_combout = (\dpwm_shake|Equal1~0_combout & (\dpwm_shake|Equal1~3_combout & (\dpwm_shake|Equal1~2_combout & \dpwm_shake|Equal1~1_combout ))) + + .dataa(\dpwm_shake|Equal1~0_combout ), + .datab(\dpwm_shake|Equal1~3_combout ), + .datac(\dpwm_shake|Equal1~2_combout ), + .datad(\dpwm_shake|Equal1~1_combout ), + .cin(gnd), + .combout(\dpwm_shake|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~4 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N1 +cycloneive_io_ibuf \control[12]~input ( + .i(control[12]), + .ibar(gnd), + .o(\control[12]~input_o )); +// synopsys translate_off +defparam \control[12]~input .bus_hold = "false"; +defparam \control[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|cat_duty~10 ( +// Equation(s): +// \dpwm_shake|cat_duty~10_combout = (\control[12]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[12]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~10_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~10 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N5 +dffeas \dpwm_shake|cat_duty[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N15 +cycloneive_io_ibuf \control[11]~input ( + .i(control[11]), + .ibar(gnd), + .o(\control[11]~input_o )); +// synopsys translate_off +defparam \control[11]~input .bus_hold = "false"; +defparam \control[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cat_duty~8 ( +// Equation(s): +// \dpwm_shake|cat_duty~8_combout = (\control[11]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[11]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~8_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~8 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N27 +dffeas \dpwm_shake|cat_duty[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[9] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y6_N22 +cycloneive_io_ibuf \control[10]~input ( + .i(control[10]), + .ibar(gnd), + .o(\control[10]~input_o )); +// synopsys translate_off +defparam \control[10]~input .bus_hold = "false"; +defparam \control[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|cat_duty~9 ( +// Equation(s): +// \dpwm_shake|cat_duty~9_combout = (\control[10]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[10]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~9_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~9 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N1 +dffeas \dpwm_shake|cat_duty[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|new_duty[8]~27 ( +// Equation(s): +// \dpwm_shake|new_duty[8]~27_combout = (\dpwm_shake|cat_duty [8] & (\dpwm_shake|new_duty[7]~26 $ (GND))) # (!\dpwm_shake|cat_duty [8] & (!\dpwm_shake|new_duty[7]~26 & VCC)) +// \dpwm_shake|new_duty[8]~28 = CARRY((\dpwm_shake|cat_duty [8] & !\dpwm_shake|new_duty[7]~26 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [8]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[7]~26 ), + .combout(\dpwm_shake|new_duty[8]~27_combout ), + .cout(\dpwm_shake|new_duty[8]~28 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[8]~27 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|new_duty[9]~29 ( +// Equation(s): +// \dpwm_shake|new_duty[9]~29_combout = (\dpwm_shake|cat_duty [9] & (!\dpwm_shake|new_duty[8]~28 )) # (!\dpwm_shake|cat_duty [9] & ((\dpwm_shake|new_duty[8]~28 ) # (GND))) +// \dpwm_shake|new_duty[9]~30 = CARRY((!\dpwm_shake|new_duty[8]~28 ) # (!\dpwm_shake|cat_duty [9])) + + .dataa(\dpwm_shake|cat_duty [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[8]~28 ), + .combout(\dpwm_shake|new_duty[9]~29_combout ), + .cout(\dpwm_shake|new_duty[9]~30 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[9]~29 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|new_duty[10]~31 ( +// Equation(s): +// \dpwm_shake|new_duty[10]~31_combout = \dpwm_shake|cat_duty [10] $ (!\dpwm_shake|new_duty[9]~30 ) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [10]), + .datac(gnd), + .datad(gnd), + .cin(\dpwm_shake|new_duty[9]~30 ), + .combout(\dpwm_shake|new_duty[10]~31_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|new_duty[10]~31 .lut_mask = 16'hC3C3; +defparam \dpwm_shake|new_duty[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y11_N25 +dffeas \dpwm_shake|new_duty[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[10]~31_combout ), + .asdata(\dpwm_shake|cat_duty [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N21 +dffeas \dpwm_shake|new_duty[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[8]~27_combout ), + .asdata(\dpwm_shake|cat_duty [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N23 +dffeas \dpwm_shake|new_duty[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[9]~29_combout ), + .asdata(\dpwm_shake|cat_duty [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|Equal1~5 ( +// Equation(s): +// \dpwm_shake|Equal1~5_combout = (\dpwm_shake|cnt [9] & (\dpwm_shake|new_duty [9] & (\dpwm_shake|cnt [8] $ (!\dpwm_shake|new_duty [8])))) # (!\dpwm_shake|cnt [9] & (!\dpwm_shake|new_duty [9] & (\dpwm_shake|cnt [8] $ (!\dpwm_shake|new_duty [8])))) + + .dataa(\dpwm_shake|cnt [9]), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|new_duty [8]), + .datad(\dpwm_shake|new_duty [9]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~5 .lut_mask = 16'h8241; +defparam \dpwm_shake|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|Equal1~6 ( +// Equation(s): +// \dpwm_shake|Equal1~6_combout = (\dpwm_shake|Equal1~4_combout & (\dpwm_shake|Equal1~5_combout & (\dpwm_shake|new_duty [10] $ (!\dpwm_shake|cnt [10])))) + + .dataa(\dpwm_shake|Equal1~4_combout ), + .datab(\dpwm_shake|new_duty [10]), + .datac(\dpwm_shake|Equal1~5_combout ), + .datad(\dpwm_shake|cnt [10]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~6 .lut_mask = 16'h8020; +defparam \dpwm_shake|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|tmp_q ( +// Equation(s): +// \dpwm_shake|tmp_q~combout = (\dpwm_shake|Equal0~0_combout & (\dpwm_shake|Equal0~2_combout & (\dpwm_shake|Equal0~1_combout & !\dpwm_shake|Equal1~6_combout ))) + + .dataa(\dpwm_shake|Equal0~0_combout ), + .datab(\dpwm_shake|Equal0~2_combout ), + .datac(\dpwm_shake|Equal0~1_combout ), + .datad(\dpwm_shake|Equal1~6_combout ), + .cin(gnd), + .combout(\dpwm_shake|tmp_q~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|tmp_q .lut_mask = 16'h0080; +defparam \dpwm_shake|tmp_q .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|pwm_out~2 ( +// Equation(s): +// \dpwm_shake|pwm_out~2_combout = (\dpwm_shake|Equal1~6_combout ) # ((\dpwm_shake|Equal0~1_combout & (\dpwm_shake|Equal0~0_combout & \dpwm_shake|Equal0~2_combout ))) + + .dataa(\dpwm_shake|Equal0~1_combout ), + .datab(\dpwm_shake|Equal0~0_combout ), + .datac(\dpwm_shake|Equal0~2_combout ), + .datad(\dpwm_shake|Equal1~6_combout ), + .cin(gnd), + .combout(\dpwm_shake|pwm_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|pwm_out~2 .lut_mask = 16'hFF80; +defparam \dpwm_shake|pwm_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|pwm_out ( +// Equation(s): +// \dpwm_shake|pwm_out~combout = (\dpwm_shake|pwm_out~2_combout & ((\dpwm_shake|tmp_q~combout ))) # (!\dpwm_shake|pwm_out~2_combout & (\dpwm_shake|pwm_out~combout )) + + .dataa(\dpwm_shake|pwm_out~combout ), + .datab(\dpwm_shake|tmp_q~combout ), + .datac(gnd), + .datad(\dpwm_shake|pwm_out~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|pwm_out~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|pwm_out .lut_mask = 16'hCCAA; +defparam \dpwm_shake|pwm_out .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_0c_slow.vo b/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..9d54ede --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_0c_slow.vo @@ -0,0 +1,2380 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" + +// DATE "12/08/2018 18:51:18" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module dpwm_top ( + clk, + rst_n, + control, + pwm_out, + pwm_out_n); +input clk; +input rst_n; +input [12:0] control; +output pwm_out; +output pwm_out_n; + +// Design Ports Information +// pwm_out => Location: PIN_K1, I/O Standard: 2.5 V, Current Strength: Default +// pwm_out_n => Location: PIN_L2, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// control[3] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// control[2] => Location: PIN_K6, I/O Standard: 2.5 V, Current Strength: Default +// control[5] => Location: PIN_L1, I/O Standard: 2.5 V, Current Strength: Default +// control[4] => Location: PIN_N2, I/O Standard: 2.5 V, Current Strength: Default +// control[7] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default +// control[6] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// control[9] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +// control[8] => Location: PIN_J6, I/O Standard: 2.5 V, Current Strength: Default +// control[11] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// control[10] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default +// control[12] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// control[0] => Location: PIN_L6, I/O Standard: 2.5 V, Current Strength: Default +// control[1] => Location: PIN_K2, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("dpwm_shake_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \clk~input_o ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \dpwm_shake|cnt[0]~30_combout ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_all~combout ; +wire \rst_all~clkctrl_outclk ; +wire \dpwm_shake|cnt[1]~10_combout ; +wire \dpwm_shake|cnt[1]~11 ; +wire \dpwm_shake|cnt[2]~12_combout ; +wire \dpwm_shake|cnt[2]~13 ; +wire \dpwm_shake|cnt[3]~14_combout ; +wire \dpwm_shake|Equal0~0_combout ; +wire \dpwm_shake|cnt[3]~15 ; +wire \dpwm_shake|cnt[4]~16_combout ; +wire \dpwm_shake|cnt[4]~17 ; +wire \dpwm_shake|cnt[5]~18_combout ; +wire \dpwm_shake|cnt[5]~19 ; +wire \dpwm_shake|cnt[6]~20_combout ; +wire \dpwm_shake|cnt[6]~21 ; +wire \dpwm_shake|cnt[7]~22_combout ; +wire \dpwm_shake|cnt[7]~23 ; +wire \dpwm_shake|cnt[8]~24_combout ; +wire \dpwm_shake|cnt[8]~25 ; +wire \dpwm_shake|cnt[9]~26_combout ; +wire \dpwm_shake|cnt[9]~27 ; +wire \dpwm_shake|cnt[10]~28_combout ; +wire \dpwm_shake|Equal0~2_combout ; +wire \dpwm_shake|Equal0~1_combout ; +wire \control[3]~input_o ; +wire \dpwm_shake|cat_duty~0_combout ; +wire \dpwm_shake|Equal2~0_combout ; +wire \dpwm_shake|Equal2~1_combout ; +wire \dpwm_shake|Equal2~2_combout ; +wire \dpwm_shake|shake_count[0]~1_combout ; +wire \dpwm_shake|shake_count[1]~0_combout ; +wire \control[2]~input_o ; +wire \dpwm_shake|cat_duty~1_combout ; +wire \control[1]~input_o ; +wire \dpwm_shake|shake_ctr~1_combout ; +wire \dpwm_shake|shakenum~2_combout ; +wire \dpwm_shake|Add2~2_combout ; +wire \control[0]~input_o ; +wire \dpwm_shake|shake_ctr~0_combout ; +wire \dpwm_shake|shakenum~0_combout ; +wire \dpwm_shake|Add2~0_combout ; +wire \dpwm_shake|shakenum~1_combout ; +wire \dpwm_shake|Add2~1_combout ; +wire \dpwm_shake|new_duty[0]~12 ; +wire \dpwm_shake|new_duty[1]~13_combout ; +wire \dpwm_shake|Add2~3_combout ; +wire \dpwm_shake|new_duty[0]~11_combout ; +wire \dpwm_shake|Equal1~0_combout ; +wire \control[9]~input_o ; +wire \dpwm_shake|cat_duty~6_combout ; +wire \control[8]~input_o ; +wire \dpwm_shake|cat_duty~7_combout ; +wire \control[7]~input_o ; +wire \dpwm_shake|cat_duty~4_combout ; +wire \control[6]~input_o ; +wire \dpwm_shake|cat_duty~5_combout ; +wire \control[5]~input_o ; +wire \dpwm_shake|cat_duty~2_combout ; +wire \control[4]~input_o ; +wire \dpwm_shake|cat_duty~3_combout ; +wire \dpwm_shake|new_duty[1]~14 ; +wire \dpwm_shake|new_duty[2]~16 ; +wire \dpwm_shake|new_duty[3]~18 ; +wire \dpwm_shake|new_duty[4]~20 ; +wire \dpwm_shake|new_duty[5]~22 ; +wire \dpwm_shake|new_duty[6]~24 ; +wire \dpwm_shake|new_duty[7]~25_combout ; +wire \dpwm_shake|new_duty[6]~23_combout ; +wire \dpwm_shake|Equal1~3_combout ; +wire \dpwm_shake|new_duty[4]~19_combout ; +wire \dpwm_shake|new_duty[5]~21_combout ; +wire \dpwm_shake|Equal1~2_combout ; +wire \dpwm_shake|new_duty[3]~17_combout ; +wire \dpwm_shake|new_duty[2]~15_combout ; +wire \dpwm_shake|Equal1~1_combout ; +wire \dpwm_shake|Equal1~4_combout ; +wire \control[12]~input_o ; +wire \dpwm_shake|cat_duty~10_combout ; +wire \control[11]~input_o ; +wire \dpwm_shake|cat_duty~8_combout ; +wire \control[10]~input_o ; +wire \dpwm_shake|cat_duty~9_combout ; +wire \dpwm_shake|new_duty[7]~26 ; +wire \dpwm_shake|new_duty[8]~28 ; +wire \dpwm_shake|new_duty[9]~30 ; +wire \dpwm_shake|new_duty[10]~31_combout ; +wire \dpwm_shake|new_duty[8]~27_combout ; +wire \dpwm_shake|new_duty[9]~29_combout ; +wire \dpwm_shake|Equal1~5_combout ; +wire \dpwm_shake|Equal1~6_combout ; +wire \dpwm_shake|tmp_q~combout ; +wire \dpwm_shake|pwm_out~2_combout ; +wire \dpwm_shake|pwm_out~combout ; +wire [10:0] \dpwm_shake|cnt ; +wire [10:0] \dpwm_shake|new_duty ; +wire [1:0] \dpwm_shake|shake_ctr ; +wire [4:0] \pwm_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [11:0] \dpwm_shake|cat_duty ; +wire [3:0] \dpwm_shake|shakenum ; +wire [1:0] \dpwm_shake|shake_count ; + +wire [4:0] \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X0_Y8_N9 +cycloneive_io_obuf \pwm_out~output ( + .i(\dpwm_shake|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out), + .obar()); +// synopsys translate_off +defparam \pwm_out~output .bus_hold = "false"; +defparam \pwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y8_N16 +cycloneive_io_obuf \pwm_out_n~output ( + .i(!\dpwm_shake|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out_n), + .obar()); +// synopsys translate_off +defparam \pwm_out_n~output .bus_hold = "false"; +defparam \pwm_out_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \pwm_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\pwm_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_high = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_low = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 10; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 49; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 19; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m = 49; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .n = 5; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "on"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 255; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneive_clkctrl \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\pwm_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|cnt[0]~30 ( +// Equation(s): +// \dpwm_shake|cnt[0]~30_combout = !\dpwm_shake|cnt [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm_shake|cnt [0]), + .cin(gnd), + .combout(\dpwm_shake|cnt[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cnt[0]~30 .lut_mask = 16'h00FF; +defparam \dpwm_shake|cnt[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y10_N4 +cycloneive_lcell_comb \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y10_N5 +dffeas \pwm_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N4 +cycloneive_lcell_comb rst_all( +// Equation(s): +// \rst_all~combout = (!\rst_n~input_o & ((!\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ))) + + .dataa(\rst_n~input_o ), + .datab(gnd), + .datac(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_all~combout ), + .cout()); +// synopsys translate_off +defparam rst_all.lut_mask = 16'h0555; +defparam rst_all.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \rst_all~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_all~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_all~clkctrl_outclk )); +// synopsys translate_off +defparam \rst_all~clkctrl .clock_type = "global clock"; +defparam \rst_all~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X1_Y11_N31 +dffeas \dpwm_shake|cnt[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\dpwm_shake|cnt[0]~30_combout ), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|cnt[1]~10 ( +// Equation(s): +// \dpwm_shake|cnt[1]~10_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] $ (VCC))) # (!\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] & VCC)) +// \dpwm_shake|cnt[1]~11 = CARRY((\dpwm_shake|cnt [1] & \dpwm_shake|cnt [0])) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm_shake|cnt[1]~10_combout ), + .cout(\dpwm_shake|cnt[1]~11 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[1]~10 .lut_mask = 16'h6688; +defparam \dpwm_shake|cnt[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y11_N11 +dffeas \dpwm_shake|cnt[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|cnt[2]~12 ( +// Equation(s): +// \dpwm_shake|cnt[2]~12_combout = (\dpwm_shake|cnt [2] & (!\dpwm_shake|cnt[1]~11 )) # (!\dpwm_shake|cnt [2] & ((\dpwm_shake|cnt[1]~11 ) # (GND))) +// \dpwm_shake|cnt[2]~13 = CARRY((!\dpwm_shake|cnt[1]~11 ) # (!\dpwm_shake|cnt [2])) + + .dataa(\dpwm_shake|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[1]~11 ), + .combout(\dpwm_shake|cnt[2]~12_combout ), + .cout(\dpwm_shake|cnt[2]~13 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[2]~12 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|cnt[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N13 +dffeas \dpwm_shake|cnt[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|cnt[3]~14 ( +// Equation(s): +// \dpwm_shake|cnt[3]~14_combout = (\dpwm_shake|cnt [3] & (\dpwm_shake|cnt[2]~13 $ (GND))) # (!\dpwm_shake|cnt [3] & (!\dpwm_shake|cnt[2]~13 & VCC)) +// \dpwm_shake|cnt[3]~15 = CARRY((\dpwm_shake|cnt [3] & !\dpwm_shake|cnt[2]~13 )) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[2]~13 ), + .combout(\dpwm_shake|cnt[3]~14_combout ), + .cout(\dpwm_shake|cnt[3]~15 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[3]~14 .lut_mask = 16'hC30C; +defparam \dpwm_shake|cnt[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N15 +dffeas \dpwm_shake|cnt[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|Equal0~0 ( +// Equation(s): +// \dpwm_shake|Equal0~0_combout = (!\dpwm_shake|cnt [1] & (!\dpwm_shake|cnt [3] & (!\dpwm_shake|cnt [0] & !\dpwm_shake|cnt [2]))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [3]), + .datac(\dpwm_shake|cnt [0]), + .datad(\dpwm_shake|cnt [2]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~0 .lut_mask = 16'h0001; +defparam \dpwm_shake|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|cnt[4]~16 ( +// Equation(s): +// \dpwm_shake|cnt[4]~16_combout = (\dpwm_shake|cnt [4] & (!\dpwm_shake|cnt[3]~15 )) # (!\dpwm_shake|cnt [4] & ((\dpwm_shake|cnt[3]~15 ) # (GND))) +// \dpwm_shake|cnt[4]~17 = CARRY((!\dpwm_shake|cnt[3]~15 ) # (!\dpwm_shake|cnt [4])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[3]~15 ), + .combout(\dpwm_shake|cnt[4]~16_combout ), + .cout(\dpwm_shake|cnt[4]~17 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[4]~16 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N17 +dffeas \dpwm_shake|cnt[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|cnt[5]~18 ( +// Equation(s): +// \dpwm_shake|cnt[5]~18_combout = (\dpwm_shake|cnt [5] & (\dpwm_shake|cnt[4]~17 $ (GND))) # (!\dpwm_shake|cnt [5] & (!\dpwm_shake|cnt[4]~17 & VCC)) +// \dpwm_shake|cnt[5]~19 = CARRY((\dpwm_shake|cnt [5] & !\dpwm_shake|cnt[4]~17 )) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[4]~17 ), + .combout(\dpwm_shake|cnt[5]~18_combout ), + .cout(\dpwm_shake|cnt[5]~19 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[5]~18 .lut_mask = 16'hC30C; +defparam \dpwm_shake|cnt[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N19 +dffeas \dpwm_shake|cnt[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|cnt[6]~20 ( +// Equation(s): +// \dpwm_shake|cnt[6]~20_combout = (\dpwm_shake|cnt [6] & (!\dpwm_shake|cnt[5]~19 )) # (!\dpwm_shake|cnt [6] & ((\dpwm_shake|cnt[5]~19 ) # (GND))) +// \dpwm_shake|cnt[6]~21 = CARRY((!\dpwm_shake|cnt[5]~19 ) # (!\dpwm_shake|cnt [6])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[5]~19 ), + .combout(\dpwm_shake|cnt[6]~20_combout ), + .cout(\dpwm_shake|cnt[6]~21 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[6]~20 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N21 +dffeas \dpwm_shake|cnt[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|cnt[7]~22 ( +// Equation(s): +// \dpwm_shake|cnt[7]~22_combout = (\dpwm_shake|cnt [7] & (\dpwm_shake|cnt[6]~21 $ (GND))) # (!\dpwm_shake|cnt [7] & (!\dpwm_shake|cnt[6]~21 & VCC)) +// \dpwm_shake|cnt[7]~23 = CARRY((\dpwm_shake|cnt [7] & !\dpwm_shake|cnt[6]~21 )) + + .dataa(\dpwm_shake|cnt [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[6]~21 ), + .combout(\dpwm_shake|cnt[7]~22_combout ), + .cout(\dpwm_shake|cnt[7]~23 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[7]~22 .lut_mask = 16'hA50A; +defparam \dpwm_shake|cnt[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N23 +dffeas \dpwm_shake|cnt[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|cnt[8]~24 ( +// Equation(s): +// \dpwm_shake|cnt[8]~24_combout = (\dpwm_shake|cnt [8] & (!\dpwm_shake|cnt[7]~23 )) # (!\dpwm_shake|cnt [8] & ((\dpwm_shake|cnt[7]~23 ) # (GND))) +// \dpwm_shake|cnt[8]~25 = CARRY((!\dpwm_shake|cnt[7]~23 ) # (!\dpwm_shake|cnt [8])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[7]~23 ), + .combout(\dpwm_shake|cnt[8]~24_combout ), + .cout(\dpwm_shake|cnt[8]~25 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[8]~24 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[8]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N25 +dffeas \dpwm_shake|cnt[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[8]~24_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cnt[9]~26 ( +// Equation(s): +// \dpwm_shake|cnt[9]~26_combout = (\dpwm_shake|cnt [9] & (\dpwm_shake|cnt[8]~25 $ (GND))) # (!\dpwm_shake|cnt [9] & (!\dpwm_shake|cnt[8]~25 & VCC)) +// \dpwm_shake|cnt[9]~27 = CARRY((\dpwm_shake|cnt [9] & !\dpwm_shake|cnt[8]~25 )) + + .dataa(\dpwm_shake|cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[8]~25 ), + .combout(\dpwm_shake|cnt[9]~26_combout ), + .cout(\dpwm_shake|cnt[9]~27 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[9]~26 .lut_mask = 16'hA50A; +defparam \dpwm_shake|cnt[9]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N27 +dffeas \dpwm_shake|cnt[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[9]~26_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|cnt[10]~28 ( +// Equation(s): +// \dpwm_shake|cnt[10]~28_combout = \dpwm_shake|cnt[9]~27 $ (\dpwm_shake|cnt [10]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm_shake|cnt [10]), + .cin(\dpwm_shake|cnt[9]~27 ), + .combout(\dpwm_shake|cnt[10]~28_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cnt[10]~28 .lut_mask = 16'h0FF0; +defparam \dpwm_shake|cnt[10]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N29 +dffeas \dpwm_shake|cnt[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[10]~28_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|Equal0~2 ( +// Equation(s): +// \dpwm_shake|Equal0~2_combout = (!\dpwm_shake|cnt [8] & (!\dpwm_shake|cnt [9] & !\dpwm_shake|cnt [10])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|cnt [9]), + .datad(\dpwm_shake|cnt [10]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~2 .lut_mask = 16'h0003; +defparam \dpwm_shake|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|Equal0~1 ( +// Equation(s): +// \dpwm_shake|Equal0~1_combout = (!\dpwm_shake|cnt [7] & (!\dpwm_shake|cnt [4] & (!\dpwm_shake|cnt [6] & !\dpwm_shake|cnt [5]))) + + .dataa(\dpwm_shake|cnt [7]), + .datab(\dpwm_shake|cnt [4]), + .datac(\dpwm_shake|cnt [6]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~1 .lut_mask = 16'h0001; +defparam \dpwm_shake|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \control[3]~input ( + .i(control[3]), + .ibar(gnd), + .o(\control[3]~input_o )); +// synopsys translate_off +defparam \control[3]~input .bus_hold = "false"; +defparam \control[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|cat_duty~0 ( +// Equation(s): +// \dpwm_shake|cat_duty~0_combout = (\control[3]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[3]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~0 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N31 +dffeas \dpwm_shake|cat_duty[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|Equal2~0 ( +// Equation(s): +// \dpwm_shake|Equal2~0_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] & (\dpwm_shake|cnt [3] & \dpwm_shake|cnt [2]))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(\dpwm_shake|cnt [3]), + .datad(\dpwm_shake|cnt [2]), + .cin(gnd), + .combout(\dpwm_shake|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~0 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|Equal2~1 ( +// Equation(s): +// \dpwm_shake|Equal2~1_combout = (\dpwm_shake|cnt [4] & (\dpwm_shake|cnt [6] & (\dpwm_shake|cnt [7] & \dpwm_shake|cnt [5]))) + + .dataa(\dpwm_shake|cnt [4]), + .datab(\dpwm_shake|cnt [6]), + .datac(\dpwm_shake|cnt [7]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~1 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|Equal2~2 ( +// Equation(s): +// \dpwm_shake|Equal2~2_combout = (\dpwm_shake|cnt [10] & (\dpwm_shake|cnt [8] & (\dpwm_shake|cnt [9] & \dpwm_shake|Equal2~1_combout ))) + + .dataa(\dpwm_shake|cnt [10]), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|cnt [9]), + .datad(\dpwm_shake|Equal2~1_combout ), + .cin(gnd), + .combout(\dpwm_shake|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~2 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|shake_count[0]~1 ( +// Equation(s): +// \dpwm_shake|shake_count[0]~1_combout = \dpwm_shake|shake_count [0] $ (((\dpwm_shake|Equal2~0_combout & \dpwm_shake|Equal2~2_combout ))) + + .dataa(\dpwm_shake|Equal2~0_combout ), + .datab(gnd), + .datac(\dpwm_shake|shake_count [0]), + .datad(\dpwm_shake|Equal2~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|shake_count[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_count[0]~1 .lut_mask = 16'h5AF0; +defparam \dpwm_shake|shake_count[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N17 +dffeas \dpwm_shake|shake_count[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_count[0]~1_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_count[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|shake_count[1]~0 ( +// Equation(s): +// \dpwm_shake|shake_count[1]~0_combout = \dpwm_shake|shake_count [1] $ (((\dpwm_shake|Equal2~0_combout & (\dpwm_shake|shake_count [0] & \dpwm_shake|Equal2~2_combout )))) + + .dataa(\dpwm_shake|Equal2~0_combout ), + .datab(\dpwm_shake|shake_count [0]), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|Equal2~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|shake_count[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_count[1]~0 .lut_mask = 16'h78F0; +defparam \dpwm_shake|shake_count[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N15 +dffeas \dpwm_shake|shake_count[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_count[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_count[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y9_N1 +cycloneive_io_ibuf \control[2]~input ( + .i(control[2]), + .ibar(gnd), + .o(\control[2]~input_o )); +// synopsys translate_off +defparam \control[2]~input .bus_hold = "false"; +defparam \control[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|cat_duty~1 ( +// Equation(s): +// \dpwm_shake|cat_duty~1_combout = (\control[2]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\control[2]~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~1 .lut_mask = 16'hA8A0; +defparam \dpwm_shake|cat_duty~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N31 +dffeas \dpwm_shake|cat_duty[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \control[1]~input ( + .i(control[1]), + .ibar(gnd), + .o(\control[1]~input_o )); +// synopsys translate_off +defparam \control[1]~input .bus_hold = "false"; +defparam \control[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|shake_ctr~1 ( +// Equation(s): +// \dpwm_shake|shake_ctr~1_combout = (\control[1]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\control[1]~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shake_ctr~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr~1 .lut_mask = 16'hE0A0; +defparam \dpwm_shake|shake_ctr~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N29 +dffeas \dpwm_shake|shake_ctr[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_ctr~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_ctr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_ctr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|shakenum~2 ( +// Equation(s): +// \dpwm_shake|shakenum~2_combout = (\dpwm_shake|shake_ctr [1] & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shakenum~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~2 .lut_mask = 16'hC888; +defparam \dpwm_shake|shakenum~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N25 +dffeas \dpwm_shake|shakenum[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|Add2~2 ( +// Equation(s): +// \dpwm_shake|Add2~2_combout = (\dpwm_shake|shake_count [1] & ((\dpwm_shake|shakenum [2]))) # (!\dpwm_shake|shake_count [1] & (\dpwm_shake|cat_duty [0])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_count [1]), + .datac(\dpwm_shake|cat_duty [0]), + .datad(\dpwm_shake|shakenum [2]), + .cin(gnd), + .combout(\dpwm_shake|Add2~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~2 .lut_mask = 16'hFC30; +defparam \dpwm_shake|Add2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y9_N8 +cycloneive_io_ibuf \control[0]~input ( + .i(control[0]), + .ibar(gnd), + .o(\control[0]~input_o )); +// synopsys translate_off +defparam \control[0]~input .bus_hold = "false"; +defparam \control[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|shake_ctr~0 ( +// Equation(s): +// \dpwm_shake|shake_ctr~0_combout = (\control[0]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\control[0]~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shake_ctr~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr~0 .lut_mask = 16'hE0A0; +defparam \dpwm_shake|shake_ctr~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N7 +dffeas \dpwm_shake|shake_ctr[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_ctr~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_ctr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_ctr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|shakenum~0 ( +// Equation(s): +// \dpwm_shake|shakenum~0_combout = (!\rst_all~combout & ((\dpwm_shake|shake_ctr [1]) # (\dpwm_shake|shake_ctr [0]))) + + .dataa(gnd), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\rst_all~combout ), + .datad(\dpwm_shake|shake_ctr [0]), + .cin(gnd), + .combout(\dpwm_shake|shakenum~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~0 .lut_mask = 16'h0F0C; +defparam \dpwm_shake|shakenum~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N9 +dffeas \dpwm_shake|shakenum[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|Add2~0 ( +// Equation(s): +// \dpwm_shake|Add2~0_combout = (!\dpwm_shake|shake_count [0] & ((\dpwm_shake|shake_count [1] & (\dpwm_shake|cat_duty [0])) # (!\dpwm_shake|shake_count [1] & ((\dpwm_shake|shakenum [0]))))) + + .dataa(\dpwm_shake|cat_duty [0]), + .datab(\dpwm_shake|shakenum [0]), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|shake_count [0]), + .cin(gnd), + .combout(\dpwm_shake|Add2~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~0 .lut_mask = 16'h00AC; +defparam \dpwm_shake|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|shakenum~1 ( +// Equation(s): +// \dpwm_shake|shakenum~1_combout = (\dpwm_shake|shake_ctr [1] & (!\rst_all~combout & \dpwm_shake|shake_ctr [0])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\rst_all~combout ), + .datad(\dpwm_shake|shake_ctr [0]), + .cin(gnd), + .combout(\dpwm_shake|shakenum~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~1 .lut_mask = 16'h0C00; +defparam \dpwm_shake|shakenum~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N21 +dffeas \dpwm_shake|shakenum[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|Add2~1 ( +// Equation(s): +// \dpwm_shake|Add2~1_combout = (\dpwm_shake|Add2~0_combout ) # ((\dpwm_shake|shake_count [0] & \dpwm_shake|shakenum [1])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_count [0]), + .datac(\dpwm_shake|Add2~0_combout ), + .datad(\dpwm_shake|shakenum [1]), + .cin(gnd), + .combout(\dpwm_shake|Add2~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~1 .lut_mask = 16'hFCF0; +defparam \dpwm_shake|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|new_duty[0]~11 ( +// Equation(s): +// \dpwm_shake|new_duty[0]~11_combout = (\dpwm_shake|Add2~2_combout & (\dpwm_shake|Add2~1_combout $ (VCC))) # (!\dpwm_shake|Add2~2_combout & (\dpwm_shake|Add2~1_combout & VCC)) +// \dpwm_shake|new_duty[0]~12 = CARRY((\dpwm_shake|Add2~2_combout & \dpwm_shake|Add2~1_combout )) + + .dataa(\dpwm_shake|Add2~2_combout ), + .datab(\dpwm_shake|Add2~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm_shake|new_duty[0]~11_combout ), + .cout(\dpwm_shake|new_duty[0]~12 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[0]~11 .lut_mask = 16'h6688; +defparam \dpwm_shake|new_duty[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|new_duty[1]~13 ( +// Equation(s): +// \dpwm_shake|new_duty[1]~13_combout = (\dpwm_shake|cat_duty [1] & (!\dpwm_shake|new_duty[0]~12 )) # (!\dpwm_shake|cat_duty [1] & ((\dpwm_shake|new_duty[0]~12 ) # (GND))) +// \dpwm_shake|new_duty[1]~14 = CARRY((!\dpwm_shake|new_duty[0]~12 ) # (!\dpwm_shake|cat_duty [1])) + + .dataa(\dpwm_shake|cat_duty [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[0]~12 ), + .combout(\dpwm_shake|new_duty[1]~13_combout ), + .cout(\dpwm_shake|new_duty[1]~14 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[1]~13 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[1]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|Add2~3 ( +// Equation(s): +// \dpwm_shake|Add2~3_combout = (\dpwm_shake|shake_count [1] & \dpwm_shake|shake_count [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|shake_count [0]), + .cin(gnd), + .combout(\dpwm_shake|Add2~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~3 .lut_mask = 16'hF000; +defparam \dpwm_shake|Add2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N7 +dffeas \dpwm_shake|new_duty[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[1]~13_combout ), + .asdata(\dpwm_shake|cat_duty [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N5 +dffeas \dpwm_shake|new_duty[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[0]~11_combout ), + .asdata(\dpwm_shake|cat_duty [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|Equal1~0 ( +// Equation(s): +// \dpwm_shake|Equal1~0_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|new_duty [1] & (\dpwm_shake|cnt [0] $ (!\dpwm_shake|new_duty [0])))) # (!\dpwm_shake|cnt [1] & (!\dpwm_shake|new_duty [1] & (\dpwm_shake|cnt [0] $ (!\dpwm_shake|new_duty [0])))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(\dpwm_shake|new_duty [1]), + .datad(\dpwm_shake|new_duty [0]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~0 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N22 +cycloneive_io_ibuf \control[9]~input ( + .i(control[9]), + .ibar(gnd), + .o(\control[9]~input_o )); +// synopsys translate_off +defparam \control[9]~input .bus_hold = "false"; +defparam \control[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|cat_duty~6 ( +// Equation(s): +// \dpwm_shake|cat_duty~6_combout = (\control[9]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[9]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~6_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~6 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N3 +dffeas \dpwm_shake|cat_duty[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N22 +cycloneive_io_ibuf \control[8]~input ( + .i(control[8]), + .ibar(gnd), + .o(\control[8]~input_o )); +// synopsys translate_off +defparam \control[8]~input .bus_hold = "false"; +defparam \control[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|cat_duty~7 ( +// Equation(s): +// \dpwm_shake|cat_duty~7_combout = (\control[8]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[8]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~7_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~7 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N1 +dffeas \dpwm_shake|cat_duty[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[6] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N1 +cycloneive_io_ibuf \control[7]~input ( + .i(control[7]), + .ibar(gnd), + .o(\control[7]~input_o )); +// synopsys translate_off +defparam \control[7]~input .bus_hold = "false"; +defparam \control[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cat_duty~4 ( +// Equation(s): +// \dpwm_shake|cat_duty~4_combout = (\control[7]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[7]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~4_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~4 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N27 +dffeas \dpwm_shake|cat_duty[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \control[6]~input ( + .i(control[6]), + .ibar(gnd), + .o(\control[6]~input_o )); +// synopsys translate_off +defparam \control[6]~input .bus_hold = "false"; +defparam \control[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|cat_duty~5 ( +// Equation(s): +// \dpwm_shake|cat_duty~5_combout = (\control[6]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[6]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~5_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~5 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N29 +dffeas \dpwm_shake|cat_duty[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[4] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N22 +cycloneive_io_ibuf \control[5]~input ( + .i(control[5]), + .ibar(gnd), + .o(\control[5]~input_o )); +// synopsys translate_off +defparam \control[5]~input .bus_hold = "false"; +defparam \control[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|cat_duty~2 ( +// Equation(s): +// \dpwm_shake|cat_duty~2_combout = (\control[5]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[5]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~2 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N17 +dffeas \dpwm_shake|cat_duty[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[3] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N15 +cycloneive_io_ibuf \control[4]~input ( + .i(control[4]), + .ibar(gnd), + .o(\control[4]~input_o )); +// synopsys translate_off +defparam \control[4]~input .bus_hold = "false"; +defparam \control[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|cat_duty~3 ( +// Equation(s): +// \dpwm_shake|cat_duty~3_combout = (\control[4]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[4]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~3 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N7 +dffeas \dpwm_shake|cat_duty[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|new_duty[2]~15 ( +// Equation(s): +// \dpwm_shake|new_duty[2]~15_combout = (\dpwm_shake|cat_duty [2] & (\dpwm_shake|new_duty[1]~14 $ (GND))) # (!\dpwm_shake|cat_duty [2] & (!\dpwm_shake|new_duty[1]~14 & VCC)) +// \dpwm_shake|new_duty[2]~16 = CARRY((\dpwm_shake|cat_duty [2] & !\dpwm_shake|new_duty[1]~14 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [2]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[1]~14 ), + .combout(\dpwm_shake|new_duty[2]~15_combout ), + .cout(\dpwm_shake|new_duty[2]~16 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[2]~15 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[2]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|new_duty[3]~17 ( +// Equation(s): +// \dpwm_shake|new_duty[3]~17_combout = (\dpwm_shake|cat_duty [3] & (!\dpwm_shake|new_duty[2]~16 )) # (!\dpwm_shake|cat_duty [3] & ((\dpwm_shake|new_duty[2]~16 ) # (GND))) +// \dpwm_shake|new_duty[3]~18 = CARRY((!\dpwm_shake|new_duty[2]~16 ) # (!\dpwm_shake|cat_duty [3])) + + .dataa(\dpwm_shake|cat_duty [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[2]~16 ), + .combout(\dpwm_shake|new_duty[3]~17_combout ), + .cout(\dpwm_shake|new_duty[3]~18 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[3]~17 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|new_duty[4]~19 ( +// Equation(s): +// \dpwm_shake|new_duty[4]~19_combout = (\dpwm_shake|cat_duty [4] & (\dpwm_shake|new_duty[3]~18 $ (GND))) # (!\dpwm_shake|cat_duty [4] & (!\dpwm_shake|new_duty[3]~18 & VCC)) +// \dpwm_shake|new_duty[4]~20 = CARRY((\dpwm_shake|cat_duty [4] & !\dpwm_shake|new_duty[3]~18 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[3]~18 ), + .combout(\dpwm_shake|new_duty[4]~19_combout ), + .cout(\dpwm_shake|new_duty[4]~20 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[4]~19 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|new_duty[5]~21 ( +// Equation(s): +// \dpwm_shake|new_duty[5]~21_combout = (\dpwm_shake|cat_duty [5] & (!\dpwm_shake|new_duty[4]~20 )) # (!\dpwm_shake|cat_duty [5] & ((\dpwm_shake|new_duty[4]~20 ) # (GND))) +// \dpwm_shake|new_duty[5]~22 = CARRY((!\dpwm_shake|new_duty[4]~20 ) # (!\dpwm_shake|cat_duty [5])) + + .dataa(\dpwm_shake|cat_duty [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[4]~20 ), + .combout(\dpwm_shake|new_duty[5]~21_combout ), + .cout(\dpwm_shake|new_duty[5]~22 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[5]~21 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|new_duty[6]~23 ( +// Equation(s): +// \dpwm_shake|new_duty[6]~23_combout = (\dpwm_shake|cat_duty [6] & (\dpwm_shake|new_duty[5]~22 $ (GND))) # (!\dpwm_shake|cat_duty [6] & (!\dpwm_shake|new_duty[5]~22 & VCC)) +// \dpwm_shake|new_duty[6]~24 = CARRY((\dpwm_shake|cat_duty [6] & !\dpwm_shake|new_duty[5]~22 )) + + .dataa(\dpwm_shake|cat_duty [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[5]~22 ), + .combout(\dpwm_shake|new_duty[6]~23_combout ), + .cout(\dpwm_shake|new_duty[6]~24 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[6]~23 .lut_mask = 16'hA50A; +defparam \dpwm_shake|new_duty[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|new_duty[7]~25 ( +// Equation(s): +// \dpwm_shake|new_duty[7]~25_combout = (\dpwm_shake|cat_duty [7] & (!\dpwm_shake|new_duty[6]~24 )) # (!\dpwm_shake|cat_duty [7] & ((\dpwm_shake|new_duty[6]~24 ) # (GND))) +// \dpwm_shake|new_duty[7]~26 = CARRY((!\dpwm_shake|new_duty[6]~24 ) # (!\dpwm_shake|cat_duty [7])) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [7]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[6]~24 ), + .combout(\dpwm_shake|new_duty[7]~25_combout ), + .cout(\dpwm_shake|new_duty[7]~26 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[7]~25 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|new_duty[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y11_N19 +dffeas \dpwm_shake|new_duty[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[7]~25_combout ), + .asdata(\dpwm_shake|cat_duty [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N17 +dffeas \dpwm_shake|new_duty[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[6]~23_combout ), + .asdata(\dpwm_shake|cat_duty [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|Equal1~3 ( +// Equation(s): +// \dpwm_shake|Equal1~3_combout = (\dpwm_shake|new_duty [7] & (\dpwm_shake|cnt [7] & (\dpwm_shake|cnt [6] $ (!\dpwm_shake|new_duty [6])))) # (!\dpwm_shake|new_duty [7] & (!\dpwm_shake|cnt [7] & (\dpwm_shake|cnt [6] $ (!\dpwm_shake|new_duty [6])))) + + .dataa(\dpwm_shake|new_duty [7]), + .datab(\dpwm_shake|cnt [6]), + .datac(\dpwm_shake|cnt [7]), + .datad(\dpwm_shake|new_duty [6]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~3 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N13 +dffeas \dpwm_shake|new_duty[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[4]~19_combout ), + .asdata(\dpwm_shake|cat_duty [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N15 +dffeas \dpwm_shake|new_duty[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[5]~21_combout ), + .asdata(\dpwm_shake|cat_duty [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|Equal1~2 ( +// Equation(s): +// \dpwm_shake|Equal1~2_combout = (\dpwm_shake|cnt [4] & (\dpwm_shake|new_duty [4] & (\dpwm_shake|new_duty [5] $ (!\dpwm_shake|cnt [5])))) # (!\dpwm_shake|cnt [4] & (!\dpwm_shake|new_duty [4] & (\dpwm_shake|new_duty [5] $ (!\dpwm_shake|cnt [5])))) + + .dataa(\dpwm_shake|cnt [4]), + .datab(\dpwm_shake|new_duty [4]), + .datac(\dpwm_shake|new_duty [5]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~2 .lut_mask = 16'h9009; +defparam \dpwm_shake|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N11 +dffeas \dpwm_shake|new_duty[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[3]~17_combout ), + .asdata(\dpwm_shake|cat_duty [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N9 +dffeas \dpwm_shake|new_duty[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[2]~15_combout ), + .asdata(\dpwm_shake|cat_duty [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|Equal1~1 ( +// Equation(s): +// \dpwm_shake|Equal1~1_combout = (\dpwm_shake|cnt [2] & (\dpwm_shake|new_duty [2] & (\dpwm_shake|new_duty [3] $ (!\dpwm_shake|cnt [3])))) # (!\dpwm_shake|cnt [2] & (!\dpwm_shake|new_duty [2] & (\dpwm_shake|new_duty [3] $ (!\dpwm_shake|cnt [3])))) + + .dataa(\dpwm_shake|cnt [2]), + .datab(\dpwm_shake|new_duty [3]), + .datac(\dpwm_shake|new_duty [2]), + .datad(\dpwm_shake|cnt [3]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~1 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|Equal1~4 ( +// Equation(s): +// \dpwm_shake|Equal1~4_combout = (\dpwm_shake|Equal1~0_combout & (\dpwm_shake|Equal1~3_combout & (\dpwm_shake|Equal1~2_combout & \dpwm_shake|Equal1~1_combout ))) + + .dataa(\dpwm_shake|Equal1~0_combout ), + .datab(\dpwm_shake|Equal1~3_combout ), + .datac(\dpwm_shake|Equal1~2_combout ), + .datad(\dpwm_shake|Equal1~1_combout ), + .cin(gnd), + .combout(\dpwm_shake|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~4 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N1 +cycloneive_io_ibuf \control[12]~input ( + .i(control[12]), + .ibar(gnd), + .o(\control[12]~input_o )); +// synopsys translate_off +defparam \control[12]~input .bus_hold = "false"; +defparam \control[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|cat_duty~10 ( +// Equation(s): +// \dpwm_shake|cat_duty~10_combout = (\control[12]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[12]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~10_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~10 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N5 +dffeas \dpwm_shake|cat_duty[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N15 +cycloneive_io_ibuf \control[11]~input ( + .i(control[11]), + .ibar(gnd), + .o(\control[11]~input_o )); +// synopsys translate_off +defparam \control[11]~input .bus_hold = "false"; +defparam \control[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cat_duty~8 ( +// Equation(s): +// \dpwm_shake|cat_duty~8_combout = (\control[11]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[11]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~8_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~8 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N27 +dffeas \dpwm_shake|cat_duty[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[9] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y6_N22 +cycloneive_io_ibuf \control[10]~input ( + .i(control[10]), + .ibar(gnd), + .o(\control[10]~input_o )); +// synopsys translate_off +defparam \control[10]~input .bus_hold = "false"; +defparam \control[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|cat_duty~9 ( +// Equation(s): +// \dpwm_shake|cat_duty~9_combout = (\control[10]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[10]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~9_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~9 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N1 +dffeas \dpwm_shake|cat_duty[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|new_duty[8]~27 ( +// Equation(s): +// \dpwm_shake|new_duty[8]~27_combout = (\dpwm_shake|cat_duty [8] & (\dpwm_shake|new_duty[7]~26 $ (GND))) # (!\dpwm_shake|cat_duty [8] & (!\dpwm_shake|new_duty[7]~26 & VCC)) +// \dpwm_shake|new_duty[8]~28 = CARRY((\dpwm_shake|cat_duty [8] & !\dpwm_shake|new_duty[7]~26 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [8]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[7]~26 ), + .combout(\dpwm_shake|new_duty[8]~27_combout ), + .cout(\dpwm_shake|new_duty[8]~28 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[8]~27 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|new_duty[9]~29 ( +// Equation(s): +// \dpwm_shake|new_duty[9]~29_combout = (\dpwm_shake|cat_duty [9] & (!\dpwm_shake|new_duty[8]~28 )) # (!\dpwm_shake|cat_duty [9] & ((\dpwm_shake|new_duty[8]~28 ) # (GND))) +// \dpwm_shake|new_duty[9]~30 = CARRY((!\dpwm_shake|new_duty[8]~28 ) # (!\dpwm_shake|cat_duty [9])) + + .dataa(\dpwm_shake|cat_duty [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[8]~28 ), + .combout(\dpwm_shake|new_duty[9]~29_combout ), + .cout(\dpwm_shake|new_duty[9]~30 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[9]~29 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|new_duty[10]~31 ( +// Equation(s): +// \dpwm_shake|new_duty[10]~31_combout = \dpwm_shake|cat_duty [10] $ (!\dpwm_shake|new_duty[9]~30 ) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [10]), + .datac(gnd), + .datad(gnd), + .cin(\dpwm_shake|new_duty[9]~30 ), + .combout(\dpwm_shake|new_duty[10]~31_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|new_duty[10]~31 .lut_mask = 16'hC3C3; +defparam \dpwm_shake|new_duty[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y11_N25 +dffeas \dpwm_shake|new_duty[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[10]~31_combout ), + .asdata(\dpwm_shake|cat_duty [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N21 +dffeas \dpwm_shake|new_duty[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[8]~27_combout ), + .asdata(\dpwm_shake|cat_duty [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N23 +dffeas \dpwm_shake|new_duty[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[9]~29_combout ), + .asdata(\dpwm_shake|cat_duty [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|Equal1~5 ( +// Equation(s): +// \dpwm_shake|Equal1~5_combout = (\dpwm_shake|cnt [9] & (\dpwm_shake|new_duty [9] & (\dpwm_shake|cnt [8] $ (!\dpwm_shake|new_duty [8])))) # (!\dpwm_shake|cnt [9] & (!\dpwm_shake|new_duty [9] & (\dpwm_shake|cnt [8] $ (!\dpwm_shake|new_duty [8])))) + + .dataa(\dpwm_shake|cnt [9]), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|new_duty [8]), + .datad(\dpwm_shake|new_duty [9]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~5 .lut_mask = 16'h8241; +defparam \dpwm_shake|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|Equal1~6 ( +// Equation(s): +// \dpwm_shake|Equal1~6_combout = (\dpwm_shake|Equal1~4_combout & (\dpwm_shake|Equal1~5_combout & (\dpwm_shake|new_duty [10] $ (!\dpwm_shake|cnt [10])))) + + .dataa(\dpwm_shake|Equal1~4_combout ), + .datab(\dpwm_shake|new_duty [10]), + .datac(\dpwm_shake|Equal1~5_combout ), + .datad(\dpwm_shake|cnt [10]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~6 .lut_mask = 16'h8020; +defparam \dpwm_shake|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|tmp_q ( +// Equation(s): +// \dpwm_shake|tmp_q~combout = (\dpwm_shake|Equal0~0_combout & (\dpwm_shake|Equal0~2_combout & (\dpwm_shake|Equal0~1_combout & !\dpwm_shake|Equal1~6_combout ))) + + .dataa(\dpwm_shake|Equal0~0_combout ), + .datab(\dpwm_shake|Equal0~2_combout ), + .datac(\dpwm_shake|Equal0~1_combout ), + .datad(\dpwm_shake|Equal1~6_combout ), + .cin(gnd), + .combout(\dpwm_shake|tmp_q~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|tmp_q .lut_mask = 16'h0080; +defparam \dpwm_shake|tmp_q .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|pwm_out~2 ( +// Equation(s): +// \dpwm_shake|pwm_out~2_combout = (\dpwm_shake|Equal1~6_combout ) # ((\dpwm_shake|Equal0~1_combout & (\dpwm_shake|Equal0~0_combout & \dpwm_shake|Equal0~2_combout ))) + + .dataa(\dpwm_shake|Equal0~1_combout ), + .datab(\dpwm_shake|Equal0~0_combout ), + .datac(\dpwm_shake|Equal0~2_combout ), + .datad(\dpwm_shake|Equal1~6_combout ), + .cin(gnd), + .combout(\dpwm_shake|pwm_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|pwm_out~2 .lut_mask = 16'hFF80; +defparam \dpwm_shake|pwm_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|pwm_out ( +// Equation(s): +// \dpwm_shake|pwm_out~combout = (\dpwm_shake|pwm_out~2_combout & ((\dpwm_shake|tmp_q~combout ))) # (!\dpwm_shake|pwm_out~2_combout & (\dpwm_shake|pwm_out~combout )) + + .dataa(\dpwm_shake|pwm_out~combout ), + .datab(\dpwm_shake|tmp_q~combout ), + .datac(gnd), + .datad(\dpwm_shake|pwm_out~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|pwm_out~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|pwm_out .lut_mask = 16'hCCAA; +defparam \dpwm_shake|pwm_out .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_0c_v_slow.sdo b/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..eee8e2c --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,1779 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "dpwm_top") + (DATE "12/08/2018 18:51:18") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (809:809:809) (701:701:701)) + (IOPATH i o (2800:2800:2800) (2762:2762:2762)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out_n\~output) + (DELAY + (ABSOLUTE + (PORT i (701:701:701) (809:809:809)) + (IOPATH i o (2762:2762:2762) (2800:2800:2800)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (758:758:758) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (194:194:194) (190:190:190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (1198:1198:1198) (1198:1198:1198)) + (PORT inclk[0] (2058:2058:2058) (2058:2058:2058)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2046:2046:2046) (2011:2011:2011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT datad (529:529:529) (512:512:512)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2044:2044:2044) (2348:2348:2348)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1526:1526:1526) (1456:1456:1456)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_all) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (843:843:843)) + (PORT datac (1679:1679:1679) (2018:2018:2018)) + (PORT datad (825:825:825) (741:741:741)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_all\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (975:975:975) (878:878:878)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT asdata (865:865:865) (808:808:808)) + (PORT clrn (1498:1498:1498) (1471:1471:1471)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (415:415:415)) + (PORT datab (1383:1383:1383) (1119:1119:1119)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1931:1931:1931) (1925:1925:1925)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1471:1471:1471)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (412:412:412)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1471:1471:1471)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (407:407:407)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1471:1471:1471)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (413:413:413)) + (PORT datab (346:346:346) (404:404:404)) + (PORT datac (297:297:297) (361:361:361)) + (PORT datad (306:306:306) (367:367:367)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (371:371:371) (429:429:429)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1471:1471:1471)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (355:355:355) (415:415:415)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1471:1471:1471)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (371:371:371) (429:429:429)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1471:1471:1471)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (426:426:426)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1471:1471:1471)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[8\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (405:405:405)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1931:1931:1931) (1925:1925:1925)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1471:1471:1471)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[9\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (411:411:411)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1471:1471:1471)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[10\]\~28) + (DELAY + (ABSOLUTE + (PORT datad (532:532:532) (513:513:513)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1471:1471:1471)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (405:405:405)) + (PORT datac (307:307:307) (374:374:374)) + (PORT datad (322:322:322) (378:378:378)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (426:426:426)) + (PORT datab (370:370:370) (427:427:427)) + (PORT datac (534:534:534) (517:517:517)) + (PORT datad (314:314:314) (377:377:377)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (758:758:758) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1507:1507:1507) (1768:1768:1768)) + (PORT datab (606:606:606) (788:788:788)) + (PORT datac (621:621:621) (789:789:789)) + (PORT datad (853:853:853) (772:772:772)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1893:1893:1893) (1890:1890:1890)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (574:574:574)) + (PORT datab (567:567:567) (548:548:548)) + (PORT datac (768:768:768) (694:694:694)) + (PORT datad (548:548:548) (519:519:519)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (557:557:557)) + (PORT datab (373:373:373) (431:431:431)) + (PORT datac (318:318:318) (390:390:390)) + (PORT datad (316:316:316) (378:378:378)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (782:782:782)) + (PORT datab (610:610:610) (562:562:562)) + (PORT datac (560:560:560) (528:528:528)) + (PORT datad (463:463:463) (382:382:382)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_count\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (623:623:623)) + (PORT datad (697:697:697) (573:573:573)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1503:1503:1503)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1470:1470:1470)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_count\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (624:624:624)) + (PORT datab (344:344:344) (407:407:407)) + (PORT datad (697:697:697) (573:573:573)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1503:1503:1503)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1498:1498:1498) (1470:1470:1470)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (708:708:708) (733:733:733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~1) + (DELAY + (ABSOLUTE + (PORT dataa (3281:3281:3281) (3282:3282:3282)) + (PORT datab (1720:1720:1720) (2069:2069:2069)) + (PORT datac (633:633:633) (795:795:795)) + (PORT datad (835:835:835) (752:752:752)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1503:1503:1503)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_ctr\~1) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (841:841:841)) + (PORT datab (1719:1719:1719) (2068:2068:2068)) + (PORT datac (3260:3260:3260) (3322:3322:3322)) + (PORT datad (834:834:834) (751:751:751)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_ctr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1923:1923:1923)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~2) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (842:842:842)) + (PORT datab (335:335:335) (396:396:396)) + (PORT datac (1683:1683:1683) (2022:2022:2022)) + (PORT datad (833:833:833) (749:749:749)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1503:1503:1503)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~2) + (DELAY + (ABSOLUTE + (PORT datab (333:333:333) (393:393:393)) + (PORT datac (309:309:309) (377:377:377)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_ctr\~0) + (DELAY + (ABSOLUTE + (PORT dataa (677:677:677) (843:843:843)) + (PORT datab (1714:1714:1714) (2064:2064:2064)) + (PORT datac (3170:3170:3170) (3210:3210:3210)) + (PORT datad (828:828:828) (743:743:743)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_ctr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1930:1930:1930) (1923:1923:1923)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~0) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (399:399:399)) + (PORT datac (256:256:256) (275:275:275)) + (PORT datad (284:284:284) (343:343:343)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1503:1503:1503)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (409:409:409)) + (PORT datab (318:318:318) (373:373:373)) + (PORT datac (291:291:291) (360:360:360)) + (PORT datad (299:299:299) (364:364:364)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~1) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (397:397:397)) + (PORT datac (258:258:258) (277:277:277)) + (PORT datad (286:286:286) (344:344:344)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1503:1503:1503)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (404:404:404)) + (PORT datac (226:226:226) (242:242:242)) + (PORT datad (277:277:277) (331:331:331)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (431:431:431)) + (PORT datab (483:483:483) (422:422:422)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (394:394:394)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT datac (293:293:293) (362:362:362)) + (PORT datad (302:302:302) (367:367:367)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1893:1893:1893) (1890:1890:1890)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (713:713:713) (779:779:779)) + (PORT sload (1213:1213:1213) (1201:1201:1201)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (989:989:989) (964:964:964)) + (PORT sload (1213:1213:1213) (1201:1201:1201)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (569:569:569)) + (PORT datab (568:568:568) (550:550:550)) + (PORT datac (722:722:722) (628:628:628)) + (PORT datad (526:526:526) (499:499:499)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1504:1504:1504) (1766:1766:1766)) + (PORT datab (3297:3297:3297) (3317:3317:3317)) + (PORT datac (624:624:624) (792:792:792)) + (PORT datad (845:845:845) (762:762:762)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1893:1893:1893) (1890:1890:1890)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~7) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (841:841:841)) + (PORT datab (1935:1935:1935) (2318:2318:2318)) + (PORT datac (909:909:909) (810:810:810)) + (PORT datad (3139:3139:3139) (3152:3152:3152)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (718:718:718) (743:743:743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1507:1507:1507) (1768:1768:1768)) + (PORT datab (3309:3309:3309) (3331:3331:3331)) + (PORT datac (621:621:621) (789:789:789)) + (PORT datad (852:852:852) (770:770:770)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1893:1893:1893) (1890:1890:1890)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1507:1507:1507) (1768:1768:1768)) + (PORT datab (3321:3321:3321) (3369:3369:3369)) + (PORT datac (621:621:621) (789:789:789)) + (PORT datad (852:852:852) (771:771:771)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1893:1893:1893) (1890:1890:1890)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (738:738:738) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~2) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (837:837:837)) + (PORT datab (1937:1937:1937) (2321:2321:2321)) + (PORT datac (913:913:913) (815:815:815)) + (PORT datad (3313:3313:3313) (3367:3367:3367)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~3) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (840:840:840)) + (PORT datab (1935:1935:1935) (2319:2319:2319)) + (PORT datac (910:910:910) (811:811:811)) + (PORT datad (3541:3541:3541) (3491:3491:3491)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (537:537:537) (512:512:512)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (551:551:551)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[5\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (391:391:391)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (544:544:544)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (397:397:397)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1893:1893:1893) (1890:1890:1890)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1814:1814:1814) (1582:1582:1582)) + (PORT sload (1213:1213:1213) (1201:1201:1201)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (960:960:960) (926:926:926)) + (PORT sload (1213:1213:1213) (1201:1201:1201)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (771:771:771) (679:679:679)) + (PORT datab (620:620:620) (568:568:568)) + (PORT datac (753:753:753) (676:676:676)) + (PORT datad (487:487:487) (474:474:474)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1893:1893:1893) (1890:1890:1890)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (941:941:941) (924:924:924)) + (PORT sload (1213:1213:1213) (1201:1201:1201)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1893:1893:1893) (1890:1890:1890)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (711:711:711) (776:776:776)) + (PORT sload (1213:1213:1213) (1201:1201:1201)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (554:554:554)) + (PORT datab (587:587:587) (541:541:541)) + (PORT datac (535:535:535) (506:506:506)) + (PORT datad (501:501:501) (481:481:481)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (968:968:968) (933:933:933)) + (PORT sload (1213:1213:1213) (1201:1201:1201)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (921:921:921) (903:903:903)) + (PORT sload (1213:1213:1213) (1201:1201:1201)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (566:566:566)) + (PORT datab (531:531:531) (515:515:515)) + (PORT datac (536:536:536) (507:507:507)) + (PORT datad (515:515:515) (495:495:495)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (267:267:267) (273:273:273)) + (PORT datac (226:226:226) (241:241:241)) + (PORT datad (227:227:227) (235:235:235)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (718:718:718) (743:743:743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~10) + (DELAY + (ABSOLUTE + (PORT dataa (675:675:675) (840:840:840)) + (PORT datab (1935:1935:1935) (2319:2319:2319)) + (PORT datac (910:910:910) (810:810:810)) + (PORT datad (3165:3165:3165) (3174:3174:3174)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~8) + (DELAY + (ABSOLUTE + (PORT dataa (670:670:670) (835:835:835)) + (PORT datab (1939:1939:1939) (2322:2322:2322)) + (PORT datac (915:915:915) (817:817:817)) + (PORT datad (3220:3220:3220) (3220:3220:3220)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (738:738:738) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1505:1505:1505) (1766:1766:1766)) + (PORT datab (3585:3585:3585) (3540:3540:3540)) + (PORT datac (624:624:624) (792:792:792)) + (PORT datad (845:845:845) (762:762:762)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1893:1893:1893) (1890:1890:1890)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[8\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (398:398:398)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[9\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (548:548:548)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[10\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (540:540:540) (524:524:524)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (922:922:922) (913:913:913)) + (PORT sload (1213:1213:1213) (1201:1201:1201)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1893:1893:1893) (1890:1890:1890)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1189:1189:1189) (1106:1106:1106)) + (PORT sload (1213:1213:1213) (1201:1201:1201)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1464:1464:1464) (1504:1504:1504)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (965:965:965) (929:929:929)) + (PORT sload (1213:1213:1213) (1201:1201:1201)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (565:565:565)) + (PORT datab (605:605:605) (557:557:557)) + (PORT datac (486:486:486) (481:481:481)) + (PORT datad (524:524:524) (499:499:499)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (280:280:280)) + (PORT datab (584:584:584) (540:540:540)) + (PORT datac (224:224:224) (239:239:239)) + (PORT datad (565:565:565) (534:534:534)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|tmp_q) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (633:633:633)) + (PORT datab (489:489:489) (424:424:424)) + (PORT datac (1020:1020:1020) (796:796:796)) + (PORT datad (250:250:250) (258:258:258)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|pwm_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (303:303:303)) + (PORT datab (289:289:289) (297:297:297)) + (PORT datac (246:246:246) (262:262:262)) + (PORT datad (498:498:498) (427:427:427)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|pwm_out) + (DELAY + (ABSOLUTE + (PORT dataa (750:750:750) (623:623:623)) + (PORT datab (741:741:741) (584:584:584)) + (PORT datad (230:230:230) (238:238:238)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) +) diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_85c_slow.vo b/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..b068b1c --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_85c_slow.vo @@ -0,0 +1,2380 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" + +// DATE "12/08/2018 18:51:18" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module dpwm_top ( + clk, + rst_n, + control, + pwm_out, + pwm_out_n); +input clk; +input rst_n; +input [12:0] control; +output pwm_out; +output pwm_out_n; + +// Design Ports Information +// pwm_out => Location: PIN_K1, I/O Standard: 2.5 V, Current Strength: Default +// pwm_out_n => Location: PIN_L2, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// control[3] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// control[2] => Location: PIN_K6, I/O Standard: 2.5 V, Current Strength: Default +// control[5] => Location: PIN_L1, I/O Standard: 2.5 V, Current Strength: Default +// control[4] => Location: PIN_N2, I/O Standard: 2.5 V, Current Strength: Default +// control[7] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default +// control[6] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// control[9] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +// control[8] => Location: PIN_J6, I/O Standard: 2.5 V, Current Strength: Default +// control[11] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// control[10] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default +// control[12] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// control[0] => Location: PIN_L6, I/O Standard: 2.5 V, Current Strength: Default +// control[1] => Location: PIN_K2, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("dpwm_shake_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \clk~input_o ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \dpwm_shake|cnt[0]~30_combout ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_all~combout ; +wire \rst_all~clkctrl_outclk ; +wire \dpwm_shake|cnt[1]~10_combout ; +wire \dpwm_shake|cnt[1]~11 ; +wire \dpwm_shake|cnt[2]~12_combout ; +wire \dpwm_shake|cnt[2]~13 ; +wire \dpwm_shake|cnt[3]~14_combout ; +wire \dpwm_shake|Equal0~0_combout ; +wire \dpwm_shake|cnt[3]~15 ; +wire \dpwm_shake|cnt[4]~16_combout ; +wire \dpwm_shake|cnt[4]~17 ; +wire \dpwm_shake|cnt[5]~18_combout ; +wire \dpwm_shake|cnt[5]~19 ; +wire \dpwm_shake|cnt[6]~20_combout ; +wire \dpwm_shake|cnt[6]~21 ; +wire \dpwm_shake|cnt[7]~22_combout ; +wire \dpwm_shake|cnt[7]~23 ; +wire \dpwm_shake|cnt[8]~24_combout ; +wire \dpwm_shake|cnt[8]~25 ; +wire \dpwm_shake|cnt[9]~26_combout ; +wire \dpwm_shake|cnt[9]~27 ; +wire \dpwm_shake|cnt[10]~28_combout ; +wire \dpwm_shake|Equal0~2_combout ; +wire \dpwm_shake|Equal0~1_combout ; +wire \control[3]~input_o ; +wire \dpwm_shake|cat_duty~0_combout ; +wire \dpwm_shake|Equal2~0_combout ; +wire \dpwm_shake|Equal2~1_combout ; +wire \dpwm_shake|Equal2~2_combout ; +wire \dpwm_shake|shake_count[0]~1_combout ; +wire \dpwm_shake|shake_count[1]~0_combout ; +wire \control[2]~input_o ; +wire \dpwm_shake|cat_duty~1_combout ; +wire \control[1]~input_o ; +wire \dpwm_shake|shake_ctr~1_combout ; +wire \dpwm_shake|shakenum~2_combout ; +wire \dpwm_shake|Add2~2_combout ; +wire \control[0]~input_o ; +wire \dpwm_shake|shake_ctr~0_combout ; +wire \dpwm_shake|shakenum~0_combout ; +wire \dpwm_shake|Add2~0_combout ; +wire \dpwm_shake|shakenum~1_combout ; +wire \dpwm_shake|Add2~1_combout ; +wire \dpwm_shake|new_duty[0]~12 ; +wire \dpwm_shake|new_duty[1]~13_combout ; +wire \dpwm_shake|Add2~3_combout ; +wire \dpwm_shake|new_duty[0]~11_combout ; +wire \dpwm_shake|Equal1~0_combout ; +wire \control[9]~input_o ; +wire \dpwm_shake|cat_duty~6_combout ; +wire \control[8]~input_o ; +wire \dpwm_shake|cat_duty~7_combout ; +wire \control[7]~input_o ; +wire \dpwm_shake|cat_duty~4_combout ; +wire \control[6]~input_o ; +wire \dpwm_shake|cat_duty~5_combout ; +wire \control[5]~input_o ; +wire \dpwm_shake|cat_duty~2_combout ; +wire \control[4]~input_o ; +wire \dpwm_shake|cat_duty~3_combout ; +wire \dpwm_shake|new_duty[1]~14 ; +wire \dpwm_shake|new_duty[2]~16 ; +wire \dpwm_shake|new_duty[3]~18 ; +wire \dpwm_shake|new_duty[4]~20 ; +wire \dpwm_shake|new_duty[5]~22 ; +wire \dpwm_shake|new_duty[6]~24 ; +wire \dpwm_shake|new_duty[7]~25_combout ; +wire \dpwm_shake|new_duty[6]~23_combout ; +wire \dpwm_shake|Equal1~3_combout ; +wire \dpwm_shake|new_duty[4]~19_combout ; +wire \dpwm_shake|new_duty[5]~21_combout ; +wire \dpwm_shake|Equal1~2_combout ; +wire \dpwm_shake|new_duty[3]~17_combout ; +wire \dpwm_shake|new_duty[2]~15_combout ; +wire \dpwm_shake|Equal1~1_combout ; +wire \dpwm_shake|Equal1~4_combout ; +wire \control[12]~input_o ; +wire \dpwm_shake|cat_duty~10_combout ; +wire \control[11]~input_o ; +wire \dpwm_shake|cat_duty~8_combout ; +wire \control[10]~input_o ; +wire \dpwm_shake|cat_duty~9_combout ; +wire \dpwm_shake|new_duty[7]~26 ; +wire \dpwm_shake|new_duty[8]~28 ; +wire \dpwm_shake|new_duty[9]~30 ; +wire \dpwm_shake|new_duty[10]~31_combout ; +wire \dpwm_shake|new_duty[8]~27_combout ; +wire \dpwm_shake|new_duty[9]~29_combout ; +wire \dpwm_shake|Equal1~5_combout ; +wire \dpwm_shake|Equal1~6_combout ; +wire \dpwm_shake|tmp_q~combout ; +wire \dpwm_shake|pwm_out~2_combout ; +wire \dpwm_shake|pwm_out~combout ; +wire [10:0] \dpwm_shake|cnt ; +wire [10:0] \dpwm_shake|new_duty ; +wire [1:0] \dpwm_shake|shake_ctr ; +wire [4:0] \pwm_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [11:0] \dpwm_shake|cat_duty ; +wire [3:0] \dpwm_shake|shakenum ; +wire [1:0] \dpwm_shake|shake_count ; + +wire [4:0] \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X0_Y8_N9 +cycloneive_io_obuf \pwm_out~output ( + .i(\dpwm_shake|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out), + .obar()); +// synopsys translate_off +defparam \pwm_out~output .bus_hold = "false"; +defparam \pwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y8_N16 +cycloneive_io_obuf \pwm_out_n~output ( + .i(!\dpwm_shake|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out_n), + .obar()); +// synopsys translate_off +defparam \pwm_out_n~output .bus_hold = "false"; +defparam \pwm_out_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \pwm_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\pwm_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_high = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_low = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 10; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 49; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 19; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m = 49; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .n = 5; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "on"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 255; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneive_clkctrl \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\pwm_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|cnt[0]~30 ( +// Equation(s): +// \dpwm_shake|cnt[0]~30_combout = !\dpwm_shake|cnt [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm_shake|cnt [0]), + .cin(gnd), + .combout(\dpwm_shake|cnt[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cnt[0]~30 .lut_mask = 16'h00FF; +defparam \dpwm_shake|cnt[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y10_N4 +cycloneive_lcell_comb \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y10_N5 +dffeas \pwm_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N4 +cycloneive_lcell_comb rst_all( +// Equation(s): +// \rst_all~combout = (!\rst_n~input_o & ((!\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ))) + + .dataa(\rst_n~input_o ), + .datab(gnd), + .datac(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_all~combout ), + .cout()); +// synopsys translate_off +defparam rst_all.lut_mask = 16'h0555; +defparam rst_all.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \rst_all~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_all~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_all~clkctrl_outclk )); +// synopsys translate_off +defparam \rst_all~clkctrl .clock_type = "global clock"; +defparam \rst_all~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X1_Y11_N31 +dffeas \dpwm_shake|cnt[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\dpwm_shake|cnt[0]~30_combout ), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|cnt[1]~10 ( +// Equation(s): +// \dpwm_shake|cnt[1]~10_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] $ (VCC))) # (!\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] & VCC)) +// \dpwm_shake|cnt[1]~11 = CARRY((\dpwm_shake|cnt [1] & \dpwm_shake|cnt [0])) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm_shake|cnt[1]~10_combout ), + .cout(\dpwm_shake|cnt[1]~11 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[1]~10 .lut_mask = 16'h6688; +defparam \dpwm_shake|cnt[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y11_N11 +dffeas \dpwm_shake|cnt[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|cnt[2]~12 ( +// Equation(s): +// \dpwm_shake|cnt[2]~12_combout = (\dpwm_shake|cnt [2] & (!\dpwm_shake|cnt[1]~11 )) # (!\dpwm_shake|cnt [2] & ((\dpwm_shake|cnt[1]~11 ) # (GND))) +// \dpwm_shake|cnt[2]~13 = CARRY((!\dpwm_shake|cnt[1]~11 ) # (!\dpwm_shake|cnt [2])) + + .dataa(\dpwm_shake|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[1]~11 ), + .combout(\dpwm_shake|cnt[2]~12_combout ), + .cout(\dpwm_shake|cnt[2]~13 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[2]~12 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|cnt[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N13 +dffeas \dpwm_shake|cnt[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|cnt[3]~14 ( +// Equation(s): +// \dpwm_shake|cnt[3]~14_combout = (\dpwm_shake|cnt [3] & (\dpwm_shake|cnt[2]~13 $ (GND))) # (!\dpwm_shake|cnt [3] & (!\dpwm_shake|cnt[2]~13 & VCC)) +// \dpwm_shake|cnt[3]~15 = CARRY((\dpwm_shake|cnt [3] & !\dpwm_shake|cnt[2]~13 )) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[2]~13 ), + .combout(\dpwm_shake|cnt[3]~14_combout ), + .cout(\dpwm_shake|cnt[3]~15 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[3]~14 .lut_mask = 16'hC30C; +defparam \dpwm_shake|cnt[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N15 +dffeas \dpwm_shake|cnt[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|Equal0~0 ( +// Equation(s): +// \dpwm_shake|Equal0~0_combout = (!\dpwm_shake|cnt [1] & (!\dpwm_shake|cnt [3] & (!\dpwm_shake|cnt [0] & !\dpwm_shake|cnt [2]))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [3]), + .datac(\dpwm_shake|cnt [0]), + .datad(\dpwm_shake|cnt [2]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~0 .lut_mask = 16'h0001; +defparam \dpwm_shake|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|cnt[4]~16 ( +// Equation(s): +// \dpwm_shake|cnt[4]~16_combout = (\dpwm_shake|cnt [4] & (!\dpwm_shake|cnt[3]~15 )) # (!\dpwm_shake|cnt [4] & ((\dpwm_shake|cnt[3]~15 ) # (GND))) +// \dpwm_shake|cnt[4]~17 = CARRY((!\dpwm_shake|cnt[3]~15 ) # (!\dpwm_shake|cnt [4])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[3]~15 ), + .combout(\dpwm_shake|cnt[4]~16_combout ), + .cout(\dpwm_shake|cnt[4]~17 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[4]~16 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N17 +dffeas \dpwm_shake|cnt[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|cnt[5]~18 ( +// Equation(s): +// \dpwm_shake|cnt[5]~18_combout = (\dpwm_shake|cnt [5] & (\dpwm_shake|cnt[4]~17 $ (GND))) # (!\dpwm_shake|cnt [5] & (!\dpwm_shake|cnt[4]~17 & VCC)) +// \dpwm_shake|cnt[5]~19 = CARRY((\dpwm_shake|cnt [5] & !\dpwm_shake|cnt[4]~17 )) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[4]~17 ), + .combout(\dpwm_shake|cnt[5]~18_combout ), + .cout(\dpwm_shake|cnt[5]~19 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[5]~18 .lut_mask = 16'hC30C; +defparam \dpwm_shake|cnt[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N19 +dffeas \dpwm_shake|cnt[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|cnt[6]~20 ( +// Equation(s): +// \dpwm_shake|cnt[6]~20_combout = (\dpwm_shake|cnt [6] & (!\dpwm_shake|cnt[5]~19 )) # (!\dpwm_shake|cnt [6] & ((\dpwm_shake|cnt[5]~19 ) # (GND))) +// \dpwm_shake|cnt[6]~21 = CARRY((!\dpwm_shake|cnt[5]~19 ) # (!\dpwm_shake|cnt [6])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[5]~19 ), + .combout(\dpwm_shake|cnt[6]~20_combout ), + .cout(\dpwm_shake|cnt[6]~21 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[6]~20 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N21 +dffeas \dpwm_shake|cnt[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|cnt[7]~22 ( +// Equation(s): +// \dpwm_shake|cnt[7]~22_combout = (\dpwm_shake|cnt [7] & (\dpwm_shake|cnt[6]~21 $ (GND))) # (!\dpwm_shake|cnt [7] & (!\dpwm_shake|cnt[6]~21 & VCC)) +// \dpwm_shake|cnt[7]~23 = CARRY((\dpwm_shake|cnt [7] & !\dpwm_shake|cnt[6]~21 )) + + .dataa(\dpwm_shake|cnt [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[6]~21 ), + .combout(\dpwm_shake|cnt[7]~22_combout ), + .cout(\dpwm_shake|cnt[7]~23 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[7]~22 .lut_mask = 16'hA50A; +defparam \dpwm_shake|cnt[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N23 +dffeas \dpwm_shake|cnt[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|cnt[8]~24 ( +// Equation(s): +// \dpwm_shake|cnt[8]~24_combout = (\dpwm_shake|cnt [8] & (!\dpwm_shake|cnt[7]~23 )) # (!\dpwm_shake|cnt [8] & ((\dpwm_shake|cnt[7]~23 ) # (GND))) +// \dpwm_shake|cnt[8]~25 = CARRY((!\dpwm_shake|cnt[7]~23 ) # (!\dpwm_shake|cnt [8])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[7]~23 ), + .combout(\dpwm_shake|cnt[8]~24_combout ), + .cout(\dpwm_shake|cnt[8]~25 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[8]~24 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[8]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N25 +dffeas \dpwm_shake|cnt[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[8]~24_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cnt[9]~26 ( +// Equation(s): +// \dpwm_shake|cnt[9]~26_combout = (\dpwm_shake|cnt [9] & (\dpwm_shake|cnt[8]~25 $ (GND))) # (!\dpwm_shake|cnt [9] & (!\dpwm_shake|cnt[8]~25 & VCC)) +// \dpwm_shake|cnt[9]~27 = CARRY((\dpwm_shake|cnt [9] & !\dpwm_shake|cnt[8]~25 )) + + .dataa(\dpwm_shake|cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[8]~25 ), + .combout(\dpwm_shake|cnt[9]~26_combout ), + .cout(\dpwm_shake|cnt[9]~27 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[9]~26 .lut_mask = 16'hA50A; +defparam \dpwm_shake|cnt[9]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N27 +dffeas \dpwm_shake|cnt[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[9]~26_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|cnt[10]~28 ( +// Equation(s): +// \dpwm_shake|cnt[10]~28_combout = \dpwm_shake|cnt[9]~27 $ (\dpwm_shake|cnt [10]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm_shake|cnt [10]), + .cin(\dpwm_shake|cnt[9]~27 ), + .combout(\dpwm_shake|cnt[10]~28_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cnt[10]~28 .lut_mask = 16'h0FF0; +defparam \dpwm_shake|cnt[10]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N29 +dffeas \dpwm_shake|cnt[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[10]~28_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|Equal0~2 ( +// Equation(s): +// \dpwm_shake|Equal0~2_combout = (!\dpwm_shake|cnt [8] & (!\dpwm_shake|cnt [9] & !\dpwm_shake|cnt [10])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|cnt [9]), + .datad(\dpwm_shake|cnt [10]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~2 .lut_mask = 16'h0003; +defparam \dpwm_shake|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|Equal0~1 ( +// Equation(s): +// \dpwm_shake|Equal0~1_combout = (!\dpwm_shake|cnt [7] & (!\dpwm_shake|cnt [4] & (!\dpwm_shake|cnt [6] & !\dpwm_shake|cnt [5]))) + + .dataa(\dpwm_shake|cnt [7]), + .datab(\dpwm_shake|cnt [4]), + .datac(\dpwm_shake|cnt [6]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~1 .lut_mask = 16'h0001; +defparam \dpwm_shake|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \control[3]~input ( + .i(control[3]), + .ibar(gnd), + .o(\control[3]~input_o )); +// synopsys translate_off +defparam \control[3]~input .bus_hold = "false"; +defparam \control[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|cat_duty~0 ( +// Equation(s): +// \dpwm_shake|cat_duty~0_combout = (\control[3]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[3]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~0 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N31 +dffeas \dpwm_shake|cat_duty[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|Equal2~0 ( +// Equation(s): +// \dpwm_shake|Equal2~0_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] & (\dpwm_shake|cnt [3] & \dpwm_shake|cnt [2]))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(\dpwm_shake|cnt [3]), + .datad(\dpwm_shake|cnt [2]), + .cin(gnd), + .combout(\dpwm_shake|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~0 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|Equal2~1 ( +// Equation(s): +// \dpwm_shake|Equal2~1_combout = (\dpwm_shake|cnt [4] & (\dpwm_shake|cnt [6] & (\dpwm_shake|cnt [7] & \dpwm_shake|cnt [5]))) + + .dataa(\dpwm_shake|cnt [4]), + .datab(\dpwm_shake|cnt [6]), + .datac(\dpwm_shake|cnt [7]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~1 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|Equal2~2 ( +// Equation(s): +// \dpwm_shake|Equal2~2_combout = (\dpwm_shake|cnt [10] & (\dpwm_shake|cnt [8] & (\dpwm_shake|cnt [9] & \dpwm_shake|Equal2~1_combout ))) + + .dataa(\dpwm_shake|cnt [10]), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|cnt [9]), + .datad(\dpwm_shake|Equal2~1_combout ), + .cin(gnd), + .combout(\dpwm_shake|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~2 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|shake_count[0]~1 ( +// Equation(s): +// \dpwm_shake|shake_count[0]~1_combout = \dpwm_shake|shake_count [0] $ (((\dpwm_shake|Equal2~0_combout & \dpwm_shake|Equal2~2_combout ))) + + .dataa(\dpwm_shake|Equal2~0_combout ), + .datab(gnd), + .datac(\dpwm_shake|shake_count [0]), + .datad(\dpwm_shake|Equal2~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|shake_count[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_count[0]~1 .lut_mask = 16'h5AF0; +defparam \dpwm_shake|shake_count[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N17 +dffeas \dpwm_shake|shake_count[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_count[0]~1_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_count[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|shake_count[1]~0 ( +// Equation(s): +// \dpwm_shake|shake_count[1]~0_combout = \dpwm_shake|shake_count [1] $ (((\dpwm_shake|Equal2~0_combout & (\dpwm_shake|shake_count [0] & \dpwm_shake|Equal2~2_combout )))) + + .dataa(\dpwm_shake|Equal2~0_combout ), + .datab(\dpwm_shake|shake_count [0]), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|Equal2~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|shake_count[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_count[1]~0 .lut_mask = 16'h78F0; +defparam \dpwm_shake|shake_count[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N15 +dffeas \dpwm_shake|shake_count[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_count[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_count[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y9_N1 +cycloneive_io_ibuf \control[2]~input ( + .i(control[2]), + .ibar(gnd), + .o(\control[2]~input_o )); +// synopsys translate_off +defparam \control[2]~input .bus_hold = "false"; +defparam \control[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|cat_duty~1 ( +// Equation(s): +// \dpwm_shake|cat_duty~1_combout = (\control[2]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\control[2]~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~1 .lut_mask = 16'hA8A0; +defparam \dpwm_shake|cat_duty~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N31 +dffeas \dpwm_shake|cat_duty[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \control[1]~input ( + .i(control[1]), + .ibar(gnd), + .o(\control[1]~input_o )); +// synopsys translate_off +defparam \control[1]~input .bus_hold = "false"; +defparam \control[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|shake_ctr~1 ( +// Equation(s): +// \dpwm_shake|shake_ctr~1_combout = (\control[1]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\control[1]~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shake_ctr~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr~1 .lut_mask = 16'hE0A0; +defparam \dpwm_shake|shake_ctr~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N29 +dffeas \dpwm_shake|shake_ctr[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_ctr~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_ctr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_ctr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|shakenum~2 ( +// Equation(s): +// \dpwm_shake|shakenum~2_combout = (\dpwm_shake|shake_ctr [1] & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shakenum~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~2 .lut_mask = 16'hC888; +defparam \dpwm_shake|shakenum~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N25 +dffeas \dpwm_shake|shakenum[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|Add2~2 ( +// Equation(s): +// \dpwm_shake|Add2~2_combout = (\dpwm_shake|shake_count [1] & ((\dpwm_shake|shakenum [2]))) # (!\dpwm_shake|shake_count [1] & (\dpwm_shake|cat_duty [0])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_count [1]), + .datac(\dpwm_shake|cat_duty [0]), + .datad(\dpwm_shake|shakenum [2]), + .cin(gnd), + .combout(\dpwm_shake|Add2~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~2 .lut_mask = 16'hFC30; +defparam \dpwm_shake|Add2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y9_N8 +cycloneive_io_ibuf \control[0]~input ( + .i(control[0]), + .ibar(gnd), + .o(\control[0]~input_o )); +// synopsys translate_off +defparam \control[0]~input .bus_hold = "false"; +defparam \control[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|shake_ctr~0 ( +// Equation(s): +// \dpwm_shake|shake_ctr~0_combout = (\control[0]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\control[0]~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shake_ctr~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr~0 .lut_mask = 16'hE0A0; +defparam \dpwm_shake|shake_ctr~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N7 +dffeas \dpwm_shake|shake_ctr[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_ctr~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_ctr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_ctr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|shakenum~0 ( +// Equation(s): +// \dpwm_shake|shakenum~0_combout = (!\rst_all~combout & ((\dpwm_shake|shake_ctr [1]) # (\dpwm_shake|shake_ctr [0]))) + + .dataa(gnd), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\rst_all~combout ), + .datad(\dpwm_shake|shake_ctr [0]), + .cin(gnd), + .combout(\dpwm_shake|shakenum~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~0 .lut_mask = 16'h0F0C; +defparam \dpwm_shake|shakenum~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N9 +dffeas \dpwm_shake|shakenum[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|Add2~0 ( +// Equation(s): +// \dpwm_shake|Add2~0_combout = (!\dpwm_shake|shake_count [0] & ((\dpwm_shake|shake_count [1] & (\dpwm_shake|cat_duty [0])) # (!\dpwm_shake|shake_count [1] & ((\dpwm_shake|shakenum [0]))))) + + .dataa(\dpwm_shake|cat_duty [0]), + .datab(\dpwm_shake|shakenum [0]), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|shake_count [0]), + .cin(gnd), + .combout(\dpwm_shake|Add2~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~0 .lut_mask = 16'h00AC; +defparam \dpwm_shake|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|shakenum~1 ( +// Equation(s): +// \dpwm_shake|shakenum~1_combout = (\dpwm_shake|shake_ctr [1] & (!\rst_all~combout & \dpwm_shake|shake_ctr [0])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\rst_all~combout ), + .datad(\dpwm_shake|shake_ctr [0]), + .cin(gnd), + .combout(\dpwm_shake|shakenum~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~1 .lut_mask = 16'h0C00; +defparam \dpwm_shake|shakenum~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N21 +dffeas \dpwm_shake|shakenum[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|Add2~1 ( +// Equation(s): +// \dpwm_shake|Add2~1_combout = (\dpwm_shake|Add2~0_combout ) # ((\dpwm_shake|shake_count [0] & \dpwm_shake|shakenum [1])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_count [0]), + .datac(\dpwm_shake|Add2~0_combout ), + .datad(\dpwm_shake|shakenum [1]), + .cin(gnd), + .combout(\dpwm_shake|Add2~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~1 .lut_mask = 16'hFCF0; +defparam \dpwm_shake|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|new_duty[0]~11 ( +// Equation(s): +// \dpwm_shake|new_duty[0]~11_combout = (\dpwm_shake|Add2~2_combout & (\dpwm_shake|Add2~1_combout $ (VCC))) # (!\dpwm_shake|Add2~2_combout & (\dpwm_shake|Add2~1_combout & VCC)) +// \dpwm_shake|new_duty[0]~12 = CARRY((\dpwm_shake|Add2~2_combout & \dpwm_shake|Add2~1_combout )) + + .dataa(\dpwm_shake|Add2~2_combout ), + .datab(\dpwm_shake|Add2~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm_shake|new_duty[0]~11_combout ), + .cout(\dpwm_shake|new_duty[0]~12 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[0]~11 .lut_mask = 16'h6688; +defparam \dpwm_shake|new_duty[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|new_duty[1]~13 ( +// Equation(s): +// \dpwm_shake|new_duty[1]~13_combout = (\dpwm_shake|cat_duty [1] & (!\dpwm_shake|new_duty[0]~12 )) # (!\dpwm_shake|cat_duty [1] & ((\dpwm_shake|new_duty[0]~12 ) # (GND))) +// \dpwm_shake|new_duty[1]~14 = CARRY((!\dpwm_shake|new_duty[0]~12 ) # (!\dpwm_shake|cat_duty [1])) + + .dataa(\dpwm_shake|cat_duty [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[0]~12 ), + .combout(\dpwm_shake|new_duty[1]~13_combout ), + .cout(\dpwm_shake|new_duty[1]~14 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[1]~13 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[1]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|Add2~3 ( +// Equation(s): +// \dpwm_shake|Add2~3_combout = (\dpwm_shake|shake_count [1] & \dpwm_shake|shake_count [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|shake_count [0]), + .cin(gnd), + .combout(\dpwm_shake|Add2~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~3 .lut_mask = 16'hF000; +defparam \dpwm_shake|Add2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N7 +dffeas \dpwm_shake|new_duty[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[1]~13_combout ), + .asdata(\dpwm_shake|cat_duty [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N5 +dffeas \dpwm_shake|new_duty[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[0]~11_combout ), + .asdata(\dpwm_shake|cat_duty [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|Equal1~0 ( +// Equation(s): +// \dpwm_shake|Equal1~0_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|new_duty [1] & (\dpwm_shake|cnt [0] $ (!\dpwm_shake|new_duty [0])))) # (!\dpwm_shake|cnt [1] & (!\dpwm_shake|new_duty [1] & (\dpwm_shake|cnt [0] $ (!\dpwm_shake|new_duty [0])))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(\dpwm_shake|new_duty [1]), + .datad(\dpwm_shake|new_duty [0]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~0 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N22 +cycloneive_io_ibuf \control[9]~input ( + .i(control[9]), + .ibar(gnd), + .o(\control[9]~input_o )); +// synopsys translate_off +defparam \control[9]~input .bus_hold = "false"; +defparam \control[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|cat_duty~6 ( +// Equation(s): +// \dpwm_shake|cat_duty~6_combout = (\control[9]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[9]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~6_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~6 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N3 +dffeas \dpwm_shake|cat_duty[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N22 +cycloneive_io_ibuf \control[8]~input ( + .i(control[8]), + .ibar(gnd), + .o(\control[8]~input_o )); +// synopsys translate_off +defparam \control[8]~input .bus_hold = "false"; +defparam \control[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|cat_duty~7 ( +// Equation(s): +// \dpwm_shake|cat_duty~7_combout = (\control[8]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[8]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~7_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~7 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N1 +dffeas \dpwm_shake|cat_duty[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[6] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N1 +cycloneive_io_ibuf \control[7]~input ( + .i(control[7]), + .ibar(gnd), + .o(\control[7]~input_o )); +// synopsys translate_off +defparam \control[7]~input .bus_hold = "false"; +defparam \control[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cat_duty~4 ( +// Equation(s): +// \dpwm_shake|cat_duty~4_combout = (\control[7]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[7]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~4_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~4 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N27 +dffeas \dpwm_shake|cat_duty[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \control[6]~input ( + .i(control[6]), + .ibar(gnd), + .o(\control[6]~input_o )); +// synopsys translate_off +defparam \control[6]~input .bus_hold = "false"; +defparam \control[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|cat_duty~5 ( +// Equation(s): +// \dpwm_shake|cat_duty~5_combout = (\control[6]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[6]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~5_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~5 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N29 +dffeas \dpwm_shake|cat_duty[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[4] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N22 +cycloneive_io_ibuf \control[5]~input ( + .i(control[5]), + .ibar(gnd), + .o(\control[5]~input_o )); +// synopsys translate_off +defparam \control[5]~input .bus_hold = "false"; +defparam \control[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|cat_duty~2 ( +// Equation(s): +// \dpwm_shake|cat_duty~2_combout = (\control[5]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[5]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~2 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N17 +dffeas \dpwm_shake|cat_duty[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[3] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N15 +cycloneive_io_ibuf \control[4]~input ( + .i(control[4]), + .ibar(gnd), + .o(\control[4]~input_o )); +// synopsys translate_off +defparam \control[4]~input .bus_hold = "false"; +defparam \control[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|cat_duty~3 ( +// Equation(s): +// \dpwm_shake|cat_duty~3_combout = (\control[4]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[4]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~3 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N7 +dffeas \dpwm_shake|cat_duty[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|new_duty[2]~15 ( +// Equation(s): +// \dpwm_shake|new_duty[2]~15_combout = (\dpwm_shake|cat_duty [2] & (\dpwm_shake|new_duty[1]~14 $ (GND))) # (!\dpwm_shake|cat_duty [2] & (!\dpwm_shake|new_duty[1]~14 & VCC)) +// \dpwm_shake|new_duty[2]~16 = CARRY((\dpwm_shake|cat_duty [2] & !\dpwm_shake|new_duty[1]~14 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [2]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[1]~14 ), + .combout(\dpwm_shake|new_duty[2]~15_combout ), + .cout(\dpwm_shake|new_duty[2]~16 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[2]~15 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[2]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|new_duty[3]~17 ( +// Equation(s): +// \dpwm_shake|new_duty[3]~17_combout = (\dpwm_shake|cat_duty [3] & (!\dpwm_shake|new_duty[2]~16 )) # (!\dpwm_shake|cat_duty [3] & ((\dpwm_shake|new_duty[2]~16 ) # (GND))) +// \dpwm_shake|new_duty[3]~18 = CARRY((!\dpwm_shake|new_duty[2]~16 ) # (!\dpwm_shake|cat_duty [3])) + + .dataa(\dpwm_shake|cat_duty [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[2]~16 ), + .combout(\dpwm_shake|new_duty[3]~17_combout ), + .cout(\dpwm_shake|new_duty[3]~18 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[3]~17 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|new_duty[4]~19 ( +// Equation(s): +// \dpwm_shake|new_duty[4]~19_combout = (\dpwm_shake|cat_duty [4] & (\dpwm_shake|new_duty[3]~18 $ (GND))) # (!\dpwm_shake|cat_duty [4] & (!\dpwm_shake|new_duty[3]~18 & VCC)) +// \dpwm_shake|new_duty[4]~20 = CARRY((\dpwm_shake|cat_duty [4] & !\dpwm_shake|new_duty[3]~18 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[3]~18 ), + .combout(\dpwm_shake|new_duty[4]~19_combout ), + .cout(\dpwm_shake|new_duty[4]~20 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[4]~19 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|new_duty[5]~21 ( +// Equation(s): +// \dpwm_shake|new_duty[5]~21_combout = (\dpwm_shake|cat_duty [5] & (!\dpwm_shake|new_duty[4]~20 )) # (!\dpwm_shake|cat_duty [5] & ((\dpwm_shake|new_duty[4]~20 ) # (GND))) +// \dpwm_shake|new_duty[5]~22 = CARRY((!\dpwm_shake|new_duty[4]~20 ) # (!\dpwm_shake|cat_duty [5])) + + .dataa(\dpwm_shake|cat_duty [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[4]~20 ), + .combout(\dpwm_shake|new_duty[5]~21_combout ), + .cout(\dpwm_shake|new_duty[5]~22 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[5]~21 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|new_duty[6]~23 ( +// Equation(s): +// \dpwm_shake|new_duty[6]~23_combout = (\dpwm_shake|cat_duty [6] & (\dpwm_shake|new_duty[5]~22 $ (GND))) # (!\dpwm_shake|cat_duty [6] & (!\dpwm_shake|new_duty[5]~22 & VCC)) +// \dpwm_shake|new_duty[6]~24 = CARRY((\dpwm_shake|cat_duty [6] & !\dpwm_shake|new_duty[5]~22 )) + + .dataa(\dpwm_shake|cat_duty [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[5]~22 ), + .combout(\dpwm_shake|new_duty[6]~23_combout ), + .cout(\dpwm_shake|new_duty[6]~24 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[6]~23 .lut_mask = 16'hA50A; +defparam \dpwm_shake|new_duty[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|new_duty[7]~25 ( +// Equation(s): +// \dpwm_shake|new_duty[7]~25_combout = (\dpwm_shake|cat_duty [7] & (!\dpwm_shake|new_duty[6]~24 )) # (!\dpwm_shake|cat_duty [7] & ((\dpwm_shake|new_duty[6]~24 ) # (GND))) +// \dpwm_shake|new_duty[7]~26 = CARRY((!\dpwm_shake|new_duty[6]~24 ) # (!\dpwm_shake|cat_duty [7])) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [7]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[6]~24 ), + .combout(\dpwm_shake|new_duty[7]~25_combout ), + .cout(\dpwm_shake|new_duty[7]~26 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[7]~25 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|new_duty[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y11_N19 +dffeas \dpwm_shake|new_duty[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[7]~25_combout ), + .asdata(\dpwm_shake|cat_duty [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N17 +dffeas \dpwm_shake|new_duty[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[6]~23_combout ), + .asdata(\dpwm_shake|cat_duty [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|Equal1~3 ( +// Equation(s): +// \dpwm_shake|Equal1~3_combout = (\dpwm_shake|new_duty [7] & (\dpwm_shake|cnt [7] & (\dpwm_shake|cnt [6] $ (!\dpwm_shake|new_duty [6])))) # (!\dpwm_shake|new_duty [7] & (!\dpwm_shake|cnt [7] & (\dpwm_shake|cnt [6] $ (!\dpwm_shake|new_duty [6])))) + + .dataa(\dpwm_shake|new_duty [7]), + .datab(\dpwm_shake|cnt [6]), + .datac(\dpwm_shake|cnt [7]), + .datad(\dpwm_shake|new_duty [6]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~3 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N13 +dffeas \dpwm_shake|new_duty[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[4]~19_combout ), + .asdata(\dpwm_shake|cat_duty [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N15 +dffeas \dpwm_shake|new_duty[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[5]~21_combout ), + .asdata(\dpwm_shake|cat_duty [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|Equal1~2 ( +// Equation(s): +// \dpwm_shake|Equal1~2_combout = (\dpwm_shake|cnt [4] & (\dpwm_shake|new_duty [4] & (\dpwm_shake|new_duty [5] $ (!\dpwm_shake|cnt [5])))) # (!\dpwm_shake|cnt [4] & (!\dpwm_shake|new_duty [4] & (\dpwm_shake|new_duty [5] $ (!\dpwm_shake|cnt [5])))) + + .dataa(\dpwm_shake|cnt [4]), + .datab(\dpwm_shake|new_duty [4]), + .datac(\dpwm_shake|new_duty [5]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~2 .lut_mask = 16'h9009; +defparam \dpwm_shake|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N11 +dffeas \dpwm_shake|new_duty[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[3]~17_combout ), + .asdata(\dpwm_shake|cat_duty [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N9 +dffeas \dpwm_shake|new_duty[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[2]~15_combout ), + .asdata(\dpwm_shake|cat_duty [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|Equal1~1 ( +// Equation(s): +// \dpwm_shake|Equal1~1_combout = (\dpwm_shake|cnt [2] & (\dpwm_shake|new_duty [2] & (\dpwm_shake|new_duty [3] $ (!\dpwm_shake|cnt [3])))) # (!\dpwm_shake|cnt [2] & (!\dpwm_shake|new_duty [2] & (\dpwm_shake|new_duty [3] $ (!\dpwm_shake|cnt [3])))) + + .dataa(\dpwm_shake|cnt [2]), + .datab(\dpwm_shake|new_duty [3]), + .datac(\dpwm_shake|new_duty [2]), + .datad(\dpwm_shake|cnt [3]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~1 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|Equal1~4 ( +// Equation(s): +// \dpwm_shake|Equal1~4_combout = (\dpwm_shake|Equal1~0_combout & (\dpwm_shake|Equal1~3_combout & (\dpwm_shake|Equal1~2_combout & \dpwm_shake|Equal1~1_combout ))) + + .dataa(\dpwm_shake|Equal1~0_combout ), + .datab(\dpwm_shake|Equal1~3_combout ), + .datac(\dpwm_shake|Equal1~2_combout ), + .datad(\dpwm_shake|Equal1~1_combout ), + .cin(gnd), + .combout(\dpwm_shake|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~4 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N1 +cycloneive_io_ibuf \control[12]~input ( + .i(control[12]), + .ibar(gnd), + .o(\control[12]~input_o )); +// synopsys translate_off +defparam \control[12]~input .bus_hold = "false"; +defparam \control[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|cat_duty~10 ( +// Equation(s): +// \dpwm_shake|cat_duty~10_combout = (\control[12]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[12]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~10_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~10 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N5 +dffeas \dpwm_shake|cat_duty[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N15 +cycloneive_io_ibuf \control[11]~input ( + .i(control[11]), + .ibar(gnd), + .o(\control[11]~input_o )); +// synopsys translate_off +defparam \control[11]~input .bus_hold = "false"; +defparam \control[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cat_duty~8 ( +// Equation(s): +// \dpwm_shake|cat_duty~8_combout = (\control[11]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[11]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~8_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~8 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N27 +dffeas \dpwm_shake|cat_duty[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[9] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y6_N22 +cycloneive_io_ibuf \control[10]~input ( + .i(control[10]), + .ibar(gnd), + .o(\control[10]~input_o )); +// synopsys translate_off +defparam \control[10]~input .bus_hold = "false"; +defparam \control[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|cat_duty~9 ( +// Equation(s): +// \dpwm_shake|cat_duty~9_combout = (\control[10]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[10]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~9_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~9 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N1 +dffeas \dpwm_shake|cat_duty[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|new_duty[8]~27 ( +// Equation(s): +// \dpwm_shake|new_duty[8]~27_combout = (\dpwm_shake|cat_duty [8] & (\dpwm_shake|new_duty[7]~26 $ (GND))) # (!\dpwm_shake|cat_duty [8] & (!\dpwm_shake|new_duty[7]~26 & VCC)) +// \dpwm_shake|new_duty[8]~28 = CARRY((\dpwm_shake|cat_duty [8] & !\dpwm_shake|new_duty[7]~26 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [8]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[7]~26 ), + .combout(\dpwm_shake|new_duty[8]~27_combout ), + .cout(\dpwm_shake|new_duty[8]~28 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[8]~27 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|new_duty[9]~29 ( +// Equation(s): +// \dpwm_shake|new_duty[9]~29_combout = (\dpwm_shake|cat_duty [9] & (!\dpwm_shake|new_duty[8]~28 )) # (!\dpwm_shake|cat_duty [9] & ((\dpwm_shake|new_duty[8]~28 ) # (GND))) +// \dpwm_shake|new_duty[9]~30 = CARRY((!\dpwm_shake|new_duty[8]~28 ) # (!\dpwm_shake|cat_duty [9])) + + .dataa(\dpwm_shake|cat_duty [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[8]~28 ), + .combout(\dpwm_shake|new_duty[9]~29_combout ), + .cout(\dpwm_shake|new_duty[9]~30 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[9]~29 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|new_duty[10]~31 ( +// Equation(s): +// \dpwm_shake|new_duty[10]~31_combout = \dpwm_shake|cat_duty [10] $ (!\dpwm_shake|new_duty[9]~30 ) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [10]), + .datac(gnd), + .datad(gnd), + .cin(\dpwm_shake|new_duty[9]~30 ), + .combout(\dpwm_shake|new_duty[10]~31_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|new_duty[10]~31 .lut_mask = 16'hC3C3; +defparam \dpwm_shake|new_duty[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y11_N25 +dffeas \dpwm_shake|new_duty[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[10]~31_combout ), + .asdata(\dpwm_shake|cat_duty [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N21 +dffeas \dpwm_shake|new_duty[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[8]~27_combout ), + .asdata(\dpwm_shake|cat_duty [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N23 +dffeas \dpwm_shake|new_duty[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[9]~29_combout ), + .asdata(\dpwm_shake|cat_duty [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|Equal1~5 ( +// Equation(s): +// \dpwm_shake|Equal1~5_combout = (\dpwm_shake|cnt [9] & (\dpwm_shake|new_duty [9] & (\dpwm_shake|cnt [8] $ (!\dpwm_shake|new_duty [8])))) # (!\dpwm_shake|cnt [9] & (!\dpwm_shake|new_duty [9] & (\dpwm_shake|cnt [8] $ (!\dpwm_shake|new_duty [8])))) + + .dataa(\dpwm_shake|cnt [9]), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|new_duty [8]), + .datad(\dpwm_shake|new_duty [9]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~5 .lut_mask = 16'h8241; +defparam \dpwm_shake|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|Equal1~6 ( +// Equation(s): +// \dpwm_shake|Equal1~6_combout = (\dpwm_shake|Equal1~4_combout & (\dpwm_shake|Equal1~5_combout & (\dpwm_shake|new_duty [10] $ (!\dpwm_shake|cnt [10])))) + + .dataa(\dpwm_shake|Equal1~4_combout ), + .datab(\dpwm_shake|new_duty [10]), + .datac(\dpwm_shake|Equal1~5_combout ), + .datad(\dpwm_shake|cnt [10]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~6 .lut_mask = 16'h8020; +defparam \dpwm_shake|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|tmp_q ( +// Equation(s): +// \dpwm_shake|tmp_q~combout = (\dpwm_shake|Equal0~0_combout & (\dpwm_shake|Equal0~2_combout & (\dpwm_shake|Equal0~1_combout & !\dpwm_shake|Equal1~6_combout ))) + + .dataa(\dpwm_shake|Equal0~0_combout ), + .datab(\dpwm_shake|Equal0~2_combout ), + .datac(\dpwm_shake|Equal0~1_combout ), + .datad(\dpwm_shake|Equal1~6_combout ), + .cin(gnd), + .combout(\dpwm_shake|tmp_q~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|tmp_q .lut_mask = 16'h0080; +defparam \dpwm_shake|tmp_q .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|pwm_out~2 ( +// Equation(s): +// \dpwm_shake|pwm_out~2_combout = (\dpwm_shake|Equal1~6_combout ) # ((\dpwm_shake|Equal0~1_combout & (\dpwm_shake|Equal0~0_combout & \dpwm_shake|Equal0~2_combout ))) + + .dataa(\dpwm_shake|Equal0~1_combout ), + .datab(\dpwm_shake|Equal0~0_combout ), + .datac(\dpwm_shake|Equal0~2_combout ), + .datad(\dpwm_shake|Equal1~6_combout ), + .cin(gnd), + .combout(\dpwm_shake|pwm_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|pwm_out~2 .lut_mask = 16'hFF80; +defparam \dpwm_shake|pwm_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|pwm_out ( +// Equation(s): +// \dpwm_shake|pwm_out~combout = (\dpwm_shake|pwm_out~2_combout & ((\dpwm_shake|tmp_q~combout ))) # (!\dpwm_shake|pwm_out~2_combout & (\dpwm_shake|pwm_out~combout )) + + .dataa(\dpwm_shake|pwm_out~combout ), + .datab(\dpwm_shake|tmp_q~combout ), + .datac(gnd), + .datad(\dpwm_shake|pwm_out~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|pwm_out~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|pwm_out .lut_mask = 16'hCCAA; +defparam \dpwm_shake|pwm_out .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_85c_v_slow.sdo b/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..11d0561 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,1779 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "dpwm_top") + (DATE "12/08/2018 18:51:18") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (838:838:838) (779:779:779)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out_n\~output) + (DELAY + (ABSOLUTE + (PORT i (779:779:779) (838:838:838)) + (IOPATH i o (3115:3115:3115) (3138:3138:3138)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (1343:1343:1343) (1343:1343:1343)) + (PORT inclk[0] (2336:2336:2336) (2336:2336:2336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2340:2340:2340) (2307:2307:2307)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT datad (548:548:548) (577:577:577)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2270:2270:2270) (2446:2446:2446)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_all) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (849:849:849)) + (PORT datac (1887:1887:1887) (2069:2069:2069)) + (PORT datad (849:849:849) (836:836:836)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_all\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1021:1021:1021) (966:966:966)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT asdata (913:913:913) (886:886:886)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (1411:1411:1411) (1261:1261:1261)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2126:2126:2126) (2140:2140:2140)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (458:458:458)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (451:451:451)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (459:459:459)) + (PORT datab (366:366:366) (449:449:449)) + (PORT datac (319:319:319) (397:397:397)) + (PORT datad (327:327:327) (404:404:404)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (476:476:476)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (460:460:460)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (476:476:476)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (473:473:473)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[8\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (449:449:449)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (2126:2126:2126) (2140:2140:2140)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[9\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (457:457:457)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[10\]\~28) + (DELAY + (ABSOLUTE + (PORT datad (549:549:549) (572:572:572)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (328:328:328) (412:412:412)) + (PORT datad (346:346:346) (417:417:417)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (473:473:473)) + (PORT datab (391:391:391) (474:474:474)) + (PORT datac (555:555:555) (574:574:574)) + (PORT datad (337:337:337) (418:418:418)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1689:1689:1689) (1806:1806:1806)) + (PORT datab (685:685:685) (798:798:798)) + (PORT datac (705:705:705) (800:800:800)) + (PORT datad (881:881:881) (870:870:870)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (647:647:647)) + (PORT datab (586:586:586) (618:618:618)) + (PORT datac (801:801:801) (779:779:779)) + (PORT datad (560:560:560) (584:584:584)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (622:622:622)) + (PORT datab (394:394:394) (478:478:478)) + (PORT datac (338:338:338) (430:430:430)) + (PORT datad (338:338:338) (419:419:419)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (878:878:878)) + (PORT datab (625:625:625) (633:633:633)) + (PORT datac (573:573:573) (593:593:593)) + (PORT datad (467:467:467) (434:434:434)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_count\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (701:701:701)) + (PORT datad (709:709:709) (646:646:646)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_count\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (702:702:702)) + (PORT datab (362:362:362) (452:452:452)) + (PORT datad (708:708:708) (645:645:645)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (726:726:726) (772:772:772)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~1) + (DELAY + (ABSOLUTE + (PORT dataa (3677:3677:3677) (3814:3814:3814)) + (PORT datab (1933:1933:1933) (2119:2119:2119)) + (PORT datac (714:714:714) (802:802:802)) + (PORT datad (859:859:859) (848:848:848)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_ctr\~1) + (DELAY + (ABSOLUTE + (PORT dataa (761:761:761) (847:847:847)) + (PORT datab (1932:1932:1932) (2118:2118:2118)) + (PORT datac (3672:3672:3672) (3852:3852:3852)) + (PORT datad (858:858:858) (847:847:847)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_ctr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2125:2125:2125) (2139:2139:2139)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~2) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (848:848:848)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (1891:1891:1891) (2072:2072:2072)) + (PORT datad (857:857:857) (845:845:845)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~2) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (435:435:435)) + (PORT datac (330:330:330) (415:415:415)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_ctr\~0) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (849:849:849)) + (PORT datab (1928:1928:1928) (2115:2115:2115)) + (PORT datac (3571:3571:3571) (3733:3733:3733)) + (PORT datad (852:852:852) (839:839:839)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_ctr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (2125:2125:2125) (2139:2139:2139)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~0) + (DELAY + (ABSOLUTE + (PORT datab (354:354:354) (444:444:444)) + (PORT datac (271:271:271) (301:301:301)) + (PORT datad (303:303:303) (377:377:377)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (456:456:456)) + (PORT datab (335:335:335) (411:411:411)) + (PORT datac (309:309:309) (398:398:398)) + (PORT datad (318:318:318) (404:404:404)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~1) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (441:441:441)) + (PORT datac (273:273:273) (304:304:304)) + (PORT datad (305:305:305) (379:379:379)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (448:448:448)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (484:484:484)) + (PORT datab (488:488:488) (473:473:473)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (436:436:436)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT datac (310:310:310) (400:400:400)) + (PORT datad (320:320:320) (407:407:407)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (771:771:771) (848:848:848)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1049:1049:1049) (1060:1060:1060)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (642:642:642)) + (PORT datab (587:587:587) (619:619:619)) + (PORT datac (733:733:733) (705:705:705)) + (PORT datad (541:541:541) (556:556:556)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1686:1686:1686) (1804:1804:1804)) + (PORT datab (3698:3698:3698) (3856:3856:3856)) + (PORT datac (707:707:707) (803:803:803)) + (PORT datad (874:874:874) (860:860:860)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~7) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (846:846:846)) + (PORT datab (2176:2176:2176) (2372:2372:2372)) + (PORT datac (930:930:930) (908:908:908)) + (PORT datad (3533:3533:3533) (3669:3669:3669)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1689:1689:1689) (1805:1805:1805)) + (PORT datab (3714:3714:3714) (3869:3869:3869)) + (PORT datac (705:705:705) (800:800:800)) + (PORT datad (880:880:880) (868:868:868)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1689:1689:1689) (1805:1805:1805)) + (PORT datab (3728:3728:3728) (3905:3905:3905)) + (PORT datac (704:704:704) (800:800:800)) + (PORT datad (881:881:881) (869:869:869)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~2) + (DELAY + (ABSOLUTE + (PORT dataa (760:760:760) (843:843:843)) + (PORT datab (2179:2179:2179) (2375:2375:2375)) + (PORT datac (934:934:934) (913:913:913)) + (PORT datad (3732:3732:3732) (3901:3901:3901)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~3) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (844:844:844)) + (PORT datab (2177:2177:2177) (2373:2373:2373)) + (PORT datac (931:931:931) (909:909:909)) + (PORT datad (3950:3950:3950) (4051:4051:4051)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (550:550:550) (575:575:575)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (621:621:621)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[5\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (613:613:613)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1883:1883:1883) (1764:1764:1764)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1007:1007:1007) (1024:1024:1024)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (766:766:766)) + (PORT datab (637:637:637) (639:639:639)) + (PORT datac (778:778:778) (755:755:755)) + (PORT datad (501:501:501) (526:526:526)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1002:1002:1002) (1015:1015:1015)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (769:769:769) (845:845:845)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (620:620:620)) + (PORT datab (599:599:599) (606:606:606)) + (PORT datac (548:548:548) (565:565:565)) + (PORT datad (519:519:519) (538:538:538)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1017:1017:1017) (1032:1032:1032)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (977:977:977) (996:996:996)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (639:639:639)) + (PORT datab (545:545:545) (572:572:572)) + (PORT datac (549:549:549) (565:565:565)) + (PORT datad (540:540:540) (555:555:555)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~10) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (845:845:845)) + (PORT datab (2177:2177:2177) (2372:2372:2372)) + (PORT datac (931:931:931) (909:909:909)) + (PORT datad (3562:3562:3562) (3698:3698:3698)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~8) + (DELAY + (ABSOLUTE + (PORT dataa (758:758:758) (841:841:841)) + (PORT datab (2181:2181:2181) (2376:2376:2376)) + (PORT datac (937:937:937) (915:915:915)) + (PORT datad (3618:3618:3618) (3751:3751:3751)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1687:1687:1687) (1804:1804:1804)) + (PORT datab (3999:3999:3999) (4100:4100:4100)) + (PORT datac (708:708:708) (803:803:803)) + (PORT datad (873:873:873) (860:860:860)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[8\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (439:439:439)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[9\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (617:617:617)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[10\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (551:551:551) (589:589:589)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (975:975:975) (1008:1008:1008)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1256:1256:1256) (1219:1219:1219)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1014:1014:1014) (1027:1027:1027)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (637:637:637)) + (PORT datab (620:620:620) (628:628:628)) + (PORT datac (500:500:500) (534:534:534)) + (PORT datad (537:537:537) (556:556:556)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (595:595:595) (606:606:606)) + (PORT datac (235:235:235) (261:261:261)) + (PORT datad (585:585:585) (599:599:599)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|tmp_q) + (DELAY + (ABSOLUTE + (PORT dataa (765:765:765) (713:713:713)) + (PORT datab (498:498:498) (477:477:477)) + (PORT datac (1039:1039:1039) (901:901:901)) + (PORT datad (265:265:265) (283:283:283)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|pwm_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (336:336:336)) + (PORT datab (303:303:303) (327:327:327)) + (PORT datac (262:262:262) (287:287:287)) + (PORT datad (509:509:509) (476:476:476)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|pwm_out) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (702:702:702)) + (PORT datab (742:742:742) (661:661:661)) + (PORT datad (241:241:241) (259:259:259)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) +) diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_85c_v_slow.sdo_typ.csd b/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_85c_v_slow.sdo_typ.csd new file mode 100644 index 0000000..83fa5f6 Binary files /dev/null and b/dpwm_shake/simulation/modelsim/dpwm_shake_8_1200mv_85c_v_slow.sdo_typ.csd differ diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_min_1200mv_0c_fast.vo b/dpwm_shake/simulation/modelsim/dpwm_shake_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..5b43a8d --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_min_1200mv_0c_fast.vo @@ -0,0 +1,2380 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" + +// DATE "12/08/2018 18:51:18" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module dpwm_top ( + clk, + rst_n, + control, + pwm_out, + pwm_out_n); +input clk; +input rst_n; +input [12:0] control; +output pwm_out; +output pwm_out_n; + +// Design Ports Information +// pwm_out => Location: PIN_K1, I/O Standard: 2.5 V, Current Strength: Default +// pwm_out_n => Location: PIN_L2, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// control[3] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// control[2] => Location: PIN_K6, I/O Standard: 2.5 V, Current Strength: Default +// control[5] => Location: PIN_L1, I/O Standard: 2.5 V, Current Strength: Default +// control[4] => Location: PIN_N2, I/O Standard: 2.5 V, Current Strength: Default +// control[7] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default +// control[6] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// control[9] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +// control[8] => Location: PIN_J6, I/O Standard: 2.5 V, Current Strength: Default +// control[11] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// control[10] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default +// control[12] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// control[0] => Location: PIN_L6, I/O Standard: 2.5 V, Current Strength: Default +// control[1] => Location: PIN_K2, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("dpwm_shake_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \clk~input_o ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \dpwm_shake|cnt[0]~30_combout ; +wire \pwm_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_all~combout ; +wire \rst_all~clkctrl_outclk ; +wire \dpwm_shake|cnt[1]~10_combout ; +wire \dpwm_shake|cnt[1]~11 ; +wire \dpwm_shake|cnt[2]~12_combout ; +wire \dpwm_shake|cnt[2]~13 ; +wire \dpwm_shake|cnt[3]~14_combout ; +wire \dpwm_shake|Equal0~0_combout ; +wire \dpwm_shake|cnt[3]~15 ; +wire \dpwm_shake|cnt[4]~16_combout ; +wire \dpwm_shake|cnt[4]~17 ; +wire \dpwm_shake|cnt[5]~18_combout ; +wire \dpwm_shake|cnt[5]~19 ; +wire \dpwm_shake|cnt[6]~20_combout ; +wire \dpwm_shake|cnt[6]~21 ; +wire \dpwm_shake|cnt[7]~22_combout ; +wire \dpwm_shake|cnt[7]~23 ; +wire \dpwm_shake|cnt[8]~24_combout ; +wire \dpwm_shake|cnt[8]~25 ; +wire \dpwm_shake|cnt[9]~26_combout ; +wire \dpwm_shake|cnt[9]~27 ; +wire \dpwm_shake|cnt[10]~28_combout ; +wire \dpwm_shake|Equal0~2_combout ; +wire \dpwm_shake|Equal0~1_combout ; +wire \control[3]~input_o ; +wire \dpwm_shake|cat_duty~0_combout ; +wire \dpwm_shake|Equal2~0_combout ; +wire \dpwm_shake|Equal2~1_combout ; +wire \dpwm_shake|Equal2~2_combout ; +wire \dpwm_shake|shake_count[0]~1_combout ; +wire \dpwm_shake|shake_count[1]~0_combout ; +wire \control[2]~input_o ; +wire \dpwm_shake|cat_duty~1_combout ; +wire \control[1]~input_o ; +wire \dpwm_shake|shake_ctr~1_combout ; +wire \dpwm_shake|shakenum~2_combout ; +wire \dpwm_shake|Add2~2_combout ; +wire \control[0]~input_o ; +wire \dpwm_shake|shake_ctr~0_combout ; +wire \dpwm_shake|shakenum~0_combout ; +wire \dpwm_shake|Add2~0_combout ; +wire \dpwm_shake|shakenum~1_combout ; +wire \dpwm_shake|Add2~1_combout ; +wire \dpwm_shake|new_duty[0]~12 ; +wire \dpwm_shake|new_duty[1]~13_combout ; +wire \dpwm_shake|Add2~3_combout ; +wire \dpwm_shake|new_duty[0]~11_combout ; +wire \dpwm_shake|Equal1~0_combout ; +wire \control[9]~input_o ; +wire \dpwm_shake|cat_duty~6_combout ; +wire \control[8]~input_o ; +wire \dpwm_shake|cat_duty~7_combout ; +wire \control[7]~input_o ; +wire \dpwm_shake|cat_duty~4_combout ; +wire \control[6]~input_o ; +wire \dpwm_shake|cat_duty~5_combout ; +wire \control[5]~input_o ; +wire \dpwm_shake|cat_duty~2_combout ; +wire \control[4]~input_o ; +wire \dpwm_shake|cat_duty~3_combout ; +wire \dpwm_shake|new_duty[1]~14 ; +wire \dpwm_shake|new_duty[2]~16 ; +wire \dpwm_shake|new_duty[3]~18 ; +wire \dpwm_shake|new_duty[4]~20 ; +wire \dpwm_shake|new_duty[5]~22 ; +wire \dpwm_shake|new_duty[6]~24 ; +wire \dpwm_shake|new_duty[7]~25_combout ; +wire \dpwm_shake|new_duty[6]~23_combout ; +wire \dpwm_shake|Equal1~3_combout ; +wire \dpwm_shake|new_duty[4]~19_combout ; +wire \dpwm_shake|new_duty[5]~21_combout ; +wire \dpwm_shake|Equal1~2_combout ; +wire \dpwm_shake|new_duty[3]~17_combout ; +wire \dpwm_shake|new_duty[2]~15_combout ; +wire \dpwm_shake|Equal1~1_combout ; +wire \dpwm_shake|Equal1~4_combout ; +wire \control[12]~input_o ; +wire \dpwm_shake|cat_duty~10_combout ; +wire \control[11]~input_o ; +wire \dpwm_shake|cat_duty~8_combout ; +wire \control[10]~input_o ; +wire \dpwm_shake|cat_duty~9_combout ; +wire \dpwm_shake|new_duty[7]~26 ; +wire \dpwm_shake|new_duty[8]~28 ; +wire \dpwm_shake|new_duty[9]~30 ; +wire \dpwm_shake|new_duty[10]~31_combout ; +wire \dpwm_shake|new_duty[8]~27_combout ; +wire \dpwm_shake|new_duty[9]~29_combout ; +wire \dpwm_shake|Equal1~5_combout ; +wire \dpwm_shake|Equal1~6_combout ; +wire \dpwm_shake|tmp_q~combout ; +wire \dpwm_shake|pwm_out~2_combout ; +wire \dpwm_shake|pwm_out~combout ; +wire [10:0] \dpwm_shake|cnt ; +wire [10:0] \dpwm_shake|new_duty ; +wire [1:0] \dpwm_shake|shake_ctr ; +wire [4:0] \pwm_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [11:0] \dpwm_shake|cat_duty ; +wire [3:0] \dpwm_shake|shakenum ; +wire [1:0] \dpwm_shake|shake_count ; + +wire [4:0] \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \pwm_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \pwm_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X0_Y8_N9 +cycloneive_io_obuf \pwm_out~output ( + .i(\dpwm_shake|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out), + .obar()); +// synopsys translate_off +defparam \pwm_out~output .bus_hold = "false"; +defparam \pwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y8_N16 +cycloneive_io_obuf \pwm_out_n~output ( + .i(!\dpwm_shake|pwm_out~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(pwm_out_n), + .obar()); +// synopsys translate_off +defparam \pwm_out_n~output .bus_hold = "false"; +defparam \pwm_out_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \pwm_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\pwm_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\pwm_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_high = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_low = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 10; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 49; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 19; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m = 49; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .n = 5; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "on"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 255; +defparam \pwm_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneive_clkctrl \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\pwm_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|cnt[0]~30 ( +// Equation(s): +// \dpwm_shake|cnt[0]~30_combout = !\dpwm_shake|cnt [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm_shake|cnt [0]), + .cin(gnd), + .combout(\dpwm_shake|cnt[0]~30_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cnt[0]~30 .lut_mask = 16'h00FF; +defparam \dpwm_shake|cnt[0]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y10_N4 +cycloneive_lcell_comb \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y10_N5 +dffeas \pwm_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \pwm_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N4 +cycloneive_lcell_comb rst_all( +// Equation(s): +// \rst_all~combout = (!\rst_n~input_o & ((!\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ))) + + .dataa(\rst_n~input_o ), + .datab(gnd), + .datac(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_all~combout ), + .cout()); +// synopsys translate_off +defparam rst_all.lut_mask = 16'h0555; +defparam rst_all.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \rst_all~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_all~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_all~clkctrl_outclk )); +// synopsys translate_off +defparam \rst_all~clkctrl .clock_type = "global clock"; +defparam \rst_all~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X1_Y11_N31 +dffeas \dpwm_shake|cnt[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\dpwm_shake|cnt[0]~30_combout ), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|cnt[1]~10 ( +// Equation(s): +// \dpwm_shake|cnt[1]~10_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] $ (VCC))) # (!\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] & VCC)) +// \dpwm_shake|cnt[1]~11 = CARRY((\dpwm_shake|cnt [1] & \dpwm_shake|cnt [0])) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm_shake|cnt[1]~10_combout ), + .cout(\dpwm_shake|cnt[1]~11 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[1]~10 .lut_mask = 16'h6688; +defparam \dpwm_shake|cnt[1]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y11_N11 +dffeas \dpwm_shake|cnt[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|cnt[2]~12 ( +// Equation(s): +// \dpwm_shake|cnt[2]~12_combout = (\dpwm_shake|cnt [2] & (!\dpwm_shake|cnt[1]~11 )) # (!\dpwm_shake|cnt [2] & ((\dpwm_shake|cnt[1]~11 ) # (GND))) +// \dpwm_shake|cnt[2]~13 = CARRY((!\dpwm_shake|cnt[1]~11 ) # (!\dpwm_shake|cnt [2])) + + .dataa(\dpwm_shake|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[1]~11 ), + .combout(\dpwm_shake|cnt[2]~12_combout ), + .cout(\dpwm_shake|cnt[2]~13 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[2]~12 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|cnt[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N13 +dffeas \dpwm_shake|cnt[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|cnt[3]~14 ( +// Equation(s): +// \dpwm_shake|cnt[3]~14_combout = (\dpwm_shake|cnt [3] & (\dpwm_shake|cnt[2]~13 $ (GND))) # (!\dpwm_shake|cnt [3] & (!\dpwm_shake|cnt[2]~13 & VCC)) +// \dpwm_shake|cnt[3]~15 = CARRY((\dpwm_shake|cnt [3] & !\dpwm_shake|cnt[2]~13 )) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[2]~13 ), + .combout(\dpwm_shake|cnt[3]~14_combout ), + .cout(\dpwm_shake|cnt[3]~15 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[3]~14 .lut_mask = 16'hC30C; +defparam \dpwm_shake|cnt[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N15 +dffeas \dpwm_shake|cnt[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|Equal0~0 ( +// Equation(s): +// \dpwm_shake|Equal0~0_combout = (!\dpwm_shake|cnt [1] & (!\dpwm_shake|cnt [3] & (!\dpwm_shake|cnt [0] & !\dpwm_shake|cnt [2]))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [3]), + .datac(\dpwm_shake|cnt [0]), + .datad(\dpwm_shake|cnt [2]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~0 .lut_mask = 16'h0001; +defparam \dpwm_shake|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|cnt[4]~16 ( +// Equation(s): +// \dpwm_shake|cnt[4]~16_combout = (\dpwm_shake|cnt [4] & (!\dpwm_shake|cnt[3]~15 )) # (!\dpwm_shake|cnt [4] & ((\dpwm_shake|cnt[3]~15 ) # (GND))) +// \dpwm_shake|cnt[4]~17 = CARRY((!\dpwm_shake|cnt[3]~15 ) # (!\dpwm_shake|cnt [4])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[3]~15 ), + .combout(\dpwm_shake|cnt[4]~16_combout ), + .cout(\dpwm_shake|cnt[4]~17 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[4]~16 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N17 +dffeas \dpwm_shake|cnt[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|cnt[5]~18 ( +// Equation(s): +// \dpwm_shake|cnt[5]~18_combout = (\dpwm_shake|cnt [5] & (\dpwm_shake|cnt[4]~17 $ (GND))) # (!\dpwm_shake|cnt [5] & (!\dpwm_shake|cnt[4]~17 & VCC)) +// \dpwm_shake|cnt[5]~19 = CARRY((\dpwm_shake|cnt [5] & !\dpwm_shake|cnt[4]~17 )) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[4]~17 ), + .combout(\dpwm_shake|cnt[5]~18_combout ), + .cout(\dpwm_shake|cnt[5]~19 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[5]~18 .lut_mask = 16'hC30C; +defparam \dpwm_shake|cnt[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N19 +dffeas \dpwm_shake|cnt[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|cnt[6]~20 ( +// Equation(s): +// \dpwm_shake|cnt[6]~20_combout = (\dpwm_shake|cnt [6] & (!\dpwm_shake|cnt[5]~19 )) # (!\dpwm_shake|cnt [6] & ((\dpwm_shake|cnt[5]~19 ) # (GND))) +// \dpwm_shake|cnt[6]~21 = CARRY((!\dpwm_shake|cnt[5]~19 ) # (!\dpwm_shake|cnt [6])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[5]~19 ), + .combout(\dpwm_shake|cnt[6]~20_combout ), + .cout(\dpwm_shake|cnt[6]~21 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[6]~20 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N21 +dffeas \dpwm_shake|cnt[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|cnt[7]~22 ( +// Equation(s): +// \dpwm_shake|cnt[7]~22_combout = (\dpwm_shake|cnt [7] & (\dpwm_shake|cnt[6]~21 $ (GND))) # (!\dpwm_shake|cnt [7] & (!\dpwm_shake|cnt[6]~21 & VCC)) +// \dpwm_shake|cnt[7]~23 = CARRY((\dpwm_shake|cnt [7] & !\dpwm_shake|cnt[6]~21 )) + + .dataa(\dpwm_shake|cnt [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[6]~21 ), + .combout(\dpwm_shake|cnt[7]~22_combout ), + .cout(\dpwm_shake|cnt[7]~23 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[7]~22 .lut_mask = 16'hA50A; +defparam \dpwm_shake|cnt[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N23 +dffeas \dpwm_shake|cnt[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|cnt[8]~24 ( +// Equation(s): +// \dpwm_shake|cnt[8]~24_combout = (\dpwm_shake|cnt [8] & (!\dpwm_shake|cnt[7]~23 )) # (!\dpwm_shake|cnt [8] & ((\dpwm_shake|cnt[7]~23 ) # (GND))) +// \dpwm_shake|cnt[8]~25 = CARRY((!\dpwm_shake|cnt[7]~23 ) # (!\dpwm_shake|cnt [8])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[7]~23 ), + .combout(\dpwm_shake|cnt[8]~24_combout ), + .cout(\dpwm_shake|cnt[8]~25 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[8]~24 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|cnt[8]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N25 +dffeas \dpwm_shake|cnt[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[8]~24_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cnt[9]~26 ( +// Equation(s): +// \dpwm_shake|cnt[9]~26_combout = (\dpwm_shake|cnt [9] & (\dpwm_shake|cnt[8]~25 $ (GND))) # (!\dpwm_shake|cnt [9] & (!\dpwm_shake|cnt[8]~25 & VCC)) +// \dpwm_shake|cnt[9]~27 = CARRY((\dpwm_shake|cnt [9] & !\dpwm_shake|cnt[8]~25 )) + + .dataa(\dpwm_shake|cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|cnt[8]~25 ), + .combout(\dpwm_shake|cnt[9]~26_combout ), + .cout(\dpwm_shake|cnt[9]~27 )); +// synopsys translate_off +defparam \dpwm_shake|cnt[9]~26 .lut_mask = 16'hA50A; +defparam \dpwm_shake|cnt[9]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N27 +dffeas \dpwm_shake|cnt[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[9]~26_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|cnt[10]~28 ( +// Equation(s): +// \dpwm_shake|cnt[10]~28_combout = \dpwm_shake|cnt[9]~27 $ (\dpwm_shake|cnt [10]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\dpwm_shake|cnt [10]), + .cin(\dpwm_shake|cnt[9]~27 ), + .combout(\dpwm_shake|cnt[10]~28_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cnt[10]~28 .lut_mask = 16'h0FF0; +defparam \dpwm_shake|cnt[10]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X1_Y11_N29 +dffeas \dpwm_shake|cnt[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cnt[10]~28_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cnt[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|Equal0~2 ( +// Equation(s): +// \dpwm_shake|Equal0~2_combout = (!\dpwm_shake|cnt [8] & (!\dpwm_shake|cnt [9] & !\dpwm_shake|cnt [10])) + + .dataa(gnd), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|cnt [9]), + .datad(\dpwm_shake|cnt [10]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~2 .lut_mask = 16'h0003; +defparam \dpwm_shake|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|Equal0~1 ( +// Equation(s): +// \dpwm_shake|Equal0~1_combout = (!\dpwm_shake|cnt [7] & (!\dpwm_shake|cnt [4] & (!\dpwm_shake|cnt [6] & !\dpwm_shake|cnt [5]))) + + .dataa(\dpwm_shake|cnt [7]), + .datab(\dpwm_shake|cnt [4]), + .datac(\dpwm_shake|cnt [6]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal0~1 .lut_mask = 16'h0001; +defparam \dpwm_shake|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \control[3]~input ( + .i(control[3]), + .ibar(gnd), + .o(\control[3]~input_o )); +// synopsys translate_off +defparam \control[3]~input .bus_hold = "false"; +defparam \control[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|cat_duty~0 ( +// Equation(s): +// \dpwm_shake|cat_duty~0_combout = (\control[3]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[3]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~0 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N31 +dffeas \dpwm_shake|cat_duty[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|Equal2~0 ( +// Equation(s): +// \dpwm_shake|Equal2~0_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|cnt [0] & (\dpwm_shake|cnt [3] & \dpwm_shake|cnt [2]))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(\dpwm_shake|cnt [3]), + .datad(\dpwm_shake|cnt [2]), + .cin(gnd), + .combout(\dpwm_shake|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~0 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|Equal2~1 ( +// Equation(s): +// \dpwm_shake|Equal2~1_combout = (\dpwm_shake|cnt [4] & (\dpwm_shake|cnt [6] & (\dpwm_shake|cnt [7] & \dpwm_shake|cnt [5]))) + + .dataa(\dpwm_shake|cnt [4]), + .datab(\dpwm_shake|cnt [6]), + .datac(\dpwm_shake|cnt [7]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~1 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|Equal2~2 ( +// Equation(s): +// \dpwm_shake|Equal2~2_combout = (\dpwm_shake|cnt [10] & (\dpwm_shake|cnt [8] & (\dpwm_shake|cnt [9] & \dpwm_shake|Equal2~1_combout ))) + + .dataa(\dpwm_shake|cnt [10]), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|cnt [9]), + .datad(\dpwm_shake|Equal2~1_combout ), + .cin(gnd), + .combout(\dpwm_shake|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal2~2 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|shake_count[0]~1 ( +// Equation(s): +// \dpwm_shake|shake_count[0]~1_combout = \dpwm_shake|shake_count [0] $ (((\dpwm_shake|Equal2~0_combout & \dpwm_shake|Equal2~2_combout ))) + + .dataa(\dpwm_shake|Equal2~0_combout ), + .datab(gnd), + .datac(\dpwm_shake|shake_count [0]), + .datad(\dpwm_shake|Equal2~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|shake_count[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_count[0]~1 .lut_mask = 16'h5AF0; +defparam \dpwm_shake|shake_count[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N17 +dffeas \dpwm_shake|shake_count[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_count[0]~1_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_count [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_count[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_count[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|shake_count[1]~0 ( +// Equation(s): +// \dpwm_shake|shake_count[1]~0_combout = \dpwm_shake|shake_count [1] $ (((\dpwm_shake|Equal2~0_combout & (\dpwm_shake|shake_count [0] & \dpwm_shake|Equal2~2_combout )))) + + .dataa(\dpwm_shake|Equal2~0_combout ), + .datab(\dpwm_shake|shake_count [0]), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|Equal2~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|shake_count[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_count[1]~0 .lut_mask = 16'h78F0; +defparam \dpwm_shake|shake_count[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N15 +dffeas \dpwm_shake|shake_count[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_count[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_all~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_count [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_count[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_count[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y9_N1 +cycloneive_io_ibuf \control[2]~input ( + .i(control[2]), + .ibar(gnd), + .o(\control[2]~input_o )); +// synopsys translate_off +defparam \control[2]~input .bus_hold = "false"; +defparam \control[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|cat_duty~1 ( +// Equation(s): +// \dpwm_shake|cat_duty~1_combout = (\control[2]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\control[2]~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~1 .lut_mask = 16'hA8A0; +defparam \dpwm_shake|cat_duty~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N31 +dffeas \dpwm_shake|cat_duty[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \control[1]~input ( + .i(control[1]), + .ibar(gnd), + .o(\control[1]~input_o )); +// synopsys translate_off +defparam \control[1]~input .bus_hold = "false"; +defparam \control[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|shake_ctr~1 ( +// Equation(s): +// \dpwm_shake|shake_ctr~1_combout = (\control[1]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\control[1]~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shake_ctr~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr~1 .lut_mask = 16'hE0A0; +defparam \dpwm_shake|shake_ctr~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N29 +dffeas \dpwm_shake|shake_ctr[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_ctr~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_ctr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_ctr[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|shakenum~2 ( +// Equation(s): +// \dpwm_shake|shakenum~2_combout = (\dpwm_shake|shake_ctr [1] & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shakenum~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~2 .lut_mask = 16'hC888; +defparam \dpwm_shake|shakenum~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N25 +dffeas \dpwm_shake|shakenum[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|Add2~2 ( +// Equation(s): +// \dpwm_shake|Add2~2_combout = (\dpwm_shake|shake_count [1] & ((\dpwm_shake|shakenum [2]))) # (!\dpwm_shake|shake_count [1] & (\dpwm_shake|cat_duty [0])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_count [1]), + .datac(\dpwm_shake|cat_duty [0]), + .datad(\dpwm_shake|shakenum [2]), + .cin(gnd), + .combout(\dpwm_shake|Add2~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~2 .lut_mask = 16'hFC30; +defparam \dpwm_shake|Add2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y9_N8 +cycloneive_io_ibuf \control[0]~input ( + .i(control[0]), + .ibar(gnd), + .o(\control[0]~input_o )); +// synopsys translate_off +defparam \control[0]~input .bus_hold = "false"; +defparam \control[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|shake_ctr~0 ( +// Equation(s): +// \dpwm_shake|shake_ctr~0_combout = (\control[0]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\control[0]~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|shake_ctr~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr~0 .lut_mask = 16'hE0A0; +defparam \dpwm_shake|shake_ctr~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N7 +dffeas \dpwm_shake|shake_ctr[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shake_ctr~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shake_ctr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shake_ctr[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shake_ctr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|shakenum~0 ( +// Equation(s): +// \dpwm_shake|shakenum~0_combout = (!\rst_all~combout & ((\dpwm_shake|shake_ctr [1]) # (\dpwm_shake|shake_ctr [0]))) + + .dataa(gnd), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\rst_all~combout ), + .datad(\dpwm_shake|shake_ctr [0]), + .cin(gnd), + .combout(\dpwm_shake|shakenum~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~0 .lut_mask = 16'h0F0C; +defparam \dpwm_shake|shakenum~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N9 +dffeas \dpwm_shake|shakenum[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|Add2~0 ( +// Equation(s): +// \dpwm_shake|Add2~0_combout = (!\dpwm_shake|shake_count [0] & ((\dpwm_shake|shake_count [1] & (\dpwm_shake|cat_duty [0])) # (!\dpwm_shake|shake_count [1] & ((\dpwm_shake|shakenum [0]))))) + + .dataa(\dpwm_shake|cat_duty [0]), + .datab(\dpwm_shake|shakenum [0]), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|shake_count [0]), + .cin(gnd), + .combout(\dpwm_shake|Add2~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~0 .lut_mask = 16'h00AC; +defparam \dpwm_shake|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|shakenum~1 ( +// Equation(s): +// \dpwm_shake|shakenum~1_combout = (\dpwm_shake|shake_ctr [1] & (!\rst_all~combout & \dpwm_shake|shake_ctr [0])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_ctr [1]), + .datac(\rst_all~combout ), + .datad(\dpwm_shake|shake_ctr [0]), + .cin(gnd), + .combout(\dpwm_shake|shakenum~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|shakenum~1 .lut_mask = 16'h0C00; +defparam \dpwm_shake|shakenum~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y11_N21 +dffeas \dpwm_shake|shakenum[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|shakenum~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|shakenum [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|shakenum[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|shakenum[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|Add2~1 ( +// Equation(s): +// \dpwm_shake|Add2~1_combout = (\dpwm_shake|Add2~0_combout ) # ((\dpwm_shake|shake_count [0] & \dpwm_shake|shakenum [1])) + + .dataa(gnd), + .datab(\dpwm_shake|shake_count [0]), + .datac(\dpwm_shake|Add2~0_combout ), + .datad(\dpwm_shake|shakenum [1]), + .cin(gnd), + .combout(\dpwm_shake|Add2~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~1 .lut_mask = 16'hFCF0; +defparam \dpwm_shake|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|new_duty[0]~11 ( +// Equation(s): +// \dpwm_shake|new_duty[0]~11_combout = (\dpwm_shake|Add2~2_combout & (\dpwm_shake|Add2~1_combout $ (VCC))) # (!\dpwm_shake|Add2~2_combout & (\dpwm_shake|Add2~1_combout & VCC)) +// \dpwm_shake|new_duty[0]~12 = CARRY((\dpwm_shake|Add2~2_combout & \dpwm_shake|Add2~1_combout )) + + .dataa(\dpwm_shake|Add2~2_combout ), + .datab(\dpwm_shake|Add2~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\dpwm_shake|new_duty[0]~11_combout ), + .cout(\dpwm_shake|new_duty[0]~12 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[0]~11 .lut_mask = 16'h6688; +defparam \dpwm_shake|new_duty[0]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|new_duty[1]~13 ( +// Equation(s): +// \dpwm_shake|new_duty[1]~13_combout = (\dpwm_shake|cat_duty [1] & (!\dpwm_shake|new_duty[0]~12 )) # (!\dpwm_shake|cat_duty [1] & ((\dpwm_shake|new_duty[0]~12 ) # (GND))) +// \dpwm_shake|new_duty[1]~14 = CARRY((!\dpwm_shake|new_duty[0]~12 ) # (!\dpwm_shake|cat_duty [1])) + + .dataa(\dpwm_shake|cat_duty [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[0]~12 ), + .combout(\dpwm_shake|new_duty[1]~13_combout ), + .cout(\dpwm_shake|new_duty[1]~14 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[1]~13 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[1]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|Add2~3 ( +// Equation(s): +// \dpwm_shake|Add2~3_combout = (\dpwm_shake|shake_count [1] & \dpwm_shake|shake_count [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\dpwm_shake|shake_count [1]), + .datad(\dpwm_shake|shake_count [0]), + .cin(gnd), + .combout(\dpwm_shake|Add2~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Add2~3 .lut_mask = 16'hF000; +defparam \dpwm_shake|Add2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N7 +dffeas \dpwm_shake|new_duty[1] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[1]~13_combout ), + .asdata(\dpwm_shake|cat_duty [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [1]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[1] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N5 +dffeas \dpwm_shake|new_duty[0] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[0]~11_combout ), + .asdata(\dpwm_shake|cat_duty [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [0]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[0] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|Equal1~0 ( +// Equation(s): +// \dpwm_shake|Equal1~0_combout = (\dpwm_shake|cnt [1] & (\dpwm_shake|new_duty [1] & (\dpwm_shake|cnt [0] $ (!\dpwm_shake|new_duty [0])))) # (!\dpwm_shake|cnt [1] & (!\dpwm_shake|new_duty [1] & (\dpwm_shake|cnt [0] $ (!\dpwm_shake|new_duty [0])))) + + .dataa(\dpwm_shake|cnt [1]), + .datab(\dpwm_shake|cnt [0]), + .datac(\dpwm_shake|new_duty [1]), + .datad(\dpwm_shake|new_duty [0]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~0 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N22 +cycloneive_io_ibuf \control[9]~input ( + .i(control[9]), + .ibar(gnd), + .o(\control[9]~input_o )); +// synopsys translate_off +defparam \control[9]~input .bus_hold = "false"; +defparam \control[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|cat_duty~6 ( +// Equation(s): +// \dpwm_shake|cat_duty~6_combout = (\control[9]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[9]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~6_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~6 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N3 +dffeas \dpwm_shake|cat_duty[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N22 +cycloneive_io_ibuf \control[8]~input ( + .i(control[8]), + .ibar(gnd), + .o(\control[8]~input_o )); +// synopsys translate_off +defparam \control[8]~input .bus_hold = "false"; +defparam \control[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|cat_duty~7 ( +// Equation(s): +// \dpwm_shake|cat_duty~7_combout = (\control[8]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[8]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~7_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~7 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N1 +dffeas \dpwm_shake|cat_duty[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[6] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N1 +cycloneive_io_ibuf \control[7]~input ( + .i(control[7]), + .ibar(gnd), + .o(\control[7]~input_o )); +// synopsys translate_off +defparam \control[7]~input .bus_hold = "false"; +defparam \control[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cat_duty~4 ( +// Equation(s): +// \dpwm_shake|cat_duty~4_combout = (\control[7]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[7]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~4_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~4 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N27 +dffeas \dpwm_shake|cat_duty[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \control[6]~input ( + .i(control[6]), + .ibar(gnd), + .o(\control[6]~input_o )); +// synopsys translate_off +defparam \control[6]~input .bus_hold = "false"; +defparam \control[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N28 +cycloneive_lcell_comb \dpwm_shake|cat_duty~5 ( +// Equation(s): +// \dpwm_shake|cat_duty~5_combout = (\control[6]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[6]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~5_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~5 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N29 +dffeas \dpwm_shake|cat_duty[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[4] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N22 +cycloneive_io_ibuf \control[5]~input ( + .i(control[5]), + .ibar(gnd), + .o(\control[5]~input_o )); +// synopsys translate_off +defparam \control[5]~input .bus_hold = "false"; +defparam \control[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|cat_duty~2 ( +// Equation(s): +// \dpwm_shake|cat_duty~2_combout = (\control[5]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[5]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~2 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N17 +dffeas \dpwm_shake|cat_duty[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[3] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N15 +cycloneive_io_ibuf \control[4]~input ( + .i(control[4]), + .ibar(gnd), + .o(\control[4]~input_o )); +// synopsys translate_off +defparam \control[4]~input .bus_hold = "false"; +defparam \control[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N6 +cycloneive_lcell_comb \dpwm_shake|cat_duty~3 ( +// Equation(s): +// \dpwm_shake|cat_duty~3_combout = (\control[4]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[4]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~3 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N7 +dffeas \dpwm_shake|cat_duty[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|new_duty[2]~15 ( +// Equation(s): +// \dpwm_shake|new_duty[2]~15_combout = (\dpwm_shake|cat_duty [2] & (\dpwm_shake|new_duty[1]~14 $ (GND))) # (!\dpwm_shake|cat_duty [2] & (!\dpwm_shake|new_duty[1]~14 & VCC)) +// \dpwm_shake|new_duty[2]~16 = CARRY((\dpwm_shake|cat_duty [2] & !\dpwm_shake|new_duty[1]~14 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [2]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[1]~14 ), + .combout(\dpwm_shake|new_duty[2]~15_combout ), + .cout(\dpwm_shake|new_duty[2]~16 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[2]~15 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[2]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|new_duty[3]~17 ( +// Equation(s): +// \dpwm_shake|new_duty[3]~17_combout = (\dpwm_shake|cat_duty [3] & (!\dpwm_shake|new_duty[2]~16 )) # (!\dpwm_shake|cat_duty [3] & ((\dpwm_shake|new_duty[2]~16 ) # (GND))) +// \dpwm_shake|new_duty[3]~18 = CARRY((!\dpwm_shake|new_duty[2]~16 ) # (!\dpwm_shake|cat_duty [3])) + + .dataa(\dpwm_shake|cat_duty [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[2]~16 ), + .combout(\dpwm_shake|new_duty[3]~17_combout ), + .cout(\dpwm_shake|new_duty[3]~18 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[3]~17 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[3]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N12 +cycloneive_lcell_comb \dpwm_shake|new_duty[4]~19 ( +// Equation(s): +// \dpwm_shake|new_duty[4]~19_combout = (\dpwm_shake|cat_duty [4] & (\dpwm_shake|new_duty[3]~18 $ (GND))) # (!\dpwm_shake|cat_duty [4] & (!\dpwm_shake|new_duty[3]~18 & VCC)) +// \dpwm_shake|new_duty[4]~20 = CARRY((\dpwm_shake|cat_duty [4] & !\dpwm_shake|new_duty[3]~18 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [4]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[3]~18 ), + .combout(\dpwm_shake|new_duty[4]~19_combout ), + .cout(\dpwm_shake|new_duty[4]~20 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[4]~19 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[4]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N14 +cycloneive_lcell_comb \dpwm_shake|new_duty[5]~21 ( +// Equation(s): +// \dpwm_shake|new_duty[5]~21_combout = (\dpwm_shake|cat_duty [5] & (!\dpwm_shake|new_duty[4]~20 )) # (!\dpwm_shake|cat_duty [5] & ((\dpwm_shake|new_duty[4]~20 ) # (GND))) +// \dpwm_shake|new_duty[5]~22 = CARRY((!\dpwm_shake|new_duty[4]~20 ) # (!\dpwm_shake|cat_duty [5])) + + .dataa(\dpwm_shake|cat_duty [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[4]~20 ), + .combout(\dpwm_shake|new_duty[5]~21_combout ), + .cout(\dpwm_shake|new_duty[5]~22 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[5]~21 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[5]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N16 +cycloneive_lcell_comb \dpwm_shake|new_duty[6]~23 ( +// Equation(s): +// \dpwm_shake|new_duty[6]~23_combout = (\dpwm_shake|cat_duty [6] & (\dpwm_shake|new_duty[5]~22 $ (GND))) # (!\dpwm_shake|cat_duty [6] & (!\dpwm_shake|new_duty[5]~22 & VCC)) +// \dpwm_shake|new_duty[6]~24 = CARRY((\dpwm_shake|cat_duty [6] & !\dpwm_shake|new_duty[5]~22 )) + + .dataa(\dpwm_shake|cat_duty [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[5]~22 ), + .combout(\dpwm_shake|new_duty[6]~23_combout ), + .cout(\dpwm_shake|new_duty[6]~24 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[6]~23 .lut_mask = 16'hA50A; +defparam \dpwm_shake|new_duty[6]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|new_duty[7]~25 ( +// Equation(s): +// \dpwm_shake|new_duty[7]~25_combout = (\dpwm_shake|cat_duty [7] & (!\dpwm_shake|new_duty[6]~24 )) # (!\dpwm_shake|cat_duty [7] & ((\dpwm_shake|new_duty[6]~24 ) # (GND))) +// \dpwm_shake|new_duty[7]~26 = CARRY((!\dpwm_shake|new_duty[6]~24 ) # (!\dpwm_shake|cat_duty [7])) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [7]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[6]~24 ), + .combout(\dpwm_shake|new_duty[7]~25_combout ), + .cout(\dpwm_shake|new_duty[7]~26 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[7]~25 .lut_mask = 16'h3C3F; +defparam \dpwm_shake|new_duty[7]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y11_N19 +dffeas \dpwm_shake|new_duty[7] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[7]~25_combout ), + .asdata(\dpwm_shake|cat_duty [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [7]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[7] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N17 +dffeas \dpwm_shake|new_duty[6] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[6]~23_combout ), + .asdata(\dpwm_shake|cat_duty [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [6]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[6] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|Equal1~3 ( +// Equation(s): +// \dpwm_shake|Equal1~3_combout = (\dpwm_shake|new_duty [7] & (\dpwm_shake|cnt [7] & (\dpwm_shake|cnt [6] $ (!\dpwm_shake|new_duty [6])))) # (!\dpwm_shake|new_duty [7] & (!\dpwm_shake|cnt [7] & (\dpwm_shake|cnt [6] $ (!\dpwm_shake|new_duty [6])))) + + .dataa(\dpwm_shake|new_duty [7]), + .datab(\dpwm_shake|cnt [6]), + .datac(\dpwm_shake|cnt [7]), + .datad(\dpwm_shake|new_duty [6]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~3 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N13 +dffeas \dpwm_shake|new_duty[4] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[4]~19_combout ), + .asdata(\dpwm_shake|cat_duty [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [4]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[4] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N15 +dffeas \dpwm_shake|new_duty[5] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[5]~21_combout ), + .asdata(\dpwm_shake|cat_duty [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [5]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[5] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N8 +cycloneive_lcell_comb \dpwm_shake|Equal1~2 ( +// Equation(s): +// \dpwm_shake|Equal1~2_combout = (\dpwm_shake|cnt [4] & (\dpwm_shake|new_duty [4] & (\dpwm_shake|new_duty [5] $ (!\dpwm_shake|cnt [5])))) # (!\dpwm_shake|cnt [4] & (!\dpwm_shake|new_duty [4] & (\dpwm_shake|new_duty [5] $ (!\dpwm_shake|cnt [5])))) + + .dataa(\dpwm_shake|cnt [4]), + .datab(\dpwm_shake|new_duty [4]), + .datac(\dpwm_shake|new_duty [5]), + .datad(\dpwm_shake|cnt [5]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~2 .lut_mask = 16'h9009; +defparam \dpwm_shake|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N11 +dffeas \dpwm_shake|new_duty[3] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[3]~17_combout ), + .asdata(\dpwm_shake|cat_duty [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [3]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[3] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N9 +dffeas \dpwm_shake|new_duty[2] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[2]~15_combout ), + .asdata(\dpwm_shake|cat_duty [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [2]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[2] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N10 +cycloneive_lcell_comb \dpwm_shake|Equal1~1 ( +// Equation(s): +// \dpwm_shake|Equal1~1_combout = (\dpwm_shake|cnt [2] & (\dpwm_shake|new_duty [2] & (\dpwm_shake|new_duty [3] $ (!\dpwm_shake|cnt [3])))) # (!\dpwm_shake|cnt [2] & (!\dpwm_shake|new_duty [2] & (\dpwm_shake|new_duty [3] $ (!\dpwm_shake|cnt [3])))) + + .dataa(\dpwm_shake|cnt [2]), + .datab(\dpwm_shake|new_duty [3]), + .datac(\dpwm_shake|new_duty [2]), + .datad(\dpwm_shake|cnt [3]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~1 .lut_mask = 16'h8421; +defparam \dpwm_shake|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|Equal1~4 ( +// Equation(s): +// \dpwm_shake|Equal1~4_combout = (\dpwm_shake|Equal1~0_combout & (\dpwm_shake|Equal1~3_combout & (\dpwm_shake|Equal1~2_combout & \dpwm_shake|Equal1~1_combout ))) + + .dataa(\dpwm_shake|Equal1~0_combout ), + .datab(\dpwm_shake|Equal1~3_combout ), + .datac(\dpwm_shake|Equal1~2_combout ), + .datad(\dpwm_shake|Equal1~1_combout ), + .cin(gnd), + .combout(\dpwm_shake|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~4 .lut_mask = 16'h8000; +defparam \dpwm_shake|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N1 +cycloneive_io_ibuf \control[12]~input ( + .i(control[12]), + .ibar(gnd), + .o(\control[12]~input_o )); +// synopsys translate_off +defparam \control[12]~input .bus_hold = "false"; +defparam \control[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N4 +cycloneive_lcell_comb \dpwm_shake|cat_duty~10 ( +// Equation(s): +// \dpwm_shake|cat_duty~10_combout = (\control[12]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[12]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~10_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~10 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N5 +dffeas \dpwm_shake|cat_duty[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~10_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N15 +cycloneive_io_ibuf \control[11]~input ( + .i(control[11]), + .ibar(gnd), + .o(\control[11]~input_o )); +// synopsys translate_off +defparam \control[11]~input .bus_hold = "false"; +defparam \control[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N26 +cycloneive_lcell_comb \dpwm_shake|cat_duty~8 ( +// Equation(s): +// \dpwm_shake|cat_duty~8_combout = (\control[11]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\rst_n~input_o ), + .datab(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datac(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .datad(\control[11]~input_o ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~8_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~8 .lut_mask = 16'hEA00; +defparam \dpwm_shake|cat_duty~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X2_Y11_N27 +dffeas \dpwm_shake|cat_duty[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[9] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y6_N22 +cycloneive_io_ibuf \control[10]~input ( + .i(control[10]), + .ibar(gnd), + .o(\control[10]~input_o )); +// synopsys translate_off +defparam \control[10]~input .bus_hold = "false"; +defparam \control[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|cat_duty~9 ( +// Equation(s): +// \dpwm_shake|cat_duty~9_combout = (\control[10]~input_o & ((\rst_n~input_o ) # ((\pwm_pll|altpll_component|auto_generated|wire_pll1_locked & \pwm_pll|altpll_component|auto_generated|pll_lock_sync~q )))) + + .dataa(\pwm_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\control[10]~input_o ), + .datac(\rst_n~input_o ), + .datad(\pwm_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\dpwm_shake|cat_duty~9_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|cat_duty~9 .lut_mask = 16'hC8C0; +defparam \dpwm_shake|cat_duty~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X3_Y11_N1 +dffeas \dpwm_shake|cat_duty[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|cat_duty~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|cat_duty [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|cat_duty[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|cat_duty[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N20 +cycloneive_lcell_comb \dpwm_shake|new_duty[8]~27 ( +// Equation(s): +// \dpwm_shake|new_duty[8]~27_combout = (\dpwm_shake|cat_duty [8] & (\dpwm_shake|new_duty[7]~26 $ (GND))) # (!\dpwm_shake|cat_duty [8] & (!\dpwm_shake|new_duty[7]~26 & VCC)) +// \dpwm_shake|new_duty[8]~28 = CARRY((\dpwm_shake|cat_duty [8] & !\dpwm_shake|new_duty[7]~26 )) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [8]), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[7]~26 ), + .combout(\dpwm_shake|new_duty[8]~27_combout ), + .cout(\dpwm_shake|new_duty[8]~28 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[8]~27 .lut_mask = 16'hC30C; +defparam \dpwm_shake|new_duty[8]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N22 +cycloneive_lcell_comb \dpwm_shake|new_duty[9]~29 ( +// Equation(s): +// \dpwm_shake|new_duty[9]~29_combout = (\dpwm_shake|cat_duty [9] & (!\dpwm_shake|new_duty[8]~28 )) # (!\dpwm_shake|cat_duty [9] & ((\dpwm_shake|new_duty[8]~28 ) # (GND))) +// \dpwm_shake|new_duty[9]~30 = CARRY((!\dpwm_shake|new_duty[8]~28 ) # (!\dpwm_shake|cat_duty [9])) + + .dataa(\dpwm_shake|cat_duty [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\dpwm_shake|new_duty[8]~28 ), + .combout(\dpwm_shake|new_duty[9]~29_combout ), + .cout(\dpwm_shake|new_duty[9]~30 )); +// synopsys translate_off +defparam \dpwm_shake|new_duty[9]~29 .lut_mask = 16'h5A5F; +defparam \dpwm_shake|new_duty[9]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y11_N24 +cycloneive_lcell_comb \dpwm_shake|new_duty[10]~31 ( +// Equation(s): +// \dpwm_shake|new_duty[10]~31_combout = \dpwm_shake|cat_duty [10] $ (!\dpwm_shake|new_duty[9]~30 ) + + .dataa(gnd), + .datab(\dpwm_shake|cat_duty [10]), + .datac(gnd), + .datad(gnd), + .cin(\dpwm_shake|new_duty[9]~30 ), + .combout(\dpwm_shake|new_duty[10]~31_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|new_duty[10]~31 .lut_mask = 16'hC3C3; +defparam \dpwm_shake|new_duty[10]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X3_Y11_N25 +dffeas \dpwm_shake|new_duty[10] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[10]~31_combout ), + .asdata(\dpwm_shake|cat_duty [10]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [10]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[10] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N21 +dffeas \dpwm_shake|new_duty[8] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[8]~27_combout ), + .asdata(\dpwm_shake|cat_duty [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [8]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[8] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X3_Y11_N23 +dffeas \dpwm_shake|new_duty[9] ( + .clk(\pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\dpwm_shake|new_duty[9]~29_combout ), + .asdata(\dpwm_shake|cat_duty [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(\dpwm_shake|Add2~3_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\dpwm_shake|new_duty [9]), + .prn(vcc)); +// synopsys translate_off +defparam \dpwm_shake|new_duty[9] .is_wysiwyg = "true"; +defparam \dpwm_shake|new_duty[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|Equal1~5 ( +// Equation(s): +// \dpwm_shake|Equal1~5_combout = (\dpwm_shake|cnt [9] & (\dpwm_shake|new_duty [9] & (\dpwm_shake|cnt [8] $ (!\dpwm_shake|new_duty [8])))) # (!\dpwm_shake|cnt [9] & (!\dpwm_shake|new_duty [9] & (\dpwm_shake|cnt [8] $ (!\dpwm_shake|new_duty [8])))) + + .dataa(\dpwm_shake|cnt [9]), + .datab(\dpwm_shake|cnt [8]), + .datac(\dpwm_shake|new_duty [8]), + .datad(\dpwm_shake|new_duty [9]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~5 .lut_mask = 16'h8241; +defparam \dpwm_shake|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N18 +cycloneive_lcell_comb \dpwm_shake|Equal1~6 ( +// Equation(s): +// \dpwm_shake|Equal1~6_combout = (\dpwm_shake|Equal1~4_combout & (\dpwm_shake|Equal1~5_combout & (\dpwm_shake|new_duty [10] $ (!\dpwm_shake|cnt [10])))) + + .dataa(\dpwm_shake|Equal1~4_combout ), + .datab(\dpwm_shake|new_duty [10]), + .datac(\dpwm_shake|Equal1~5_combout ), + .datad(\dpwm_shake|cnt [10]), + .cin(gnd), + .combout(\dpwm_shake|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|Equal1~6 .lut_mask = 16'h8020; +defparam \dpwm_shake|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y11_N2 +cycloneive_lcell_comb \dpwm_shake|tmp_q ( +// Equation(s): +// \dpwm_shake|tmp_q~combout = (\dpwm_shake|Equal0~0_combout & (\dpwm_shake|Equal0~2_combout & (\dpwm_shake|Equal0~1_combout & !\dpwm_shake|Equal1~6_combout ))) + + .dataa(\dpwm_shake|Equal0~0_combout ), + .datab(\dpwm_shake|Equal0~2_combout ), + .datac(\dpwm_shake|Equal0~1_combout ), + .datad(\dpwm_shake|Equal1~6_combout ), + .cin(gnd), + .combout(\dpwm_shake|tmp_q~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|tmp_q .lut_mask = 16'h0080; +defparam \dpwm_shake|tmp_q .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N0 +cycloneive_lcell_comb \dpwm_shake|pwm_out~2 ( +// Equation(s): +// \dpwm_shake|pwm_out~2_combout = (\dpwm_shake|Equal1~6_combout ) # ((\dpwm_shake|Equal0~1_combout & (\dpwm_shake|Equal0~0_combout & \dpwm_shake|Equal0~2_combout ))) + + .dataa(\dpwm_shake|Equal0~1_combout ), + .datab(\dpwm_shake|Equal0~0_combout ), + .datac(\dpwm_shake|Equal0~2_combout ), + .datad(\dpwm_shake|Equal1~6_combout ), + .cin(gnd), + .combout(\dpwm_shake|pwm_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|pwm_out~2 .lut_mask = 16'hFF80; +defparam \dpwm_shake|pwm_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y11_N30 +cycloneive_lcell_comb \dpwm_shake|pwm_out ( +// Equation(s): +// \dpwm_shake|pwm_out~combout = (\dpwm_shake|pwm_out~2_combout & ((\dpwm_shake|tmp_q~combout ))) # (!\dpwm_shake|pwm_out~2_combout & (\dpwm_shake|pwm_out~combout )) + + .dataa(\dpwm_shake|pwm_out~combout ), + .datab(\dpwm_shake|tmp_q~combout ), + .datac(gnd), + .datad(\dpwm_shake|pwm_out~2_combout ), + .cin(gnd), + .combout(\dpwm_shake|pwm_out~combout ), + .cout()); +// synopsys translate_off +defparam \dpwm_shake|pwm_out .lut_mask = 16'hCCAA; +defparam \dpwm_shake|pwm_out .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_min_1200mv_0c_v_fast.sdo b/dpwm_shake/simulation/modelsim/dpwm_shake_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..26f7106 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,1779 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE10F17C8, +// with speed grade M, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "dpwm_top") + (DATE "12/08/2018 18:51:18") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (333:333:333) (377:377:377)) + (IOPATH i o (1599:1599:1599) (1624:1624:1624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out_n\~output) + (DELAY + (ABSOLUTE + (PORT i (377:377:377) (333:333:333)) + (IOPATH i o (1624:1624:1624) (1599:1599:1599)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (108:108:108) (89:89:89)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (624:624:624) (624:624:624)) + (PORT inclk[0] (1111:1111:1111) (1111:1111:1111)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1121:1121:1121) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT datad (210:210:210) (257:257:257)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1106:1106:1106) (998:998:998)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (776:776:776) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_all) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (333:333:333)) + (PORT datac (947:947:947) (824:824:824)) + (PORT datad (325:325:325) (387:387:387)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_all\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (409:409:409) (431:431:431)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT asdata (339:339:339) (369:369:369)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (201:201:201)) + (PORT datab (511:511:511) (588:588:588)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (966:966:966) (1008:1008:1008)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (198:198:198)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (197:197:197)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (199:199:199)) + (PORT datab (146:146:146) (195:195:195)) + (PORT datac (130:130:130) (172:172:172)) + (PORT datad (133:133:133) (172:172:172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (158:158:158) (208:208:208)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (150:150:150) (202:202:202)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (159:159:159) (208:208:208)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (153:153:153) (207:207:207)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[8\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (196:196:196)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (966:966:966) (1008:1008:1008)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[9\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (200:200:200)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[10\]\~28) + (DELAY + (ABSOLUTE + (PORT datad (210:210:210) (252:252:252)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (148:148:148) (198:198:198)) + (PORT datac (135:135:135) (179:179:179)) + (PORT datad (143:143:143) (180:180:180)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (210:210:210)) + (PORT datab (159:159:159) (208:208:208)) + (PORT datac (211:211:211) (255:255:255)) + (PORT datad (138:138:138) (180:180:180)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (736:736:736)) + (PORT datab (330:330:330) (304:304:304)) + (PORT datac (337:337:337) (312:312:312)) + (PORT datad (341:341:341) (409:409:409)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (953:953:953) (987:987:987)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (291:291:291)) + (PORT datab (222:222:222) (278:278:278)) + (PORT datac (301:301:301) (356:356:356)) + (PORT datad (211:211:211) (261:261:261)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (279:279:279)) + (PORT datab (161:161:161) (211:211:211)) + (PORT datac (141:141:141) (188:188:188)) + (PORT datad (140:140:140) (181:181:181)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (402:402:402)) + (PORT datab (232:232:232) (286:286:286)) + (PORT datac (213:213:213) (267:267:267)) + (PORT datad (167:167:167) (195:195:195)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_count\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (330:330:330)) + (PORT datad (266:266:266) (300:300:300)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_count\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (330:330:330)) + (PORT datab (143:143:143) (197:197:197)) + (PORT datad (266:266:266) (299:299:299)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (749:749:749) (768:768:768)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (658:658:658)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1711:1711:1711) (1911:1911:1911)) + (PORT datab (975:975:975) (845:845:845)) + (PORT datac (341:341:341) (314:314:314)) + (PORT datad (333:333:333) (397:397:397)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_ctr\~1) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (331:331:331)) + (PORT datab (975:975:975) (845:845:845)) + (PORT datac (1740:1740:1740) (1942:1942:1942)) + (PORT datad (333:333:333) (396:396:396)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_ctr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (966:966:966) (1008:1008:1008)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~2) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (331:331:331)) + (PORT datab (139:139:139) (192:192:192)) + (PORT datac (951:951:951) (827:827:827)) + (PORT datad (331:331:331) (395:395:395)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~2) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (192:192:192)) + (PORT datac (136:136:136) (181:181:181)) + (PORT datad (119:119:119) (157:157:157)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_ctr\~0) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (333:333:333)) + (PORT datab (971:971:971) (841:841:841)) + (PORT datac (1685:1685:1685) (1869:1869:1869)) + (PORT datad (326:326:326) (388:388:388)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_ctr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (966:966:966) (1008:1008:1008)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~0) + (DELAY + (ABSOLUTE + (PORT datab (143:143:143) (196:196:196)) + (PORT datac (107:107:107) (130:130:130)) + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (199:199:199)) + (PORT datab (132:132:132) (180:180:180)) + (PORT datac (126:126:126) (171:171:171)) + (PORT datad (130:130:130) (172:172:172)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~1) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (193:193:193)) + (PORT datac (109:109:109) (133:133:133)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT datab (143:143:143) (197:197:197)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (219:219:219)) + (PORT datab (175:175:175) (215:215:215)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (194:194:194)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT datac (125:125:125) (170:170:170)) + (PORT datad (130:130:130) (174:174:174)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (953:953:953) (987:987:987)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (302:302:302) (345:345:345)) + (PORT sload (488:488:488) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (394:394:394) (446:446:446)) + (PORT sload (488:488:488) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (287:287:287)) + (PORT datab (224:224:224) (281:281:281)) + (PORT datac (266:266:266) (319:319:319)) + (PORT datad (197:197:197) (248:248:248)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~6) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (733:733:733)) + (PORT datab (1734:1734:1734) (1935:1935:1935)) + (PORT datac (340:340:340) (314:314:314)) + (PORT datad (332:332:332) (399:399:399)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (953:953:953) (987:987:987)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~7) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (330:330:330)) + (PORT datab (1099:1099:1099) (944:944:944)) + (PORT datac (351:351:351) (427:427:427)) + (PORT datad (1653:1653:1653) (1830:1830:1830)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (668:668:668)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~4) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (735:735:735)) + (PORT datab (1741:1741:1741) (1942:1942:1942)) + (PORT datac (337:337:337) (312:312:312)) + (PORT datad (340:340:340) (408:408:408)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (953:953:953) (987:987:987)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~5) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (735:735:735)) + (PORT datab (1771:1771:1771) (1977:1977:1977)) + (PORT datac (337:337:337) (312:312:312)) + (PORT datad (340:340:340) (408:408:408)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (953:953:953) (987:987:987)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (688:688:688)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~2) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (327:327:327)) + (PORT datab (1102:1102:1102) (946:946:946)) + (PORT datac (356:356:356) (432:432:432)) + (PORT datad (1756:1756:1756) (1969:1969:1969)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~3) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (329:329:329)) + (PORT datab (1100:1100:1100) (944:944:944)) + (PORT datac (353:353:353) (429:429:429)) + (PORT datad (1826:1826:1826) (2030:2030:2030)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (204:204:204) (260:260:260)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (282:282:282)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (193:193:193)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[5\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (192:192:192)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (278:278:278)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (193:193:193)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (953:953:953) (987:987:987)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (713:713:713) (792:792:792)) + (PORT sload (488:488:488) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (376:376:376) (429:429:429)) + (PORT sload (488:488:488) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (349:349:349)) + (PORT datab (234:234:234) (287:287:287)) + (PORT datac (293:293:293) (342:342:342)) + (PORT datad (187:187:187) (234:234:234)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (953:953:953) (987:987:987)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (378:378:378) (422:422:422)) + (PORT sload (488:488:488) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (953:953:953) (987:987:987)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (300:300:300) (342:342:342)) + (PORT sload (488:488:488) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (277:277:277)) + (PORT datab (215:215:215) (273:273:273)) + (PORT datac (199:199:199) (253:253:253)) + (PORT datad (196:196:196) (239:239:239)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (380:380:380) (434:434:434)) + (PORT sload (488:488:488) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (367:367:367) (414:414:414)) + (PORT sload (488:488:488) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (286:286:286)) + (PORT datab (200:200:200) (259:259:259)) + (PORT datac (199:199:199) (253:253:253)) + (PORT datad (204:204:204) (247:247:247)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (103:103:103) (130:130:130)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (668:668:668)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~10) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (329:329:329)) + (PORT datab (1100:1100:1100) (944:944:944)) + (PORT datac (352:352:352) (428:428:428)) + (PORT datad (1663:1663:1663) (1845:1845:1845)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~8) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (325:325:325)) + (PORT datab (1104:1104:1104) (948:948:948)) + (PORT datac (359:359:359) (435:435:435)) + (PORT datad (1684:1684:1684) (1871:1871:1871)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (765:765:765) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (688:688:688)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~9) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (733:733:733)) + (PORT datab (1845:1845:1845) (2058:2058:2058)) + (PORT datac (340:340:340) (315:315:315)) + (PORT datad (332:332:332) (399:399:399)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (953:953:953) (987:987:987)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[8\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (194:194:194)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[9\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (279:279:279)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[10\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (210:210:210) (269:269:269)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (372:372:372) (422:422:422)) + (PORT sload (488:488:488) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (953:953:953) (987:987:987)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (472:472:472) (520:520:520)) + (PORT sload (488:488:488) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (784:784:784)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (377:377:377) (431:431:431)) + (PORT sload (488:488:488) (541:541:541)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (286:286:286)) + (PORT datab (228:228:228) (282:282:282)) + (PORT datac (186:186:186) (238:238:238)) + (PORT datad (197:197:197) (248:248:248)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (215:215:215) (273:273:273)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (220:220:220) (267:267:267)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|tmp_q) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (329:329:329)) + (PORT datab (182:182:182) (216:216:216)) + (PORT datac (372:372:372) (419:419:419)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|pwm_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (115:115:115) (146:146:146)) + (PORT datab (115:115:115) (143:143:143)) + (PORT datac (101:101:101) (122:122:122)) + (PORT datad (186:186:186) (215:215:215)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|pwm_out) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (324:324:324)) + (PORT datab (262:262:262) (308:308:308)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) +) diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_modelsim.xrf b/dpwm_shake/simulation/modelsim/dpwm_shake_modelsim.xrf new file mode 100644 index 0000000..df1b2a2 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_modelsim.xrf @@ -0,0 +1,143 @@ +vendor_name = ModelSim +source_file = 1, F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v +source_file = 1, F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.qip +source_file = 1, F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v +source_file = 1, F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v +source_file = 1, F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v +source_file = 1, F:/Code/FPGA/reserve/dpwm_shake/dpwm_shake.out.sdc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/altpll.tdf +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/aglobal181.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/stratix_pll.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/stratixii_pll.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/cycloneii_pll.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/cbx.lst +source_file = 1, F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v +design_name = dpwm_top +instance = comp, \pwm_out~output , pwm_out~output, dpwm_top, 1 +instance = comp, \pwm_out_n~output , pwm_out_n~output, dpwm_top, 1 +instance = comp, \~ALTERA_DCLK~~obuf , ~ALTERA_DCLK~~obuf, dpwm_top, 1 +instance = comp, \~ALTERA_nCEO~~obuf , ~ALTERA_nCEO~~obuf, dpwm_top, 1 +instance = comp, \rst_n~input , rst_n~input, dpwm_top, 1 +instance = comp, \rst_n~inputclkctrl , rst_n~inputclkctrl, dpwm_top, 1 +instance = comp, \clk~input , clk~input, dpwm_top, 1 +instance = comp, \pwm_pll|altpll_component|auto_generated|pll1 , pwm_pll|altpll_component|auto_generated|pll1, dpwm_top, 1 +instance = comp, \pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , pwm_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[0]~30 , dpwm_shake|cnt[0]~30, dpwm_top, 1 +instance = comp, \pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder , pwm_pll|altpll_component|auto_generated|pll_lock_sync~feeder, dpwm_top, 1 +instance = comp, \pwm_pll|altpll_component|auto_generated|pll_lock_sync , pwm_pll|altpll_component|auto_generated|pll_lock_sync, dpwm_top, 1 +instance = comp, \rst_all~clkctrl , rst_all~clkctrl, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[0] , dpwm_shake|cnt[0], dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[1]~10 , dpwm_shake|cnt[1]~10, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[1] , dpwm_shake|cnt[1], dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[2]~12 , dpwm_shake|cnt[2]~12, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[2] , dpwm_shake|cnt[2], dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[3]~14 , dpwm_shake|cnt[3]~14, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[3] , dpwm_shake|cnt[3], dpwm_top, 1 +instance = comp, \dpwm_shake|Equal0~0 , dpwm_shake|Equal0~0, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[4]~16 , dpwm_shake|cnt[4]~16, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[4] , dpwm_shake|cnt[4], dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[5]~18 , dpwm_shake|cnt[5]~18, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[5] , dpwm_shake|cnt[5], dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[6]~20 , dpwm_shake|cnt[6]~20, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[6] , dpwm_shake|cnt[6], dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[7]~22 , dpwm_shake|cnt[7]~22, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[7] , dpwm_shake|cnt[7], dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[8]~24 , dpwm_shake|cnt[8]~24, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[8] , dpwm_shake|cnt[8], dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[9]~26 , dpwm_shake|cnt[9]~26, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[9] , dpwm_shake|cnt[9], dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[10]~28 , dpwm_shake|cnt[10]~28, dpwm_top, 1 +instance = comp, \dpwm_shake|cnt[10] , dpwm_shake|cnt[10], dpwm_top, 1 +instance = comp, \dpwm_shake|Equal0~2 , dpwm_shake|Equal0~2, dpwm_top, 1 +instance = comp, \dpwm_shake|Equal0~1 , dpwm_shake|Equal0~1, dpwm_top, 1 +instance = comp, \control[3]~input , control[3]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty~0 , dpwm_shake|cat_duty~0, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty[1] , dpwm_shake|cat_duty[1], dpwm_top, 1 +instance = comp, \dpwm_shake|Equal2~0 , dpwm_shake|Equal2~0, dpwm_top, 1 +instance = comp, \dpwm_shake|Equal2~1 , dpwm_shake|Equal2~1, dpwm_top, 1 +instance = comp, \dpwm_shake|Equal2~2 , dpwm_shake|Equal2~2, dpwm_top, 1 +instance = comp, \dpwm_shake|shake_count[0]~1 , dpwm_shake|shake_count[0]~1, dpwm_top, 1 +instance = comp, \dpwm_shake|shake_count[0] , dpwm_shake|shake_count[0], dpwm_top, 1 +instance = comp, \dpwm_shake|shake_count[1]~0 , dpwm_shake|shake_count[1]~0, dpwm_top, 1 +instance = comp, \dpwm_shake|shake_count[1] , dpwm_shake|shake_count[1], dpwm_top, 1 +instance = comp, \control[2]~input , control[2]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty~1 , dpwm_shake|cat_duty~1, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty[0] , dpwm_shake|cat_duty[0], dpwm_top, 1 +instance = comp, \control[1]~input , control[1]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|shake_ctr~1 , dpwm_shake|shake_ctr~1, dpwm_top, 1 +instance = comp, \dpwm_shake|shake_ctr[1] , dpwm_shake|shake_ctr[1], dpwm_top, 1 +instance = comp, \dpwm_shake|shakenum~2 , dpwm_shake|shakenum~2, dpwm_top, 1 +instance = comp, \dpwm_shake|shakenum[2] , dpwm_shake|shakenum[2], dpwm_top, 1 +instance = comp, \dpwm_shake|Add2~2 , dpwm_shake|Add2~2, dpwm_top, 1 +instance = comp, \control[0]~input , control[0]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|shake_ctr~0 , dpwm_shake|shake_ctr~0, dpwm_top, 1 +instance = comp, \dpwm_shake|shake_ctr[0] , dpwm_shake|shake_ctr[0], dpwm_top, 1 +instance = comp, \dpwm_shake|shakenum~0 , dpwm_shake|shakenum~0, dpwm_top, 1 +instance = comp, \dpwm_shake|shakenum[0] , dpwm_shake|shakenum[0], dpwm_top, 1 +instance = comp, \dpwm_shake|Add2~0 , dpwm_shake|Add2~0, dpwm_top, 1 +instance = comp, \dpwm_shake|shakenum~1 , dpwm_shake|shakenum~1, dpwm_top, 1 +instance = comp, \dpwm_shake|shakenum[1] , dpwm_shake|shakenum[1], dpwm_top, 1 +instance = comp, \dpwm_shake|Add2~1 , dpwm_shake|Add2~1, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[0]~11 , dpwm_shake|new_duty[0]~11, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[1]~13 , dpwm_shake|new_duty[1]~13, dpwm_top, 1 +instance = comp, \dpwm_shake|Add2~3 , dpwm_shake|Add2~3, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[1] , dpwm_shake|new_duty[1], dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[0] , dpwm_shake|new_duty[0], dpwm_top, 1 +instance = comp, \dpwm_shake|Equal1~0 , dpwm_shake|Equal1~0, dpwm_top, 1 +instance = comp, \control[9]~input , control[9]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty~6 , dpwm_shake|cat_duty~6, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty[7] , dpwm_shake|cat_duty[7], dpwm_top, 1 +instance = comp, \control[8]~input , control[8]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty~7 , dpwm_shake|cat_duty~7, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty[6] , dpwm_shake|cat_duty[6], dpwm_top, 1 +instance = comp, \control[7]~input , control[7]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty~4 , dpwm_shake|cat_duty~4, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty[5] , dpwm_shake|cat_duty[5], dpwm_top, 1 +instance = comp, \control[6]~input , control[6]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty~5 , dpwm_shake|cat_duty~5, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty[4] , dpwm_shake|cat_duty[4], dpwm_top, 1 +instance = comp, \control[5]~input , control[5]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty~2 , dpwm_shake|cat_duty~2, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty[3] , dpwm_shake|cat_duty[3], dpwm_top, 1 +instance = comp, \control[4]~input , control[4]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty~3 , dpwm_shake|cat_duty~3, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty[2] , dpwm_shake|cat_duty[2], dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[2]~15 , dpwm_shake|new_duty[2]~15, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[3]~17 , dpwm_shake|new_duty[3]~17, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[4]~19 , dpwm_shake|new_duty[4]~19, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[5]~21 , dpwm_shake|new_duty[5]~21, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[6]~23 , dpwm_shake|new_duty[6]~23, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[7]~25 , dpwm_shake|new_duty[7]~25, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[7] , dpwm_shake|new_duty[7], dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[6] , dpwm_shake|new_duty[6], dpwm_top, 1 +instance = comp, \dpwm_shake|Equal1~3 , dpwm_shake|Equal1~3, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[4] , dpwm_shake|new_duty[4], dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[5] , dpwm_shake|new_duty[5], dpwm_top, 1 +instance = comp, \dpwm_shake|Equal1~2 , dpwm_shake|Equal1~2, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[3] , dpwm_shake|new_duty[3], dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[2] , dpwm_shake|new_duty[2], dpwm_top, 1 +instance = comp, \dpwm_shake|Equal1~1 , dpwm_shake|Equal1~1, dpwm_top, 1 +instance = comp, \dpwm_shake|Equal1~4 , dpwm_shake|Equal1~4, dpwm_top, 1 +instance = comp, \control[12]~input , control[12]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty~10 , dpwm_shake|cat_duty~10, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty[10] , dpwm_shake|cat_duty[10], dpwm_top, 1 +instance = comp, \control[11]~input , control[11]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty~8 , dpwm_shake|cat_duty~8, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty[9] , dpwm_shake|cat_duty[9], dpwm_top, 1 +instance = comp, \control[10]~input , control[10]~input, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty~9 , dpwm_shake|cat_duty~9, dpwm_top, 1 +instance = comp, \dpwm_shake|cat_duty[8] , dpwm_shake|cat_duty[8], dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[8]~27 , dpwm_shake|new_duty[8]~27, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[9]~29 , dpwm_shake|new_duty[9]~29, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[10]~31 , dpwm_shake|new_duty[10]~31, dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[10] , dpwm_shake|new_duty[10], dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[8] , dpwm_shake|new_duty[8], dpwm_top, 1 +instance = comp, \dpwm_shake|new_duty[9] , dpwm_shake|new_duty[9], dpwm_top, 1 +instance = comp, \dpwm_shake|Equal1~5 , dpwm_shake|Equal1~5, dpwm_top, 1 +instance = comp, \dpwm_shake|Equal1~6 , dpwm_shake|Equal1~6, dpwm_top, 1 +instance = comp, \dpwm_shake|tmp_q , dpwm_shake|tmp_q, dpwm_top, 1 +instance = comp, \dpwm_shake|pwm_out~2 , dpwm_shake|pwm_out~2, dpwm_top, 1 +instance = comp, \dpwm_shake|pwm_out , dpwm_shake|pwm_out, dpwm_top, 1 +instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, dpwm_top, 1 +instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, dpwm_top, 1 +instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, dpwm_top, 1 diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do new file mode 100644 index 0000000..9543695 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_shake_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak new file mode 100644 index 0000000..9543695 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_shake_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak1 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak1 new file mode 100644 index 0000000..9543695 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak1 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_shake_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak2 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak2 new file mode 100644 index 0000000..9543695 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak2 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_shake_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak3 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak3 new file mode 100644 index 0000000..9543695 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak3 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_shake_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak4 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak4 new file mode 100644 index 0000000..9543695 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak4 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_shake_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak5 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak5 new file mode 100644 index 0000000..9543695 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak5 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_shake_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak6 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak6 new file mode 100644 index 0000000..9543695 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak6 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_shake_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak7 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak7 new file mode 100644 index 0000000..9543695 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_gate_verilog.do.bak7 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {dpwm_shake_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do new file mode 100644 index 0000000..c405643 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/ip {F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/db {F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak new file mode 100644 index 0000000..054a4e8 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak @@ -0,0 +1,9 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} + diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak1 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak1 new file mode 100644 index 0000000..c79229b --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak1 @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak10 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak10 new file mode 100644 index 0000000..c405643 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak10 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/ip {F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/db {F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak11 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak11 new file mode 100644 index 0000000..c405643 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak11 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/ip {F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/db {F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak2 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak2 new file mode 100644 index 0000000..c405643 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak2 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/ip {F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/db {F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak3 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak3 new file mode 100644 index 0000000..c405643 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak3 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/ip {F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/db {F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak4 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak4 new file mode 100644 index 0000000..c405643 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak4 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/ip {F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/db {F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak5 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak5 new file mode 100644 index 0000000..c405643 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak5 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/ip {F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/db {F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak6 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak6 new file mode 100644 index 0000000..c405643 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak6 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/ip {F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/db {F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak7 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak7 new file mode 100644 index 0000000..c405643 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak7 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/ip {F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/db {F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak8 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak8 new file mode 100644 index 0000000..c405643 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak8 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/ip {F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/db {F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak9 b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak9 new file mode 100644 index 0000000..c405643 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_run_msim_rtl_verilog.do.bak9 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_shake.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/ip {F:/Code/FPGA/reserve/dpwm_shake/ip/pwm_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl {F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/db {F:/Code/FPGA/reserve/dpwm_shake/db/pwm_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" dpwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/dpwm_shake/simulation/modelsim/dpwm_shake_v.sdo b/dpwm_shake/simulation/modelsim/dpwm_shake_v.sdo new file mode 100644 index 0000000..11d0561 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/dpwm_shake_v.sdo @@ -0,0 +1,1779 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "dpwm_top") + (DATE "12/08/2018 18:51:18") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (838:838:838) (779:779:779)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE pwm_out_n\~output) + (DELAY + (ABSOLUTE + (PORT i (779:779:779) (838:838:838)) + (IOPATH i o (3115:3115:3115) (3138:3138:3138)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (1343:1343:1343) (1343:1343:1343)) + (PORT inclk[0] (2336:2336:2336) (2336:2336:2336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2340:2340:2340) (2307:2307:2307)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[0\]\~30) + (DELAY + (ABSOLUTE + (PORT datad (548:548:548) (577:577:577)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE pwm_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2270:2270:2270) (2446:2446:2446)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_all) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (849:849:849)) + (PORT datac (1887:1887:1887) (2069:2069:2069)) + (PORT datad (849:849:849) (836:836:836)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_all\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1021:1021:1021) (966:966:966)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT asdata (913:913:913) (886:886:886)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (1411:1411:1411) (1261:1261:1261)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2126:2126:2126) (2140:2140:2140)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (458:458:458)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (451:451:451)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (459:459:459)) + (PORT datab (366:366:366) (449:449:449)) + (PORT datac (319:319:319) (397:397:397)) + (PORT datad (327:327:327) (404:404:404)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (476:476:476)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (460:460:460)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (393:393:393) (476:476:476)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (378:378:378) (473:473:473)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[8\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (449:449:449)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (2126:2126:2126) (2140:2140:2140)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[9\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (457:457:457)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cnt\[10\]\~28) + (DELAY + (ABSOLUTE + (PORT datad (549:549:549) (572:572:572)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (328:328:328) (412:412:412)) + (PORT datad (346:346:346) (417:417:417)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (473:473:473)) + (PORT datab (391:391:391) (474:474:474)) + (PORT datac (555:555:555) (574:574:574)) + (PORT datad (337:337:337) (418:418:418)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1689:1689:1689) (1806:1806:1806)) + (PORT datab (685:685:685) (798:798:798)) + (PORT datac (705:705:705) (800:800:800)) + (PORT datad (881:881:881) (870:870:870)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (647:647:647)) + (PORT datab (586:586:586) (618:618:618)) + (PORT datac (801:801:801) (779:779:779)) + (PORT datad (560:560:560) (584:584:584)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (622:622:622)) + (PORT datab (394:394:394) (478:478:478)) + (PORT datac (338:338:338) (430:430:430)) + (PORT datad (338:338:338) (419:419:419)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (878:878:878)) + (PORT datab (625:625:625) (633:633:633)) + (PORT datac (573:573:573) (593:593:593)) + (PORT datad (467:467:467) (434:434:434)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_count\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (701:701:701)) + (PORT datad (709:709:709) (646:646:646)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_count\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_count\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (702:702:702)) + (PORT datab (362:362:362) (452:452:452)) + (PORT datad (708:708:708) (645:645:645)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_count\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1663:1663:1663) (1657:1657:1657)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (726:726:726) (772:772:772)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~1) + (DELAY + (ABSOLUTE + (PORT dataa (3677:3677:3677) (3814:3814:3814)) + (PORT datab (1933:1933:1933) (2119:2119:2119)) + (PORT datac (714:714:714) (802:802:802)) + (PORT datad (859:859:859) (848:848:848)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_ctr\~1) + (DELAY + (ABSOLUTE + (PORT dataa (761:761:761) (847:847:847)) + (PORT datab (1932:1932:1932) (2118:2118:2118)) + (PORT datac (3672:3672:3672) (3852:3852:3852)) + (PORT datad (858:858:858) (847:847:847)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_ctr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2125:2125:2125) (2139:2139:2139)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~2) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (848:848:848)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (1891:1891:1891) (2072:2072:2072)) + (PORT datad (857:857:857) (845:845:845)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~2) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (435:435:435)) + (PORT datac (330:330:330) (415:415:415)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shake_ctr\~0) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (849:849:849)) + (PORT datab (1928:1928:1928) (2115:2115:2115)) + (PORT datac (3571:3571:3571) (3733:3733:3733)) + (PORT datad (852:852:852) (839:839:839)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shake_ctr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (2125:2125:2125) (2139:2139:2139)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~0) + (DELAY + (ABSOLUTE + (PORT datab (354:354:354) (444:444:444)) + (PORT datac (271:271:271) (301:301:301)) + (PORT datad (303:303:303) (377:377:377)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (456:456:456)) + (PORT datab (335:335:335) (411:411:411)) + (PORT datac (309:309:309) (398:398:398)) + (PORT datad (318:318:318) (404:404:404)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|shakenum\~1) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (441:441:441)) + (PORT datac (273:273:273) (304:304:304)) + (PORT datad (305:305:305) (379:379:379)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|shakenum\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (448:448:448)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[0\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (484:484:484)) + (PORT datab (488:488:488) (473:473:473)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[1\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (436:436:436)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT datac (310:310:310) (400:400:400)) + (PORT datad (320:320:320) (407:407:407)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (771:771:771) (848:848:848)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1049:1049:1049) (1060:1060:1060)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (642:642:642)) + (PORT datab (587:587:587) (619:619:619)) + (PORT datac (733:733:733) (705:705:705)) + (PORT datad (541:541:541) (556:556:556)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1686:1686:1686) (1804:1804:1804)) + (PORT datab (3698:3698:3698) (3856:3856:3856)) + (PORT datac (707:707:707) (803:803:803)) + (PORT datad (874:874:874) (860:860:860)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~7) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (846:846:846)) + (PORT datab (2176:2176:2176) (2372:2372:2372)) + (PORT datac (930:930:930) (908:908:908)) + (PORT datad (3533:3533:3533) (3669:3669:3669)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1689:1689:1689) (1805:1805:1805)) + (PORT datab (3714:3714:3714) (3869:3869:3869)) + (PORT datac (705:705:705) (800:800:800)) + (PORT datad (880:880:880) (868:868:868)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1689:1689:1689) (1805:1805:1805)) + (PORT datab (3728:3728:3728) (3905:3905:3905)) + (PORT datac (704:704:704) (800:800:800)) + (PORT datad (881:881:881) (869:869:869)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~2) + (DELAY + (ABSOLUTE + (PORT dataa (760:760:760) (843:843:843)) + (PORT datab (2179:2179:2179) (2375:2375:2375)) + (PORT datac (934:934:934) (913:913:913)) + (PORT datad (3732:3732:3732) (3901:3901:3901)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~3) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (844:844:844)) + (PORT datab (2177:2177:2177) (2373:2373:2373)) + (PORT datac (931:931:931) (909:909:909)) + (PORT datad (3950:3950:3950) (4051:4051:4051)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (550:550:550) (575:575:575)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[3\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (621:621:621)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[4\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[5\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[6\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (613:613:613)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[7\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1883:1883:1883) (1764:1764:1764)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1007:1007:1007) (1024:1024:1024)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (781:781:781) (766:766:766)) + (PORT datab (637:637:637) (639:639:639)) + (PORT datac (778:778:778) (755:755:755)) + (PORT datad (501:501:501) (526:526:526)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1002:1002:1002) (1015:1015:1015)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (769:769:769) (845:845:845)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (620:620:620)) + (PORT datab (599:599:599) (606:606:606)) + (PORT datac (548:548:548) (565:565:565)) + (PORT datad (519:519:519) (538:538:538)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1017:1017:1017) (1032:1032:1032)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (977:977:977) (996:996:996)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (639:639:639)) + (PORT datab (545:545:545) (572:572:572)) + (PORT datac (549:549:549) (565:565:565)) + (PORT datad (540:540:540) (555:555:555)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~10) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (845:845:845)) + (PORT datab (2177:2177:2177) (2372:2372:2372)) + (PORT datac (931:931:931) (909:909:909)) + (PORT datad (3562:3562:3562) (3698:3698:3698)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~8) + (DELAY + (ABSOLUTE + (PORT dataa (758:758:758) (841:841:841)) + (PORT datab (2181:2181:2181) (2376:2376:2376)) + (PORT datac (937:937:937) (915:915:915)) + (PORT datad (3618:3618:3618) (3751:3751:3751)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE control\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|cat_duty\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1687:1687:1687) (1804:1804:1804)) + (PORT datab (3999:3999:3999) (4100:4100:4100)) + (PORT datac (708:708:708) (803:803:803)) + (PORT datad (873:873:873) (860:860:860)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|cat_duty\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[8\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (439:439:439)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[9\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (608:608:608) (617:617:617)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|new_duty\[10\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (551:551:551) (589:589:589)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (975:975:975) (1008:1008:1008)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (2089:2089:2089) (2099:2099:2099)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1256:1256:1256) (1219:1219:1219)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE dpwm_shake\|new_duty\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1629:1629:1629) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1014:1014:1014) (1027:1027:1027)) + (PORT sload (1288:1288:1288) (1323:1323:1323)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (637:637:637)) + (PORT datab (620:620:620) (628:628:628)) + (PORT datac (500:500:500) (534:534:534)) + (PORT datad (537:537:537) (556:556:556)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (595:595:595) (606:606:606)) + (PORT datac (235:235:235) (261:261:261)) + (PORT datad (585:585:585) (599:599:599)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|tmp_q) + (DELAY + (ABSOLUTE + (PORT dataa (765:765:765) (713:713:713)) + (PORT datab (498:498:498) (477:477:477)) + (PORT datac (1039:1039:1039) (901:901:901)) + (PORT datad (265:265:265) (283:283:283)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|pwm_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (336:336:336)) + (PORT datab (303:303:303) (327:327:327)) + (PORT datac (262:262:262) (287:287:287)) + (PORT datad (509:509:509) (476:476:476)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE dpwm_shake\|pwm_out) + (DELAY + (ABSOLUTE + (PORT dataa (766:766:766) (702:702:702)) + (PORT datab (742:742:742) (661:661:661)) + (PORT datad (241:241:241) (259:259:259)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) +) diff --git a/dpwm_shake/simulation/modelsim/gate_work/_info b/dpwm_shake/simulation/modelsim/gate_work/_info new file mode 100644 index 0000000..0a71ec0 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/gate_work/_info @@ -0,0 +1,54 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dF:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim +vdpwm_top +Z1 !s110 1541586555 +!i10b 1 +!s100 iBSSkbWG;embKog=hnY^>1 +INk6Tjf@0UAKS9kVH8Zc8m0 +Z2 VDg1SIo80bB@j0V0VzS_@n1 +R0 +w1541586424 +8dpwm_shake_8_1200mv_85c_slow.vo +Fdpwm_shake_8_1200mv_85c_slow.vo +L0 31 +Z3 OV;L;10.5b;63 +r1 +!s85 0 +31 +Z4 !s108 1541586555.000000 +!s107 dpwm_shake_8_1200mv_85c_slow.vo| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+.|dpwm_shake_8_1200mv_85c_slow.vo| +!i113 1 +Z5 o-vlog01compat -work work +!s92 -vlog01compat -work work +incdir+. +Z6 tCvgOpt 0 +vdpwm_top_tb +R1 +!i10b 1 +!s100 AOj:Tj 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/dpwm_shake/simulation/modelsim/msim_transcript b/dpwm_shake/simulation/modelsim/msim_transcript new file mode 100644 index 0000000..f5b18a5 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/msim_transcript @@ -0,0 +1,75 @@ +# Reading D:/intelFPGA/18.0/modelsim_ase/tcl/vsim/pref.tcl +# do dpwm_shake_run_msim_gate_verilog.do +# if {[file exists gate_work]} { +# vdel -lib gate_work -all +# } +# vlib gate_work +# vmap work gate_work +# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 +# vmap work gate_work +# Copying D:/intelFPGA/18.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini +# Modifying modelsim.ini +# +# vlog -vlog01compat -work work +incdir+. {dpwm_shake_8_1200mv_85c_slow.vo} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:29:15 on Nov 07,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+." dpwm_shake_8_1200mv_85c_slow.vo +# -- Compiling module dpwm_top +# +# Top level modules: +# dpwm_top +# End time: 18:29:15 on Nov 07,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation {F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:29:15 on Nov 07,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/dpwm_shake/simulation" F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v +# -- Compiling module dpwm_top_tb +# +# Top level modules: +# dpwm_top_tb +# End time: 18:29:15 on Nov 07,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# +# vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" dpwm_top_tb +# vsim -t 1ps "+transport_int_delays" "+transport_path_delays" -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs=""+acc"" dpwm_top_tb +# Start time: 18:29:15 on Nov 07,2018 +# Loading work.dpwm_top_tb +# Loading work.dpwm_top +# Loading cycloneive_ver.cycloneive_io_obuf +# Loading cycloneive_ver.cycloneive_io_ibuf +# Loading cycloneive_ver.cycloneive_clkctrl +# Loading cycloneive_ver.cycloneive_mux41 +# Loading cycloneive_ver.cycloneive_ena_reg +# Loading cycloneive_ver.cycloneive_pll +# Loading cycloneive_ver.cycloneive_m_cntr +# Loading cycloneive_ver.cycloneive_n_cntr +# Loading cycloneive_ver.cycloneive_scale_cntr +# Loading cycloneive_ver.cycloneive_lcell_comb +# Loading altera_ver.dffeas +# SDF 10.5b Compiler 2016.10 Oct 5 2016 +# +# Loading instances from dpwm_shake_8_1200mv_85c_v_slow.sdo +# Loading altera_ver.PRIM_GDFF_LOW +# Loading timing data from dpwm_shake_8_1200mv_85c_v_slow.sdo +# ** Note: (vsim-3587) SDF Backannotation Successfully Completed. +# Time: 0 ps Iteration: 0 Instance: /dpwm_top_tb File: F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v +# +# add wave * +# view structure +# .main_pane.structure.interior.cs.body.struct +# view signals +# .main_pane.objects.interior.cs.body.tree +# run -all +# Note : Cycloneive PLL self reset due to loss of lock +# Time: 0 Instance: dpwm_top_tb.dpwm_top.\pwm_pll|altpll_component|auto_generated|pll1 +# Note : Cycloneive PLL was reset +# Time: 1551 Instance: dpwm_top_tb.dpwm_top.\pwm_pll|altpll_component|auto_generated|pll1 +# Note : Cycloneive PLL locked to incoming clock +# Time: 4303102 Instance: dpwm_top_tb.dpwm_top.\pwm_pll|altpll_component|auto_generated|pll1 +# ** Note: $stop : F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v(48) +# Time: 1004 us Iteration: 0 Instance: /dpwm_top_tb +# Break in Module dpwm_top_tb at F:/Code/FPGA/reserve/dpwm_shake/simulation/dpwm_top_tb.v line 48 +# End time: 18:30:50 on Nov 07,2018, Elapsed time: 0:01:35 +# Errors: 0, Warnings: 0 diff --git a/dpwm_shake/simulation/modelsim/rtl_work/_info b/dpwm_shake/simulation/modelsim/rtl_work/_info new file mode 100644 index 0000000..83657a5 --- /dev/null +++ b/dpwm_shake/simulation/modelsim/rtl_work/_info @@ -0,0 +1,120 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dF:/Code/FPGA/reserve/dpwm_shake/simulation/modelsim +vdpwm_shake +Z1 !s110 1541586227 +!i10b 1 +!s100 `1eNP]hmz=ib2^O3a^jC4V5X:ZV3 +R2 +R0 +w1541580261 +8F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v +FF:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v +L0 1 +R3 +r1 +!s85 0 +31 +Z7 !s108 1541586227.000000 +!s107 F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+F:/Code/FPGA/reserve/dpwm_shake/rtl|F:/Code/FPGA/reserve/dpwm_shake/rtl/dpwm_top.v| +!i113 1 +R4 +R5 +R6 +vdpwm_top_tb +!s110 1541586228 +!i10b 1 +!s100 AOj:Tj + + + + diff --git a/pid/db/pid.cmp.idb b/pid/db/pid.cmp.idb new file mode 100644 index 0000000..bb5ca13 Binary files /dev/null and b/pid/db/pid.cmp.idb differ diff --git a/pid/db/pid.cmp.rdb b/pid/db/pid.cmp.rdb new file mode 100644 index 0000000..5e1bde5 Binary files /dev/null and b/pid/db/pid.cmp.rdb differ diff --git a/pid/db/pid.cmp_merge.kpt b/pid/db/pid.cmp_merge.kpt new file mode 100644 index 0000000..d9114a0 Binary files /dev/null and b/pid/db/pid.cmp_merge.kpt differ diff --git a/pid/db/pid.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/pid/db/pid.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd new file mode 100644 index 0000000..d24bd1b Binary files /dev/null and b/pid/db/pid.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd differ diff --git a/pid/db/pid.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd b/pid/db/pid.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd new file mode 100644 index 0000000..87b0f3a Binary files /dev/null and b/pid/db/pid.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd differ diff --git a/pid/db/pid.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd b/pid/db/pid.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd new file mode 100644 index 0000000..5116cf6 Binary files /dev/null and b/pid/db/pid.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd differ diff --git a/pid/db/pid.cycloneive_io_sim_cache.45um_tt_1200mv_85c_nom.hsd b/pid/db/pid.cycloneive_io_sim_cache.45um_tt_1200mv_85c_nom.hsd new file mode 100644 index 0000000..d85be9b Binary files /dev/null and b/pid/db/pid.cycloneive_io_sim_cache.45um_tt_1200mv_85c_nom.hsd differ diff --git a/pid/db/pid.db_info b/pid/db/pid.db_info new file mode 100644 index 0000000..4893208 --- /dev/null +++ b/pid/db/pid.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Version_Index = 486699264 +Creation_Time = Sat Dec 08 18:15:41 2018 diff --git a/pid/db/pid.eda.qmsg b/pid/db/pid.eda.qmsg new file mode 100644 index 0000000..eb2a374 --- /dev/null +++ b/pid/db/pid.eda.qmsg @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543905397930 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543905397942 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 04 14:36:37 2018 " "Processing started: Tue Dec 04 14:36:37 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543905397942 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1543905397942 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off pid -c pid " "Command: quartus_eda --read_settings_files=off --write_settings_files=off pid -c pid" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1543905397942 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1543905398666 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "pid_8_1200mv_85c_slow.vo F:/Code/FPGA/reserve/pid/simulation/modelsim/ simulation " "Generated file pid_8_1200mv_85c_slow.vo in folder \"F:/Code/FPGA/reserve/pid/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1543905398914 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "pid_8_1200mv_0c_slow.vo F:/Code/FPGA/reserve/pid/simulation/modelsim/ simulation " "Generated file pid_8_1200mv_0c_slow.vo in folder \"F:/Code/FPGA/reserve/pid/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1543905398987 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "pid_min_1200mv_0c_fast.vo F:/Code/FPGA/reserve/pid/simulation/modelsim/ simulation " "Generated file pid_min_1200mv_0c_fast.vo in folder \"F:/Code/FPGA/reserve/pid/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1543905399124 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "pid.vo F:/Code/FPGA/reserve/pid/simulation/modelsim/ simulation " "Generated file pid.vo in folder \"F:/Code/FPGA/reserve/pid/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1543905399186 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "pid_8_1200mv_85c_v_slow.sdo F:/Code/FPGA/reserve/pid/simulation/modelsim/ simulation " "Generated file pid_8_1200mv_85c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/pid/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1543905399258 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "pid_8_1200mv_0c_v_slow.sdo F:/Code/FPGA/reserve/pid/simulation/modelsim/ simulation " "Generated file pid_8_1200mv_0c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/pid/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1543905399313 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "pid_min_1200mv_0c_v_fast.sdo F:/Code/FPGA/reserve/pid/simulation/modelsim/ simulation " "Generated file pid_min_1200mv_0c_v_fast.sdo in folder \"F:/Code/FPGA/reserve/pid/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1543905399361 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "pid_v.sdo F:/Code/FPGA/reserve/pid/simulation/modelsim/ simulation " "Generated file pid_v.sdo in folder \"F:/Code/FPGA/reserve/pid/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1543905399414 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4667 " "Peak virtual memory: 4667 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543905399472 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 04 14:36:39 2018 " "Processing ended: Tue Dec 04 14:36:39 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543905399472 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543905399472 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543905399472 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1543905399472 ""} diff --git a/pid/db/pid.fit.qmsg b/pid/db/pid.fit.qmsg new file mode 100644 index 0000000..7e23cbd --- /dev/null +++ b/pid/db/pid.fit.qmsg @@ -0,0 +1,46 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1543905380579 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1543905380579 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "pid EP4CE10F17C8 " "Selected device EP4CE10F17C8 for design \"pid\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1543905380646 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1543905380770 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1543905380770 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1543905380925 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Device EP4CE6F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1543905381204 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1543905381204 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1543905381204 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1543905381204 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/pid/" { { 0 { 0 ""} 0 817 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1543905381223 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/pid/" { { 0 { 0 ""} 0 819 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1543905381223 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/pid/" { { 0 { 0 ""} 0 821 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1543905381223 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/pid/" { { 0 { 0 ""} 0 823 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1543905381223 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/pid/" { { 0 { 0 ""} 0 825 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1543905381223 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1543905381223 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1543905381231 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "68 68 " "No exact pin location assignment(s) for 68 pins of 68 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1543905381586 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "pid.sdc " "Synopsys Design Constraints File file not found: 'pid.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1543905381960 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1543905381961 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1543905381967 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1543905381967 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1543905381968 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1543905382024 ""} } { { "rtl/pid.v" "" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 15 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/pid/" { { 0 { 0 ""} 0 761 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1543905382024 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1543905382025 ""} } { { "rtl/pid.v" "" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 15 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/pid/" { { 0 { 0 ""} 0 762 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1543905382025 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1543905382281 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1543905382283 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1543905382283 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1543905382284 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1543905382285 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1543905382286 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1543905382318 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "14 Embedded multiplier block " "Packed 14 registers into blocks of type Embedded multiplier block" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Design Software" 0 -1 1543905382318 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "14 " "Created 14 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Design Software" 0 -1 1543905382318 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1543905382318 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "66 unused 2.5V 52 14 0 " "Number of I/O pins in group: 66 (unused VREF, 2.5V VCCIO, 52 input, 14 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1543905382324 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1543905382324 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1543905382324 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 12 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1543905382325 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 18 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1543905382325 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 26 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1543905382325 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 27 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1543905382325 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 25 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1543905382325 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 13 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1543905382325 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 26 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1543905382325 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 26 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1543905382325 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1543905382325 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1543905382325 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1543905382387 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1543905382407 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1543905383095 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1543905383218 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1543905383244 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1543905386136 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1543905386136 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1543905386450 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "3 X11_Y12 X22_Y24 " "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24" { } { { "loc" "" { Generic "F:/Code/FPGA/reserve/pid/" { { 1 { 0 "Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} { { 12 { 0 ""} 11 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1543905387020 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1543905387020 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1543905387554 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1543905387554 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1543905387559 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.37 " "Total time spent on timing analysis during the Fitter is 0.37 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1543905387732 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1543905387743 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1543905387943 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1543905387943 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1543905388186 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1543905388658 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/Code/FPGA/reserve/pid/output_files/pid.fit.smsg " "Generated suppressed messages file F:/Code/FPGA/reserve/pid/output_files/pid.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1543905389084 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5566 " "Peak virtual memory: 5566 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543905389543 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 04 14:36:29 2018 " "Processing ended: Tue Dec 04 14:36:29 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543905389543 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543905389543 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543905389543 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1543905389543 ""} diff --git a/pid/db/pid.hier_info b/pid/db/pid.hier_info new file mode 100644 index 0000000..111afa5 --- /dev/null +++ b/pid/db/pid.hier_info @@ -0,0 +1,386 @@ +|pid +clk => Vout[0]~reg0.CLK +clk => Vout[1]~reg0.CLK +clk => Vout[2]~reg0.CLK +clk => Vout[3]~reg0.CLK +clk => Vout[4]~reg0.CLK +clk => Vout[5]~reg0.CLK +clk => Vout[6]~reg0.CLK +clk => Vout[7]~reg0.CLK +clk => Vout[8]~reg0.CLK +clk => Vout[9]~reg0.CLK +clk => Vout[10]~reg0.CLK +clk => Vout[11]~reg0.CLK +clk => Vout[12]~reg0.CLK +clk => Vout[13]~reg0.CLK +clk => Kd_Out[0].CLK +clk => Kd_Out[1].CLK +clk => Kd_Out[2].CLK +clk => Kd_Out[3].CLK +clk => Kd_Out[4].CLK +clk => Kd_Out[5].CLK +clk => Kd_Out[6].CLK +clk => Kd_Out[7].CLK +clk => Kd_Out[8].CLK +clk => Kd_Out[9].CLK +clk => Kd_Out[10].CLK +clk => Kd_Out[11].CLK +clk => Kd_Out[12].CLK +clk => Kd_Out[13].CLK +clk => Kd_Out[14].CLK +clk => Kd_Out[15].CLK +clk => Kd_Out[16].CLK +clk => Kd_Out[17].CLK +clk => Kd_Out[18].CLK +clk => Kd_Out[19].CLK +clk => Kd_Out[20].CLK +clk => Kd_Out[21].CLK +clk => Kd_Out[22].CLK +clk => Ki_Out[0].CLK +clk => Ki_Out[1].CLK +clk => Ki_Out[2].CLK +clk => Ki_Out[3].CLK +clk => Ki_Out[4].CLK +clk => Ki_Out[5].CLK +clk => Ki_Out[6].CLK +clk => Ki_Out[7].CLK +clk => Ki_Out[8].CLK +clk => Ki_Out[9].CLK +clk => Ki_Out[10].CLK +clk => Ki_Out[11].CLK +clk => Ki_Out[12].CLK +clk => Ki_Out[13].CLK +clk => Ki_Out[14].CLK +clk => Ki_Out[15].CLK +clk => Ki_Out[16].CLK +clk => Ki_Out[17].CLK +clk => Ki_Out[18].CLK +clk => Ki_Out[19].CLK +clk => Ki_Out[20].CLK +clk => Ki_Out[21].CLK +clk => Ki_Out[22].CLK +clk => Kp_Out[0].CLK +clk => Kp_Out[1].CLK +clk => Kp_Out[2].CLK +clk => Kp_Out[3].CLK +clk => Kp_Out[4].CLK +clk => Kp_Out[5].CLK +clk => Kp_Out[6].CLK +clk => Kp_Out[7].CLK +clk => Kp_Out[8].CLK +clk => Kp_Out[9].CLK +clk => Kp_Out[10].CLK +clk => Kp_Out[11].CLK +clk => Kp_Out[12].CLK +clk => Kp_Out[13].CLK +clk => Kp_Out[14].CLK +clk => Kp_Out[15].CLK +clk => Kp_Out[16].CLK +clk => Kp_Out[17].CLK +clk => Kp_Out[18].CLK +clk => Kp_Out[19].CLK +clk => Kp_Out[20].CLK +clk => Kp_Out[21].CLK +clk => Kp_Out[22].CLK +clk => kpid[0].CLK +clk => kpid[1].CLK +clk => kpid[2].CLK +clk => kpid[3].CLK +clk => kpid[4].CLK +clk => kpid[5].CLK +clk => kpid[6].CLK +clk => kpid[7].CLK +clk => kpid[8].CLK +clk => EETMP[0].CLK +clk => EETMP[1].CLK +clk => EETMP[2].CLK +clk => EETMP[3].CLK +clk => EETMP[4].CLK +clk => EETMP[5].CLK +clk => EETMP[6].CLK +clk => EETMP[7].CLK +clk => EETMP[8].CLK +clk => EETMP[9].CLK +clk => EETMP[10].CLK +clk => EETMP[11].CLK +clk => EETMP[12].CLK +clk => EETMP[13].CLK +clk => EE0[0].CLK +clk => EE0[1].CLK +clk => EE0[2].CLK +clk => EE0[3].CLK +clk => EE0[4].CLK +clk => EE0[5].CLK +clk => EE0[6].CLK +clk => EE0[7].CLK +clk => EE0[8].CLK +clk => EE0[9].CLK +clk => EE0[10].CLK +clk => EE0[11].CLK +clk => EE0[12].CLK +clk => EE0[13].CLK +clk => EE2[0].CLK +clk => EE2[1].CLK +clk => EE2[2].CLK +clk => EE2[3].CLK +clk => EE2[4].CLK +clk => EE2[5].CLK +clk => EE2[6].CLK +clk => EE2[7].CLK +clk => EE2[8].CLK +clk => EE2[9].CLK +clk => EE2[10].CLK +clk => EE2[11].CLK +clk => EE2[12].CLK +clk => EE2[13].CLK +clk => EE1[0].CLK +clk => EE1[1].CLK +clk => EE1[2].CLK +clk => EE1[3].CLK +clk => EE1[4].CLK +clk => EE1[5].CLK +clk => EE1[6].CLK +clk => EE1[7].CLK +clk => EE1[8].CLK +clk => EE1[9].CLK +clk => EE1[10].CLK +clk => EE1[11].CLK +clk => EE1[12].CLK +clk => EE1[13].CLK +clk => period[0].CLK +clk => period[1].CLK +clk => period[2].CLK +clk => period[3].CLK +clk => period[4].CLK +clk => period[5].CLK +clk => period[6].CLK +clk => period[7].CLK +clk => status~1.DATAIN +rst_n => Vout[0]~reg0.ACLR +rst_n => Vout[1]~reg0.ACLR +rst_n => Vout[2]~reg0.ACLR +rst_n => Vout[3]~reg0.ACLR +rst_n => Vout[4]~reg0.ACLR +rst_n => Vout[5]~reg0.ACLR +rst_n => Vout[6]~reg0.ACLR +rst_n => Vout[7]~reg0.ACLR +rst_n => Vout[8]~reg0.ACLR +rst_n => Vout[9]~reg0.ACLR +rst_n => Vout[10]~reg0.ACLR +rst_n => Vout[11]~reg0.ACLR +rst_n => Vout[12]~reg0.ACLR +rst_n => Vout[13]~reg0.ACLR +rst_n => Kd_Out[0].ACLR +rst_n => Kd_Out[1].ACLR +rst_n => Kd_Out[2].ACLR +rst_n => Kd_Out[3].ACLR +rst_n => Kd_Out[4].ACLR +rst_n => Kd_Out[5].ACLR +rst_n => Kd_Out[6].ACLR +rst_n => Kd_Out[7].ACLR +rst_n => Kd_Out[8].ACLR +rst_n => Kd_Out[9].ACLR +rst_n => Kd_Out[10].ACLR +rst_n => Kd_Out[11].ACLR +rst_n => Kd_Out[12].ACLR +rst_n => Kd_Out[13].ACLR +rst_n => Kd_Out[14].ACLR +rst_n => Kd_Out[15].ACLR +rst_n => Kd_Out[16].ACLR +rst_n => Kd_Out[17].ACLR +rst_n => Kd_Out[18].ACLR +rst_n => Kd_Out[19].ACLR +rst_n => Kd_Out[20].ACLR +rst_n => Kd_Out[21].ACLR +rst_n => Kd_Out[22].ACLR +rst_n => Ki_Out[0].ACLR +rst_n => Ki_Out[1].ACLR +rst_n => Ki_Out[2].ACLR +rst_n => Ki_Out[3].ACLR +rst_n => Ki_Out[4].ACLR +rst_n => Ki_Out[5].ACLR +rst_n => Ki_Out[6].ACLR +rst_n => Ki_Out[7].ACLR +rst_n => Ki_Out[8].ACLR +rst_n => Ki_Out[9].ACLR +rst_n => Ki_Out[10].ACLR +rst_n => Ki_Out[11].ACLR +rst_n => Ki_Out[12].ACLR +rst_n => Ki_Out[13].ACLR +rst_n => Ki_Out[14].ACLR +rst_n => Ki_Out[15].ACLR +rst_n => Ki_Out[16].ACLR +rst_n => Ki_Out[17].ACLR +rst_n => Ki_Out[18].ACLR +rst_n => Ki_Out[19].ACLR +rst_n => Ki_Out[20].ACLR +rst_n => Ki_Out[21].ACLR +rst_n => Ki_Out[22].ACLR +rst_n => Kp_Out[0].ACLR +rst_n => Kp_Out[1].ACLR +rst_n => Kp_Out[2].ACLR +rst_n => Kp_Out[3].ACLR +rst_n => Kp_Out[4].ACLR +rst_n => Kp_Out[5].ACLR +rst_n => Kp_Out[6].ACLR +rst_n => Kp_Out[7].ACLR +rst_n => Kp_Out[8].ACLR +rst_n => Kp_Out[9].ACLR +rst_n => Kp_Out[10].ACLR +rst_n => Kp_Out[11].ACLR +rst_n => Kp_Out[12].ACLR +rst_n => Kp_Out[13].ACLR +rst_n => Kp_Out[14].ACLR +rst_n => Kp_Out[15].ACLR +rst_n => Kp_Out[16].ACLR +rst_n => Kp_Out[17].ACLR +rst_n => Kp_Out[18].ACLR +rst_n => Kp_Out[19].ACLR +rst_n => Kp_Out[20].ACLR +rst_n => Kp_Out[21].ACLR +rst_n => Kp_Out[22].ACLR +rst_n => kpid[0].ACLR +rst_n => kpid[1].ACLR +rst_n => kpid[2].ACLR +rst_n => kpid[3].ACLR +rst_n => kpid[4].ACLR +rst_n => kpid[5].ACLR +rst_n => kpid[6].ACLR +rst_n => kpid[7].ACLR +rst_n => kpid[8].ACLR +rst_n => EETMP[0].ACLR +rst_n => EETMP[1].ACLR +rst_n => EETMP[2].ACLR +rst_n => EETMP[3].ACLR +rst_n => EETMP[4].ACLR +rst_n => EETMP[5].ACLR +rst_n => EETMP[6].ACLR +rst_n => EETMP[7].ACLR +rst_n => EETMP[8].ACLR +rst_n => EETMP[9].ACLR +rst_n => EETMP[10].ACLR +rst_n => EETMP[11].ACLR +rst_n => EETMP[12].ACLR +rst_n => EETMP[13].ACLR +rst_n => EE0[0].ACLR +rst_n => EE0[1].ACLR +rst_n => EE0[2].ACLR +rst_n => EE0[3].ACLR +rst_n => EE0[4].ACLR +rst_n => EE0[5].ACLR +rst_n => EE0[6].ACLR +rst_n => EE0[7].ACLR +rst_n => EE0[8].ACLR +rst_n => EE0[9].ACLR +rst_n => EE0[10].ACLR +rst_n => EE0[11].ACLR +rst_n => EE0[12].ACLR +rst_n => EE0[13].ACLR +rst_n => EE2[0].ACLR +rst_n => EE2[1].ACLR +rst_n => EE2[2].ACLR +rst_n => EE2[3].ACLR +rst_n => EE2[4].ACLR +rst_n => EE2[5].ACLR +rst_n => EE2[6].ACLR +rst_n => EE2[7].ACLR +rst_n => EE2[8].ACLR +rst_n => EE2[9].ACLR +rst_n => EE2[10].ACLR +rst_n => EE2[11].ACLR +rst_n => EE2[12].ACLR +rst_n => EE2[13].ACLR +rst_n => EE1[0].ACLR +rst_n => EE1[1].ACLR +rst_n => EE1[2].ACLR +rst_n => EE1[3].ACLR +rst_n => EE1[4].ACLR +rst_n => EE1[5].ACLR +rst_n => EE1[6].ACLR +rst_n => EE1[7].ACLR +rst_n => EE1[8].ACLR +rst_n => EE1[9].ACLR +rst_n => EE1[10].ACLR +rst_n => EE1[11].ACLR +rst_n => EE1[12].ACLR +rst_n => EE1[13].ACLR +rst_n => period[0].ACLR +rst_n => period[1].ACLR +rst_n => period[2].ACLR +rst_n => period[3].ACLR +rst_n => period[4].ACLR +rst_n => period[5].ACLR +rst_n => period[6].ACLR +rst_n => period[7].ACLR +rst_n => status~3.DATAIN +Sample[0] => Add1.IN14 +Sample[1] => Add1.IN13 +Sample[2] => Add1.IN12 +Sample[3] => Add1.IN11 +Sample[4] => Add1.IN10 +Sample[5] => Add1.IN9 +Sample[6] => Add1.IN8 +Sample[7] => Add1.IN7 +Sample[8] => Add1.IN6 +Sample[9] => Add1.IN5 +Sample[10] => Add1.IN4 +Sample[11] => Add1.IN3 +Sample[12] => Add1.IN2 +Sample[13] => Add1.IN1 +SetPoint[0] => Add1.IN28 +SetPoint[1] => Add1.IN27 +SetPoint[2] => Add1.IN26 +SetPoint[3] => Add1.IN25 +SetPoint[4] => Add1.IN24 +SetPoint[5] => Add1.IN23 +SetPoint[6] => Add1.IN22 +SetPoint[7] => Add1.IN21 +SetPoint[8] => Add1.IN20 +SetPoint[9] => Add1.IN19 +SetPoint[10] => Add1.IN18 +SetPoint[11] => Add1.IN17 +SetPoint[12] => Add1.IN16 +SetPoint[13] => Add1.IN15 +Kp[0] => Selector22.IN1 +Kp[1] => Selector21.IN1 +Kp[2] => Selector20.IN1 +Kp[3] => Selector19.IN1 +Kp[4] => Selector18.IN1 +Kp[5] => Selector17.IN1 +Kp[6] => Selector16.IN1 +Kp[7] => Selector15.IN1 +Kp[8] => Selector14.IN1 +Ki[0] => Selector22.IN2 +Ki[1] => Selector21.IN2 +Ki[2] => Selector20.IN2 +Ki[3] => Selector19.IN2 +Ki[4] => Selector18.IN2 +Ki[5] => Selector17.IN2 +Ki[6] => Selector16.IN2 +Ki[7] => Selector15.IN2 +Ki[8] => Selector14.IN2 +Kd[0] => Selector22.IN3 +Kd[1] => Selector21.IN3 +Kd[2] => Selector20.IN3 +Kd[3] => Selector19.IN3 +Kd[4] => Selector18.IN3 +Kd[5] => Selector17.IN3 +Kd[6] => Selector16.IN3 +Kd[7] => Selector15.IN3 +Kd[8] => Selector14.IN3 +Vout[0] <= Vout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[1] <= Vout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[2] <= Vout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[3] <= Vout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[4] <= Vout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[5] <= Vout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[6] <= Vout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[7] <= Vout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[8] <= Vout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[9] <= Vout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[10] <= Vout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[11] <= Vout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[12] <= Vout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[13] <= Vout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/pid/db/pid.hif b/pid/db/pid.hif new file mode 100644 index 0000000..7d6fba0 Binary files /dev/null and b/pid/db/pid.hif differ diff --git a/pid/db/pid.lpc.html b/pid/db/pid.lpc.html new file mode 100644 index 0000000..fbc5ab5 --- /dev/null +++ b/pid/db/pid.lpc.html @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
diff --git a/pid/db/pid.lpc.rdb b/pid/db/pid.lpc.rdb new file mode 100644 index 0000000..e9a0f4d Binary files /dev/null and b/pid/db/pid.lpc.rdb differ diff --git a/pid/db/pid.lpc.txt b/pid/db/pid.lpc.txt new file mode 100644 index 0000000..a463804 --- /dev/null +++ b/pid/db/pid.lpc.txt @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/pid/db/pid.map.ammdb b/pid/db/pid.map.ammdb new file mode 100644 index 0000000..73f234e Binary files /dev/null and b/pid/db/pid.map.ammdb differ diff --git a/pid/db/pid.map.bpm b/pid/db/pid.map.bpm new file mode 100644 index 0000000..f89afff Binary files /dev/null and b/pid/db/pid.map.bpm differ diff --git a/pid/db/pid.map.cdb b/pid/db/pid.map.cdb new file mode 100644 index 0000000..339ed1b Binary files /dev/null and b/pid/db/pid.map.cdb differ diff --git a/pid/db/pid.map.hdb b/pid/db/pid.map.hdb new file mode 100644 index 0000000..c8fc61b Binary files /dev/null and b/pid/db/pid.map.hdb differ diff --git a/pid/db/pid.map.kpt b/pid/db/pid.map.kpt new file mode 100644 index 0000000..0941b70 Binary files /dev/null and b/pid/db/pid.map.kpt differ diff --git a/pid/db/pid.map.logdb b/pid/db/pid.map.logdb new file mode 100644 index 0000000..53551d7 --- /dev/null +++ b/pid/db/pid.map.logdb @@ -0,0 +1,2 @@ +v1 +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,lpm_mult:Mult0|mult_k4t:auto_generated|mac_out2, diff --git a/pid/db/pid.map.qmsg b/pid/db/pid.map.qmsg new file mode 100644 index 0000000..6ba4a6a --- /dev/null +++ b/pid/db/pid.map.qmsg @@ -0,0 +1,18 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544265849335 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544265849353 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 18:44:09 2018 " "Processing started: Sat Dec 08 18:44:09 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544265849353 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544265849353 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pid -c pid " "Command: quartus_map --read_settings_files=on --write_settings_files=off pid -c pid" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544265849353 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1544265849987 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1544265849987 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/pid.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/pid.v" { { "Info" "ISGN_ENTITY_NAME" "1 pid " "Found entity 1: pid" { } { { "rtl/pid.v" "" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544265863338 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544265863338 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testbench/pid_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file testbench/pid_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 pid_tb " "Found entity 1: pid_tb" { } { { "testbench/pid_tb.v" "" { Text "F:/Code/FPGA/reserve/pid/testbench/pid_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544265863343 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544265863343 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "pid " "Elaborating entity \"pid\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1544265863436 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "23 14 pid.v(75) " "Verilog HDL assignment warning at pid.v(75): truncated value with size 23 to match size of target (14)" { } { { "rtl/pid.v" "" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 75 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1544265863450 "|pid"} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult0\"" { } { { "rtl/pid.v" "Mult0" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 70 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1544265863789 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1544265863789 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\"" { } { { "rtl/pid.v" "" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 70 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544265863864 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult0 " "Instantiated megafunction \"lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 14 " "Parameter \"LPM_WIDTHA\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544265863864 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544265863864 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 23 " "Parameter \"LPM_WIDTHP\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544265863864 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 23 " "Parameter \"LPM_WIDTHR\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544265863864 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544265863864 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544265863864 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544265863864 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544265863864 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544265863864 ""} } { { "rtl/pid.v" "" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 70 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1544265863864 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_k4t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_k4t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_k4t " "Found entity 1: mult_k4t" { } { { "db/mult_k4t.tdf" "" { Text "F:/Code/FPGA/reserve/pid/db/mult_k4t.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544265863927 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544265863927 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1544265864301 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "7 " "7 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1544265864756 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1544265864889 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544265864889 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "277 " "Implemented 277 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "57 " "Implemented 57 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1544265864953 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1544265864953 ""} { "Info" "ICUT_CUT_TM_LCELLS" "204 " "Implemented 204 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1544265864953 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "2 " "Implemented 2 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "Design Software" 0 -1 1544265864953 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1544265864953 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4792 " "Peak virtual memory: 4792 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544265864970 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:44:24 2018 " "Processing ended: Sat Dec 08 18:44:24 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544265864970 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544265864970 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544265864970 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1544265864970 ""} diff --git a/pid/db/pid.map.rdb b/pid/db/pid.map.rdb new file mode 100644 index 0000000..9e68074 Binary files /dev/null and b/pid/db/pid.map.rdb differ diff --git a/pid/db/pid.map_bb.cdb b/pid/db/pid.map_bb.cdb new file mode 100644 index 0000000..ed5b345 Binary files /dev/null and b/pid/db/pid.map_bb.cdb differ diff --git a/pid/db/pid.map_bb.hdb b/pid/db/pid.map_bb.hdb new file mode 100644 index 0000000..fea5dac Binary files /dev/null and b/pid/db/pid.map_bb.hdb differ diff --git a/pid/db/pid.map_bb.logdb b/pid/db/pid.map_bb.logdb new file mode 100644 index 0000000..53551d7 --- /dev/null +++ b/pid/db/pid.map_bb.logdb @@ -0,0 +1,2 @@ +v1 +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,lpm_mult:Mult0|mult_k4t:auto_generated|mac_out2, diff --git a/pid/db/pid.npp.qmsg b/pid/db/pid.npp.qmsg new file mode 100644 index 0000000..0f3e462 --- /dev/null +++ b/pid/db/pid.npp.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544263837514 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544263837526 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 18:10:37 2018 " "Processing started: Sat Dec 08 18:10:37 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544263837526 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1544263837526 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp pid -c pid --netlist_type=sm_process " "Command: quartus_npp pid -c pid --netlist_type=sm_process" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1544263837526 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1544263837845 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4567 " "Peak virtual memory: 4567 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544263837864 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:10:37 2018 " "Processing ended: Sat Dec 08 18:10:37 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544263837864 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544263837864 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544263837864 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1544263837864 ""} diff --git a/pid/db/pid.pow.qmsg b/pid/db/pid.pow.qmsg new file mode 100644 index 0000000..67bae00 --- /dev/null +++ b/pid/db/pid.pow.qmsg @@ -0,0 +1,18 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543905422887 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Power Analyzer Quartus Prime " "Running Quartus Prime Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543905422899 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 04 14:37:02 2018 " "Processing started: Tue Dec 04 14:37:02 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543905422899 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Power Analyzer" 0 -1 1543905422899 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=on --write_settings_files=off pid -c pid " "Command: quartus_pow --read_settings_files=on --write_settings_files=off pid -c pid" { } { } 0 0 "Command: %1!s!" 0 0 "Power Analyzer" 0 -1 1543905422899 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Power Analyzer" 0 -1 1543905423562 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1543905423573 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1543905423573 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "pid.sdc " "Synopsys Design Constraints File file not found: 'pid.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Power Analyzer" 0 -1 1543905423903 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk " "Node: clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register Vout\[0\]~reg0 clk " "Register Vout\[0\]~reg0 is being clocked by clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1543905423906 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1543905423906 "|pid|clk"} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Power Analyzer" 0 -1 1543905423907 ""} +{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1543905423920 ""} +{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" { } { } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "Power Analyzer" 0 -1 1543905423923 ""} +{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1543905423933 ""} +{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "Power Analyzer" 0 -1 1543905424136 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Power Analyzer" 0 -1 1543905424194 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Power Analyzer" 0 -1 1543905424446 ""} +{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.000 millions of transitions / sec " "Average toggle rate for this design is 0.000 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "Power Analyzer" 0 -1 1543905425394 ""} +{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "77.30 mW " "Total thermal power estimate for the design is 77.30 mW" { } { { "d:/intelfpga/18.1/quartus/bin64/Report_Window_01.qrpt" "" { Report "d:/intelfpga/18.1/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "Power Analyzer" 0 -1 1543905425401 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Power Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Power Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4819 " "Peak virtual memory: 4819 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543905425619 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 04 14:37:05 2018 " "Processing ended: Tue Dec 04 14:37:05 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543905425619 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543905425619 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543905425619 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Power Analyzer" 0 -1 1543905425619 ""} diff --git a/pid/db/pid.pplq.rdb b/pid/db/pid.pplq.rdb new file mode 100644 index 0000000..098c14e Binary files /dev/null and b/pid/db/pid.pplq.rdb differ diff --git a/pid/db/pid.pre_map.cdb b/pid/db/pid.pre_map.cdb new file mode 100644 index 0000000..0547492 Binary files /dev/null and b/pid/db/pid.pre_map.cdb differ diff --git a/pid/db/pid.pre_map.hdb b/pid/db/pid.pre_map.hdb new file mode 100644 index 0000000..7e07b53 Binary files /dev/null and b/pid/db/pid.pre_map.hdb differ diff --git a/pid/db/pid.root_partition.map.reg_db.cdb b/pid/db/pid.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..308f511 Binary files /dev/null and b/pid/db/pid.root_partition.map.reg_db.cdb differ diff --git a/pid/db/pid.routing.rdb b/pid/db/pid.routing.rdb new file mode 100644 index 0000000..72468b8 Binary files /dev/null and b/pid/db/pid.routing.rdb differ diff --git a/pid/db/pid.rtlv.hdb b/pid/db/pid.rtlv.hdb new file mode 100644 index 0000000..ccc786c Binary files /dev/null and b/pid/db/pid.rtlv.hdb differ diff --git a/pid/db/pid.rtlv_sg.cdb b/pid/db/pid.rtlv_sg.cdb new file mode 100644 index 0000000..61e9742 Binary files /dev/null and b/pid/db/pid.rtlv_sg.cdb differ diff --git a/pid/db/pid.rtlv_sg_swap.cdb b/pid/db/pid.rtlv_sg_swap.cdb new file mode 100644 index 0000000..9e44adf Binary files /dev/null and b/pid/db/pid.rtlv_sg_swap.cdb differ diff --git a/pid/db/pid.sgate.nvd b/pid/db/pid.sgate.nvd new file mode 100644 index 0000000..4f3dd0f Binary files /dev/null and b/pid/db/pid.sgate.nvd differ diff --git a/pid/db/pid.sgate_sm.nvd b/pid/db/pid.sgate_sm.nvd new file mode 100644 index 0000000..e73d220 Binary files /dev/null and b/pid/db/pid.sgate_sm.nvd differ diff --git a/pid/db/pid.sgate_sm_bdd.nvd b/pid/db/pid.sgate_sm_bdd.nvd new file mode 100644 index 0000000..81217b1 Binary files /dev/null and b/pid/db/pid.sgate_sm_bdd.nvd differ diff --git a/pid/db/pid.sld_design_entry.sci b/pid/db/pid.sld_design_entry.sci new file mode 100644 index 0000000..0cf4f27 Binary files /dev/null and b/pid/db/pid.sld_design_entry.sci differ diff --git a/pid/db/pid.sld_design_entry_dsc.sci b/pid/db/pid.sld_design_entry_dsc.sci new file mode 100644 index 0000000..0cf4f27 Binary files /dev/null and b/pid/db/pid.sld_design_entry_dsc.sci differ diff --git a/pid/db/pid.smart_action.txt b/pid/db/pid.smart_action.txt new file mode 100644 index 0000000..e04bbcf --- /dev/null +++ b/pid/db/pid.smart_action.txt @@ -0,0 +1 @@ +FIT diff --git a/pid/db/pid.smp_dump.txt b/pid/db/pid.smp_dump.txt new file mode 100644 index 0000000..da5cbf7 --- /dev/null +++ b/pid/db/pid.smp_dump.txt @@ -0,0 +1,11 @@ + +State Machine - |pid|status +Name status.s5 status.s4 status.s6 status.s7 status.s2 status.s3 status.s1 status.s0 +status.s0 0 0 0 0 0 0 0 0 +status.s1 0 0 0 0 0 0 1 1 +status.s3 0 0 0 0 0 1 0 1 +status.s2 0 0 0 0 1 0 0 1 +status.s7 0 0 0 1 0 0 0 1 +status.s6 0 0 1 0 0 0 0 1 +status.s4 0 1 0 0 0 0 0 1 +status.s5 1 0 0 0 0 0 0 1 diff --git a/pid/db/pid.sta.qmsg b/pid/db/pid.sta.qmsg new file mode 100644 index 0000000..a3a1f47 --- /dev/null +++ b/pid/db/pid.sta.qmsg @@ -0,0 +1,42 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1543905394216 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1543905394229 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 04 14:36:33 2018 " "Processing started: Tue Dec 04 14:36:33 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1543905394229 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1543905394229 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta pid -c pid " "Command: quartus_sta pid -c pid" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1543905394229 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1543905394450 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1543905394727 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1543905394727 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905394802 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905394802 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "pid.sdc " "Synopsys Design Constraints File file not found: 'pid.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1543905395027 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905395027 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1543905395028 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1543905395028 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1543905395031 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1543905395031 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1543905395034 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1543905395049 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1543905395087 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1543905395087 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -5.488 " "Worst-case setup slack is -5.488" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.488 -529.506 clk " " -5.488 -529.506 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395091 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905395091 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.509 " "Worst-case hold slack is 0.509" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395096 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395096 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.509 0.000 clk " " 0.509 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395096 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905395096 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543905395100 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543905395103 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.000 " "Worst-case minimum pulse width slack is -4.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395106 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.000 -254.273 clk " " -4.000 -254.273 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395106 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905395106 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1543905395153 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1543905395182 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1543905395535 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1543905395613 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1543905395623 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1543905395623 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.999 " "Worst-case setup slack is -4.999" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395630 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395630 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.999 -474.425 clk " " -4.999 -474.425 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395630 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905395630 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.470 " "Worst-case hold slack is 0.470" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395636 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395636 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.470 0.000 clk " " 0.470 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395636 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905395636 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543905395640 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543905395644 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -4.000 " "Worst-case minimum pulse width slack is -4.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395647 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.000 -253.825 clk " " -4.000 -253.825 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395647 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905395647 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1543905395681 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1543905395818 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1543905395820 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1543905395820 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.852 " "Worst-case setup slack is -1.852" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395825 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395825 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.852 -152.887 clk " " -1.852 -152.887 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395825 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905395825 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.205 " "Worst-case hold slack is 0.205" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395831 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395831 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.205 0.000 clk " " 0.205 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395831 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905395831 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543905395836 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1543905395842 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395846 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395846 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -158.600 clk " " -3.000 -158.600 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1543905395846 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1543905395846 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1543905396330 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1543905396333 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4778 " "Peak virtual memory: 4778 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1543905396401 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 04 14:36:36 2018 " "Processing ended: Tue Dec 04 14:36:36 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1543905396401 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1543905396401 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1543905396401 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1543905396401 ""} diff --git a/pid/db/pid.sta.rdb b/pid/db/pid.sta.rdb new file mode 100644 index 0000000..9f5b55c Binary files /dev/null and b/pid/db/pid.sta.rdb differ diff --git a/pid/db/pid.tis_db_list.ddb b/pid/db/pid.tis_db_list.ddb new file mode 100644 index 0000000..12425a9 Binary files /dev/null and b/pid/db/pid.tis_db_list.ddb differ diff --git a/pid/db/pid.tiscmp.fast_1200mv_0c.ddb b/pid/db/pid.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..e9c06c6 Binary files /dev/null and b/pid/db/pid.tiscmp.fast_1200mv_0c.ddb differ diff --git a/pid/db/pid.tiscmp.fastest_slow_1200mv_0c.ddb b/pid/db/pid.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..61bf9b3 Binary files /dev/null and b/pid/db/pid.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/pid/db/pid.tiscmp.fastest_slow_1200mv_85c.ddb b/pid/db/pid.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..8549890 Binary files /dev/null and b/pid/db/pid.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/pid/db/pid.tiscmp.slow_1200mv_0c.ddb b/pid/db/pid.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..0608c74 Binary files /dev/null and b/pid/db/pid.tiscmp.slow_1200mv_0c.ddb differ diff --git a/pid/db/pid.tiscmp.slow_1200mv_85c.ddb b/pid/db/pid.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..77a7b58 Binary files /dev/null and b/pid/db/pid.tiscmp.slow_1200mv_85c.ddb differ diff --git a/pid/db/pid.tmw_info b/pid/db/pid.tmw_info new file mode 100644 index 0000000..baf0e34 --- /dev/null +++ b/pid/db/pid.tmw_info @@ -0,0 +1,2 @@ +start_analysis_synthesis:s:00:00:17 +start_analysis_elaboration:s diff --git a/pid/db/pid.vpr.ammdb b/pid/db/pid.vpr.ammdb new file mode 100644 index 0000000..a8da519 Binary files /dev/null and b/pid/db/pid.vpr.ammdb differ diff --git a/pid/db/pid_partition_pins.json b/pid/db/pid_partition_pins.json new file mode 100644 index 0000000..d72bd0b --- /dev/null +++ b/pid/db/pid_partition_pins.json @@ -0,0 +1,293 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "Vout[0]", + "strict" : false + }, + { + "name" : "Vout[1]", + "strict" : false + }, + { + "name" : "Vout[2]", + "strict" : false + }, + { + "name" : "Vout[3]", + "strict" : false + }, + { + "name" : "Vout[4]", + "strict" : false + }, + { + "name" : "Vout[5]", + "strict" : false + }, + { + "name" : "Vout[6]", + "strict" : false + }, + { + "name" : "Vout[7]", + "strict" : false + }, + { + "name" : "Vout[8]", + "strict" : false + }, + { + "name" : "Vout[9]", + "strict" : false + }, + { + "name" : "Vout[10]", + "strict" : false + }, + { + "name" : "Vout[11]", + "strict" : false + }, + { + "name" : "Vout[12]", + "strict" : false + }, + { + "name" : "Vout[13]", + "strict" : false + }, + { + "name" : "clk", + "strict" : false + }, + { + "name" : "rst_n", + "strict" : false + }, + { + "name" : "Kp[0]", + "strict" : false + }, + { + "name" : "Ki[0]", + "strict" : false + }, + { + "name" : "Kd[0]", + "strict" : false + }, + { + "name" : "Kp[1]", + "strict" : false + }, + { + "name" : "Ki[1]", + "strict" : false + }, + { + "name" : "Kd[1]", + "strict" : false + }, + { + "name" : "Kp[2]", + "strict" : false + }, + { + "name" : "Ki[2]", + "strict" : false + }, + { + "name" : "Kd[2]", + "strict" : false + }, + { + "name" : "Kp[3]", + "strict" : false + }, + { + "name" : "Ki[3]", + "strict" : false + }, + { + "name" : "Kd[3]", + "strict" : false + }, + { + "name" : "Kp[4]", + "strict" : false + }, + { + "name" : "Ki[4]", + "strict" : false + }, + { + "name" : "Kd[4]", + "strict" : false + }, + { + "name" : "Kp[5]", + "strict" : false + }, + { + "name" : "Ki[5]", + "strict" : false + }, + { + "name" : "Kd[5]", + "strict" : false + }, + { + "name" : "Kp[6]", + "strict" : false + }, + { + "name" : "Ki[6]", + "strict" : false + }, + { + "name" : "Kd[6]", + "strict" : false + }, + { + "name" : "Kp[7]", + "strict" : false + }, + { + "name" : "Ki[7]", + "strict" : false + }, + { + "name" : "Kd[7]", + "strict" : false + }, + { + "name" : "Kp[8]", + "strict" : false + }, + { + "name" : "Ki[8]", + "strict" : false + }, + { + "name" : "Kd[8]", + "strict" : false + }, + { + "name" : "SetPoint[0]", + "strict" : false + }, + { + "name" : "Sample[0]", + "strict" : false + }, + { + "name" : "SetPoint[1]", + "strict" : false + }, + { + "name" : "Sample[1]", + "strict" : false + }, + { + "name" : "SetPoint[2]", + "strict" : false + }, + { + "name" : "Sample[2]", + "strict" : false + }, + { + "name" : "SetPoint[3]", + "strict" : false + }, + { + "name" : "Sample[3]", + "strict" : false + }, + { + "name" : "SetPoint[4]", + "strict" : false + }, + { + "name" : "Sample[4]", + "strict" : false + }, + { + "name" : "SetPoint[5]", + "strict" : false + }, + { + "name" : "Sample[5]", + "strict" : false + }, + { + "name" : "SetPoint[6]", + "strict" : false + }, + { + "name" : "Sample[6]", + "strict" : false + }, + { + "name" : "SetPoint[7]", + "strict" : false + }, + { + "name" : "Sample[7]", + "strict" : false + }, + { + "name" : "SetPoint[8]", + "strict" : false + }, + { + "name" : "Sample[8]", + "strict" : false + }, + { + "name" : "SetPoint[9]", + "strict" : false + }, + { + "name" : "Sample[9]", + "strict" : false + }, + { + "name" : "SetPoint[10]", + "strict" : false + }, + { + "name" : "Sample[10]", + "strict" : false + }, + { + "name" : "SetPoint[11]", + "strict" : false + }, + { + "name" : "Sample[11]", + "strict" : false + }, + { + "name" : "SetPoint[12]", + "strict" : false + }, + { + "name" : "Sample[12]", + "strict" : false + }, + { + "name" : "SetPoint[13]", + "strict" : false + }, + { + "name" : "Sample[13]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/pid/db/prev_cmp_pid.qmsg b/pid/db/prev_cmp_pid.qmsg new file mode 100644 index 0000000..3e3e8fc --- /dev/null +++ b/pid/db/prev_cmp_pid.qmsg @@ -0,0 +1,18 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544264606010 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544264606061 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 18:23:25 2018 " "Processing started: Sat Dec 08 18:23:25 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544264606061 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544264606061 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pid -c pid " "Command: quartus_map --read_settings_files=on --write_settings_files=off pid -c pid" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544264606061 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1544264606666 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1544264606667 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/pid.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/pid.v" { { "Info" "ISGN_ENTITY_NAME" "1 pid " "Found entity 1: pid" { } { { "rtl/pid.v" "" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544264619079 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544264619079 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testbench/pid_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file testbench/pid_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 pid_tb " "Found entity 1: pid_tb" { } { { "testbench/pid_tb.v" "" { Text "F:/Code/FPGA/reserve/pid/testbench/pid_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544264619082 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544264619082 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "pid " "Elaborating entity \"pid\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1544264619178 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "22 14 pid.v(86) " "Verilog HDL assignment warning at pid.v(86): truncated value with size 22 to match size of target (14)" { } { { "rtl/pid.v" "" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 86 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1544264619180 "|pid"} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult0\"" { } { { "rtl/pid.v" "Mult0" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 84 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1544264619511 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1544264619511 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\"" { } { { "rtl/pid.v" "" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 84 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544264619586 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult0 " "Instantiated megafunction \"lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 14 " "Parameter \"LPM_WIDTHA\" = \"14\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544264619587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544264619587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 23 " "Parameter \"LPM_WIDTHP\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544264619587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 23 " "Parameter \"LPM_WIDTHR\" = \"23\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544264619587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544264619587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION SIGNED " "Parameter \"LPM_REPRESENTATION\" = \"SIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544264619587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544264619587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544264619587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544264619587 ""} } { { "rtl/pid.v" "" { Text "F:/Code/FPGA/reserve/pid/rtl/pid.v" 84 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1544264619587 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_k4t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_k4t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_k4t " "Found entity 1: mult_k4t" { } { { "db/mult_k4t.tdf" "" { Text "F:/Code/FPGA/reserve/pid/db/mult_k4t.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544264619650 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544264619650 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1544264620033 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 " "2 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1544264620461 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1544264620593 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544264620593 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "272 " "Implemented 272 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "57 " "Implemented 57 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1544264620651 ""} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Implemented 14 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1544264620651 ""} { "Info" "ICUT_CUT_TM_LCELLS" "199 " "Implemented 199 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1544264620651 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "2 " "Implemented 2 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "Design Software" 0 -1 1544264620651 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1544264620651 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4793 " "Peak virtual memory: 4793 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544264620666 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 08 18:23:40 2018 " "Processing ended: Sat Dec 08 18:23:40 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544264620666 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544264620666 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:31 " "Total CPU time (on all processors): 00:00:31" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544264620666 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1544264620666 ""} diff --git a/pid/incremental_db/README b/pid/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/pid/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/pid/incremental_db/compiled_partitions/pid.db_info b/pid/incremental_db/compiled_partitions/pid.db_info new file mode 100644 index 0000000..8d10357 --- /dev/null +++ b/pid/incremental_db/compiled_partitions/pid.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Version_Index = 486699264 +Creation_Time = Mon Dec 03 11:05:10 2018 diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.ammdb b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.ammdb new file mode 100644 index 0000000..b913366 Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.ammdb differ diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.cdb b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.cdb new file mode 100644 index 0000000..f93a719 Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.cdb differ diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.dfp b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.dfp differ diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.hdb b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.hdb new file mode 100644 index 0000000..33c9d30 Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.hdb differ diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.logdb b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.logdb new file mode 100644 index 0000000..c4a84df --- /dev/null +++ b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.logdb @@ -0,0 +1,5 @@ +v1 +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,lpm_mult:Mult0|mult_kbt:auto_generated|mac_out2, +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,lpm_mult:Mult1|mult_gbt:auto_generated|mac_out2, +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,lpm_mult:Mult2|mult_gbt:auto_generated|mac_out2, +PORT_SWAPPING,PORT_SWAPPING_FINISHED,lpm_mult:Mult2|mult_gbt:auto_generated|mac_mult1, diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.rcfdb b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.rcfdb new file mode 100644 index 0000000..1913a85 Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.cmp.rcfdb differ diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.map.cdb b/pid/incremental_db/compiled_partitions/pid.root_partition.map.cdb new file mode 100644 index 0000000..35a668d Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.map.cdb differ diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.map.dpi b/pid/incremental_db/compiled_partitions/pid.root_partition.map.dpi new file mode 100644 index 0000000..a449a6e Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.map.dpi differ diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.cdb b/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..11b7a23 Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.cdb differ diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.hb_info b/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.hb_info differ diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.hdb b/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..8d52e51 Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.hdb differ diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.sig b/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.sig new file mode 100644 index 0000000..6c0af65 --- /dev/null +++ b/pid/incremental_db/compiled_partitions/pid.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +c5eb7f6cdd530884c3b884e0a3668ea4 \ No newline at end of file diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.map.hdb b/pid/incremental_db/compiled_partitions/pid.root_partition.map.hdb new file mode 100644 index 0000000..ec135b0 Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.map.hdb differ diff --git a/pid/incremental_db/compiled_partitions/pid.root_partition.map.kpt b/pid/incremental_db/compiled_partitions/pid.root_partition.map.kpt new file mode 100644 index 0000000..fb3af13 Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.root_partition.map.kpt differ diff --git a/pid/incremental_db/compiled_partitions/pid.rrp.hdb b/pid/incremental_db/compiled_partitions/pid.rrp.hdb new file mode 100644 index 0000000..528b97b Binary files /dev/null and b/pid/incremental_db/compiled_partitions/pid.rrp.hdb differ diff --git a/pid/output_files/pid.asm.rpt b/pid/output_files/pid.asm.rpt new file mode 100644 index 0000000..7ae9a3b --- /dev/null +++ b/pid/output_files/pid.asm.rpt @@ -0,0 +1,91 @@ +Assembler report for pid +Tue Dec 04 14:36:32 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: F:/Code/FPGA/reserve/pid/output_files/pid.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Tue Dec 04 14:36:32 2018 ; +; Revision Name ; pid ; +; Top-level Entity Name ; pid ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-----------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------+ +; File Name ; ++-----------------------------------------------+ +; F:/Code/FPGA/reserve/pid/output_files/pid.sof ; ++-----------------------------------------------+ + + ++-------------------------------------------------------------------------+ +; Assembler Device Options: F:/Code/FPGA/reserve/pid/output_files/pid.sof ; ++----------------+--------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------+ +; JTAG usercode ; 0x000AF308 ; +; Checksum ; 0x000AF308 ; ++----------------+--------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Tue Dec 04 14:36:30 2018 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off pid -c pid +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4695 megabytes + Info: Processing ended: Tue Dec 04 14:36:32 2018 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/pid/output_files/pid.done b/pid/output_files/pid.done new file mode 100644 index 0000000..175159d --- /dev/null +++ b/pid/output_files/pid.done @@ -0,0 +1 @@ +Sat Dec 08 18:44:25 2018 diff --git a/pid/output_files/pid.eda.rpt b/pid/output_files/pid.eda.rpt new file mode 100644 index 0000000..6b54375 --- /dev/null +++ b/pid/output_files/pid.eda.rpt @@ -0,0 +1,108 @@ +EDA Netlist Writer report for pid +Tue Dec 04 14:36:39 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Tue Dec 04 14:36:39 2018 ; +; Revision Name ; pid ; +; Top-level Entity Name ; pid ; +; Family ; Cyclone IV E ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++---------------------------------------------------------------------------+ +; Simulation Generated Files ; ++---------------------------------------------------------------------------+ +; Generated Files ; ++---------------------------------------------------------------------------+ +; F:/Code/FPGA/reserve/pid/simulation/modelsim/pid_8_1200mv_85c_slow.vo ; +; F:/Code/FPGA/reserve/pid/simulation/modelsim/pid_8_1200mv_0c_slow.vo ; +; F:/Code/FPGA/reserve/pid/simulation/modelsim/pid_min_1200mv_0c_fast.vo ; +; F:/Code/FPGA/reserve/pid/simulation/modelsim/pid.vo ; +; F:/Code/FPGA/reserve/pid/simulation/modelsim/pid_8_1200mv_85c_v_slow.sdo ; +; F:/Code/FPGA/reserve/pid/simulation/modelsim/pid_8_1200mv_0c_v_slow.sdo ; +; F:/Code/FPGA/reserve/pid/simulation/modelsim/pid_min_1200mv_0c_v_fast.sdo ; +; F:/Code/FPGA/reserve/pid/simulation/modelsim/pid_v.sdo ; ++---------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Tue Dec 04 14:36:37 2018 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off pid -c pid +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file pid_8_1200mv_85c_slow.vo in folder "F:/Code/FPGA/reserve/pid/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file pid_8_1200mv_0c_slow.vo in folder "F:/Code/FPGA/reserve/pid/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file pid_min_1200mv_0c_fast.vo in folder "F:/Code/FPGA/reserve/pid/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file pid.vo in folder "F:/Code/FPGA/reserve/pid/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file pid_8_1200mv_85c_v_slow.sdo in folder "F:/Code/FPGA/reserve/pid/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file pid_8_1200mv_0c_v_slow.sdo in folder "F:/Code/FPGA/reserve/pid/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file pid_min_1200mv_0c_v_fast.sdo in folder "F:/Code/FPGA/reserve/pid/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file pid_v.sdo in folder "F:/Code/FPGA/reserve/pid/simulation/modelsim/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4667 megabytes + Info: Processing ended: Tue Dec 04 14:36:39 2018 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/pid/output_files/pid.fit.rpt b/pid/output_files/pid.fit.rpt new file mode 100644 index 0000000..ca921cd --- /dev/null +++ b/pid/output_files/pid.fit.rpt @@ -0,0 +1,1587 @@ +Fitter report for pid +Tue Dec 04 14:36:29 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Fitter Netlist Optimizations + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. I/O Assignment Warnings + 18. Fitter Resource Utilization by Entity + 19. Delay Chain Summary + 20. Pad To Core Delay Chain Fanout + 21. Control Signals + 22. Global & Other Fast Signals + 23. Fitter DSP Block Usage Summary + 24. DSP Block Details + 25. Routing Usage Summary + 26. LAB Logic Elements + 27. LAB-wide Signals + 28. LAB Signals Sourced + 29. LAB Signals Sourced Out + 30. LAB Distinct Inputs + 31. I/O Rules Summary + 32. I/O Rules Details + 33. I/O Rules Matrix + 34. Fitter Device Options + 35. Operating Settings and Conditions + 36. Fitter Messages + 37. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Tue Dec 04 14:36:29 2018 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; pid ; +; Top-level Entity Name ; pid ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Total logic elements ; 244 / 10,320 ( 2 % ) ; +; Total combinational functions ; 238 / 10,320 ( 2 % ) ; +; Dedicated logic registers ; 131 / 10,320 ( 1 % ) ; +; Total registers ; 131 ; +; Total pins ; 68 / 180 ( 38 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 6 / 46 ( 13 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP4CE10F17C8 ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.05 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 1.7% ; +; Processor 3 ; 1.7% ; +; Processor 4 ; 1.7% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++---------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++---------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------+------------------+-----------------------+ +; EE0[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[0] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[0]~_Duplicate_1 ; Q ; ; +; EE0[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[1] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[1]~_Duplicate_1 ; Q ; ; +; EE0[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[2] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[2]~_Duplicate_1 ; Q ; ; +; EE0[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[3] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[3]~_Duplicate_1 ; Q ; ; +; EE0[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[4] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[4]~_Duplicate_1 ; Q ; ; +; EE0[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[5] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[5]~_Duplicate_1 ; Q ; ; +; EE0[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[6] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[6]~_Duplicate_1 ; Q ; ; +; EE0[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[7] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[7]~_Duplicate_1 ; Q ; ; +; EE0[8] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[8] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[8]~_Duplicate_1 ; Q ; ; +; EE0[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[9] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[9]~_Duplicate_1 ; Q ; ; +; EE0[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[10] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[10]~_Duplicate_1 ; Q ; ; +; EE0[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[11] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[11]~_Duplicate_1 ; Q ; ; +; EE0[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[12] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[12]~_Duplicate_1 ; Q ; ; +; EE0[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; DATAA ; ; +; EE0[13] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; EE0[13]~_Duplicate_1 ; Q ; ; ++---------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------+------------------+-----------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 523 ) ; 0.00 % ( 0 / 523 ) ; 0.00 % ( 0 / 523 ) ; +; -- Achieved ; 0.00 % ( 0 / 523 ) ; 0.00 % ( 0 / 523 ) ; 0.00 % ( 0 / 523 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 513 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in F:/Code/FPGA/reserve/pid/output_files/pid.pin. + + ++--------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------+ +; Total logic elements ; 244 / 10,320 ( 2 % ) ; +; -- Combinational with no register ; 113 ; +; -- Register only ; 6 ; +; -- Combinational with a register ; 125 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 6 ; +; -- 3 input functions ; 81 ; +; -- <=2 input functions ; 151 ; +; -- Register only ; 6 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 88 ; +; -- arithmetic mode ; 150 ; +; ; ; +; Total registers* ; 131 / 11,172 ( 1 % ) ; +; -- Dedicated logic registers ; 131 / 10,320 ( 1 % ) ; +; -- I/O registers ; 0 / 852 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 23 / 645 ( 4 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 68 / 180 ( 38 % ) ; +; -- Clock pins ; 2 / 3 ( 67 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; M9Ks ; 0 / 46 ( 0 % ) ; +; Total block memory bits ; 0 / 423,936 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 6 / 46 ( 13 % ) ; +; PLLs ; 0 / 2 ( 0 % ) ; +; Global signals ; 2 ; +; -- Global clocks ; 2 / 10 ( 20 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 1.1% / 1.0% / 1.2% ; +; Peak interconnect usage (total/H/V) ; 4.4% / 3.8% / 5.2% ; +; Maximum fan-out ; 132 ; +; Highest non-global fan-out ; 120 ; +; Total fan-out ; 1418 ; +; Average fan-out ; 2.68 ; ++---------------------------------------------+----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 244 / 10320 ( 2 % ) ; 0 / 10320 ( 0 % ) ; +; -- Combinational with no register ; 113 ; 0 ; +; -- Register only ; 6 ; 0 ; +; -- Combinational with a register ; 125 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 6 ; 0 ; +; -- 3 input functions ; 81 ; 0 ; +; -- <=2 input functions ; 151 ; 0 ; +; -- Register only ; 6 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 88 ; 0 ; +; -- arithmetic mode ; 150 ; 0 ; +; ; ; ; +; Total registers ; 131 ; 0 ; +; -- Dedicated logic registers ; 131 / 10320 ( 1 % ) ; 0 / 10320 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 23 / 645 ( 4 % ) ; 0 / 645 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 68 ; 0 ; +; Embedded Multiplier 9-bit elements ; 6 / 46 ( 13 % ) ; 0 / 46 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; Clock control block ; 2 / 12 ( 16 % ) ; 0 / 12 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 1518 ; 5 ; +; -- Registered Connections ; 550 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 54 ; 0 ; +; -- Output Ports ; 14 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Kd[0] ; T9 ; 4 ; 18 ; 0 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kd[1] ; R10 ; 4 ; 21 ; 0 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kd[2] ; J14 ; 5 ; 34 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kd[3] ; N9 ; 4 ; 21 ; 0 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kd[4] ; J15 ; 5 ; 34 ; 10 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kd[5] ; K9 ; 4 ; 18 ; 0 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kd[6] ; L9 ; 4 ; 18 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kd[7] ; R9 ; 4 ; 18 ; 0 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Ki[0] ; G16 ; 6 ; 34 ; 17 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Ki[1] ; C8 ; 8 ; 13 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Ki[2] ; B6 ; 8 ; 9 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Ki[3] ; D14 ; 7 ; 32 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Ki[4] ; F6 ; 8 ; 11 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Ki[5] ; J12 ; 5 ; 34 ; 11 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Ki[6] ; D15 ; 6 ; 34 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Ki[7] ; B9 ; 7 ; 16 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kp[0] ; G2 ; 1 ; 0 ; 18 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kp[1] ; E10 ; 7 ; 28 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kp[2] ; M9 ; 4 ; 21 ; 0 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kp[3] ; G1 ; 1 ; 0 ; 18 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kp[4] ; D9 ; 7 ; 18 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kp[5] ; A8 ; 8 ; 16 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kp[6] ; A14 ; 7 ; 28 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Kp[7] ; B8 ; 8 ; 16 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[0] ; M1 ; 2 ; 0 ; 11 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[10] ; C11 ; 7 ; 23 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[11] ; B13 ; 7 ; 30 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[12] ; C15 ; 6 ; 34 ; 20 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[13] ; B12 ; 7 ; 25 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[1] ; D16 ; 6 ; 34 ; 19 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[2] ; B11 ; 7 ; 25 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[3] ; F11 ; 7 ; 23 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[4] ; G11 ; 6 ; 34 ; 20 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[5] ; F8 ; 8 ; 13 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[6] ; F14 ; 6 ; 34 ; 19 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[7] ; A11 ; 7 ; 25 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[8] ; A15 ; 7 ; 21 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Sample[9] ; C9 ; 7 ; 18 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[0] ; R12 ; 4 ; 23 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[10] ; T10 ; 4 ; 21 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[11] ; B14 ; 7 ; 28 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[12] ; F10 ; 7 ; 23 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[13] ; D11 ; 7 ; 32 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[1] ; B16 ; 6 ; 34 ; 18 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[2] ; A12 ; 7 ; 25 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[3] ; F9 ; 7 ; 23 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[4] ; B10 ; 7 ; 21 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[5] ; A10 ; 7 ; 21 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[6] ; E11 ; 7 ; 28 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[7] ; A13 ; 7 ; 30 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[8] ; E9 ; 7 ; 18 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; SetPoint[9] ; F15 ; 6 ; 34 ; 18 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; clk ; E1 ; 1 ; 0 ; 11 ; 7 ; 132 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; rst_n ; M2 ; 2 ; 0 ; 11 ; 14 ; 132 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Vout[0] ; A5 ; 8 ; 7 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[10] ; F7 ; 8 ; 11 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[11] ; F2 ; 1 ; 0 ; 19 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[12] ; E6 ; 8 ; 7 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[13] ; D8 ; 8 ; 13 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[1] ; B7 ; 8 ; 11 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[2] ; N8 ; 3 ; 16 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[3] ; E8 ; 8 ; 13 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[4] ; A7 ; 8 ; 11 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[5] ; E7 ; 8 ; 7 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[6] ; G15 ; 6 ; 34 ; 17 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[7] ; A6 ; 8 ; 9 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[8] ; A9 ; 7 ; 16 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Vout[9] ; F13 ; 6 ; 34 ; 17 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; ++----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; C1 ; DIFFIO_L1n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; D2 ; DIFFIO_L2p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; F4 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; H1 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; H2 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; H5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; J3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; J15 ; DIFFIO_R7p, DEV_CLRn ; Use as regular IO ; Kd[4] ; Dual Purpose Pin ; +; H14 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; H13 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; H12 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; G16 ; DIFFIO_R4n, INIT_DONE ; Use as regular IO ; Ki[0] ; Dual Purpose Pin ; +; G15 ; DIFFIO_R4p, CRC_ERROR ; Use as regular IO ; Vout[6] ; Dual Purpose Pin ; +; F16 ; DIFFIO_R3n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; +; F15 ; DIFFIO_R3p, CLKUSR ; Use as regular IO ; SetPoint[9] ; Dual Purpose Pin ; +; E8 ; DIFFIO_T10n, DATA2 ; Use as regular IO ; Vout[3] ; Dual Purpose Pin ; +; F8 ; DIFFIO_T10p, DATA3 ; Use as regular IO ; Sample[5] ; Dual Purpose Pin ; +; B7 ; DIFFIO_T9p, DATA4 ; Use as regular IO ; Vout[1] ; Dual Purpose Pin ; +; E7 ; DATA5 ; Use as regular IO ; Vout[5] ; Dual Purpose Pin ; +; E6 ; DATA6 ; Use as regular IO ; Vout[12] ; Dual Purpose Pin ; +; A5 ; DIFFIO_T6n, DATA7 ; Use as regular IO ; Vout[0] ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 8 / 17 ( 47 % ) ; 2.5V ; -- ; +; 2 ; 2 / 19 ( 11 % ) ; 2.5V ; -- ; +; 3 ; 1 / 26 ( 4 % ) ; 2.5V ; -- ; +; 4 ; 9 / 27 ( 33 % ) ; 2.5V ; -- ; +; 5 ; 3 / 25 ( 12 % ) ; 2.5V ; -- ; +; 6 ; 11 / 14 ( 79 % ) ; 2.5V ; -- ; +; 7 ; 24 / 26 ( 92 % ) ; 2.5V ; -- ; +; 8 ; 15 / 26 ( 58 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A2 ; 194 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 200 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 196 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 192 ; 8 ; Vout[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A6 ; 188 ; 8 ; Vout[7] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A7 ; 183 ; 8 ; Vout[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A8 ; 177 ; 8 ; Kp[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A9 ; 175 ; 7 ; Vout[8] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A10 ; 168 ; 7 ; SetPoint[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A11 ; 161 ; 7 ; Sample[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A12 ; 159 ; 7 ; SetPoint[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A13 ; 153 ; 7 ; SetPoint[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A14 ; 155 ; 7 ; Kp[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A15 ; 167 ; 7 ; Sample[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 201 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 197 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 195 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 189 ; 8 ; Ki[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B7 ; 184 ; 8 ; Vout[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B8 ; 178 ; 8 ; Kp[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B9 ; 176 ; 7 ; Ki[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B10 ; 169 ; 7 ; SetPoint[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B11 ; 162 ; 7 ; Sample[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B12 ; 160 ; 7 ; Sample[13] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B13 ; 154 ; 7 ; Sample[11] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B14 ; 156 ; 7 ; SetPoint[11] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B16 ; 141 ; 6 ; SetPoint[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; C1 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; C2 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C3 ; 202 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 187 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C7 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C8 ; 179 ; 8 ; Ki[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C9 ; 172 ; 7 ; Sample[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C10 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C11 ; 163 ; 7 ; Sample[10] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C14 ; 149 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 147 ; 6 ; Sample[12] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; C16 ; 146 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; D3 ; 203 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D4 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D5 ; 198 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 199 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D8 ; 180 ; 8 ; Vout[13] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D9 ; 173 ; 7 ; Kp[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 151 ; 7 ; SetPoint[13] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D12 ; 152 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; D14 ; 150 ; 7 ; Ki[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D15 ; 144 ; 6 ; Ki[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; D16 ; 143 ; 6 ; Sample[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E1 ; 24 ; 1 ; clk ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E5 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E6 ; 191 ; 8 ; Vout[12] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E7 ; 190 ; 8 ; Vout[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E8 ; 181 ; 8 ; Vout[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E9 ; 174 ; 7 ; SetPoint[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E10 ; 158 ; 7 ; Kp[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E11 ; 157 ; 7 ; SetPoint[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E12 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E15 ; 128 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; E16 ; 127 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; F1 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 11 ; 1 ; Vout[11] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F3 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; F4 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; F5 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; 185 ; 8 ; Ki[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F7 ; 186 ; 8 ; Vout[10] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F8 ; 182 ; 8 ; Sample[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F9 ; 165 ; 7 ; SetPoint[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F10 ; 164 ; 7 ; SetPoint[12] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F11 ; 166 ; 7 ; Sample[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F12 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; 138 ; 6 ; Vout[9] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F14 ; 142 ; 6 ; Sample[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F15 ; 140 ; 6 ; SetPoint[9] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F16 ; 139 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G1 ; 14 ; 1 ; Kp[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G2 ; 13 ; 1 ; Kp[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 10 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G11 ; 145 ; 6 ; Sample[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G12 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G12 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; 137 ; 6 ; Vout[6] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G16 ; 136 ; 6 ; Ki[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H1 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H2 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H3 ; 19 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; H4 ; 18 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; H5 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H12 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; H13 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; H14 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J1 ; 28 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; 27 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J3 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 21 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; J5 ; 20 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; J6 ; 29 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J11 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J12 ; 123 ; 5 ; Ki[5] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J13 ; 124 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J14 ; 122 ; 5 ; Kd[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J15 ; 121 ; 5 ; Kd[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J16 ; 120 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 33 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 32 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K5 ; 39 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 30 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K8 ; 60 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; 76 ; 4 ; Kd[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; K10 ; 87 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K11 ; 110 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K12 ; 105 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K15 ; 119 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; 118 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 35 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 34 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; 36 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; L4 ; 40 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L5 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L6 ; 31 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L7 ; 65 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L8 ; 68 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L9 ; 77 ; 4 ; Kd[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; L10 ; 88 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L11 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L12 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L13 ; 114 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L14 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; L15 ; 116 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; 115 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 26 ; 2 ; Sample[0] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M2 ; 25 ; 2 ; rst_n ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; 57 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M7 ; 59 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M8 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M9 ; 78 ; 4 ; Kp[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; M10 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M11 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M12 ; 103 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M15 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M16 ; 125 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 38 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 37 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 45 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N4 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N5 ; 55 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N6 ; 56 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; 70 ; 3 ; Vout[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N9 ; 79 ; 4 ; Kd[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N12 ; 101 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N13 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N14 ; 106 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 112 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; 111 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P4 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; P7 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 71 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P9 ; 89 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P11 ; 90 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P14 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P15 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 108 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; 47 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R4 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R5 ; 61 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R6 ; 63 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R7 ; 66 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R8 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R9 ; 74 ; 4 ; Kd[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R10 ; 80 ; 4 ; Kd[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R11 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 85 ; 4 ; SetPoint[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R13 ; 91 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; 109 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T2 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T3 ; 48 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T4 ; 54 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T5 ; 62 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T6 ; 64 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T7 ; 67 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T8 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 75 ; 4 ; Kd[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T10 ; 81 ; 4 ; SetPoint[10] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T11 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 86 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; 92 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T14 ; 95 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T15 ; 96 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++----------------------------------------------+ +; I/O Assignment Warnings ; ++--------------+-------------------------------+ +; Pin Name ; Reason ; ++--------------+-------------------------------+ +; Vout[0] ; Incomplete set of assignments ; +; Vout[1] ; Incomplete set of assignments ; +; Vout[2] ; Incomplete set of assignments ; +; Vout[3] ; Incomplete set of assignments ; +; Vout[4] ; Incomplete set of assignments ; +; Vout[5] ; Incomplete set of assignments ; +; Vout[6] ; Incomplete set of assignments ; +; Vout[7] ; Incomplete set of assignments ; +; Vout[8] ; Incomplete set of assignments ; +; Vout[9] ; Incomplete set of assignments ; +; Vout[10] ; Incomplete set of assignments ; +; Vout[11] ; Incomplete set of assignments ; +; Vout[12] ; Incomplete set of assignments ; +; Vout[13] ; Incomplete set of assignments ; +; clk ; Incomplete set of assignments ; +; rst_n ; Incomplete set of assignments ; +; SetPoint[13] ; Incomplete set of assignments ; +; Sample[13] ; Incomplete set of assignments ; +; Sample[12] ; Incomplete set of assignments ; +; SetPoint[12] ; Incomplete set of assignments ; +; Sample[11] ; Incomplete set of assignments ; +; SetPoint[11] ; Incomplete set of assignments ; +; Sample[10] ; Incomplete set of assignments ; +; SetPoint[10] ; Incomplete set of assignments ; +; Sample[9] ; Incomplete set of assignments ; +; SetPoint[9] ; Incomplete set of assignments ; +; Sample[8] ; Incomplete set of assignments ; +; SetPoint[8] ; Incomplete set of assignments ; +; Sample[7] ; Incomplete set of assignments ; +; SetPoint[7] ; Incomplete set of assignments ; +; Sample[6] ; Incomplete set of assignments ; +; SetPoint[6] ; Incomplete set of assignments ; +; Sample[5] ; Incomplete set of assignments ; +; SetPoint[5] ; Incomplete set of assignments ; +; Sample[4] ; Incomplete set of assignments ; +; SetPoint[4] ; Incomplete set of assignments ; +; Sample[3] ; Incomplete set of assignments ; +; SetPoint[3] ; Incomplete set of assignments ; +; Sample[2] ; Incomplete set of assignments ; +; SetPoint[2] ; Incomplete set of assignments ; +; Sample[1] ; Incomplete set of assignments ; +; SetPoint[1] ; Incomplete set of assignments ; +; Sample[0] ; Incomplete set of assignments ; +; SetPoint[0] ; Incomplete set of assignments ; +; Kd[0] ; Incomplete set of assignments ; +; Kd[1] ; Incomplete set of assignments ; +; Kd[2] ; Incomplete set of assignments ; +; Kd[3] ; Incomplete set of assignments ; +; Kd[4] ; Incomplete set of assignments ; +; Kd[5] ; Incomplete set of assignments ; +; Kd[6] ; Incomplete set of assignments ; +; Kd[7] ; Incomplete set of assignments ; +; Ki[0] ; Incomplete set of assignments ; +; Ki[1] ; Incomplete set of assignments ; +; Ki[2] ; Incomplete set of assignments ; +; Ki[3] ; Incomplete set of assignments ; +; Ki[4] ; Incomplete set of assignments ; +; Ki[5] ; Incomplete set of assignments ; +; Ki[6] ; Incomplete set of assignments ; +; Ki[7] ; Incomplete set of assignments ; +; Kp[0] ; Incomplete set of assignments ; +; Kp[1] ; Incomplete set of assignments ; +; Kp[2] ; Incomplete set of assignments ; +; Kp[3] ; Incomplete set of assignments ; +; Kp[4] ; Incomplete set of assignments ; +; Kp[5] ; Incomplete set of assignments ; +; Kp[6] ; Incomplete set of assignments ; +; Kp[7] ; Incomplete set of assignments ; +; Vout[0] ; Missing location assignment ; +; Vout[1] ; Missing location assignment ; +; Vout[2] ; Missing location assignment ; +; Vout[3] ; Missing location assignment ; +; Vout[4] ; Missing location assignment ; +; Vout[5] ; Missing location assignment ; +; Vout[6] ; Missing location assignment ; +; Vout[7] ; Missing location assignment ; +; Vout[8] ; Missing location assignment ; +; Vout[9] ; Missing location assignment ; +; Vout[10] ; Missing location assignment ; +; Vout[11] ; Missing location assignment ; +; Vout[12] ; Missing location assignment ; +; Vout[13] ; Missing location assignment ; +; clk ; Missing location assignment ; +; rst_n ; Missing location assignment ; +; SetPoint[13] ; Missing location assignment ; +; Sample[13] ; Missing location assignment ; +; Sample[12] ; Missing location assignment ; +; SetPoint[12] ; Missing location assignment ; +; Sample[11] ; Missing location assignment ; +; SetPoint[11] ; Missing location assignment ; +; Sample[10] ; Missing location assignment ; +; SetPoint[10] ; Missing location assignment ; +; Sample[9] ; Missing location assignment ; +; SetPoint[9] ; Missing location assignment ; +; Sample[8] ; Missing location assignment ; +; SetPoint[8] ; Missing location assignment ; +; Sample[7] ; Missing location assignment ; +; SetPoint[7] ; Missing location assignment ; +; Sample[6] ; Missing location assignment ; +; SetPoint[6] ; Missing location assignment ; +; Sample[5] ; Missing location assignment ; +; SetPoint[5] ; Missing location assignment ; +; Sample[4] ; Missing location assignment ; +; SetPoint[4] ; Missing location assignment ; +; Sample[3] ; Missing location assignment ; +; SetPoint[3] ; Missing location assignment ; +; Sample[2] ; Missing location assignment ; +; SetPoint[2] ; Missing location assignment ; +; Sample[1] ; Missing location assignment ; +; SetPoint[1] ; Missing location assignment ; +; Sample[0] ; Missing location assignment ; +; SetPoint[0] ; Missing location assignment ; +; Kd[0] ; Missing location assignment ; +; Kd[1] ; Missing location assignment ; +; Kd[2] ; Missing location assignment ; +; Kd[3] ; Missing location assignment ; +; Kd[4] ; Missing location assignment ; +; Kd[5] ; Missing location assignment ; +; Kd[6] ; Missing location assignment ; +; Kd[7] ; Missing location assignment ; +; Ki[0] ; Missing location assignment ; +; Ki[1] ; Missing location assignment ; +; Ki[2] ; Missing location assignment ; +; Ki[3] ; Missing location assignment ; +; Ki[4] ; Missing location assignment ; +; Ki[5] ; Missing location assignment ; +; Ki[6] ; Missing location assignment ; +; Ki[7] ; Missing location assignment ; +; Kp[0] ; Missing location assignment ; +; Kp[1] ; Missing location assignment ; +; Kp[2] ; Missing location assignment ; +; Kp[3] ; Missing location assignment ; +; Kp[4] ; Missing location assignment ; +; Kp[5] ; Missing location assignment ; +; Kp[6] ; Missing location assignment ; +; Kp[7] ; Missing location assignment ; ++--------------+-------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------+-------------+--------------+ +; |pid ; 244 (244) ; 131 (131) ; 0 (0) ; 0 ; 0 ; 6 ; 0 ; 3 ; 68 ; 0 ; 113 (113) ; 6 (6) ; 125 (125) ; |pid ; pid ; work ; +; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |pid|lpm_mult:Mult0 ; lpm_mult ; work ; +; |mult_kbt:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |pid|lpm_mult:Mult0|mult_kbt:auto_generated ; mult_kbt ; work ; +; |lpm_mult:Mult1| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |pid|lpm_mult:Mult1 ; lpm_mult ; work ; +; |mult_gbt:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |pid|lpm_mult:Mult1|mult_gbt:auto_generated ; mult_gbt ; work ; +; |lpm_mult:Mult2| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |pid|lpm_mult:Mult2 ; lpm_mult ; work ; +; |mult_gbt:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |pid|lpm_mult:Mult2|mult_gbt:auto_generated ; mult_gbt ; work ; ++---------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------------------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++--------------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++--------------+----------+---------------+---------------+-----------------------+-----+------+ +; Vout[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[10] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[11] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[12] ; Output ; -- ; -- ; -- ; -- ; -- ; +; Vout[13] ; Output ; -- ; -- ; -- ; -- ; -- ; +; clk ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; rst_n ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SetPoint[13] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Sample[13] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Sample[12] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SetPoint[12] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Sample[11] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SetPoint[11] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Sample[10] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SetPoint[10] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Sample[9] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SetPoint[9] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Sample[8] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SetPoint[8] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Sample[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SetPoint[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Sample[6] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SetPoint[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Sample[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SetPoint[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Sample[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SetPoint[4] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Sample[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SetPoint[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Sample[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SetPoint[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Sample[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; SetPoint[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Sample[0] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SetPoint[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Kd[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Kd[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Kd[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Kd[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Kd[4] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Kd[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Kd[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Kd[7] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Ki[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Ki[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Ki[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Ki[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Ki[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Ki[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Ki[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Ki[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Kp[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Kp[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Kp[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Kp[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Kp[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Kp[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Kp[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Kp[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; ++--------------+----------+---------------+---------------+-----------------------+-----+------+ + + ++---------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------------------------------------------+-------------------+---------+ +; clk ; ; ; +; rst_n ; ; ; +; SetPoint[13] ; ; ; +; - Add1~0 ; 0 ; 6 ; +; Sample[13] ; ; ; +; - Add1~1 ; 1 ; 6 ; +; Sample[12] ; ; ; +; - Add1~2 ; 0 ; 6 ; +; SetPoint[12] ; ; ; +; - Add1~3 ; 0 ; 6 ; +; Sample[11] ; ; ; +; - Add1~4 ; 1 ; 6 ; +; SetPoint[11] ; ; ; +; - Add1~5 ; 1 ; 6 ; +; Sample[10] ; ; ; +; - Add1~6 ; 0 ; 6 ; +; SetPoint[10] ; ; ; +; - Add1~7 ; 1 ; 6 ; +; Sample[9] ; ; ; +; - Add1~8 ; 1 ; 6 ; +; SetPoint[9] ; ; ; +; - Add1~9 ; 0 ; 6 ; +; Sample[8] ; ; ; +; - Add1~10 ; 0 ; 6 ; +; SetPoint[8] ; ; ; +; - Add1~11 ; 1 ; 6 ; +; Sample[7] ; ; ; +; - Add1~12 ; 0 ; 6 ; +; SetPoint[7] ; ; ; +; - Add1~13 ; 0 ; 6 ; +; Sample[6] ; ; ; +; - Add1~14 ; 1 ; 6 ; +; SetPoint[6] ; ; ; +; - Add1~15 ; 0 ; 6 ; +; Sample[5] ; ; ; +; - Add1~16 ; 0 ; 6 ; +; SetPoint[5] ; ; ; +; - Add1~17 ; 0 ; 6 ; +; Sample[4] ; ; ; +; - Add1~18 ; 0 ; 6 ; +; SetPoint[4] ; ; ; +; - Add1~19 ; 1 ; 6 ; +; Sample[3] ; ; ; +; - Add1~20 ; 1 ; 6 ; +; SetPoint[3] ; ; ; +; - Add1~21 ; 0 ; 6 ; +; Sample[2] ; ; ; +; - Add1~22 ; 0 ; 6 ; +; SetPoint[2] ; ; ; +; - Add1~23 ; 0 ; 6 ; +; Sample[1] ; ; ; +; - Add1~24 ; 1 ; 6 ; +; SetPoint[1] ; ; ; +; - Add1~25 ; 0 ; 6 ; +; Sample[0] ; ; ; +; SetPoint[0] ; ; ; +; - Add1~27 ; 0 ; 6 ; +; Kd[0] ; ; ; +; - lpm_mult:Mult2|mult_gbt:auto_generated|mac_mult1 ; 1 ; 6 ; +; Kd[1] ; ; ; +; - lpm_mult:Mult2|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Kd[2] ; ; ; +; - lpm_mult:Mult2|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Kd[3] ; ; ; +; - lpm_mult:Mult2|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Kd[4] ; ; ; +; - lpm_mult:Mult2|mult_gbt:auto_generated|mac_mult1 ; 1 ; 6 ; +; Kd[5] ; ; ; +; - lpm_mult:Mult2|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Kd[6] ; ; ; +; - lpm_mult:Mult2|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Kd[7] ; ; ; +; - lpm_mult:Mult2|mult_gbt:auto_generated|mac_mult1 ; 1 ; 6 ; +; Ki[0] ; ; ; +; - lpm_mult:Mult1|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Ki[1] ; ; ; +; - lpm_mult:Mult1|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Ki[2] ; ; ; +; - lpm_mult:Mult1|mult_gbt:auto_generated|mac_mult1 ; 1 ; 6 ; +; Ki[3] ; ; ; +; - lpm_mult:Mult1|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Ki[4] ; ; ; +; - lpm_mult:Mult1|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Ki[5] ; ; ; +; - lpm_mult:Mult1|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Ki[6] ; ; ; +; - lpm_mult:Mult1|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Ki[7] ; ; ; +; - lpm_mult:Mult1|mult_gbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Kp[0] ; ; ; +; - lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; 1 ; 6 ; +; Kp[1] ; ; ; +; - lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; 1 ; 6 ; +; Kp[2] ; ; ; +; - lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; 1 ; 6 ; +; Kp[3] ; ; ; +; - lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; 1 ; 6 ; +; Kp[4] ; ; ; +; - lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Kp[5] ; ; ; +; - lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Kp[6] ; ; ; +; - lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; 0 ; 6 ; +; Kp[7] ; ; ; +; - lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; 0 ; 6 ; ++---------------------------------------------------------+-------------------+---------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++----------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Clk_Ctrl ; FF_X23_Y13_N1 ; 120 ; Clock enable ; no ; -- ; -- ; -- ; +; EE0[13]~_Duplicate_1 ; FF_X21_Y18_N31 ; 51 ; Sync. load ; no ; -- ; -- ; -- ; +; EE1[13] ; FF_X21_Y17_N29 ; 37 ; Sync. load ; no ; -- ; -- ; -- ; +; EE2[13] ; FF_X21_Y14_N31 ; 36 ; Sync. load ; no ; -- ; -- ; -- ; +; clk ; PIN_E1 ; 132 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; +; rst_n ; PIN_M2 ; 132 ; Async. clear ; yes ; Global Clock ; GCLK4 ; -- ; ++----------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; clk ; PIN_E1 ; 132 ; 50 ; Global Clock ; GCLK2 ; -- ; +; rst_n ; PIN_M2 ; 132 ; 0 ; Global Clock ; GCLK4 ; -- ; ++-------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------+ +; Fitter DSP Block Usage Summary ; ++---------------------------------------+-------------+---------------------+-------------------+ +; Statistic ; Number Used ; Available per Block ; Maximum Available ; ++---------------------------------------+-------------+---------------------+-------------------+ +; Simple Multipliers (9-bit) ; 0 ; 2 ; 46 ; +; Simple Multipliers (18-bit) ; 3 ; 1 ; 23 ; +; Embedded Multiplier Blocks ; 3 ; -- ; 23 ; +; Embedded Multiplier 9-bit elements ; 6 ; 2 ; 46 ; +; Signed Embedded Multipliers ; 0 ; -- ; -- ; +; Unsigned Embedded Multipliers ; 3 ; -- ; -- ; +; Mixed Sign Embedded Multipliers ; 0 ; -- ; -- ; +; Variable Sign Embedded Multipliers ; 0 ; -- ; -- ; +; Dedicated Input Shift Register Chains ; 0 ; -- ; -- ; ++---------------------------------------+-------------+---------------------+-------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; DSP Block Details ; ++-----------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ +; Name ; Mode ; Location ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ; ++-----------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ +; lpm_mult:Mult2|mult_gbt:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X20_Y14_N2 ; ; No ; ; ; ; no ; +; lpm_mult:Mult2|mult_gbt:auto_generated|mac_mult1 ; ; DSPMULT_X20_Y14_N0 ; Unsigned ; ; no ; no ; no ; ; +; lpm_mult:Mult1|mult_gbt:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X20_Y17_N2 ; ; No ; ; ; ; no ; +; lpm_mult:Mult1|mult_gbt:auto_generated|mac_mult1 ; ; DSPMULT_X20_Y17_N0 ; Unsigned ; ; no ; no ; no ; ; +; lpm_mult:Mult0|mult_kbt:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X20_Y18_N2 ; ; No ; ; ; ; no ; +; lpm_mult:Mult0|mult_kbt:auto_generated|mac_mult1 ; ; DSPMULT_X20_Y18_N0 ; Unsigned ; ; yes ; no ; no ; ; ++-----------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 407 / 32,401 ( 1 % ) ; +; C16 interconnects ; 38 / 1,326 ( 3 % ) ; +; C4 interconnects ; 202 / 21,816 ( < 1 % ) ; +; Direct links ; 117 / 32,401 ( < 1 % ) ; +; Global clocks ; 2 / 10 ( 20 % ) ; +; Local interconnects ; 134 / 10,320 ( 1 % ) ; +; R24 interconnects ; 23 / 1,289 ( 2 % ) ; +; R4 interconnects ; 215 / 28,186 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+------------------------------+ +; Number of Logic Elements (Average = 10.61) ; Number of LABs (Total = 23) ; ++---------------------------------------------+------------------------------+ +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 2 ; +; 4 ; 2 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 3 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 1 ; +; 15 ; 1 ; +; 16 ; 8 ; ++---------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 1.87) ; Number of LABs (Total = 23) ; ++------------------------------------+------------------------------+ +; 1 Async. clear ; 13 ; +; 1 Clock ; 13 ; +; 1 Clock enable ; 11 ; +; 1 Sync. load ; 6 ; ++------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 15.96) ; Number of LABs (Total = 23) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 2 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 4 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 1 ; +; 21 ; 1 ; +; 22 ; 1 ; +; 23 ; 1 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 1 ; +; 27 ; 1 ; +; 28 ; 1 ; +; 29 ; 2 ; +; 30 ; 0 ; +; 31 ; 0 ; +; 32 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++--------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 9.43) ; Number of LABs (Total = 23) ; ++-------------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 3 ; +; 4 ; 2 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 5 ; +; 12 ; 2 ; +; 13 ; 1 ; +; 14 ; 0 ; +; 15 ; 1 ; +; 16 ; 2 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 1 ; ++-------------------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 15.04) ; Number of LABs (Total = 23) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 2 ; +; 5 ; 2 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 1 ; +; 15 ; 1 ; +; 16 ; 3 ; +; 17 ; 1 ; +; 18 ; 1 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 1 ; +; 24 ; 1 ; +; 25 ; 0 ; +; 26 ; 2 ; +; 27 ; 1 ; +; 28 ; 0 ; +; 29 ; 1 ; +; 30 ; 0 ; +; 31 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 68 ; 0 ; 0 ; 68 ; 68 ; 0 ; 14 ; 0 ; 0 ; 54 ; 0 ; 14 ; 54 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 68 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 68 ; 68 ; 68 ; 68 ; 68 ; 0 ; 68 ; 68 ; 0 ; 0 ; 68 ; 54 ; 68 ; 68 ; 14 ; 68 ; 54 ; 14 ; 68 ; 68 ; 68 ; 54 ; 68 ; 68 ; 68 ; 68 ; 68 ; 0 ; 68 ; 68 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Vout[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Vout[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; clk ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; rst_n ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Sample[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SetPoint[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kd[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kd[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kd[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kd[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kd[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kd[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kd[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kd[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Ki[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Ki[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Ki[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Ki[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Ki[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Ki[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Ki[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Ki[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kp[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kp[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kp[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kp[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kp[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kp[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kp[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Kp[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 C ; +; High Junction Temperature ; 85 C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device EP4CE10F17C8 for design "pid" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE6F17C8 is compatible + Info (176445): Device EP4CE15F17C8 is compatible + Info (176445): Device EP4CE22F17C8 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 68 pins of 68 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Critical Warning (332012): Synopsys Design Constraints File file not found: 'pid.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) File: F:/Code/FPGA/reserve/pid/rtl/pid.v Line: 15 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 +Info (176353): Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) File: F:/Code/FPGA/reserve/pid/rtl/pid.v Line: 15 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176218): Packed 14 registers into blocks of type Embedded multiplier block + Extra Info (176220): Created 14 register duplicates +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 66 (unused VREF, 2.5V VCCIO, 52 input, 14 output, 0 bidirectional) + Info (176212): I/O standards used: 2.5 V. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:03 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 0.37 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (144001): Generated suppressed messages file F:/Code/FPGA/reserve/pid/output_files/pid.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 5566 megabytes + Info: Processing ended: Tue Dec 04 14:36:29 2018 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:12 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in F:/Code/FPGA/reserve/pid/output_files/pid.fit.smsg. + + diff --git a/pid/output_files/pid.fit.smsg b/pid/output_files/pid.fit.smsg new file mode 100644 index 0000000..ed080d6 --- /dev/null +++ b/pid/output_files/pid.fit.smsg @@ -0,0 +1,6 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/pid/output_files/pid.fit.summary b/pid/output_files/pid.fit.summary new file mode 100644 index 0000000..932dac1 --- /dev/null +++ b/pid/output_files/pid.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Tue Dec 04 14:36:29 2018 +Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Revision Name : pid +Top-level Entity Name : pid +Family : Cyclone IV E +Device : EP4CE10F17C8 +Timing Models : Final +Total logic elements : 244 / 10,320 ( 2 % ) + Total combinational functions : 238 / 10,320 ( 2 % ) + Dedicated logic registers : 131 / 10,320 ( 1 % ) +Total registers : 131 +Total pins : 68 / 180 ( 38 % ) +Total virtual pins : 0 +Total memory bits : 0 / 423,936 ( 0 % ) +Embedded Multiplier 9-bit elements : 6 / 46 ( 13 % ) +Total PLLs : 0 / 2 ( 0 % ) diff --git a/pid/output_files/pid.flow.rpt b/pid/output_files/pid.flow.rpt new file mode 100644 index 0000000..566e296 --- /dev/null +++ b/pid/output_files/pid.flow.rpt @@ -0,0 +1,125 @@ +Flow report for pid +Sat Dec 08 18:44:24 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Sat Dec 08 18:44:24 2018 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; pid ; +; Top-level Entity Name ; pid ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Total logic elements ; 204 ; +; Total combinational functions ; 104 ; +; Dedicated logic registers ; 161 ; +; Total registers ; 161 ; +; Total pins ; 71 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 2 ; +; Total PLLs ; 0 ; ++------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/08/2018 18:44:09 ; +; Main task ; Compilation ; +; Revision Name ; pid ; ++-------------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++--------------------------------------+----------------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++--------------------------------------+----------------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 93383153531551.154426584911168 ; -- ; -- ; -- ; +; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; pid_tb ; +; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; pid_tb ; -- ; -- ; eda_simulation ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; +; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ; +; EDA_TEST_BENCH_FILE ; testbench/pid_tb.v ; -- ; -- ; pid_tb ; +; EDA_TEST_BENCH_MODULE_NAME ; pid_tb ; -- ; -- ; pid_tb ; +; EDA_TEST_BENCH_NAME ; pid_tb ; -- ; -- ; eda_simulation ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++--------------------------------------+----------------------------------------+---------------+-------------+----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:15 ; 1.0 ; 4792 MB ; 00:00:32 ; +; Total ; 00:00:15 ; -- ; -- ; 00:00:32 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; ++----------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off pid -c pid + + + diff --git a/pid/output_files/pid.jdi b/pid/output_files/pid.jdi new file mode 100644 index 0000000..9fb52df --- /dev/null +++ b/pid/output_files/pid.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/pid/output_files/pid.map.rpt b/pid/output_files/pid.map.rpt new file mode 100644 index 0000000..70f9243 --- /dev/null +++ b/pid/output_files/pid.map.rpt @@ -0,0 +1,462 @@ +Analysis & Synthesis report for pid +Sat Dec 08 18:44:24 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis DSP Block Usage Summary + 9. State Machine - |pid|status + 10. Registers Removed During Synthesis + 11. General Register Statistics + 12. Multiplexer Restructuring Statistics (Restructuring Performed) + 13. Parameter Settings for User Entity Instance: Top-level Entity: |pid + 14. Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0 + 15. lpm_mult Parameter Settings by Entity Instance + 16. Post-Synthesis Netlist Statistics for Top Partition + 17. Elapsed Time Per Partition + 18. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sat Dec 08 18:44:24 2018 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; pid ; +; Top-level Entity Name ; pid ; +; Family ; Cyclone IV E ; +; Total logic elements ; 204 ; +; Total combinational functions ; 104 ; +; Dedicated logic registers ; 161 ; +; Total registers ; 161 ; +; Total pins ; 71 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 2 ; +; Total PLLs ; 0 ; ++------------------------------------+-------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP4CE10F17C8 ; ; +; Top-level entity name ; pid ; pid ; +; Family name ; Cyclone IV E ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.0% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+---------+ +; rtl/pid.v ; yes ; User Verilog HDL File ; F:/Code/FPGA/reserve/pid/rtl/pid.v ; ; +; lpm_mult.tdf ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf ; ; +; aglobal181.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/aglobal181.inc ; ; +; lpm_add_sub.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; +; multcore.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/multcore.inc ; ; +; bypassff.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/bypassff.inc ; ; +; altshift.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/altshift.inc ; ; +; db/mult_k4t.tdf ; yes ; Auto-Generated Megafunction ; F:/Code/FPGA/reserve/pid/db/mult_k4t.tdf ; ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------+---------+ + + ++---------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-----------+ +; Resource ; Usage ; ++---------------------------------------------+-----------+ +; Estimated Total logic elements ; 204 ; +; ; ; +; Total combinational functions ; 104 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 3 ; +; -- 3 input functions ; 86 ; +; -- <=2 input functions ; 15 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 42 ; +; -- arithmetic mode ; 62 ; +; ; ; +; Total registers ; 161 ; +; -- Dedicated logic registers ; 161 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 71 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 2 ; +; ; ; +; Maximum fan-out node ; clk~input ; +; Maximum fan-out ; 161 ; +; Total fan-out ; 1088 ; +; Average fan-out ; 2.66 ; ++---------------------------------------------+-----------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++---------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++---------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------+-------------+--------------+ +; |pid ; 104 (104) ; 161 (161) ; 0 ; 2 ; 0 ; 1 ; 71 ; 0 ; |pid ; pid ; work ; +; |lpm_mult:Mult0| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |pid|lpm_mult:Mult0 ; lpm_mult ; work ; +; |mult_k4t:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |pid|lpm_mult:Mult0|mult_k4t:auto_generated ; mult_k4t ; work ; ++---------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-----------------------------------------------------+ +; Analysis & Synthesis DSP Block Usage Summary ; ++---------------------------------------+-------------+ +; Statistic ; Number Used ; ++---------------------------------------+-------------+ +; Simple Multipliers (9-bit) ; 0 ; +; Simple Multipliers (18-bit) ; 1 ; +; Embedded Multiplier Blocks ; -- ; +; Embedded Multiplier 9-bit elements ; 2 ; +; Signed Embedded Multipliers ; 1 ; +; Unsigned Embedded Multipliers ; 0 ; +; Mixed Sign Embedded Multipliers ; 0 ; +; Variable Sign Embedded Multipliers ; 0 ; +; Dedicated Input Shift Register Chains ; 0 ; ++---------------------------------------+-------------+ +Note: number of Embedded Multiplier Blocks used is only available after a successful fit. + + +Encoding Type: One-Hot ++-----------------------------------------------------------------------------------------------------------+ +; State Machine - |pid|status ; ++-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+ +; Name ; status.s5 ; status.s4 ; status.s6 ; status.s7 ; status.s2 ; status.s3 ; status.s1 ; status.s0 ; ++-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+ +; status.s0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; status.s1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; status.s3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; status.s2 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; status.s7 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; status.s6 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; status.s4 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; status.s5 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+ + + ++------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------+--------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------+--------------------+ +; Kd_Out[22] ; Lost fanout ; +; Kp_Out[22] ; Lost fanout ; +; Ki_Out[22] ; Lost fanout ; +; status~4 ; Lost fanout ; +; status~5 ; Lost fanout ; +; status~6 ; Lost fanout ; +; status~7 ; Lost fanout ; +; Total Number of Removed Registers = 7 ; ; ++---------------------------------------+--------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 161 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 23 ; +; Number of registers using Asynchronous Clear ; 161 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 153 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; 4:1 ; 23 bits ; 46 LEs ; 46 LEs ; 0 LEs ; Yes ; |pid|EETMP[10] ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ + + ++---------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Top-level Entity: |pid ; ++----------------+-------+--------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------+ +; par0 ; 6 ; Signed Integer ; +; s0 ; 0000 ; Unsigned Binary ; +; s1 ; 0001 ; Unsigned Binary ; +; s2 ; 0011 ; Unsigned Binary ; +; s3 ; 0010 ; Unsigned Binary ; +; s4 ; 0110 ; Unsigned Binary ; +; s5 ; 0111 ; Unsigned Binary ; +; s6 ; 0101 ; Unsigned Binary ; +; s7 ; 0100 ; Unsigned Binary ; ++----------------+-------+--------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0 ; ++------------------------------------------------+--------------+---------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------------------+--------------+---------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTHA ; 14 ; Untyped ; +; LPM_WIDTHB ; 9 ; Untyped ; +; LPM_WIDTHP ; 23 ; Untyped ; +; LPM_WIDTHR ; 23 ; Untyped ; +; LPM_WIDTHS ; 1 ; Untyped ; +; LPM_REPRESENTATION ; SIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LATENCY ; 0 ; Untyped ; +; INPUT_A_IS_CONSTANT ; NO ; Untyped ; +; INPUT_B_IS_CONSTANT ; NO ; Untyped ; +; USE_EAB ; OFF ; Untyped ; +; MAXIMIZE_SPEED ; 6 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; +; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; CBXI_PARAMETER ; mult_k4t ; Untyped ; +; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; +; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; +; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; ++------------------------------------------------+--------------+---------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------+ +; lpm_mult Parameter Settings by Entity Instance ; ++---------------------------------------+----------------+ +; Name ; Value ; ++---------------------------------------+----------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; lpm_mult:Mult0 ; +; -- LPM_WIDTHA ; 14 ; +; -- LPM_WIDTHB ; 9 ; +; -- LPM_WIDTHP ; 23 ; +; -- LPM_REPRESENTATION ; SIGNED ; +; -- INPUT_A_IS_CONSTANT ; NO ; +; -- INPUT_B_IS_CONSTANT ; NO ; +; -- USE_EAB ; OFF ; +; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; +; -- INPUT_A_FIXED_VALUE ; Bx ; +; -- INPUT_B_FIXED_VALUE ; Bx ; ++---------------------------------------+----------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 71 ; +; cycloneiii_ff ; 161 ; +; CLR ; 8 ; +; ENA CLR ; 130 ; +; ENA CLR SLD ; 23 ; +; cycloneiii_lcell_comb ; 104 ; +; arith ; 62 ; +; 2 data inputs ; 7 ; +; 3 data inputs ; 55 ; +; normal ; 42 ; +; 1 data inputs ; 3 ; +; 2 data inputs ; 5 ; +; 3 data inputs ; 31 ; +; 4 data inputs ; 3 ; +; cycloneiii_mac_mult ; 1 ; +; cycloneiii_mac_out ; 1 ; +; ; ; +; Max LUT depth ; 4.10 ; +; Average LUT depth ; 1.76 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Sat Dec 08 18:44:09 2018 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pid -c pid +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file rtl/pid.v + Info (12023): Found entity 1: pid File: F:/Code/FPGA/reserve/pid/rtl/pid.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file testbench/pid_tb.v + Info (12023): Found entity 1: pid_tb File: F:/Code/FPGA/reserve/pid/testbench/pid_tb.v Line: 5 +Info (12127): Elaborating entity "pid" for the top level hierarchy +Warning (10230): Verilog HDL assignment warning at pid.v(75): truncated value with size 23 to match size of target (14) File: F:/Code/FPGA/reserve/pid/rtl/pid.v Line: 75 +Info (278001): Inferred 1 megafunctions from design logic + Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "Mult0" File: F:/Code/FPGA/reserve/pid/rtl/pid.v Line: 70 +Info (12130): Elaborated megafunction instantiation "lpm_mult:Mult0" File: F:/Code/FPGA/reserve/pid/rtl/pid.v Line: 70 +Info (12133): Instantiated megafunction "lpm_mult:Mult0" with the following parameter: File: F:/Code/FPGA/reserve/pid/rtl/pid.v Line: 70 + Info (12134): Parameter "LPM_WIDTHA" = "14" + Info (12134): Parameter "LPM_WIDTHB" = "9" + Info (12134): Parameter "LPM_WIDTHP" = "23" + Info (12134): Parameter "LPM_WIDTHR" = "23" + Info (12134): Parameter "LPM_WIDTHS" = "1" + Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED" + Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" + Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO" + Info (12134): Parameter "MAXIMIZE_SPEED" = "6" +Info (12021): Found 1 design units, including 1 entities, in source file db/mult_k4t.tdf + Info (12023): Found entity 1: mult_k4t File: F:/Code/FPGA/reserve/pid/db/mult_k4t.tdf Line: 28 +Info (286030): Timing-Driven Synthesis is running +Info (17049): 7 registers lost all their fanouts during netlist optimizations. +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 277 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 57 input pins + Info (21059): Implemented 14 output pins + Info (21061): Implemented 204 logic cells + Info (21062): Implemented 2 DSP elements +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 4792 megabytes + Info: Processing ended: Sat Dec 08 18:44:24 2018 + Info: Elapsed time: 00:00:15 + Info: Total CPU time (on all processors): 00:00:32 + + diff --git a/pid/output_files/pid.map.smsg b/pid/output_files/pid.map.smsg new file mode 100644 index 0000000..2c9de05 --- /dev/null +++ b/pid/output_files/pid.map.smsg @@ -0,0 +1 @@ +Warning (10268): Verilog HDL information at pid.v(42): always construct contains both blocking and non-blocking assignments File: F:/Code/FPGA/reserve/pid/rtl/pid.v Line: 42 diff --git a/pid/output_files/pid.map.summary b/pid/output_files/pid.map.summary new file mode 100644 index 0000000..4774954 --- /dev/null +++ b/pid/output_files/pid.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Sat Dec 08 18:44:24 2018 +Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Revision Name : pid +Top-level Entity Name : pid +Family : Cyclone IV E +Total logic elements : 204 + Total combinational functions : 104 + Dedicated logic registers : 161 +Total registers : 161 +Total pins : 71 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 2 +Total PLLs : 0 diff --git a/pid/output_files/pid.pin b/pid/output_files/pid.pin new file mode 100644 index 0000000..1cab564 --- /dev/null +++ b/pid/output_files/pid.pin @@ -0,0 +1,326 @@ + -- Copyright (C) 2018 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +CHIP "pid" ASSIGNED TO AN: EP4CE10F17C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +VCCIO8 : A1 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 : +Vout[0] : A5 : output : 2.5 V : : 8 : N +Vout[7] : A6 : output : 2.5 V : : 8 : N +Vout[4] : A7 : output : 2.5 V : : 8 : N +Kp[5] : A8 : input : 2.5 V : : 8 : N +Vout[8] : A9 : output : 2.5 V : : 7 : N +SetPoint[5] : A10 : input : 2.5 V : : 7 : N +Sample[7] : A11 : input : 2.5 V : : 7 : N +SetPoint[2] : A12 : input : 2.5 V : : 7 : N +SetPoint[7] : A13 : input : 2.5 V : : 7 : N +Kp[6] : A14 : input : 2.5 V : : 7 : N +Sample[8] : A15 : input : 2.5 V : : 7 : N +VCCIO7 : A16 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 1 : +GND : B2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +Ki[2] : B6 : input : 2.5 V : : 8 : N +Vout[1] : B7 : output : 2.5 V : : 8 : N +Kp[7] : B8 : input : 2.5 V : : 8 : N +Ki[7] : B9 : input : 2.5 V : : 7 : N +SetPoint[4] : B10 : input : 2.5 V : : 7 : N +Sample[2] : B11 : input : 2.5 V : : 7 : N +Sample[13] : B12 : input : 2.5 V : : 7 : N +Sample[11] : B13 : input : 2.5 V : : 7 : N +SetPoint[11] : B14 : input : 2.5 V : : 7 : N +GND : B15 : gnd : : : : +SetPoint[1] : B16 : input : 2.5 V : : 6 : N +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +VCCIO8 : C4 : power : : 2.5V : 8 : +GND : C5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +VCCIO8 : C7 : power : : 2.5V : 8 : +Ki[1] : C8 : input : 2.5 V : : 8 : N +Sample[9] : C9 : input : 2.5 V : : 7 : N +VCCIO7 : C10 : power : : 2.5V : 7 : +Sample[10] : C11 : input : 2.5 V : : 7 : N +GND : C12 : gnd : : : : +VCCIO7 : C13 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +Sample[12] : C15 : input : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 : +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 : +GND : D7 : gnd : : : : +Vout[13] : D8 : output : 2.5 V : : 8 : N +Kp[4] : D9 : input : 2.5 V : : 7 : N +GND : D10 : gnd : : : : +SetPoint[13] : D11 : input : 2.5 V : : 7 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 : +VCCD_PLL2 : D13 : power : : 1.2V : : +Ki[3] : D14 : input : 2.5 V : : 7 : N +Ki[6] : D15 : input : 2.5 V : : 6 : N +Sample[1] : D16 : input : 2.5 V : : 6 : N +clk : E1 : input : 2.5 V : : 1 : N +GND : E2 : gnd : : : : +VCCIO1 : E3 : power : : 2.5V : 1 : +GND : E4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 1 : +Vout[12] : E6 : output : 2.5 V : : 8 : N +Vout[5] : E7 : output : 2.5 V : : 8 : N +Vout[3] : E8 : output : 2.5 V : : 8 : N +SetPoint[8] : E9 : input : 2.5 V : : 7 : N +Kp[1] : E10 : input : 2.5 V : : 7 : N +SetPoint[6] : E11 : input : 2.5 V : : 7 : N +GNDA2 : E12 : gnd : : : : +GND : E13 : gnd : : : : +VCCIO6 : E14 : power : : 2.5V : 6 : +GND+ : E15 : : : : 6 : +GND+ : E16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : +Vout[11] : F2 : output : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 : +nSTATUS : F4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 : +Ki[4] : F6 : input : 2.5 V : : 8 : N +Vout[10] : F7 : output : 2.5 V : : 8 : N +Sample[5] : F8 : input : 2.5 V : : 8 : N +SetPoint[3] : F9 : input : 2.5 V : : 7 : N +SetPoint[12] : F10 : input : 2.5 V : : 7 : N +Sample[3] : F11 : input : 2.5 V : : 7 : N +VCCA2 : F12 : power : : 2.5V : : +Vout[9] : F13 : output : 2.5 V : : 6 : N +Sample[6] : F14 : input : 2.5 V : : 6 : N +SetPoint[9] : F15 : input : 2.5 V : : 6 : N +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 2.5 V : : 6 : N +Kp[3] : G1 : input : 2.5 V : : 1 : N +Kp[0] : G2 : input : 2.5 V : : 1 : N +VCCIO1 : G3 : power : : 2.5V : 1 : +GND : G4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 : +VCCINT : G6 : power : : 1.2V : : +VCCINT : G7 : power : : 1.2V : : +VCCINT : G8 : power : : 1.2V : : +VCCINT : G9 : power : : 1.2V : : +VCCINT : G10 : power : : 1.2V : : +Sample[4] : G11 : input : 2.5 V : : 6 : N +MSEL2 : G12 : : : : 6 : +GND : G13 : gnd : : : : +VCCIO6 : G14 : power : : 2.5V : 6 : +Vout[6] : G15 : output : 2.5 V : : 6 : N +Ki[0] : G16 : input : 2.5 V : : 6 : N +~ALTERA_DCLK~ : H1 : output : 2.5 V : : 1 : N +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V : : 1 : N +TCK : H3 : input : : : 1 : +TDI : H4 : input : : : 1 : +nCONFIG : H5 : : : : 1 : +VCCINT : H6 : power : : 1.2V : : +GND : H7 : gnd : : : : +GND : H8 : gnd : : : : +GND : H9 : gnd : : : : +GND : H10 : gnd : : : : +VCCINT : H11 : power : : 1.2V : : +MSEL1 : H12 : : : : 6 : +MSEL0 : H13 : : : : 6 : +CONF_DONE : H14 : : : : 6 : +GND : H15 : gnd : : : : +GND : H16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 2 : +nCE : J3 : : : : 1 : +TDO : J4 : output : : : 1 : +TMS : J5 : input : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 2 : +GND : J7 : gnd : : : : +GND : J8 : gnd : : : : +GND : J9 : gnd : : : : +GND : J10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 5 : +Ki[5] : J12 : input : 2.5 V : : 5 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 5 : +Kd[2] : J14 : input : 2.5 V : : 5 : N +Kd[4] : J15 : input : 2.5 V : : 5 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 2 : +VCCIO2 : K3 : power : : 2.5V : 2 : +GND : K4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 2 : +VCCINT : K7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 3 : +Kd[5] : K9 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 5 : +GND : K13 : gnd : : : : +VCCIO5 : K14 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 2 : +VCCA1 : L5 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 3 : +Kd[6] : L9 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : L10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L12 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 5 : +Sample[0] : M1 : input : 2.5 V : : 2 : N +rst_n : M2 : input : 2.5 V : : 2 : N +VCCIO2 : M3 : power : : 2.5V : 2 : +GND : M4 : gnd : : : : +GNDA1 : M5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 3 : +Kp[2] : M9 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M12 : : : : 5 : +GND : M13 : gnd : : : : +VCCIO5 : M14 : power : : 2.5V : 5 : +GND+ : M15 : : : : 5 : +GND+ : M16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 3 : +VCCD_PLL1 : N4 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 3 : +GND : N7 : gnd : : : : +Vout[2] : N8 : output : 2.5 V : : 3 : N +Kd[3] : N9 : input : 2.5 V : : 4 : N +GND : N10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3 : +VCCIO3 : P4 : power : : 2.5V : 3 : +GND : P5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 3 : +VCCIO3 : P7 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 4 : +VCCIO4 : P10 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 4 : +GND : P12 : gnd : : : : +VCCIO4 : P13 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +GND : R2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3 : +Kd[7] : R9 : input : 2.5 V : : 4 : N +Kd[1] : R10 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 4 : +SetPoint[0] : R12 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : +GND : R15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 5 : +VCCIO3 : T1 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3 : +Kd[0] : T9 : input : 2.5 V : : 4 : N +SetPoint[10] : T10 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 : +VCCIO4 : T16 : power : : 2.5V : 4 : diff --git a/pid/output_files/pid.pow.rpt b/pid/output_files/pid.pow.rpt new file mode 100644 index 0000000..edb979a --- /dev/null +++ b/pid/output_files/pid.pow.rpt @@ -0,0 +1,349 @@ +Power Analyzer report for pid +Tue Dec 04 14:37:05 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Parallel Compilation + 3. Power Analyzer Summary + 4. Power Analyzer Settings + 5. Indeterminate Toggle Rates + 6. Operating Conditions Used + 7. Thermal Power Dissipation by Block + 8. Thermal Power Dissipation by Block Type + 9. Thermal Power Dissipation by Hierarchy + 10. Core Dynamic Thermal Power Dissipation by Clock Domain + 11. Current Drawn from Voltage Supplies Summary + 12. VCCIO Supply Current Drawn by I/O Bank + 13. VCCIO Supply Current Drawn by Voltage + 14. Confidence Metric Details + 15. Signal Activities + 16. Power Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.03 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 1.1% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------+ +; Power Analyzer Summary ; ++----------------------------------------+--------------------------------------------------+ +; Power Analyzer Status ; Successful - Tue Dec 04 14:37:05 2018 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; pid ; +; Top-level Entity Name ; pid ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; +; Power Models ; Final ; +; Total Thermal Power Dissipation ; 77.30 mW ; +; Core Dynamic Thermal Power Dissipation ; 0.00 mW ; +; Core Static Thermal Power Dissipation ; 42.86 mW ; +; I/O Thermal Power Dissipation ; 34.44 mW ; +; Power Estimation Confidence ; Low: user provided insufficient toggle rate data ; ++----------------------------------------+--------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Power Analyzer Settings ; ++------------------------------------------------------------------+---------------------------------------+---------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+---------------------------------------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Preset Cooling Solution ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; ; +; Board thermal model ; None (CONSERVATIVE) ; ; +; Default Power Toggle Rate ; 12.5% ; 12.5% ; +; Default Power Input I/O Toggle Rate ; 12.5% ; 12.5% ; +; Use vectorless estimation ; On ; On ; +; Use Input Files ; Off ; Off ; +; Filter Glitches in VCD File Reader ; On ; On ; +; Power Analyzer Report Signal Activity ; Off ; Off ; +; Power Analyzer Report Power Dissipation ; Off ; Off ; +; Device Power Characteristics ; TYPICAL ; TYPICAL ; +; Automatically Compute Junction Temperature ; On ; On ; +; Specified Junction Temperature ; 25 ; 25 ; +; Ambient Temperature ; 25 ; 25 ; +; Use Custom Cooling Solution ; Off ; Off ; +; Board Temperature ; 25 ; 25 ; ++------------------------------------------------------------------+---------------------------------------+---------------+ + + ++--------------------------------------------+ +; Indeterminate Toggle Rates ; ++--------------+-----------------------------+ +; Node ; Reason ; ++--------------+-----------------------------+ +; clk ; No valid clock domain found ; +; rst_n ; No valid clock domain found ; +; SetPoint[13] ; No valid clock domain found ; +; Sample[13] ; No valid clock domain found ; +; Sample[12] ; No valid clock domain found ; +; SetPoint[12] ; No valid clock domain found ; +; Sample[11] ; No valid clock domain found ; +; SetPoint[11] ; No valid clock domain found ; +; Sample[10] ; No valid clock domain found ; +; SetPoint[10] ; No valid clock domain found ; +; Sample[9] ; No valid clock domain found ; +; SetPoint[9] ; No valid clock domain found ; +; Sample[8] ; No valid clock domain found ; +; SetPoint[8] ; No valid clock domain found ; +; Sample[7] ; No valid clock domain found ; +; SetPoint[7] ; No valid clock domain found ; +; Sample[6] ; No valid clock domain found ; +; SetPoint[6] ; No valid clock domain found ; +; Sample[5] ; No valid clock domain found ; +; SetPoint[5] ; No valid clock domain found ; +; Sample[4] ; No valid clock domain found ; +; SetPoint[4] ; No valid clock domain found ; +; Sample[3] ; No valid clock domain found ; +; SetPoint[3] ; No valid clock domain found ; +; Sample[2] ; No valid clock domain found ; +; SetPoint[2] ; No valid clock domain found ; +; Sample[1] ; No valid clock domain found ; +; SetPoint[1] ; No valid clock domain found ; +; Sample[0] ; No valid clock domain found ; +; SetPoint[0] ; No valid clock domain found ; +; Kd[0] ; No valid clock domain found ; +; Kd[1] ; No valid clock domain found ; +; Kd[2] ; No valid clock domain found ; +; Kd[3] ; No valid clock domain found ; +; Kd[4] ; No valid clock domain found ; +; Kd[5] ; No valid clock domain found ; +; Kd[6] ; No valid clock domain found ; +; Kd[7] ; No valid clock domain found ; +; Ki[0] ; No valid clock domain found ; +; Ki[1] ; No valid clock domain found ; +; Ki[2] ; No valid clock domain found ; +; Ki[3] ; No valid clock domain found ; +; Ki[4] ; No valid clock domain found ; +; Ki[5] ; No valid clock domain found ; +; Ki[6] ; No valid clock domain found ; +; Ki[7] ; No valid clock domain found ; +; Kp[0] ; No valid clock domain found ; +; Kp[1] ; No valid clock domain found ; +; Kp[2] ; No valid clock domain found ; +; Kp[3] ; No valid clock domain found ; +; Kp[4] ; No valid clock domain found ; +; Kp[5] ; No valid clock domain found ; +; Kp[6] ; No valid clock domain found ; +; Kp[7] ; No valid clock domain found ; ++--------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Operating Conditions Used ; ++---------------------------------------------+---------------------------+ +; Setting ; Value ; ++---------------------------------------------+---------------------------+ +; Device power characteristics ; Typical ; +; ; ; +; Voltages ; ; +; VCCINT ; 1.20 V ; +; VCCA ; 2.50 V ; +; VCCD ; 1.20 V ; +; 2.5 V I/O Standard ; 2.5 V ; +; ; ; +; Auto computed junction temperature ; 26.1 degrees Celsius ; +; Ambient temperature ; 25.0 degrees Celsius ; +; Junction-to-Case thermal resistance ; 9.80 degrees Celsius/Watt ; +; Case-to-Heat Sink thermal resistance ; 0.10 degrees Celsius/Watt ; +; Heat Sink-to-Ambient thermal resistance ; 4.30 degrees Celsius/Watt ; +; ; ; +; Board model used ; None ; ++---------------------------------------------+---------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Thermal Power Dissipation by Block ; ++------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+ +; Block Name ; Block Type ; Total Thermal Power ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; ++------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+ +(1) The "Thermal Power Dissipation by Block" Table has been hidden. To show this table, please select the "Write power dissipation by block to report file" option under "PowerPlay Power Analyzer Settings". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Thermal Power Dissipation by Block Type ; ++----------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ +; Block Type ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ; ++----------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ +; Embedded multiplier block ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; +; Embedded multiplier output ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; +; Combinational cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; +; Clock control block ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; +; Register cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; +; I/O ; 19.44 mW ; 0.00 mW ; 19.44 mW ; 0.00 mW ; 0.000 ; ++----------------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ +(1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing. + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Thermal Power Dissipation by Hierarchy ; ++-------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+---------------------------------------------+ +; Compilation Hierarchy Node ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name ; ++-------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+---------------------------------------------+ +; |pid ; 19.44 mW (19.44 mW) ; 0.00 mW (0.00 mW) ; 19.44 mW (19.44 mW) ; 0.00 mW (0.00 mW) ; |pid ; +; |lpm_mult:Mult0 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |pid|lpm_mult:Mult0 ; +; |mult_kbt:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |pid|lpm_mult:Mult0|mult_kbt:auto_generated ; +; |lpm_mult:Mult1 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |pid|lpm_mult:Mult1 ; +; |mult_gbt:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |pid|lpm_mult:Mult1|mult_gbt:auto_generated ; +; |lpm_mult:Mult2 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |pid|lpm_mult:Mult2 ; +; |mult_gbt:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |pid|lpm_mult:Mult2|mult_gbt:auto_generated ; +; |hard_block:auto_generated_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |pid|hard_block:auto_generated_inst ; ++-------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+---------------------------------------------+ +(1) Value in parentheses is the power consumed at that level of hierarchy. Value not in parentheses is the power consumed at that level of hierarchy plus the power consumed by all levels of hierarchy below it. + +(2) The "Block Thermal Static Power" for all levels of hierarchy except the top-level hierarchy is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing. + + ++--------------------------------------------------------------------+ +; Core Dynamic Thermal Power Dissipation by Clock Domain ; ++-----------------+-----------------------+--------------------------+ +; Clock Domain ; Clock Frequency (MHz) ; Total Core Dynamic Power ; ++-----------------+-----------------------+--------------------------+ +; No clock domain ; 0.00 ; 0.00 ; ++-----------------+-----------------------+--------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Current Drawn from Voltage Supplies Summary ; ++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ; ++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; VCCINT ; 18.04 mA ; 0.00 mA ; 18.04 mA ; 18.04 mA ; +; VCCIO ; 6.28 mA ; 0.00 mA ; 6.28 mA ; 6.28 mA ; +; VCCA ; 15.50 mA ; 0.00 mA ; 15.50 mA ; 15.50 mA ; +; VCCD ; 1.00 mA ; 0.00 mA ; 1.00 mA ; 1.00 mA ; ++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device. +(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device. + + ++-----------------------------------------------------------------------------------------------+ +; VCCIO Supply Current Drawn by I/O Bank ; ++----------+---------------+---------------------+-----------------------+----------------------+ +; I/O Bank ; VCCIO Voltage ; Total Current Drawn ; Dynamic Current Drawn ; Static Current Drawn ; ++----------+---------------+---------------------+-----------------------+----------------------+ +; 1 ; 2.5V ; 0.78 mA ; 0.00 mA ; 0.78 mA ; +; 2 ; 2.5V ; 0.76 mA ; 0.00 mA ; 0.76 mA ; +; 3 ; 2.5V ; 0.75 mA ; 0.00 mA ; 0.75 mA ; +; 4 ; 2.5V ; 0.79 mA ; 0.00 mA ; 0.79 mA ; +; 5 ; 2.5V ; 0.76 mA ; 0.00 mA ; 0.76 mA ; +; 6 ; 2.5V ; 0.79 mA ; 0.00 mA ; 0.79 mA ; +; 7 ; 2.5V ; 0.84 mA ; 0.00 mA ; 0.84 mA ; +; 8 ; 2.5V ; 0.81 mA ; 0.00 mA ; 0.81 mA ; ++----------+---------------+---------------------+-----------------------+----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; VCCIO Supply Current Drawn by Voltage ; ++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ; ++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; 2.5V ; 6.28 mA ; 0.00 mA ; 6.28 mA ; 6.28 mA ; ++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device. +(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device. + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Confidence Metric Details ; ++----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+ +; Data Source ; Total ; Pin ; Registered ; Combinational ; ++----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+ +; Simulation (from file) ; ; ; ; ; +; -- Number of signals with Toggle Rate from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; -- Number of signals with Static Probability from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; ; ; ; ; ; +; Node, entity or clock assignment ; ; ; ; ; +; -- Number of signals with Toggle Rate from Node, entity or clock assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; -- Number of signals with Static Probability from Node, entity or clock assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; ; ; ; ; ; +; Vectorless estimation ; ; ; ; ; +; -- Number of signals with Toggle Rate from Vectorless estimation ; 775 (93.3%) ; 17 (23.3%) ; 131 (100.0%) ; 627 (100.0%) ; +; -- Number of signals with Zero toggle rate, from Vectorless estimation ; 105 (12.6%) ; 2 (2.7%) ; 0 (0.0%) ; 103 (16.4%) ; +; -- Number of signals with Static Probability from Vectorless estimation ; 775 (93.3%) ; 17 (23.3%) ; 131 (100.0%) ; 627 (100.0%) ; +; ; ; ; ; ; +; Default assignment ; ; ; ; ; +; -- Number of signals with Toggle Rate from Default assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; -- Number of signals with Static Probability from Default assignment ; 56 (6.7%) ; 56 (76.7%) ; 0 (0.0%) ; 0 (0.0%) ; +; ; ; ; ; ; +; Assumed 0 ; ; ; ; ; +; -- Number of signals with Toggle Rate assumed 0 ; 56 (6.7%) ; 56 (76.7%) ; 0 (0.0%) ; 0 (0.0%) ; ++----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Activities ; ++--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+ +; Signal ; Type ; Toggle Rate (millions of transitions / sec) ; Toggle Rate Data Source ; Static Probability ; Static Probability Data Source ; ++--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+ +(1) The "Signal Activity" Table has been hidden. To show this table, please select the "Write signal activities to report file" option under "PowerPlay Power Analyzer Settings". + + ++-------------------------+ +; Power Analyzer Messages ; ++-------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Power Analyzer + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Tue Dec 04 14:37:02 2018 +Info: Command: quartus_pow --read_settings_files=on --write_settings_files=off pid -c pid +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'pid.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Warning (332060): Node: clk was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register Vout[0]~reg0 is being clocked by clk +Warning (332068): No clocks defined in design. +Info (223000): Starting Vectorless Power Activity Estimation +Warning (222013): Relative toggle rates could not be calculated because no clock domain could be identified for some nodes +Info (223001): Completed Vectorless Power Activity Estimation +Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (215049): Average toggle rate for this design is 0.000 millions of transitions / sec +Info (215031): Total thermal power estimate for the design is 77.30 mW +Info: Quartus Prime Power Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 4819 megabytes + Info: Processing ended: Tue Dec 04 14:37:05 2018 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/pid/output_files/pid.pow.summary b/pid/output_files/pid.pow.summary new file mode 100644 index 0000000..fda3482 --- /dev/null +++ b/pid/output_files/pid.pow.summary @@ -0,0 +1,12 @@ +Power Analyzer Status : Successful - Tue Dec 04 14:37:05 2018 +Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Revision Name : pid +Top-level Entity Name : pid +Family : Cyclone IV E +Device : EP4CE10F17C8 +Power Models : Final +Total Thermal Power Dissipation : 77.30 mW +Core Dynamic Thermal Power Dissipation : 0.00 mW +Core Static Thermal Power Dissipation : 42.86 mW +I/O Thermal Power Dissipation : 34.44 mW +Power Estimation Confidence : Low: user provided insufficient toggle rate data diff --git a/pid/output_files/pid.sld b/pid/output_files/pid.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/pid/output_files/pid.sld @@ -0,0 +1 @@ + diff --git a/pid/output_files/pid.sof b/pid/output_files/pid.sof new file mode 100644 index 0000000..3a3e121 Binary files /dev/null and b/pid/output_files/pid.sof differ diff --git a/pid/output_files/pid.sta.rpt b/pid/output_files/pid.sta.rpt new file mode 100644 index 0000000..e9e8a48 --- /dev/null +++ b/pid/output_files/pid.sta.rpt @@ -0,0 +1,1406 @@ +Timing Analyzer report for pid +Tue Dec 04 14:36:36 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Slow 1200mV 85C Model Setup: 'clk' + 13. Slow 1200mV 85C Model Hold: 'clk' + 14. Slow 1200mV 85C Model Metastability Summary + 15. Slow 1200mV 0C Model Fmax Summary + 16. Slow 1200mV 0C Model Setup Summary + 17. Slow 1200mV 0C Model Hold Summary + 18. Slow 1200mV 0C Model Recovery Summary + 19. Slow 1200mV 0C Model Removal Summary + 20. Slow 1200mV 0C Model Minimum Pulse Width Summary + 21. Slow 1200mV 0C Model Setup: 'clk' + 22. Slow 1200mV 0C Model Hold: 'clk' + 23. Slow 1200mV 0C Model Metastability Summary + 24. Fast 1200mV 0C Model Setup Summary + 25. Fast 1200mV 0C Model Hold Summary + 26. Fast 1200mV 0C Model Recovery Summary + 27. Fast 1200mV 0C Model Removal Summary + 28. Fast 1200mV 0C Model Minimum Pulse Width Summary + 29. Fast 1200mV 0C Model Setup: 'clk' + 30. Fast 1200mV 0C Model Hold: 'clk' + 31. Fast 1200mV 0C Model Metastability Summary + 32. Multicorner Timing Analysis Summary + 33. Board Trace Model Assignments + 34. Input Transition Times + 35. Signal Integrity Metrics (Slow 1200mv 0c Model) + 36. Signal Integrity Metrics (Slow 1200mv 85c Model) + 37. Signal Integrity Metrics (Fast 1200mv 0c Model) + 38. Setup Transfers + 39. Hold Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths Summary + 43. Clock Status Summary + 44. Unconstrained Input Ports + 45. Unconstrained Output Ports + 46. Unconstrained Input Ports + 47. Unconstrained Output Ports + 48. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+---------------------------------------------------------+ +; Quartus Prime Version ; Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; pid ; +; Device Family ; Cyclone IV E ; +; Device Name ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+---------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.11 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 5.3% ; +; Processors 3-4 ; 2.7% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ + + ++--------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 154.13 MHz ; 154.13 MHz ; clk ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++-------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++-------+--------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+--------------------+ +; clk ; -5.488 ; -529.506 ; ++-------+--------+--------------------+ + + ++------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++-------+-------+--------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+--------------------+ +; clk ; 0.509 ; 0.000 ; ++-------+-------+--------------------+ + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++-------+--------+----------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+----------------------------------+ +; clk ; -4.000 ; -254.273 ; ++-------+--------+----------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'clk' ; ++--------+-----------+---------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+---------------+--------------+-------------+--------------+------------+------------+ +; -5.488 ; EE1[4] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.845 ; +; -5.464 ; EE1[10] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.821 ; +; -5.461 ; EE1[7] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.818 ; +; -5.458 ; EE1[4] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.815 ; +; -5.454 ; EE1[4] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.811 ; +; -5.447 ; EE1[2] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.804 ; +; -5.445 ; EE1[4] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.356 ; 6.802 ; +; -5.434 ; EE1[10] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.791 ; +; -5.431 ; EE1[7] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.788 ; +; -5.430 ; EE1[10] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.787 ; +; -5.428 ; EE1[4] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.356 ; 6.785 ; +; -5.427 ; EE1[7] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.784 ; +; -5.421 ; EE1[10] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.356 ; 6.778 ; +; -5.418 ; EE1[7] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.356 ; 6.775 ; +; -5.417 ; EE1[2] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.774 ; +; -5.413 ; EE1[2] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.770 ; +; -5.404 ; EE1[2] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.356 ; 6.761 ; +; -5.404 ; EE1[10] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.356 ; 6.761 ; +; -5.401 ; EE1[7] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.356 ; 6.758 ; +; -5.395 ; EE1[4] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.356 ; 6.752 ; +; -5.395 ; EE1[4] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.356 ; 6.752 ; +; -5.387 ; EE1[2] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.356 ; 6.744 ; +; -5.384 ; EE1[4] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.356 ; 6.741 ; +; -5.380 ; EE1[4] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.356 ; 6.737 ; +; -5.377 ; EE1[4] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.348 ; 6.726 ; +; -5.371 ; EE1[10] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.356 ; 6.728 ; +; -5.371 ; EE1[10] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.356 ; 6.728 ; +; -5.368 ; EE1[7] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.356 ; 6.725 ; +; -5.368 ; EE1[7] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.356 ; 6.725 ; +; -5.365 ; EE2[8] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.353 ; 6.719 ; +; -5.362 ; EE2[4] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.353 ; 6.716 ; +; -5.360 ; EE1[10] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.356 ; 6.717 ; +; -5.359 ; EE2[10] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.353 ; 6.713 ; +; -5.357 ; EE1[7] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.356 ; 6.714 ; +; -5.356 ; EE1[4] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.356 ; 6.713 ; +; -5.356 ; EE1[10] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.356 ; 6.713 ; +; -5.355 ; EE2[8] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.359 ; 6.715 ; +; -5.354 ; EE1[2] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.356 ; 6.711 ; +; -5.354 ; EE1[2] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.356 ; 6.711 ; +; -5.354 ; EE2[7] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.353 ; 6.708 ; +; -5.353 ; EE1[7] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.356 ; 6.710 ; +; -5.353 ; EE1[10] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.348 ; 6.702 ; +; -5.352 ; EE2[4] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.359 ; 6.712 ; +; -5.350 ; EE1[7] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.348 ; 6.699 ; +; -5.349 ; EE2[10] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.359 ; 6.709 ; +; -5.344 ; EE2[7] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.359 ; 6.704 ; +; -5.343 ; EE1[2] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.356 ; 6.700 ; +; -5.339 ; EE1[2] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.356 ; 6.696 ; +; -5.336 ; EE1[2] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.348 ; 6.685 ; +; -5.332 ; EE1[10] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.356 ; 6.689 ; +; -5.329 ; EE1[7] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.356 ; 6.686 ; +; -5.315 ; EE1[2] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.356 ; 6.672 ; +; -5.314 ; EE2[8] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.353 ; 6.668 ; +; -5.311 ; EE2[4] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.353 ; 6.665 ; +; -5.309 ; EE2[8] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.353 ; 6.663 ; +; -5.308 ; EE2[10] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.353 ; 6.662 ; +; -5.306 ; EE2[4] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.353 ; 6.660 ; +; -5.303 ; EE2[7] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.353 ; 6.657 ; +; -5.303 ; EE2[10] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.353 ; 6.657 ; +; -5.298 ; EE2[7] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.353 ; 6.652 ; +; -5.286 ; EE2[8] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.353 ; 6.640 ; +; -5.283 ; EE2[4] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.353 ; 6.637 ; +; -5.280 ; EE2[10] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.353 ; 6.634 ; +; -5.275 ; EE2[7] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.353 ; 6.629 ; +; -5.238 ; EE1[3] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.595 ; +; -5.230 ; EE1[1] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.587 ; +; -5.226 ; EE1[11] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.583 ; +; -5.225 ; EE1[5] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.582 ; +; -5.224 ; EE1[8] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.581 ; +; -5.214 ; EE1[0] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.571 ; +; -5.209 ; EE1[9] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.566 ; +; -5.208 ; EE1[3] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.565 ; +; -5.204 ; EE1[6] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.356 ; 6.561 ; +; -5.204 ; EE1[3] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.561 ; +; -5.203 ; Ki_Out[0] ; Vout[13]~reg0 ; clk ; clk ; 1.000 ; -0.038 ; 6.166 ; +; -5.200 ; EE1[1] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.557 ; +; -5.196 ; EE1[11] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.553 ; +; -5.196 ; EE1[1] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.553 ; +; -5.195 ; EE1[5] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.552 ; +; -5.195 ; EE1[3] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.356 ; 6.552 ; +; -5.194 ; EE1[8] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.551 ; +; -5.192 ; EE1[11] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.549 ; +; -5.191 ; EE1[5] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.548 ; +; -5.190 ; EE1[8] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.547 ; +; -5.187 ; EE1[1] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.356 ; 6.544 ; +; -5.184 ; EE1[0] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.541 ; +; -5.183 ; EE1[11] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.356 ; 6.540 ; +; -5.182 ; EE1[5] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.356 ; 6.539 ; +; -5.181 ; EE1[8] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.356 ; 6.538 ; +; -5.180 ; EE1[0] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.537 ; +; -5.179 ; EE1[9] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.536 ; +; -5.178 ; EE1[3] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.356 ; 6.535 ; +; -5.175 ; EE1[9] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.532 ; +; -5.174 ; EE1[6] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.356 ; 6.531 ; +; -5.171 ; EE1[0] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.356 ; 6.528 ; +; -5.170 ; EE1[6] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.356 ; 6.527 ; +; -5.170 ; EE1[1] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.356 ; 6.527 ; +; -5.166 ; EE1[9] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.356 ; 6.523 ; +; -5.166 ; EE1[11] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.356 ; 6.523 ; +; -5.165 ; EE1[5] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.356 ; 6.522 ; ++--------+-----------+---------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'clk' ; ++-------+----------------------+------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+----------------------+------------+--------------+-------------+--------------+------------+------------+ +; 0.509 ; Kd_Out[20] ; Kd_Out[20] ; clk ; clk ; 0.000 ; 0.081 ; 0.802 ; +; 0.509 ; Ki_Out[20] ; Ki_Out[20] ; clk ; clk ; 0.000 ; 0.081 ; 0.802 ; +; 0.509 ; Kp_Out[20] ; Kp_Out[20] ; clk ; clk ; 0.000 ; 0.081 ; 0.802 ; +; 0.509 ; period[10] ; period[10] ; clk ; clk ; 0.000 ; 0.081 ; 0.802 ; +; 0.517 ; EE1[13] ; EE1[13] ; clk ; clk ; 0.000 ; 0.081 ; 0.810 ; +; 0.739 ; EE2[12] ; EE2[12] ; clk ; clk ; 0.000 ; 0.080 ; 1.031 ; +; 0.743 ; Kd_Out[16] ; Kd_Out[16] ; clk ; clk ; 0.000 ; 0.099 ; 1.054 ; +; 0.743 ; Kd_Out[10] ; Kd_Out[10] ; clk ; clk ; 0.000 ; 0.099 ; 1.054 ; +; 0.743 ; Kd_Out[8] ; Kd_Out[8] ; clk ; clk ; 0.000 ; 0.099 ; 1.054 ; +; 0.743 ; Kd_Out[0] ; Kd_Out[0] ; clk ; clk ; 0.000 ; 0.099 ; 1.054 ; +; 0.743 ; Ki_Out[0] ; Ki_Out[0] ; clk ; clk ; 0.000 ; 0.099 ; 1.054 ; +; 0.744 ; Ki_Out[16] ; Ki_Out[16] ; clk ; clk ; 0.000 ; 0.099 ; 1.055 ; +; 0.744 ; Kd_Out[12] ; Kd_Out[12] ; clk ; clk ; 0.000 ; 0.099 ; 1.055 ; +; 0.744 ; Ki_Out[10] ; Ki_Out[10] ; clk ; clk ; 0.000 ; 0.099 ; 1.055 ; +; 0.744 ; Ki_Out[9] ; Ki_Out[9] ; clk ; clk ; 0.000 ; 0.099 ; 1.055 ; +; 0.744 ; Kd_Out[9] ; Kd_Out[9] ; clk ; clk ; 0.000 ; 0.099 ; 1.055 ; +; 0.744 ; Ki_Out[8] ; Ki_Out[8] ; clk ; clk ; 0.000 ; 0.099 ; 1.055 ; +; 0.744 ; Kd_Out[7] ; Kd_Out[7] ; clk ; clk ; 0.000 ; 0.099 ; 1.055 ; +; 0.744 ; Kd_Out[6] ; Kd_Out[6] ; clk ; clk ; 0.000 ; 0.099 ; 1.055 ; +; 0.744 ; Kd_Out[4] ; Kd_Out[4] ; clk ; clk ; 0.000 ; 0.099 ; 1.055 ; +; 0.745 ; Ki_Out[14] ; Ki_Out[14] ; clk ; clk ; 0.000 ; 0.099 ; 1.056 ; +; 0.745 ; Kd_Out[13] ; Kd_Out[13] ; clk ; clk ; 0.000 ; 0.099 ; 1.056 ; +; 0.745 ; Ki_Out[12] ; Ki_Out[12] ; clk ; clk ; 0.000 ; 0.099 ; 1.056 ; +; 0.745 ; Kd_Out[5] ; Kd_Out[5] ; clk ; clk ; 0.000 ; 0.099 ; 1.056 ; +; 0.745 ; Kd_Out[2] ; Kd_Out[2] ; clk ; clk ; 0.000 ; 0.099 ; 1.056 ; +; 0.745 ; Ki_Out[7] ; Ki_Out[7] ; clk ; clk ; 0.000 ; 0.099 ; 1.056 ; +; 0.745 ; Ki_Out[6] ; Ki_Out[6] ; clk ; clk ; 0.000 ; 0.099 ; 1.056 ; +; 0.745 ; Ki_Out[5] ; Ki_Out[5] ; clk ; clk ; 0.000 ; 0.099 ; 1.056 ; +; 0.745 ; Ki_Out[4] ; Ki_Out[4] ; clk ; clk ; 0.000 ; 0.099 ; 1.056 ; +; 0.745 ; Ki_Out[2] ; Ki_Out[2] ; clk ; clk ; 0.000 ; 0.099 ; 1.056 ; +; 0.746 ; Ki_Out[18] ; Ki_Out[18] ; clk ; clk ; 0.000 ; 0.099 ; 1.057 ; +; 0.746 ; Ki_Out[15] ; Ki_Out[15] ; clk ; clk ; 0.000 ; 0.099 ; 1.057 ; +; 0.746 ; Ki_Out[13] ; Ki_Out[13] ; clk ; clk ; 0.000 ; 0.099 ; 1.057 ; +; 0.746 ; Ki_Out[11] ; Ki_Out[11] ; clk ; clk ; 0.000 ; 0.099 ; 1.057 ; +; 0.746 ; Kd_Out[3] ; Kd_Out[3] ; clk ; clk ; 0.000 ; 0.099 ; 1.057 ; +; 0.746 ; Kd_Out[1] ; Kd_Out[1] ; clk ; clk ; 0.000 ; 0.099 ; 1.057 ; +; 0.746 ; period[9] ; period[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.039 ; +; 0.746 ; period[5] ; period[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.039 ; +; 0.747 ; Ki_Out[3] ; Ki_Out[3] ; clk ; clk ; 0.000 ; 0.099 ; 1.058 ; +; 0.747 ; Ki_Out[1] ; Ki_Out[1] ; clk ; clk ; 0.000 ; 0.099 ; 1.058 ; +; 0.747 ; period[4] ; period[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.040 ; +; 0.748 ; Ki_Out[19] ; Ki_Out[19] ; clk ; clk ; 0.000 ; 0.099 ; 1.059 ; +; 0.748 ; Ki_Out[17] ; Ki_Out[17] ; clk ; clk ; 0.000 ; 0.099 ; 1.059 ; +; 0.749 ; period[8] ; period[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.042 ; +; 0.761 ; Kp_Out[0] ; Kp_Out[0] ; clk ; clk ; 0.000 ; 0.081 ; 1.054 ; +; 0.761 ; period[1] ; period[1] ; clk ; clk ; 0.000 ; 0.081 ; 1.054 ; +; 0.762 ; Kp_Out[16] ; Kp_Out[16] ; clk ; clk ; 0.000 ; 0.081 ; 1.055 ; +; 0.762 ; Kp_Out[10] ; Kp_Out[10] ; clk ; clk ; 0.000 ; 0.081 ; 1.055 ; +; 0.762 ; Kp_Out[9] ; Kp_Out[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.055 ; +; 0.762 ; Kp_Out[8] ; Kp_Out[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.055 ; +; 0.762 ; EE1[12] ; EE1[12] ; clk ; clk ; 0.000 ; 0.081 ; 1.055 ; +; 0.763 ; Kp_Out[14] ; Kp_Out[14] ; clk ; clk ; 0.000 ; 0.081 ; 1.056 ; +; 0.763 ; Kp_Out[12] ; Kp_Out[12] ; clk ; clk ; 0.000 ; 0.081 ; 1.056 ; +; 0.763 ; EE2[4] ; EE2[4] ; clk ; clk ; 0.000 ; 0.080 ; 1.055 ; +; 0.763 ; EE2[0] ; EE2[0] ; clk ; clk ; 0.000 ; 0.080 ; 1.055 ; +; 0.763 ; Kp_Out[7] ; Kp_Out[7] ; clk ; clk ; 0.000 ; 0.081 ; 1.056 ; +; 0.763 ; Kp_Out[6] ; Kp_Out[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.056 ; +; 0.763 ; Kp_Out[5] ; Kp_Out[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.056 ; +; 0.763 ; Kp_Out[4] ; Kp_Out[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.056 ; +; 0.763 ; Kp_Out[2] ; Kp_Out[2] ; clk ; clk ; 0.000 ; 0.081 ; 1.056 ; +; 0.764 ; Kp_Out[18] ; Kp_Out[18] ; clk ; clk ; 0.000 ; 0.081 ; 1.057 ; +; 0.764 ; Kp_Out[15] ; Kp_Out[15] ; clk ; clk ; 0.000 ; 0.081 ; 1.057 ; +; 0.764 ; Kp_Out[13] ; Kp_Out[13] ; clk ; clk ; 0.000 ; 0.081 ; 1.057 ; +; 0.764 ; Kp_Out[11] ; Kp_Out[11] ; clk ; clk ; 0.000 ; 0.081 ; 1.057 ; +; 0.764 ; EE2[2] ; EE2[2] ; clk ; clk ; 0.000 ; 0.080 ; 1.056 ; +; 0.764 ; EE2[1] ; EE2[1] ; clk ; clk ; 0.000 ; 0.080 ; 1.056 ; +; 0.764 ; EE1[8] ; EE1[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.057 ; +; 0.765 ; EE2[11] ; EE2[11] ; clk ; clk ; 0.000 ; 0.080 ; 1.057 ; +; 0.765 ; EE2[10] ; EE2[10] ; clk ; clk ; 0.000 ; 0.080 ; 1.057 ; +; 0.765 ; EE2[9] ; EE2[9] ; clk ; clk ; 0.000 ; 0.080 ; 1.057 ; +; 0.765 ; EE2[8] ; EE2[8] ; clk ; clk ; 0.000 ; 0.080 ; 1.057 ; +; 0.765 ; EE2[6] ; EE2[6] ; clk ; clk ; 0.000 ; 0.080 ; 1.057 ; +; 0.765 ; EE2[3] ; EE2[3] ; clk ; clk ; 0.000 ; 0.080 ; 1.057 ; +; 0.765 ; Kp_Out[3] ; Kp_Out[3] ; clk ; clk ; 0.000 ; 0.081 ; 1.058 ; +; 0.765 ; Kp_Out[1] ; Kp_Out[1] ; clk ; clk ; 0.000 ; 0.081 ; 1.058 ; +; 0.765 ; period[2] ; period[2] ; clk ; clk ; 0.000 ; 0.081 ; 1.058 ; +; 0.766 ; Kp_Out[19] ; Kp_Out[19] ; clk ; clk ; 0.000 ; 0.081 ; 1.059 ; +; 0.766 ; Kp_Out[17] ; Kp_Out[17] ; clk ; clk ; 0.000 ; 0.081 ; 1.059 ; +; 0.767 ; EE2[7] ; EE2[7] ; clk ; clk ; 0.000 ; 0.080 ; 1.059 ; +; 0.767 ; EE2[5] ; EE2[5] ; clk ; clk ; 0.000 ; 0.080 ; 1.059 ; +; 0.775 ; EE2[13] ; EE2[13] ; clk ; clk ; 0.000 ; 0.080 ; 1.067 ; +; 0.785 ; EE1[4] ; EE1[4] ; clk ; clk ; 0.000 ; 0.081 ; 1.078 ; +; 0.785 ; EE1[2] ; EE1[2] ; clk ; clk ; 0.000 ; 0.081 ; 1.078 ; +; 0.785 ; EE1[0] ; EE1[0] ; clk ; clk ; 0.000 ; 0.081 ; 1.078 ; +; 0.786 ; EE1[10] ; EE1[10] ; clk ; clk ; 0.000 ; 0.081 ; 1.079 ; +; 0.787 ; EE1[6] ; EE1[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.080 ; +; 0.788 ; EE1[5] ; EE1[5] ; clk ; clk ; 0.000 ; 0.081 ; 1.081 ; +; 0.788 ; EE1[1] ; EE1[1] ; clk ; clk ; 0.000 ; 0.081 ; 1.081 ; +; 0.789 ; EE1[11] ; EE1[11] ; clk ; clk ; 0.000 ; 0.081 ; 1.082 ; +; 0.789 ; EE1[3] ; EE1[3] ; clk ; clk ; 0.000 ; 0.081 ; 1.082 ; +; 0.790 ; EE1[9] ; EE1[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.083 ; +; 0.790 ; EE1[7] ; EE1[7] ; clk ; clk ; 0.000 ; 0.081 ; 1.083 ; +; 0.951 ; period[4] ; period[6] ; clk ; clk ; 0.000 ; 0.081 ; 1.244 ; +; 0.951 ; period[4] ; period[7] ; clk ; clk ; 0.000 ; 0.081 ; 1.244 ; +; 0.991 ; EE0[13]~_Duplicate_1 ; EE1[13] ; clk ; clk ; 0.000 ; 0.080 ; 1.283 ; +; 1.012 ; EE1[13] ; EE1[12] ; clk ; clk ; 0.000 ; 0.081 ; 1.305 ; +; 1.012 ; EE1[13] ; EE1[11] ; clk ; clk ; 0.000 ; 0.081 ; 1.305 ; +; 1.012 ; EE1[13] ; EE1[10] ; clk ; clk ; 0.000 ; 0.081 ; 1.305 ; +; 1.012 ; EE1[13] ; EE1[9] ; clk ; clk ; 0.000 ; 0.081 ; 1.305 ; +; 1.012 ; EE1[13] ; EE1[8] ; clk ; clk ; 0.000 ; 0.081 ; 1.305 ; ++-------+----------------------+------------+--------------+-------------+--------------+------------+------------+ + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 166.69 MHz ; 166.69 MHz ; clk ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++-------+--------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-------------------+ +; clk ; -4.999 ; -474.425 ; ++-------+--------+-------------------+ + + ++-----------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++-------+-------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+-------------------+ +; clk ; 0.470 ; 0.000 ; ++-------+-------+-------------------+ + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++-------+--------+---------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------------------------+ +; clk ; -4.000 ; -253.825 ; ++-------+--------+---------------------------------+ + + ++-------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'clk' ; ++--------+-----------+------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+------------+--------------+-------------+--------------+------------+------------+ +; -4.999 ; EE1[4] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.342 ; +; -4.973 ; EE1[10] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.316 ; +; -4.972 ; EE1[4] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.315 ; +; -4.971 ; EE1[7] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.314 ; +; -4.964 ; EE1[4] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.307 ; +; -4.958 ; EE1[2] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.301 ; +; -4.956 ; EE1[4] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.299 ; +; -4.946 ; EE1[10] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.289 ; +; -4.944 ; EE1[7] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.287 ; +; -4.943 ; EE1[4] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.341 ; 6.286 ; +; -4.938 ; EE1[10] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.281 ; +; -4.936 ; EE1[7] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.279 ; +; -4.931 ; EE1[2] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.274 ; +; -4.930 ; EE1[10] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.273 ; +; -4.928 ; EE1[7] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.271 ; +; -4.923 ; EE1[2] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.266 ; +; -4.917 ; EE1[10] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.341 ; 6.260 ; +; -4.915 ; EE1[2] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.258 ; +; -4.915 ; EE1[7] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.341 ; 6.258 ; +; -4.914 ; EE1[4] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.341 ; 6.257 ; +; -4.912 ; EE1[4] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.341 ; 6.255 ; +; -4.902 ; EE1[4] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.330 ; 6.234 ; +; -4.902 ; EE1[2] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.341 ; 6.245 ; +; -4.894 ; EE2[4] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.333 ; 6.229 ; +; -4.894 ; EE2[8] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.333 ; 6.229 ; +; -4.893 ; EE1[4] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.341 ; 6.236 ; +; -4.891 ; EE1[4] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.341 ; 6.234 ; +; -4.888 ; EE1[10] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.341 ; 6.231 ; +; -4.888 ; EE2[10] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.333 ; 6.223 ; +; -4.886 ; EE1[7] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.341 ; 6.229 ; +; -4.886 ; EE1[10] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.341 ; 6.229 ; +; -4.886 ; EE2[7] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.333 ; 6.221 ; +; -4.884 ; EE1[7] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.341 ; 6.227 ; +; -4.876 ; EE1[10] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.330 ; 6.208 ; +; -4.874 ; EE1[7] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.330 ; 6.206 ; +; -4.873 ; EE1[2] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.341 ; 6.216 ; +; -4.871 ; EE1[2] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.341 ; 6.214 ; +; -4.870 ; EE2[4] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.339 ; 6.211 ; +; -4.870 ; EE2[8] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.339 ; 6.211 ; +; -4.867 ; EE1[10] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.341 ; 6.210 ; +; -4.866 ; EE1[4] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.341 ; 6.209 ; +; -4.865 ; EE1[7] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.341 ; 6.208 ; +; -4.865 ; EE1[10] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.341 ; 6.208 ; +; -4.864 ; EE2[10] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.339 ; 6.205 ; +; -4.863 ; EE1[7] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.341 ; 6.206 ; +; -4.862 ; EE2[7] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.339 ; 6.203 ; +; -4.861 ; EE1[2] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.330 ; 6.193 ; +; -4.852 ; EE1[2] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.341 ; 6.195 ; +; -4.850 ; EE1[2] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.341 ; 6.193 ; +; -4.844 ; EE2[4] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.333 ; 6.179 ; +; -4.844 ; EE2[8] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.333 ; 6.179 ; +; -4.840 ; EE1[10] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.341 ; 6.183 ; +; -4.838 ; EE1[7] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.341 ; 6.181 ; +; -4.838 ; EE2[10] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.333 ; 6.173 ; +; -4.836 ; EE2[7] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.333 ; 6.171 ; +; -4.835 ; EE2[4] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.333 ; 6.170 ; +; -4.835 ; EE2[8] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.333 ; 6.170 ; +; -4.829 ; EE2[10] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.333 ; 6.164 ; +; -4.827 ; EE2[7] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.333 ; 6.162 ; +; -4.825 ; EE1[2] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.341 ; 6.168 ; +; -4.808 ; EE2[4] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.333 ; 6.143 ; +; -4.808 ; EE2[8] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.333 ; 6.143 ; +; -4.802 ; EE2[10] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.333 ; 6.137 ; +; -4.800 ; EE2[7] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.333 ; 6.135 ; +; -4.735 ; EE1[3] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.078 ; +; -4.729 ; EE1[1] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.072 ; +; -4.726 ; EE1[5] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.069 ; +; -4.724 ; EE1[11] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.067 ; +; -4.710 ; EE1[8] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.053 ; +; -4.708 ; EE1[3] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.051 ; +; -4.707 ; EE1[0] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.050 ; +; -4.702 ; EE1[6] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.045 ; +; -4.702 ; EE1[9] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.341 ; 6.045 ; +; -4.702 ; EE1[1] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.045 ; +; -4.700 ; EE1[3] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.043 ; +; -4.699 ; EE1[5] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.042 ; +; -4.697 ; EE1[11] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.040 ; +; -4.694 ; EE1[1] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.037 ; +; -4.692 ; EE1[3] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.035 ; +; -4.691 ; EE1[5] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.034 ; +; -4.689 ; EE1[11] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.032 ; +; -4.686 ; EE1[1] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.029 ; +; -4.683 ; EE1[8] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.026 ; +; -4.683 ; EE1[5] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.026 ; +; -4.681 ; EE1[11] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.024 ; +; -4.680 ; EE1[0] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.023 ; +; -4.679 ; EE1[3] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.341 ; 6.022 ; +; -4.675 ; EE1[6] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.018 ; +; -4.675 ; EE1[9] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.341 ; 6.018 ; +; -4.675 ; EE1[8] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.018 ; +; -4.673 ; EE1[1] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.341 ; 6.016 ; +; -4.672 ; EE1[0] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.015 ; +; -4.670 ; EE1[5] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.341 ; 6.013 ; +; -4.668 ; EE1[11] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.341 ; 6.011 ; +; -4.667 ; EE1[6] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.010 ; +; -4.667 ; EE1[9] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.341 ; 6.010 ; +; -4.667 ; EE1[8] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.010 ; +; -4.664 ; EE1[0] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.007 ; +; -4.659 ; EE1[6] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.002 ; +; -4.659 ; EE1[9] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.341 ; 6.002 ; ++--------+-----------+------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'clk' ; ++-------+----------------------+------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+----------------------+------------+--------------+-------------+--------------+------------+------------+ +; 0.470 ; Kd_Out[20] ; Kd_Out[20] ; clk ; clk ; 0.000 ; 0.072 ; 0.737 ; +; 0.470 ; Ki_Out[20] ; Ki_Out[20] ; clk ; clk ; 0.000 ; 0.072 ; 0.737 ; +; 0.470 ; Kp_Out[20] ; Kp_Out[20] ; clk ; clk ; 0.000 ; 0.072 ; 0.737 ; +; 0.470 ; period[10] ; period[10] ; clk ; clk ; 0.000 ; 0.072 ; 0.737 ; +; 0.476 ; EE1[13] ; EE1[13] ; clk ; clk ; 0.000 ; 0.073 ; 0.744 ; +; 0.688 ; Kd_Out[16] ; Kd_Out[16] ; clk ; clk ; 0.000 ; 0.090 ; 0.973 ; +; 0.688 ; Kd_Out[0] ; Kd_Out[0] ; clk ; clk ; 0.000 ; 0.089 ; 0.972 ; +; 0.688 ; EE2[12] ; EE2[12] ; clk ; clk ; 0.000 ; 0.072 ; 0.955 ; +; 0.688 ; Ki_Out[0] ; Ki_Out[0] ; clk ; clk ; 0.000 ; 0.090 ; 0.973 ; +; 0.689 ; Kd_Out[13] ; Kd_Out[13] ; clk ; clk ; 0.000 ; 0.090 ; 0.974 ; +; 0.689 ; Kd_Out[12] ; Kd_Out[12] ; clk ; clk ; 0.000 ; 0.090 ; 0.974 ; +; 0.689 ; Kd_Out[10] ; Kd_Out[10] ; clk ; clk ; 0.000 ; 0.090 ; 0.974 ; +; 0.689 ; Ki_Out[9] ; Ki_Out[9] ; clk ; clk ; 0.000 ; 0.090 ; 0.974 ; +; 0.689 ; Kd_Out[9] ; Kd_Out[9] ; clk ; clk ; 0.000 ; 0.089 ; 0.973 ; +; 0.689 ; Ki_Out[7] ; Ki_Out[7] ; clk ; clk ; 0.000 ; 0.090 ; 0.974 ; +; 0.690 ; Ki_Out[16] ; Ki_Out[16] ; clk ; clk ; 0.000 ; 0.089 ; 0.974 ; +; 0.690 ; Kd_Out[8] ; Kd_Out[8] ; clk ; clk ; 0.000 ; 0.089 ; 0.974 ; +; 0.690 ; Ki_Out[8] ; Ki_Out[8] ; clk ; clk ; 0.000 ; 0.090 ; 0.975 ; +; 0.690 ; Kd_Out[7] ; Kd_Out[7] ; clk ; clk ; 0.000 ; 0.089 ; 0.974 ; +; 0.690 ; Kd_Out[5] ; Kd_Out[5] ; clk ; clk ; 0.000 ; 0.089 ; 0.974 ; +; 0.690 ; Ki_Out[6] ; Ki_Out[6] ; clk ; clk ; 0.000 ; 0.090 ; 0.975 ; +; 0.690 ; Ki_Out[5] ; Ki_Out[5] ; clk ; clk ; 0.000 ; 0.090 ; 0.975 ; +; 0.691 ; Ki_Out[13] ; Ki_Out[13] ; clk ; clk ; 0.000 ; 0.089 ; 0.975 ; +; 0.691 ; Ki_Out[12] ; Ki_Out[12] ; clk ; clk ; 0.000 ; 0.089 ; 0.975 ; +; 0.691 ; Ki_Out[10] ; Ki_Out[10] ; clk ; clk ; 0.000 ; 0.089 ; 0.975 ; +; 0.691 ; Kd_Out[6] ; Kd_Out[6] ; clk ; clk ; 0.000 ; 0.089 ; 0.975 ; +; 0.691 ; Kd_Out[4] ; Kd_Out[4] ; clk ; clk ; 0.000 ; 0.089 ; 0.975 ; +; 0.691 ; Kd_Out[2] ; Kd_Out[2] ; clk ; clk ; 0.000 ; 0.089 ; 0.975 ; +; 0.691 ; Ki_Out[4] ; Ki_Out[4] ; clk ; clk ; 0.000 ; 0.090 ; 0.976 ; +; 0.691 ; Ki_Out[2] ; Ki_Out[2] ; clk ; clk ; 0.000 ; 0.090 ; 0.976 ; +; 0.692 ; Ki_Out[15] ; Ki_Out[15] ; clk ; clk ; 0.000 ; 0.089 ; 0.976 ; +; 0.692 ; Ki_Out[14] ; Ki_Out[14] ; clk ; clk ; 0.000 ; 0.089 ; 0.976 ; +; 0.693 ; Ki_Out[18] ; Ki_Out[18] ; clk ; clk ; 0.000 ; 0.089 ; 0.977 ; +; 0.694 ; Ki_Out[11] ; Ki_Out[11] ; clk ; clk ; 0.000 ; 0.089 ; 0.978 ; +; 0.694 ; Kd_Out[3] ; Kd_Out[3] ; clk ; clk ; 0.000 ; 0.089 ; 0.978 ; +; 0.694 ; Kd_Out[1] ; Kd_Out[1] ; clk ; clk ; 0.000 ; 0.089 ; 0.978 ; +; 0.694 ; Ki_Out[3] ; Ki_Out[3] ; clk ; clk ; 0.000 ; 0.090 ; 0.979 ; +; 0.694 ; Ki_Out[1] ; Ki_Out[1] ; clk ; clk ; 0.000 ; 0.090 ; 0.979 ; +; 0.694 ; period[9] ; period[9] ; clk ; clk ; 0.000 ; 0.072 ; 0.961 ; +; 0.694 ; period[4] ; period[4] ; clk ; clk ; 0.000 ; 0.072 ; 0.961 ; +; 0.696 ; Ki_Out[19] ; Ki_Out[19] ; clk ; clk ; 0.000 ; 0.089 ; 0.980 ; +; 0.696 ; Ki_Out[17] ; Ki_Out[17] ; clk ; clk ; 0.000 ; 0.089 ; 0.980 ; +; 0.696 ; period[5] ; period[5] ; clk ; clk ; 0.000 ; 0.072 ; 0.963 ; +; 0.700 ; period[8] ; period[8] ; clk ; clk ; 0.000 ; 0.072 ; 0.967 ; +; 0.705 ; period[1] ; period[1] ; clk ; clk ; 0.000 ; 0.072 ; 0.972 ; +; 0.706 ; EE2[4] ; EE2[4] ; clk ; clk ; 0.000 ; 0.072 ; 0.973 ; +; 0.706 ; Kp_Out[0] ; Kp_Out[0] ; clk ; clk ; 0.000 ; 0.072 ; 0.973 ; +; 0.706 ; EE1[12] ; EE1[12] ; clk ; clk ; 0.000 ; 0.073 ; 0.974 ; +; 0.707 ; Kp_Out[16] ; Kp_Out[16] ; clk ; clk ; 0.000 ; 0.072 ; 0.974 ; +; 0.707 ; Kp_Out[9] ; Kp_Out[9] ; clk ; clk ; 0.000 ; 0.072 ; 0.974 ; +; 0.707 ; Kp_Out[7] ; Kp_Out[7] ; clk ; clk ; 0.000 ; 0.072 ; 0.974 ; +; 0.708 ; Kp_Out[13] ; Kp_Out[13] ; clk ; clk ; 0.000 ; 0.072 ; 0.975 ; +; 0.708 ; Kp_Out[12] ; Kp_Out[12] ; clk ; clk ; 0.000 ; 0.072 ; 0.975 ; +; 0.708 ; Kp_Out[10] ; Kp_Out[10] ; clk ; clk ; 0.000 ; 0.072 ; 0.975 ; +; 0.708 ; Kp_Out[8] ; Kp_Out[8] ; clk ; clk ; 0.000 ; 0.072 ; 0.975 ; +; 0.708 ; EE2[11] ; EE2[11] ; clk ; clk ; 0.000 ; 0.072 ; 0.975 ; +; 0.708 ; EE2[3] ; EE2[3] ; clk ; clk ; 0.000 ; 0.072 ; 0.975 ; +; 0.708 ; EE2[1] ; EE2[1] ; clk ; clk ; 0.000 ; 0.072 ; 0.975 ; +; 0.708 ; EE2[0] ; EE2[0] ; clk ; clk ; 0.000 ; 0.072 ; 0.975 ; +; 0.708 ; Kp_Out[6] ; Kp_Out[6] ; clk ; clk ; 0.000 ; 0.072 ; 0.975 ; +; 0.708 ; Kp_Out[5] ; Kp_Out[5] ; clk ; clk ; 0.000 ; 0.072 ; 0.975 ; +; 0.709 ; Kp_Out[15] ; Kp_Out[15] ; clk ; clk ; 0.000 ; 0.072 ; 0.976 ; +; 0.709 ; Kp_Out[14] ; Kp_Out[14] ; clk ; clk ; 0.000 ; 0.072 ; 0.976 ; +; 0.709 ; EE2[10] ; EE2[10] ; clk ; clk ; 0.000 ; 0.072 ; 0.976 ; +; 0.709 ; EE2[9] ; EE2[9] ; clk ; clk ; 0.000 ; 0.072 ; 0.976 ; +; 0.709 ; EE2[8] ; EE2[8] ; clk ; clk ; 0.000 ; 0.072 ; 0.976 ; +; 0.709 ; EE2[2] ; EE2[2] ; clk ; clk ; 0.000 ; 0.072 ; 0.976 ; +; 0.709 ; Kp_Out[4] ; Kp_Out[4] ; clk ; clk ; 0.000 ; 0.072 ; 0.976 ; +; 0.709 ; Kp_Out[2] ; Kp_Out[2] ; clk ; clk ; 0.000 ; 0.072 ; 0.976 ; +; 0.709 ; EE1[8] ; EE1[8] ; clk ; clk ; 0.000 ; 0.073 ; 0.977 ; +; 0.710 ; Kp_Out[18] ; Kp_Out[18] ; clk ; clk ; 0.000 ; 0.072 ; 0.977 ; +; 0.710 ; EE2[6] ; EE2[6] ; clk ; clk ; 0.000 ; 0.072 ; 0.977 ; +; 0.711 ; Kp_Out[11] ; Kp_Out[11] ; clk ; clk ; 0.000 ; 0.072 ; 0.978 ; +; 0.711 ; period[2] ; period[2] ; clk ; clk ; 0.000 ; 0.072 ; 0.978 ; +; 0.712 ; EE2[7] ; EE2[7] ; clk ; clk ; 0.000 ; 0.072 ; 0.979 ; +; 0.712 ; EE2[5] ; EE2[5] ; clk ; clk ; 0.000 ; 0.072 ; 0.979 ; +; 0.712 ; Kp_Out[3] ; Kp_Out[3] ; clk ; clk ; 0.000 ; 0.072 ; 0.979 ; +; 0.712 ; Kp_Out[1] ; Kp_Out[1] ; clk ; clk ; 0.000 ; 0.072 ; 0.979 ; +; 0.713 ; Kp_Out[19] ; Kp_Out[19] ; clk ; clk ; 0.000 ; 0.072 ; 0.980 ; +; 0.713 ; Kp_Out[17] ; Kp_Out[17] ; clk ; clk ; 0.000 ; 0.072 ; 0.980 ; +; 0.718 ; EE2[13] ; EE2[13] ; clk ; clk ; 0.000 ; 0.072 ; 0.985 ; +; 0.727 ; EE1[4] ; EE1[4] ; clk ; clk ; 0.000 ; 0.073 ; 0.995 ; +; 0.727 ; EE1[2] ; EE1[2] ; clk ; clk ; 0.000 ; 0.073 ; 0.995 ; +; 0.728 ; EE1[10] ; EE1[10] ; clk ; clk ; 0.000 ; 0.073 ; 0.996 ; +; 0.729 ; EE1[5] ; EE1[5] ; clk ; clk ; 0.000 ; 0.073 ; 0.997 ; +; 0.729 ; EE1[0] ; EE1[0] ; clk ; clk ; 0.000 ; 0.073 ; 0.997 ; +; 0.730 ; EE1[6] ; EE1[6] ; clk ; clk ; 0.000 ; 0.073 ; 0.998 ; +; 0.732 ; EE1[1] ; EE1[1] ; clk ; clk ; 0.000 ; 0.073 ; 1.000 ; +; 0.733 ; EE1[11] ; EE1[11] ; clk ; clk ; 0.000 ; 0.073 ; 1.001 ; +; 0.733 ; EE1[3] ; EE1[3] ; clk ; clk ; 0.000 ; 0.073 ; 1.001 ; +; 0.734 ; EE1[9] ; EE1[9] ; clk ; clk ; 0.000 ; 0.073 ; 1.002 ; +; 0.734 ; EE1[7] ; EE1[7] ; clk ; clk ; 0.000 ; 0.073 ; 1.002 ; +; 0.873 ; period[4] ; period[6] ; clk ; clk ; 0.000 ; 0.072 ; 1.140 ; +; 0.873 ; period[4] ; period[7] ; clk ; clk ; 0.000 ; 0.072 ; 1.140 ; +; 0.919 ; EE2[13] ; Kd_Out[16] ; clk ; clk ; 0.000 ; 0.501 ; 1.615 ; +; 0.919 ; EE2[13] ; Kd_Out[13] ; clk ; clk ; 0.000 ; 0.501 ; 1.615 ; +; 0.919 ; EE2[13] ; Kd_Out[12] ; clk ; clk ; 0.000 ; 0.501 ; 1.615 ; +; 0.919 ; EE2[13] ; Kd_Out[10] ; clk ; clk ; 0.000 ; 0.501 ; 1.615 ; +; 0.922 ; EE0[13]~_Duplicate_1 ; EE1[13] ; clk ; clk ; 0.000 ; 0.070 ; 1.187 ; +; 0.936 ; EE1[13] ; EE1[12] ; clk ; clk ; 0.000 ; 0.073 ; 1.204 ; ++-------+----------------------+------------+--------------+-------------+--------------+------------+------------+ + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++-------+--------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-------------------+ +; clk ; -1.852 ; -152.887 ; ++-------+--------+-------------------+ + + ++-----------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++-------+-------+-------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+-------------------+ +; clk ; 0.205 ; 0.000 ; ++-------+-------+-------------------+ + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++-------+--------+---------------------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------------------------+ +; clk ; -3.000 ; -158.600 ; ++-------+--------+---------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'clk' ; ++--------+---------------+---------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+---------------+---------------+--------------+-------------+--------------+------------+------------+ +; -1.852 ; EE1[4] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.982 ; +; -1.840 ; EE1[4] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.970 ; +; -1.835 ; EE1[4] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.965 ; +; -1.831 ; EE1[2] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.961 ; +; -1.830 ; EE1[10] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.960 ; +; -1.828 ; EE1[7] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.958 ; +; -1.827 ; EE1[4] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.143 ; 2.957 ; +; -1.822 ; EE1[4] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.143 ; 2.952 ; +; -1.819 ; EE1[2] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.949 ; +; -1.818 ; EE1[10] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.948 ; +; -1.816 ; EE1[7] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.946 ; +; -1.814 ; EE1[2] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.944 ; +; -1.813 ; EE1[10] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.943 ; +; -1.812 ; EE1[4] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.143 ; 2.942 ; +; -1.811 ; EE1[7] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.941 ; +; -1.807 ; EE1[4] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.143 ; 2.937 ; +; -1.807 ; EE1[4] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.143 ; 2.937 ; +; -1.806 ; EE1[4] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.143 ; 2.936 ; +; -1.806 ; EE1[2] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.143 ; 2.936 ; +; -1.805 ; EE1[10] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.143 ; 2.935 ; +; -1.803 ; EE1[7] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.143 ; 2.933 ; +; -1.801 ; EE1[2] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.143 ; 2.931 ; +; -1.800 ; EE1[10] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.143 ; 2.930 ; +; -1.798 ; EE1[7] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.143 ; 2.928 ; +; -1.797 ; Ki_Out[0] ; Vout[13]~reg0 ; clk ; clk ; 1.000 ; -0.020 ; 2.764 ; +; -1.791 ; EE1[2] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.143 ; 2.921 ; +; -1.790 ; EE2[8] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.140 ; 2.917 ; +; -1.790 ; EE1[10] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.143 ; 2.920 ; +; -1.788 ; EE1[7] ; Ki_Out[4] ; clk ; clk ; 1.000 ; 0.143 ; 2.918 ; +; -1.786 ; EE1[4] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.143 ; 2.916 ; +; -1.786 ; EE1[2] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.143 ; 2.916 ; +; -1.786 ; EE1[2] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.143 ; 2.916 ; +; -1.785 ; EE1[10] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.143 ; 2.915 ; +; -1.785 ; EE1[10] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.143 ; 2.915 ; +; -1.785 ; EE1[2] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.143 ; 2.915 ; +; -1.784 ; EE1[10] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.143 ; 2.914 ; +; -1.783 ; EE1[7] ; Ki_Out[6] ; clk ; clk ; 1.000 ; 0.143 ; 2.913 ; +; -1.783 ; EE1[7] ; Ki_Out[5] ; clk ; clk ; 1.000 ; 0.143 ; 2.913 ; +; -1.783 ; EE2[4] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.140 ; 2.910 ; +; -1.782 ; EE1[7] ; Ki_Out[7] ; clk ; clk ; 1.000 ; 0.143 ; 2.912 ; +; -1.777 ; EE2[10] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.140 ; 2.904 ; +; -1.775 ; EE2[7] ; Kd_Out[10] ; clk ; clk ; 1.000 ; 0.140 ; 2.902 ; +; -1.772 ; EE1[4] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.137 ; 2.896 ; +; -1.770 ; EE2[8] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.137 ; 2.894 ; +; -1.765 ; EE1[2] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.143 ; 2.895 ; +; -1.764 ; EE1[10] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.143 ; 2.894 ; +; -1.763 ; EE2[4] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.137 ; 2.887 ; +; -1.762 ; EE1[7] ; Ki_Out[0] ; clk ; clk ; 1.000 ; 0.143 ; 2.892 ; +; -1.757 ; EE2[10] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.137 ; 2.881 ; +; -1.755 ; EE2[7] ; Kd_Out[17] ; clk ; clk ; 1.000 ; 0.137 ; 2.879 ; +; -1.751 ; EE1[2] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.137 ; 2.875 ; +; -1.750 ; EE1[10] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.137 ; 2.874 ; +; -1.748 ; EE2[8] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.137 ; 2.872 ; +; -1.748 ; EE1[7] ; Ki_Out[10] ; clk ; clk ; 1.000 ; 0.137 ; 2.872 ; +; -1.744 ; EE2[8] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.137 ; 2.868 ; +; -1.741 ; EE2[4] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.137 ; 2.865 ; +; -1.739 ; EE1[3] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.869 ; +; -1.737 ; EE2[4] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.137 ; 2.861 ; +; -1.736 ; EE1[1] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.866 ; +; -1.735 ; EE2[10] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.137 ; 2.859 ; +; -1.734 ; EE1[8] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.864 ; +; -1.733 ; Ki_Out[0] ; Vout[12]~reg0 ; clk ; clk ; 1.000 ; -0.020 ; 2.700 ; +; -1.733 ; EE2[8] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.137 ; 2.857 ; +; -1.733 ; EE1[5] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.863 ; +; -1.733 ; EE1[11] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.863 ; +; -1.733 ; EE2[7] ; Kd_Out[0] ; clk ; clk ; 1.000 ; 0.137 ; 2.857 ; +; -1.731 ; EE2[10] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.137 ; 2.855 ; +; -1.729 ; Ki_Out[0] ; Vout[11]~reg0 ; clk ; clk ; 1.000 ; -0.020 ; 2.696 ; +; -1.729 ; EE2[7] ; Kd_Out[19] ; clk ; clk ; 1.000 ; 0.137 ; 2.853 ; +; -1.728 ; EE1[0] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.858 ; +; -1.727 ; EE1[3] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.857 ; +; -1.726 ; Vout[13]~reg0 ; Vout[13]~reg0 ; clk ; clk ; 1.000 ; -0.045 ; 2.668 ; +; -1.726 ; EE2[4] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.137 ; 2.850 ; +; -1.725 ; EE1[9] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.855 ; +; -1.724 ; EE1[1] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.854 ; +; -1.723 ; EE1[6] ; Ki_Out[9] ; clk ; clk ; 1.000 ; 0.143 ; 2.853 ; +; -1.722 ; EE1[8] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.852 ; +; -1.722 ; EE1[3] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.852 ; +; -1.722 ; Vout[13]~reg0 ; Vout[12]~reg0 ; clk ; clk ; 1.000 ; -0.045 ; 2.664 ; +; -1.721 ; EE1[5] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.851 ; +; -1.721 ; EE1[11] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.851 ; +; -1.720 ; EE2[10] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.137 ; 2.844 ; +; -1.719 ; EE1[1] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.849 ; +; -1.718 ; EE2[7] ; Kd_Out[14] ; clk ; clk ; 1.000 ; 0.137 ; 2.842 ; +; -1.717 ; EE1[8] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.847 ; +; -1.716 ; EE1[0] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.846 ; +; -1.716 ; EE1[5] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.846 ; +; -1.716 ; EE1[11] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.846 ; +; -1.714 ; EE1[3] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.143 ; 2.844 ; +; -1.713 ; EE1[9] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.843 ; +; -1.711 ; EE1[6] ; Ki_Out[8] ; clk ; clk ; 1.000 ; 0.143 ; 2.841 ; +; -1.711 ; EE1[0] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.841 ; +; -1.711 ; EE1[1] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.143 ; 2.841 ; +; -1.711 ; Ki_Out[1] ; Vout[13]~reg0 ; clk ; clk ; 1.000 ; -0.020 ; 2.678 ; +; -1.709 ; EE1[8] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.143 ; 2.839 ; +; -1.709 ; EE1[3] ; Ki_Out[2] ; clk ; clk ; 1.000 ; 0.143 ; 2.839 ; +; -1.708 ; EE1[9] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.838 ; +; -1.708 ; EE1[5] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.143 ; 2.838 ; +; -1.708 ; EE1[11] ; Ki_Out[3] ; clk ; clk ; 1.000 ; 0.143 ; 2.838 ; +; -1.706 ; EE1[6] ; Ki_Out[1] ; clk ; clk ; 1.000 ; 0.143 ; 2.836 ; ++--------+---------------+---------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'clk' ; ++-------+----------------------+------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+----------------------+------------+--------------+-------------+--------------+------------+------------+ +; 0.205 ; Kd_Out[20] ; Kd_Out[20] ; clk ; clk ; 0.000 ; 0.036 ; 0.325 ; +; 0.205 ; Ki_Out[20] ; Ki_Out[20] ; clk ; clk ; 0.000 ; 0.036 ; 0.325 ; +; 0.205 ; Kp_Out[20] ; Kp_Out[20] ; clk ; clk ; 0.000 ; 0.036 ; 0.325 ; +; 0.205 ; period[10] ; period[10] ; clk ; clk ; 0.000 ; 0.036 ; 0.325 ; +; 0.208 ; EE1[13] ; EE1[13] ; clk ; clk ; 0.000 ; 0.036 ; 0.328 ; +; 0.294 ; EE2[12] ; EE2[12] ; clk ; clk ; 0.000 ; 0.036 ; 0.414 ; +; 0.296 ; Kd_Out[9] ; Kd_Out[9] ; clk ; clk ; 0.000 ; 0.044 ; 0.424 ; +; 0.296 ; Kd_Out[0] ; Kd_Out[0] ; clk ; clk ; 0.000 ; 0.044 ; 0.424 ; +; 0.297 ; Ki_Out[16] ; Ki_Out[16] ; clk ; clk ; 0.000 ; 0.044 ; 0.425 ; +; 0.297 ; Ki_Out[10] ; Ki_Out[10] ; clk ; clk ; 0.000 ; 0.044 ; 0.425 ; +; 0.297 ; Kd_Out[10] ; Kd_Out[10] ; clk ; clk ; 0.000 ; 0.043 ; 0.424 ; +; 0.297 ; Kd_Out[8] ; Kd_Out[8] ; clk ; clk ; 0.000 ; 0.044 ; 0.425 ; +; 0.297 ; Kd_Out[7] ; Kd_Out[7] ; clk ; clk ; 0.000 ; 0.044 ; 0.425 ; +; 0.297 ; Kd_Out[5] ; Kd_Out[5] ; clk ; clk ; 0.000 ; 0.044 ; 0.425 ; +; 0.297 ; Kd_Out[2] ; Kd_Out[2] ; clk ; clk ; 0.000 ; 0.044 ; 0.425 ; +; 0.297 ; Ki_Out[0] ; Ki_Out[0] ; clk ; clk ; 0.000 ; 0.043 ; 0.424 ; +; 0.298 ; Ki_Out[18] ; Ki_Out[18] ; clk ; clk ; 0.000 ; 0.044 ; 0.426 ; +; 0.298 ; Kd_Out[16] ; Kd_Out[16] ; clk ; clk ; 0.000 ; 0.043 ; 0.425 ; +; 0.298 ; Ki_Out[15] ; Ki_Out[15] ; clk ; clk ; 0.000 ; 0.044 ; 0.426 ; +; 0.298 ; Ki_Out[14] ; Ki_Out[14] ; clk ; clk ; 0.000 ; 0.044 ; 0.426 ; +; 0.298 ; Kd_Out[13] ; Kd_Out[13] ; clk ; clk ; 0.000 ; 0.043 ; 0.425 ; +; 0.298 ; Ki_Out[13] ; Ki_Out[13] ; clk ; clk ; 0.000 ; 0.044 ; 0.426 ; +; 0.298 ; Kd_Out[12] ; Kd_Out[12] ; clk ; clk ; 0.000 ; 0.043 ; 0.425 ; +; 0.298 ; Ki_Out[12] ; Ki_Out[12] ; clk ; clk ; 0.000 ; 0.044 ; 0.426 ; +; 0.298 ; Ki_Out[11] ; Ki_Out[11] ; clk ; clk ; 0.000 ; 0.044 ; 0.426 ; +; 0.298 ; Ki_Out[9] ; Ki_Out[9] ; clk ; clk ; 0.000 ; 0.043 ; 0.425 ; +; 0.298 ; Ki_Out[8] ; Ki_Out[8] ; clk ; clk ; 0.000 ; 0.043 ; 0.425 ; +; 0.298 ; Kd_Out[6] ; Kd_Out[6] ; clk ; clk ; 0.000 ; 0.044 ; 0.426 ; +; 0.298 ; Kd_Out[4] ; Kd_Out[4] ; clk ; clk ; 0.000 ; 0.044 ; 0.426 ; +; 0.298 ; Kd_Out[3] ; Kd_Out[3] ; clk ; clk ; 0.000 ; 0.044 ; 0.426 ; +; 0.298 ; Kd_Out[1] ; Kd_Out[1] ; clk ; clk ; 0.000 ; 0.044 ; 0.426 ; +; 0.298 ; Ki_Out[7] ; Ki_Out[7] ; clk ; clk ; 0.000 ; 0.043 ; 0.425 ; +; 0.299 ; Ki_Out[17] ; Ki_Out[17] ; clk ; clk ; 0.000 ; 0.044 ; 0.427 ; +; 0.299 ; Ki_Out[6] ; Ki_Out[6] ; clk ; clk ; 0.000 ; 0.043 ; 0.426 ; +; 0.299 ; Ki_Out[5] ; Ki_Out[5] ; clk ; clk ; 0.000 ; 0.043 ; 0.426 ; +; 0.299 ; Ki_Out[4] ; Ki_Out[4] ; clk ; clk ; 0.000 ; 0.043 ; 0.426 ; +; 0.299 ; Ki_Out[2] ; Ki_Out[2] ; clk ; clk ; 0.000 ; 0.043 ; 0.426 ; +; 0.299 ; Ki_Out[1] ; Ki_Out[1] ; clk ; clk ; 0.000 ; 0.043 ; 0.426 ; +; 0.299 ; period[9] ; period[9] ; clk ; clk ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; period[5] ; period[5] ; clk ; clk ; 0.000 ; 0.036 ; 0.419 ; +; 0.299 ; period[4] ; period[4] ; clk ; clk ; 0.000 ; 0.036 ; 0.419 ; +; 0.300 ; Ki_Out[19] ; Ki_Out[19] ; clk ; clk ; 0.000 ; 0.044 ; 0.428 ; +; 0.300 ; Ki_Out[3] ; Ki_Out[3] ; clk ; clk ; 0.000 ; 0.043 ; 0.427 ; +; 0.301 ; period[8] ; period[8] ; clk ; clk ; 0.000 ; 0.036 ; 0.421 ; +; 0.304 ; Kp_Out[0] ; Kp_Out[0] ; clk ; clk ; 0.000 ; 0.036 ; 0.424 ; +; 0.305 ; Kp_Out[16] ; Kp_Out[16] ; clk ; clk ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; Kp_Out[10] ; Kp_Out[10] ; clk ; clk ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; Kp_Out[9] ; Kp_Out[9] ; clk ; clk ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; Kp_Out[8] ; Kp_Out[8] ; clk ; clk ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; EE2[4] ; EE2[4] ; clk ; clk ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; Kp_Out[7] ; Kp_Out[7] ; clk ; clk ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; EE1[12] ; EE1[12] ; clk ; clk ; 0.000 ; 0.036 ; 0.425 ; +; 0.305 ; period[1] ; period[1] ; clk ; clk ; 0.000 ; 0.036 ; 0.425 ; +; 0.306 ; Kp_Out[18] ; Kp_Out[18] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; Kp_Out[15] ; Kp_Out[15] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; Kp_Out[14] ; Kp_Out[14] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; Kp_Out[13] ; Kp_Out[13] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; Kp_Out[12] ; Kp_Out[12] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; Kp_Out[11] ; Kp_Out[11] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; EE2[11] ; EE2[11] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; EE2[9] ; EE2[9] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; EE2[6] ; EE2[6] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; EE2[3] ; EE2[3] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; EE2[2] ; EE2[2] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; EE2[1] ; EE2[1] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; EE2[0] ; EE2[0] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; Kp_Out[6] ; Kp_Out[6] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; Kp_Out[5] ; Kp_Out[5] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; Kp_Out[4] ; Kp_Out[4] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; Kp_Out[2] ; Kp_Out[2] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; Kp_Out[1] ; Kp_Out[1] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.306 ; EE1[8] ; EE1[8] ; clk ; clk ; 0.000 ; 0.036 ; 0.426 ; +; 0.307 ; Kp_Out[17] ; Kp_Out[17] ; clk ; clk ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; EE2[10] ; EE2[10] ; clk ; clk ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; EE2[8] ; EE2[8] ; clk ; clk ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; EE2[7] ; EE2[7] ; clk ; clk ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; EE2[5] ; EE2[5] ; clk ; clk ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; Kp_Out[3] ; Kp_Out[3] ; clk ; clk ; 0.000 ; 0.036 ; 0.427 ; +; 0.307 ; period[2] ; period[2] ; clk ; clk ; 0.000 ; 0.036 ; 0.427 ; +; 0.308 ; Kp_Out[19] ; Kp_Out[19] ; clk ; clk ; 0.000 ; 0.036 ; 0.428 ; +; 0.310 ; EE2[13] ; EE2[13] ; clk ; clk ; 0.000 ; 0.036 ; 0.430 ; +; 0.316 ; EE1[2] ; EE1[2] ; clk ; clk ; 0.000 ; 0.036 ; 0.436 ; +; 0.317 ; EE1[10] ; EE1[10] ; clk ; clk ; 0.000 ; 0.036 ; 0.437 ; +; 0.317 ; EE1[4] ; EE1[4] ; clk ; clk ; 0.000 ; 0.036 ; 0.437 ; +; 0.317 ; EE1[0] ; EE1[0] ; clk ; clk ; 0.000 ; 0.036 ; 0.437 ; +; 0.318 ; EE1[6] ; EE1[6] ; clk ; clk ; 0.000 ; 0.036 ; 0.438 ; +; 0.318 ; EE1[5] ; EE1[5] ; clk ; clk ; 0.000 ; 0.036 ; 0.438 ; +; 0.318 ; EE1[1] ; EE1[1] ; clk ; clk ; 0.000 ; 0.036 ; 0.438 ; +; 0.319 ; EE1[11] ; EE1[11] ; clk ; clk ; 0.000 ; 0.036 ; 0.439 ; +; 0.319 ; EE1[9] ; EE1[9] ; clk ; clk ; 0.000 ; 0.036 ; 0.439 ; +; 0.319 ; EE1[7] ; EE1[7] ; clk ; clk ; 0.000 ; 0.036 ; 0.439 ; +; 0.319 ; EE1[3] ; EE1[3] ; clk ; clk ; 0.000 ; 0.036 ; 0.439 ; +; 0.380 ; EE0[13]~_Duplicate_1 ; EE1[13] ; clk ; clk ; 0.000 ; 0.032 ; 0.496 ; +; 0.399 ; period[4] ; period[7] ; clk ; clk ; 0.000 ; 0.036 ; 0.519 ; +; 0.400 ; EE2[13] ; Kd_Out[16] ; clk ; clk ; 0.000 ; 0.219 ; 0.703 ; +; 0.400 ; EE2[13] ; Kd_Out[13] ; clk ; clk ; 0.000 ; 0.219 ; 0.703 ; +; 0.400 ; EE2[13] ; Kd_Out[12] ; clk ; clk ; 0.000 ; 0.219 ; 0.703 ; +; 0.400 ; EE2[13] ; Kd_Out[10] ; clk ; clk ; 0.000 ; 0.219 ; 0.703 ; +; 0.400 ; period[4] ; period[6] ; clk ; clk ; 0.000 ; 0.036 ; 0.520 ; +; 0.414 ; EE1[13] ; EE1[12] ; clk ; clk ; 0.000 ; 0.036 ; 0.534 ; ++-------+----------------------+------------+--------------+-------------+--------------+------------+------------+ + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+----------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+----------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -5.488 ; 0.205 ; N/A ; N/A ; -4.000 ; +; clk ; -5.488 ; 0.205 ; N/A ; N/A ; -4.000 ; +; Design-wide TNS ; -529.506 ; 0.0 ; 0.0 ; 0.0 ; -254.273 ; +; clk ; -529.506 ; 0.000 ; N/A ; N/A ; -254.273 ; ++------------------+----------+-------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Vout[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Vout[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; clk ; 2.5 V ; 2000 ps ; 2000 ps ; +; rst_n ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Sample[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SetPoint[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kd[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kd[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kd[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kd[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kd[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kd[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kd[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kd[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Ki[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Ki[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Ki[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Ki[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Ki[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Ki[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Ki[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Ki[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kp[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kp[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kp[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kp[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kp[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kp[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kp[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Kp[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Vout[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; Vout[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; Vout[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; Vout[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; Vout[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; Vout[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; Vout[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; Vout[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; Vout[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; Vout[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.38 V ; -0.0073 V ; 0.097 V ; 0.018 V ; 4.24e-10 s ; 3.65e-10 s ; No ; Yes ; 2.32 V ; 2.07e-09 V ; 2.38 V ; -0.0073 V ; 0.097 V ; 0.018 V ; 4.24e-10 s ; 3.65e-10 s ; No ; Yes ; +; Vout[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; Vout[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; Vout[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; Vout[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Vout[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; Vout[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; Vout[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; Vout[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; Vout[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; Vout[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; Vout[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; Vout[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; Vout[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; Vout[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.35 V ; -0.00834 V ; 0.127 V ; 0.035 V ; 4.7e-10 s ; 4.64e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.35 V ; -0.00834 V ; 0.127 V ; 0.035 V ; 4.7e-10 s ; 4.64e-10 s ; Yes ; Yes ; +; Vout[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; Vout[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; Vout[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; Vout[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Vout[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; Vout[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; Vout[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; Vout[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; Vout[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; Vout[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; Vout[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; Vout[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; Vout[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; Vout[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; Vout[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; Vout[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; Vout[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; Vout[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk ; clk ; 6793 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk ; clk ; 6793 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 53 ; 53 ; +; Unconstrained Input Port Paths ; 1053 ; 1053 ; +; Unconstrained Output Ports ; 14 ; 14 ; +; Unconstrained Output Port Paths ; 14 ; 14 ; ++---------------------------------+-------+------+ + + ++-------------------------------------+ +; Clock Status Summary ; ++--------+-------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++--------+-------+------+-------------+ +; clk ; clk ; Base ; Constrained ; ++--------+-------+------+-------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++--------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++--------------+--------------------------------------------------------------------------------------+ +; Kd[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++--------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[13] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++--------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++--------------+--------------------------------------------------------------------------------------+ +; Kd[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kd[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ki[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Kp[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Sample[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; SetPoint[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++--------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[13] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Tue Dec 04 14:36:33 2018 +Info: Command: quartus_sta pid -c pid +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'pid.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name clk clk +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -5.488 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -5.488 -529.506 clk +Info (332146): Worst-case hold slack is 0.509 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.509 0.000 clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -4.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -4.000 -254.273 clk +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -4.999 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -4.999 -474.425 clk +Info (332146): Worst-case hold slack is 0.470 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.470 0.000 clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -4.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -4.000 -253.825 clk +Info: Analyzing Fast 1200mV 0C Model +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -1.852 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -1.852 -152.887 clk +Info (332146): Worst-case hold slack is 0.205 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.205 0.000 clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -3.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -3.000 -158.600 clk +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 4778 megabytes + Info: Processing ended: Tue Dec 04 14:36:36 2018 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/pid/output_files/pid.sta.summary b/pid/output_files/pid.sta.summary new file mode 100644 index 0000000..a165cfd --- /dev/null +++ b/pid/output_files/pid.sta.summary @@ -0,0 +1,41 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1200mV 85C Model Setup 'clk' +Slack : -5.488 +TNS : -529.506 + +Type : Slow 1200mV 85C Model Hold 'clk' +Slack : 0.509 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk' +Slack : -4.000 +TNS : -254.273 + +Type : Slow 1200mV 0C Model Setup 'clk' +Slack : -4.999 +TNS : -474.425 + +Type : Slow 1200mV 0C Model Hold 'clk' +Slack : 0.470 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk' +Slack : -4.000 +TNS : -253.825 + +Type : Fast 1200mV 0C Model Setup 'clk' +Slack : -1.852 +TNS : -152.887 + +Type : Fast 1200mV 0C Model Hold 'clk' +Slack : 0.205 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk' +Slack : -3.000 +TNS : -158.600 + +------------------------------------------------------------ diff --git a/pid/pid.qpf b/pid/pid.qpf new file mode 100644 index 0000000..33cd943 --- /dev/null +++ b/pid/pid.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 11:02:55 December 03, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "11:02:55 December 03, 2018" + +# Revisions + +PROJECT_REVISION = "pid" diff --git a/pid/pid.qsf b/pid/pid.qsf new file mode 100644 index 0000000..63f91ab --- /dev/null +++ b/pid/pid.qsf @@ -0,0 +1,68 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 11:02:55 December 03, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# pid_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE10F17C8 +set_global_assignment -name TOP_LEVEL_ENTITY pid +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:02:55 DECEMBER 03, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name VERILOG_FILE rtl/pid.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VERILOG_FILE testbench/pid_tb.v +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH pid_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME pid_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id pid_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME pid_tb -section_id pid_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/pid_tb.v -section_id pid_tb +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/pid/pid.qws b/pid/pid.qws new file mode 100644 index 0000000..15292f1 Binary files /dev/null and b/pid/pid.qws differ diff --git a/pid/pid_nativelink_simulation.rpt b/pid/pid_nativelink_simulation.rpt new file mode 100644 index 0000000..4377181 --- /dev/null +++ b/pid/pid_nativelink_simulation.rpt @@ -0,0 +1,23 @@ +Info: Start Nativelink Simulation process +Info: NativeLink has detected Verilog design -- Verilog simulation models will be used + +========= EDA Simulation Settings ===================== + +Sim Mode : RTL +Family : cycloneive +Quartus root : d:/intelfpga/18.1/quartus/bin64/ +Quartus sim root : d:/intelfpga/18.1/quartus/eda/sim_lib +Simulation Tool : modelsim-altera +Simulation Language : verilog +Simulation Mode : GUI +Sim Output File : +Sim SDF file : +Sim dir : simulation\modelsim + +======================================================= + +Info: Starting NativeLink simulation with ModelSim-Altera software +Sourced NativeLink script d:/intelfpga/18.1/quartus/common/tcl/internal/nativelink/modelsim.tcl +Warning: File pid_run_msim_rtl_verilog.do already exists - backing up current file as pid_run_msim_rtl_verilog.do.bak10 +Info: Spawning ModelSim-Altera Simulation software +Info: NativeLink simulation flow was successful diff --git a/pid/rtl/pid.v b/pid/rtl/pid.v new file mode 100644 index 0000000..88f59bd --- /dev/null +++ b/pid/rtl/pid.v @@ -0,0 +1,80 @@ +module pid + ( + clk, + rst_n,//50Mhz + Sample, //要比AD数字量多一位 + SetPoint, + Kp, + Ki, + Kd, + Vout //DA/PWM占空比调节 + ); + + parameter par0= 7-1; //调整周期 + + input clk,rst_n;//50Mhz + input signed [13:0]Sample; + input signed [13:0]SetPoint; + input signed [8:0]Kp; + input signed [8:0]Ki; + input signed [8:0]Kd; + + output reg signed [13:0] Vout ; + + reg signed [13:0]EE0,EE1,EE2,EETMP; + reg signed [22:0]Kp_Out,Ki_Out,Kd_Out; + + reg signed [8:0]kpid; + + reg [7:0]period; + + reg [3:0] status; + + parameter s0 = 4'b0000,s1 = 4'b0001,s2 = 4'b0011, + s3 = 4'b0010,s4 = 4'b0110,s5 = 4'b0111, + s6 = 4'b0101,s7 = 4'b0100; + + always @ (posedge clk or negedge rst_n) + if(!rst_n) + period <= 8'd0; + else if (period == par0) + period <= 8'd0; + else + period <= period + 1'd1; + +//***************************************// + + always @ (posedge clk or negedge rst_n) + if(!rst_n) + begin + EE1 <= 0; + EE2 <= 0; + EE0 <= 0; + + EETMP <= 0; + kpid <= 0; + + Kp_Out <= 0; + Ki_Out <= 0; + Kd_Out <= 0; + + status <= s0; + + Vout<=14'd0; + + end + else if (period == par0) begin + case (status) + s0:begin EE0 <= SetPoint-Sample;EE2 <= EE1;EE1 <= EE0; status <= s1;end + s1:begin EETMP <= EE0;kpid <= Kp; status <= s2;end + s2:begin Kp_Out<= EETMP*kpid; status <= s3;end + s3:begin EETMP <= EE1;kpid <= Ki; status <= s4;end + s4:begin Ki_Out<= EETMP*kpid; status <= s5;end + s5:begin EETMP <= EE2;kpid <= Kd; status <= s6;end + s6:begin Kd_Out<= EETMP*kpid; status <= s7;end + s7:begin Vout<= ((Kp_Out - Ki_Out + Kd_Out) >> 4'd8); status <= s0;end + default:begin status <= s0; end + endcase + end + +endmodule diff --git a/pid/rtl/pid.v.bak b/pid/rtl/pid.v.bak new file mode 100644 index 0000000..95f8b74 --- /dev/null +++ b/pid/rtl/pid.v.bak @@ -0,0 +1,151 @@ +module My_PID + ( + input clk,rst_n,//50Mhz + input [13:0]Sample, //要比AD数字量多一位 + input [13:0]Position, + input [7:0]Kp, + input [7:0]Ki, + input [7:0]Kd, + output reg [15:0]Out_Ctrl //DA/PWM占空比调节 + ); + +parameter par0=16'h2549; //调整周期 +parameter lowlimit=14'h0; +parameter uplimit=14'd2000; + +//**************************************************// +//调整时钟 +// +//*************************************************// +reg [15:0]period; +reg Clk_Ctrl; +always@(posedge clk or negedge rst_n) + if(!rst_n) + begin + period<=16'd0; + Clk_Ctrl<=1'd0; + end + else + begin + if(period==par0) + begin + period<=16'd0; + Clk_Ctrl<=~Clk_Ctrl; + end + else + begin + period=period+1'd1; + + end + end +//***************************************// + wire [13:0]rSample; + assign rSample=(Sample[13])?14'd0:Sample; + reg flag; + reg [13:0]delta; + reg [13:0]EE0; + reg [13:0]EE1; + reg [13:0]EE2; + reg [13:0]ERRO0; + reg [13:0]ERRO1; + reg [16:0]Kd_delta; + reg [4:0]step; + reg [21:0]Kp_Out; + reg [21:0]Ki_Out; + reg [21:0]Kd_Out; + reg [13:0]Vout; +always@(posedge Clk_Ctrl or negedge rst_n) + if(!rst_n) + begin + step<=5'd0; + delta<=14'd0; + EE0<=14'd0; + EE1<=14'd0; + EE2<=14'd0; + ERRO0<=14'd0; + ERRO1<=14'd0; + Vout<=14'd0; + Kd_delta<=14'd0; + Kp_Out<=22'd0; + Ki_Out<=22'd0; + Kd_Out<=22'd0; + flag<=1'd0; + end + else + case(step) + 5'd0: + begin + EE0<=Position-rSample; + step<=step+1'd1; + end + 5'd1: + begin + ERRO0<=EE0-EE1; + ERRO1<=EE2-EE1; + step<=step+1'd1; + end + 5'd2: + begin + Kd_delta<=ERRO0-ERRO1; + step<=step+1'd1; + end + 5'd3: + begin + if(ERRO0[13]) + Kp_Out=~(((~ERRO0+1'd1)*Kp)-1'd1);//得到绝对值 + else + Kp_Out=(ERRO0*Kp); + step<=step+1'd1; + end + 5'd4: + begin + if(EE0[13]) + Ki_Out<=~(((~EE0+1'd1)*Ki)-1'd1); + else + Ki_Out<=(EE0*Ki); + step<=step+1'd1; + end + 5'd5: + begin + if(Kd_delta[13]) + Kd_Out<=~(((~Kd_delta+1'd1)*Kd)-1'd1); + else + Kd_Out<=(Kd_delta)*Kd; + step<=step+1'd1; + end + 5'd6: + begin + EE2<=EE1; + delta<=(Ki_Out+Kp_Out+Kd_Out)>>8'd8; + step<=step+1'd1; + end + 5'd7: + begin + EE1<=EE0; + step<=step+1'd1; + if(delta[13]&&(delta<14'h2f38)) + delta<=14'h2f38; + else if((!delta[13])&&(delta>14'hc8)) + delta<=14'hc8; + end + 5'd8: + begin + Vout<=Vout+delta; + step<=step+1'd1; + end + 5'd9: + begin + if(Vout[13]==1) + Vout<=lowlimit; + else if(Vout>=uplimit) + Vout<=uplimit; + step<=5'd0; + end + endcase +always@(posedge Clk_Ctrl or negedge rst_n) + if(!rst_n) + Out_Ctrl<=14'd0; + else + if(step==5'd0) + Out_Ctrl<=Vout; +endmodule diff --git a/pid/simulation/modelsim/modelsim.ini b/pid/simulation/modelsim/modelsim.ini new file mode 100644 index 0000000..29480d4 --- /dev/null +++ b/pid/simulation/modelsim/modelsim.ini @@ -0,0 +1,324 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +work = rtl_work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/pid/simulation/modelsim/msim_transcript b/pid/simulation/modelsim/msim_transcript new file mode 100644 index 0000000..13bc460 --- /dev/null +++ b/pid/simulation/modelsim/msim_transcript @@ -0,0 +1,373 @@ +# Reading D:/intelFPGA/modelsim_ase/tcl/vsim/pref.tcl +# do pid_run_msim_rtl_verilog.do +# if {[file exists rtl_work]} { +# vdel -lib rtl_work -all +# } +# vlib rtl_work +# vmap work rtl_work +# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 +# vmap work rtl_work +# Copying D:/intelFPGA/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini +# Modifying modelsim.ini +# +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 17:24:38 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/rtl" F:/Code/FPGA/reserve/pid/rtl/pid.v +# -- Compiling module pid +# +# Top level modules: +# pid +# End time: 17:24:38 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 17:24:38 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/testbench" F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# -- Compiling module pid_tb +# +# Top level modules: +# pid_tb +# End time: 17:24:38 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# +# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb +# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=""+acc"" pid_tb +# Start time: 17:24:39 on Dec 08,2018 +# Loading work.pid_tb +# Loading work.pid +# +# add wave * +# ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf +# File in use by: sansi Hostname: DESKTOP-U8FBMPE ProcessID: 7900 +# Attempting to use alternate WLF file "./wlft5vs1nh". +# ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf +# Using alternate file: ./wlft5vs1nh +# view structure +# .main_pane.structure.interior.cs.body.struct +# view signals +# .main_pane.objects.interior.cs.body.tree +# run -all +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl F:/Code/FPGA/reserve/pid/rtl/pid.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 17:26:14 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/rtl" F:/Code/FPGA/reserve/pid/rtl/pid.v +# -- Compiling module pid +# +# Top level modules: +# pid +# End time: 17:26:14 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 17:26:14 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/testbench" F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# -- Compiling module pid_tb +# +# Top level modules: +# pid_tb +# End time: 17:26:14 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +restart +# Loading work.pid_tb +# Loading work.pid +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl F:/Code/FPGA/reserve/pid/rtl/pid.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:14:34 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/rtl" F:/Code/FPGA/reserve/pid/rtl/pid.v +# -- Compiling module pid +# +# Top level modules: +# pid +# End time: 18:14:34 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:14:34 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/testbench" F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# -- Compiling module pid_tb +# +# Top level modules: +# pid_tb +# End time: 18:14:34 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +run +restart +# Loading work.pid_tb +# Loading work.pid +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl F:/Code/FPGA/reserve/pid/rtl/pid.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:16:22 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/rtl" F:/Code/FPGA/reserve/pid/rtl/pid.v +# -- Compiling module pid +# +# Top level modules: +# pid +# End time: 18:16:22 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:16:22 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/testbench" F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# -- Compiling module pid_tb +# +# Top level modules: +# pid_tb +# End time: 18:16:22 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +restart +# Loading work.pid_tb +# Loading work.pid +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +restart +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl F:/Code/FPGA/reserve/pid/rtl/pid.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:18:23 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/rtl" F:/Code/FPGA/reserve/pid/rtl/pid.v +# -- Compiling module pid +# +# Top level modules: +# pid +# End time: 18:18:23 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:18:24 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/testbench" F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# -- Compiling module pid_tb +# +# Top level modules: +# pid_tb +# End time: 18:18:24 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +restart +# Loading work.pid_tb +# Loading work.pid +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl F:/Code/FPGA/reserve/pid/rtl/pid.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:20:08 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/rtl" F:/Code/FPGA/reserve/pid/rtl/pid.v +# -- Compiling module pid +# +# Top level modules: +# pid +# End time: 18:20:08 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:20:08 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/testbench" F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# -- Compiling module pid_tb +# +# Top level modules: +# pid_tb +# End time: 18:20:08 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +restart +# Loading work.pid_tb +# Loading work.pid +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +restart +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +restart +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl F:/Code/FPGA/reserve/pid/rtl/pid.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:22:09 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/rtl" F:/Code/FPGA/reserve/pid/rtl/pid.v +# -- Compiling module pid +# +# Top level modules: +# pid +# End time: 18:22:10 on Dec 08,2018, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:22:10 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/testbench" F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# -- Compiling module pid_tb +# +# Top level modules: +# pid_tb +# End time: 18:22:10 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +restart +# Loading work.pid_tb +# Loading work.pid +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +restart +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl F:/Code/FPGA/reserve/pid/rtl/pid.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:23:18 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/rtl" F:/Code/FPGA/reserve/pid/rtl/pid.v +# -- Compiling module pid +# +# Top level modules: +# pid +# End time: 18:23:19 on Dec 08,2018, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:23:19 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/testbench" F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# -- Compiling module pid_tb +# +# Top level modules: +# pid_tb +# End time: 18:23:19 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +restart +# Loading work.pid_tb +# Loading work.pid +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +add wave -position insertpoint sim:/pid_tb/pid/* +restart +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +restart +restart +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +restart +restart +restart +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl F:/Code/FPGA/reserve/pid/rtl/pid.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:30:19 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/rtl" F:/Code/FPGA/reserve/pid/rtl/pid.v +# -- Compiling module pid +# +# Top level modules: +# pid +# End time: 18:30:19 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:30:19 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/testbench" F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# -- Compiling module pid_tb +# +# Top level modules: +# pid_tb +# End time: 18:30:19 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +restart +# Loading work.pid_tb +# Loading work.pid +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl F:/Code/FPGA/reserve/pid/rtl/pid.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:44:13 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/rtl" F:/Code/FPGA/reserve/pid/rtl/pid.v +# -- Compiling module pid +# +# Top level modules: +# pid +# End time: 18:44:13 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:44:13 on Dec 08,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/pid/testbench" F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +# -- Compiling module pid_tb +# +# Top level modules: +# pid_tb +# End time: 18:44:13 on Dec 08,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +restart +# Loading work.pid_tb +# Loading work.pid +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/pid/testbench/pid_tb.v(68) +# Time: 2320600 ns Iteration: 0 Instance: /pid_tb +# Break in Module pid_tb at F:/Code/FPGA/reserve/pid/testbench/pid_tb.v line 68 +# End time: 18:44:39 on Dec 08,2018, Elapsed time: 1:20:00 +# Errors: 0, Warnings: 2 diff --git a/pid/simulation/modelsim/pid.sft b/pid/simulation/modelsim/pid.sft new file mode 100644 index 0000000..6efb85b --- /dev/null +++ b/pid/simulation/modelsim/pid.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim-Altera (Verilog)" +set corner_file_list { + {{"Slow -8 1.2V 85 Model"} {pid_8_1200mv_85c_slow.vo pid_8_1200mv_85c_v_slow.sdo}} + {{"Slow -8 1.2V 0 Model"} {pid_8_1200mv_0c_slow.vo pid_8_1200mv_0c_v_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {pid_min_1200mv_0c_fast.vo pid_min_1200mv_0c_v_fast.sdo}} +} diff --git a/pid/simulation/modelsim/pid.vo b/pid/simulation/modelsim/pid.vo new file mode 100644 index 0000000..ad7bb17 --- /dev/null +++ b/pid/simulation/modelsim/pid.vo @@ -0,0 +1,8790 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" + +// DATE "12/04/2018 14:36:39" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module pid ( + clk, + rst_n, + Sample, + SetPoint, + Kp, + Ki, + Kd, + Vout); +input clk; +input rst_n; +input [13:0] Sample; +input [13:0] SetPoint; +input [7:0] Kp; +input [7:0] Ki; +input [7:0] Kd; +output [13:0] Vout; + +// Design Ports Information +// Vout[0] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// Vout[1] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[2] => Location: PIN_N8, I/O Standard: 2.5 V, Current Strength: Default +// Vout[3] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default +// Vout[4] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[5] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[6] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default +// Vout[7] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// Vout[8] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// Vout[9] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default +// Vout[10] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[11] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// Vout[12] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +// Vout[13] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[13] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default +// Sample[13] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default +// Sample[12] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[12] => Location: PIN_F10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[11] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[11] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default +// Sample[10] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[10] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[9] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[9] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default +// Sample[8] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[8] => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// Sample[7] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[7] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default +// Sample[6] => Location: PIN_F14, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[6] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default +// Sample[5] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[5] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[4] => Location: PIN_G11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[4] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[3] => Location: PIN_F11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[3] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default +// Sample[2] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[2] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default +// Sample[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[1] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default +// Sample[0] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[0] => Location: PIN_R12, I/O Standard: 2.5 V, Current Strength: Default +// Kd[0] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[1] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default +// Kd[2] => Location: PIN_J14, I/O Standard: 2.5 V, Current Strength: Default +// Kd[3] => Location: PIN_N9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[4] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default +// Kd[5] => Location: PIN_K9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[6] => Location: PIN_L9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[7] => Location: PIN_R9, I/O Standard: 2.5 V, Current Strength: Default +// Ki[0] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default +// Ki[1] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// Ki[2] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// Ki[3] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default +// Ki[4] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// Ki[5] => Location: PIN_J12, I/O Standard: 2.5 V, Current Strength: Default +// Ki[6] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default +// Ki[7] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[0] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// Kp[1] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default +// Kp[2] => Location: PIN_M9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[3] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default +// Kp[4] => Location: PIN_D9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[5] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// Kp[6] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// Kp[7] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("pid_v.sdo"); +// synopsys translate_on + +wire \Mult2|auto_generated|mac_out2~0 ; +wire \Mult2|auto_generated|mac_out2~1 ; +wire \Mult2|auto_generated|mac_out2~2 ; +wire \Mult2|auto_generated|mac_out2~3 ; +wire \Mult2|auto_generated|mac_out2~4 ; +wire \Mult2|auto_generated|mac_out2~5 ; +wire \Mult2|auto_generated|mac_out2~6 ; +wire \Mult2|auto_generated|mac_out2~7 ; +wire \Mult2|auto_generated|mac_out2~8 ; +wire \Mult2|auto_generated|mac_out2~9 ; +wire \Mult2|auto_generated|mac_out2~10 ; +wire \Mult2|auto_generated|mac_out2~11 ; +wire \Mult2|auto_generated|mac_out2~12 ; +wire \Mult2|auto_generated|mac_out2~13 ; +wire \Mult2|auto_generated|mac_out2~14 ; +wire \Mult2|auto_generated|mac_out2~15 ; +wire \Mult1|auto_generated|mac_out2~0 ; +wire \Mult1|auto_generated|mac_out2~1 ; +wire \Mult1|auto_generated|mac_out2~2 ; +wire \Mult1|auto_generated|mac_out2~3 ; +wire \Mult1|auto_generated|mac_out2~4 ; +wire \Mult1|auto_generated|mac_out2~5 ; +wire \Mult1|auto_generated|mac_out2~6 ; +wire \Mult1|auto_generated|mac_out2~7 ; +wire \Mult1|auto_generated|mac_out2~8 ; +wire \Mult1|auto_generated|mac_out2~9 ; +wire \Mult1|auto_generated|mac_out2~10 ; +wire \Mult1|auto_generated|mac_out2~11 ; +wire \Mult1|auto_generated|mac_out2~12 ; +wire \Mult1|auto_generated|mac_out2~13 ; +wire \Mult1|auto_generated|mac_out2~14 ; +wire \Mult1|auto_generated|mac_out2~15 ; +wire \Mult0|auto_generated|mac_out2~DATAOUT21 ; +wire \Mult0|auto_generated|mac_out2~0 ; +wire \Mult0|auto_generated|mac_out2~1 ; +wire \Mult0|auto_generated|mac_out2~2 ; +wire \Mult0|auto_generated|mac_out2~3 ; +wire \Mult0|auto_generated|mac_out2~4 ; +wire \Mult0|auto_generated|mac_out2~5 ; +wire \Mult0|auto_generated|mac_out2~6 ; +wire \Mult0|auto_generated|mac_out2~7 ; +wire \Mult0|auto_generated|mac_out2~8 ; +wire \Mult0|auto_generated|mac_out2~9 ; +wire \Mult0|auto_generated|mac_out2~10 ; +wire \Mult0|auto_generated|mac_out2~11 ; +wire \Mult0|auto_generated|mac_out2~12 ; +wire \Mult0|auto_generated|mac_out2~13 ; +wire \Vout[0]~output_o ; +wire \Vout[1]~output_o ; +wire \Vout[2]~output_o ; +wire \Vout[3]~output_o ; +wire \Vout[4]~output_o ; +wire \Vout[5]~output_o ; +wire \Vout[6]~output_o ; +wire \Vout[7]~output_o ; +wire \Vout[8]~output_o ; +wire \Vout[9]~output_o ; +wire \Vout[10]~output_o ; +wire \Vout[11]~output_o ; +wire \Vout[12]~output_o ; +wire \Vout[13]~output_o ; +wire \clk~input_o ; +wire \clk~inputclkctrl_outclk ; +wire \Kd_Out[0]~21_combout ; +wire \EE2[0]~14_combout ; +wire \EE1[0]~14_combout ; +wire \SetPoint[0]~input_o ; +wire \Sample[13]~input_o ; +wire \Add1~1_combout ; +wire \SetPoint[13]~input_o ; +wire \Add1~0_combout ; +wire \Sample[12]~input_o ; +wire \Add1~2_combout ; +wire \SetPoint[12]~input_o ; +wire \Sample[11]~input_o ; +wire \Add1~4_combout ; +wire \SetPoint[11]~input_o ; +wire \SetPoint[10]~input_o ; +wire \Sample[10]~input_o ; +wire \Add1~6_combout ; +wire \Sample[9]~input_o ; +wire \Add1~8_combout ; +wire \SetPoint[9]~input_o ; +wire \SetPoint[8]~input_o ; +wire \Sample[8]~input_o ; +wire \Add1~10_combout ; +wire \Sample[7]~input_o ; +wire \Add1~12_combout ; +wire \SetPoint[7]~input_o ; +wire \SetPoint[6]~input_o ; +wire \Sample[6]~input_o ; +wire \Add1~14_combout ; +wire \Sample[5]~input_o ; +wire \Add1~16_combout ; +wire \SetPoint[4]~input_o ; +wire \Sample[4]~input_o ; +wire \Add1~18_combout ; +wire \Sample[3]~input_o ; +wire \Add1~20_combout ; +wire \SetPoint[2]~input_o ; +wire \Sample[2]~input_o ; +wire \Add1~22_combout ; +wire \Sample[1]~input_o ; +wire \Add1~24_combout ; +wire \SetPoint[1]~input_o ; +wire \Sample[0]~input_o ; +wire \Add1~26_combout ; +wire \EE0[0]~15_cout ; +wire \EE0[0]~17 ; +wire \EE0[1]~18_combout ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \Add0~0_combout ; +wire \period~3_combout ; +wire \Add0~1 ; +wire \Add0~2_combout ; +wire \Add0~3 ; +wire \Add0~4_combout ; +wire \Equal0~2_combout ; +wire \Add0~5 ; +wire \Add0~6_combout ; +wire \period~2_combout ; +wire \Add0~7 ; +wire \Add0~8_combout ; +wire \Add0~9 ; +wire \Add0~10_combout ; +wire \Add0~11 ; +wire \Add0~13 ; +wire \Add0~14_combout ; +wire \period~0_combout ; +wire \Add0~15 ; +wire \Add0~16_combout ; +wire \Add0~17 ; +wire \Add0~18_combout ; +wire \Add0~19 ; +wire \Add0~20_combout ; +wire \Equal0~0_combout ; +wire \Add0~12_combout ; +wire \period~1_combout ; +wire \Equal0~1_combout ; +wire \Equal0~3_combout ; +wire \Clk_Ctrl~q ; +wire \EE0[1]~_Duplicate_1_q ; +wire \Add1~25_combout ; +wire \EE0[1]~19 ; +wire \EE0[2]~20_combout ; +wire \EE0[2]~_Duplicate_1_q ; +wire \Add1~23_combout ; +wire \EE0[2]~21 ; +wire \EE0[3]~22_combout ; +wire \EE0[3]~_Duplicate_1_q ; +wire \SetPoint[3]~input_o ; +wire \Add1~21_combout ; +wire \EE0[3]~23 ; +wire \EE0[4]~24_combout ; +wire \EE0[4]~_Duplicate_1_q ; +wire \Add1~19_combout ; +wire \EE0[4]~25 ; +wire \EE0[5]~26_combout ; +wire \EE0[5]~_Duplicate_1_q ; +wire \SetPoint[5]~input_o ; +wire \Add1~17_combout ; +wire \EE0[5]~27 ; +wire \EE0[6]~28_combout ; +wire \EE0[6]~_Duplicate_1_q ; +wire \Add1~15_combout ; +wire \EE0[6]~29 ; +wire \EE0[7]~30_combout ; +wire \EE0[7]~_Duplicate_1_q ; +wire \Add1~13_combout ; +wire \EE0[7]~31 ; +wire \EE0[8]~32_combout ; +wire \EE0[8]~_Duplicate_1_q ; +wire \Add1~11_combout ; +wire \EE0[8]~33 ; +wire \EE0[9]~34_combout ; +wire \EE0[9]~_Duplicate_1_q ; +wire \Add1~9_combout ; +wire \EE0[9]~35 ; +wire \EE0[10]~36_combout ; +wire \EE0[10]~_Duplicate_1_q ; +wire \Add1~7_combout ; +wire \EE0[10]~37 ; +wire \EE0[11]~38_combout ; +wire \EE0[11]~_Duplicate_1_q ; +wire \Add1~5_combout ; +wire \EE0[11]~39 ; +wire \EE0[12]~40_combout ; +wire \EE0[12]~_Duplicate_1_q ; +wire \Add1~3_combout ; +wire \EE0[12]~41 ; +wire \EE0[13]~42_combout ; +wire \EE0[13]~_Duplicate_1_q ; +wire \Add1~27_combout ; +wire \EE0[0]~16_combout ; +wire \EE0[0]~_Duplicate_1_q ; +wire \EE1[0]~15 ; +wire \EE1[1]~16_combout ; +wire \EE1[1]~17 ; +wire \EE1[2]~18_combout ; +wire \EE1[2]~19 ; +wire \EE1[3]~20_combout ; +wire \EE1[3]~21 ; +wire \EE1[4]~22_combout ; +wire \EE1[4]~23 ; +wire \EE1[5]~24_combout ; +wire \EE1[5]~25 ; +wire \EE1[6]~26_combout ; +wire \EE1[6]~27 ; +wire \EE1[7]~28_combout ; +wire \EE1[7]~29 ; +wire \EE1[8]~30_combout ; +wire \EE1[8]~31 ; +wire \EE1[9]~32_combout ; +wire \EE1[9]~33 ; +wire \EE1[10]~34_combout ; +wire \EE1[10]~35 ; +wire \EE1[11]~36_combout ; +wire \EE1[11]~37 ; +wire \EE1[12]~38_combout ; +wire \EE1[12]~39 ; +wire \EE1[13]~40_combout ; +wire \EE2[0]~15 ; +wire \EE2[1]~16_combout ; +wire \EE2[1]~17 ; +wire \EE2[2]~18_combout ; +wire \EE2[2]~19 ; +wire \EE2[3]~20_combout ; +wire \EE2[3]~21 ; +wire \EE2[4]~22_combout ; +wire \EE2[4]~23 ; +wire \EE2[5]~24_combout ; +wire \EE2[5]~25 ; +wire \EE2[6]~26_combout ; +wire \EE2[6]~27 ; +wire \EE2[7]~28_combout ; +wire \EE2[7]~29 ; +wire \EE2[8]~30_combout ; +wire \EE2[8]~31 ; +wire \EE2[9]~32_combout ; +wire \EE2[9]~33 ; +wire \EE2[10]~34_combout ; +wire \EE2[10]~35 ; +wire \EE2[11]~36_combout ; +wire \EE2[11]~37 ; +wire \EE2[12]~38_combout ; +wire \EE2[12]~39 ; +wire \EE2[13]~40_combout ; +wire \Kd[0]~input_o ; +wire \Kd[1]~input_o ; +wire \Kd[2]~input_o ; +wire \Kd[3]~input_o ; +wire \Kd[4]~input_o ; +wire \Kd[5]~input_o ; +wire \Kd[6]~input_o ; +wire \Kd[7]~input_o ; +wire \Mult2|auto_generated|mac_mult1~dataout ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult2|auto_generated|mac_mult1~0 ; +wire \Mult2|auto_generated|mac_mult1~1 ; +wire \Mult2|auto_generated|mac_mult1~2 ; +wire \Mult2|auto_generated|mac_mult1~3 ; +wire \Mult2|auto_generated|mac_mult1~4 ; +wire \Mult2|auto_generated|mac_mult1~5 ; +wire \Mult2|auto_generated|mac_mult1~6 ; +wire \Mult2|auto_generated|mac_mult1~7 ; +wire \Mult2|auto_generated|mac_mult1~8 ; +wire \Mult2|auto_generated|mac_mult1~9 ; +wire \Mult2|auto_generated|mac_mult1~10 ; +wire \Mult2|auto_generated|mac_mult1~11 ; +wire \Mult2|auto_generated|mac_mult1~12 ; +wire \Mult2|auto_generated|mac_mult1~13 ; +wire \Mult2|auto_generated|mac_mult1~14 ; +wire \Mult2|auto_generated|mac_mult1~15 ; +wire \Mult2|auto_generated|mac_out2~dataout ; +wire \Kd_Out[0]~22 ; +wire \Kd_Out[1]~23_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT1 ; +wire \Kd_Out[1]~24 ; +wire \Kd_Out[2]~25_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT2 ; +wire \Kd_Out[2]~26 ; +wire \Kd_Out[3]~27_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT3 ; +wire \Kd_Out[3]~28 ; +wire \Kd_Out[4]~29_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT4 ; +wire \Kd_Out[4]~30 ; +wire \Kd_Out[5]~31_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT5 ; +wire \Kd_Out[5]~32 ; +wire \Kd_Out[6]~33_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT6 ; +wire \Kd_Out[6]~34 ; +wire \Kd_Out[7]~35_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT7 ; +wire \Kd_Out[7]~36 ; +wire \Kd_Out[8]~37_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT8 ; +wire \Kd_Out[8]~38 ; +wire \Kd_Out[9]~39_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT9 ; +wire \Kd_Out[9]~40 ; +wire \Kd_Out[10]~41_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT10 ; +wire \Kd_Out[10]~42 ; +wire \Kd_Out[11]~43_combout ; +wire \Kd_Out[11]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT11 ; +wire \Kd_Out[11]~44 ; +wire \Kd_Out[12]~45_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT12 ; +wire \Kd_Out[12]~46 ; +wire \Kd_Out[13]~47_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT13 ; +wire \Kd_Out[13]~48 ; +wire \Kd_Out[14]~49_combout ; +wire \Kd_Out[14]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT14 ; +wire \Kd_Out[14]~50 ; +wire \Kd_Out[15]~51_combout ; +wire \Kd_Out[15]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT15 ; +wire \Kd_Out[15]~52 ; +wire \Kd_Out[16]~53_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT16 ; +wire \Kd_Out[16]~54 ; +wire \Kd_Out[17]~55_combout ; +wire \Kd_Out[17]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT17 ; +wire \Kd_Out[17]~56 ; +wire \Kd_Out[18]~57_combout ; +wire \Kd_Out[18]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT18 ; +wire \Kd_Out[18]~58 ; +wire \Kd_Out[19]~59_combout ; +wire \Kd_Out[19]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT19 ; +wire \Kd_Out[19]~60 ; +wire \Kd_Out[20]~61_combout ; +wire \~GND~combout ; +wire \Add7~20_combout ; +wire \Ki_Out[0]~21_combout ; +wire \Ki[0]~input_o ; +wire \Ki[1]~input_o ; +wire \Ki[2]~input_o ; +wire \Ki[3]~input_o ; +wire \Ki[4]~input_o ; +wire \Ki[5]~input_o ; +wire \Ki[6]~input_o ; +wire \Ki[7]~input_o ; +wire \Mult1|auto_generated|mac_mult1~dataout ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult1|auto_generated|mac_mult1~0 ; +wire \Mult1|auto_generated|mac_mult1~1 ; +wire \Mult1|auto_generated|mac_mult1~2 ; +wire \Mult1|auto_generated|mac_mult1~3 ; +wire \Mult1|auto_generated|mac_mult1~4 ; +wire \Mult1|auto_generated|mac_mult1~5 ; +wire \Mult1|auto_generated|mac_mult1~6 ; +wire \Mult1|auto_generated|mac_mult1~7 ; +wire \Mult1|auto_generated|mac_mult1~8 ; +wire \Mult1|auto_generated|mac_mult1~9 ; +wire \Mult1|auto_generated|mac_mult1~10 ; +wire \Mult1|auto_generated|mac_mult1~11 ; +wire \Mult1|auto_generated|mac_mult1~12 ; +wire \Mult1|auto_generated|mac_mult1~13 ; +wire \Mult1|auto_generated|mac_mult1~14 ; +wire \Mult1|auto_generated|mac_mult1~15 ; +wire \Mult1|auto_generated|mac_out2~dataout ; +wire \Ki_Out[0]~22 ; +wire \Ki_Out[1]~23_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT1 ; +wire \Ki_Out[1]~24 ; +wire \Ki_Out[2]~25_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT2 ; +wire \Ki_Out[2]~26 ; +wire \Ki_Out[3]~27_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT3 ; +wire \Ki_Out[3]~28 ; +wire \Ki_Out[4]~29_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT4 ; +wire \Ki_Out[4]~30 ; +wire \Ki_Out[5]~31_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT5 ; +wire \Ki_Out[5]~32 ; +wire \Ki_Out[6]~33_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT6 ; +wire \Ki_Out[6]~34 ; +wire \Ki_Out[7]~35_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT7 ; +wire \Ki_Out[7]~36 ; +wire \Ki_Out[8]~37_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT8 ; +wire \Ki_Out[8]~38 ; +wire \Ki_Out[9]~39_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT9 ; +wire \Ki_Out[9]~40 ; +wire \Ki_Out[10]~41_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT10 ; +wire \Ki_Out[10]~42 ; +wire \Ki_Out[11]~43_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT11 ; +wire \Ki_Out[11]~44 ; +wire \Ki_Out[12]~45_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT12 ; +wire \Ki_Out[12]~46 ; +wire \Ki_Out[13]~47_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT13 ; +wire \Ki_Out[13]~48 ; +wire \Ki_Out[14]~49_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT14 ; +wire \Ki_Out[14]~50 ; +wire \Ki_Out[15]~51_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT15 ; +wire \Ki_Out[15]~52 ; +wire \Ki_Out[16]~53_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT16 ; +wire \Ki_Out[16]~54 ; +wire \Ki_Out[17]~55_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT17 ; +wire \Ki_Out[17]~56 ; +wire \Ki_Out[18]~57_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT18 ; +wire \Ki_Out[18]~58 ; +wire \Ki_Out[19]~59_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT19 ; +wire \Ki_Out[19]~60 ; +wire \Ki_Out[20]~61_combout ; +wire \Kp_Out[0]~21_combout ; +wire \Kp[0]~input_o ; +wire \Kp[1]~input_o ; +wire \Kp[2]~input_o ; +wire \Kp[3]~input_o ; +wire \Kp[4]~input_o ; +wire \Kp[5]~input_o ; +wire \Kp[6]~input_o ; +wire \Kp[7]~input_o ; +wire \Mult0|auto_generated|mac_mult1~dataout ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT20 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT21 ; +wire \Mult0|auto_generated|mac_mult1~0 ; +wire \Mult0|auto_generated|mac_mult1~1 ; +wire \Mult0|auto_generated|mac_mult1~2 ; +wire \Mult0|auto_generated|mac_mult1~3 ; +wire \Mult0|auto_generated|mac_mult1~4 ; +wire \Mult0|auto_generated|mac_mult1~5 ; +wire \Mult0|auto_generated|mac_mult1~6 ; +wire \Mult0|auto_generated|mac_mult1~7 ; +wire \Mult0|auto_generated|mac_mult1~8 ; +wire \Mult0|auto_generated|mac_mult1~9 ; +wire \Mult0|auto_generated|mac_mult1~10 ; +wire \Mult0|auto_generated|mac_mult1~11 ; +wire \Mult0|auto_generated|mac_mult1~12 ; +wire \Mult0|auto_generated|mac_mult1~13 ; +wire \Mult0|auto_generated|mac_out2~dataout ; +wire \Kp_Out[0]~22 ; +wire \Kp_Out[1]~23_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT1 ; +wire \Kp_Out[1]~24 ; +wire \Kp_Out[2]~25_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT2 ; +wire \Kp_Out[2]~26 ; +wire \Kp_Out[3]~27_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT3 ; +wire \Kp_Out[3]~28 ; +wire \Kp_Out[4]~29_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT4 ; +wire \Kp_Out[4]~30 ; +wire \Kp_Out[5]~31_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT5 ; +wire \Kp_Out[5]~32 ; +wire \Kp_Out[6]~33_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT6 ; +wire \Kp_Out[6]~34 ; +wire \Kp_Out[7]~35_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT7 ; +wire \Kp_Out[7]~36 ; +wire \Kp_Out[8]~37_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT8 ; +wire \Kp_Out[8]~38 ; +wire \Kp_Out[9]~39_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT9 ; +wire \Kp_Out[9]~40 ; +wire \Kp_Out[10]~41_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT10 ; +wire \Kp_Out[10]~42 ; +wire \Kp_Out[11]~43_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT11 ; +wire \Kp_Out[11]~44 ; +wire \Kp_Out[12]~45_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT12 ; +wire \Kp_Out[12]~46 ; +wire \Kp_Out[13]~47_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT13 ; +wire \Kp_Out[13]~48 ; +wire \Kp_Out[14]~49_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT14 ; +wire \Kp_Out[14]~50 ; +wire \Kp_Out[15]~51_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT15 ; +wire \Kp_Out[15]~52 ; +wire \Kp_Out[16]~53_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT16 ; +wire \Kp_Out[16]~54 ; +wire \Kp_Out[17]~55_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT17 ; +wire \Kp_Out[17]~56 ; +wire \Kp_Out[18]~57_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT18 ; +wire \Kp_Out[18]~58 ; +wire \Kp_Out[19]~59_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT19 ; +wire \Kp_Out[19]~60 ; +wire \Kp_Out[20]~61_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT20 ; +wire \Add5~1 ; +wire \Add5~3 ; +wire \Add5~5 ; +wire \Add5~7 ; +wire \Add5~9 ; +wire \Add5~11 ; +wire \Add5~13 ; +wire \Add5~15 ; +wire \Add5~25 ; +wire \Add5~28 ; +wire \Add5~31 ; +wire \Add5~34 ; +wire \Add5~37 ; +wire \Add5~40 ; +wire \Add5~43 ; +wire \Add5~46 ; +wire \Add5~49 ; +wire \Add5~52 ; +wire \Add5~55 ; +wire \Add5~58 ; +wire \Add5~60_combout ; +wire \Add5~62_combout ; +wire \Add7~19_combout ; +wire \Add7~18_combout ; +wire \Add7~17_combout ; +wire \Add7~16_combout ; +wire \Add5~48_combout ; +wire \Add7~15_combout ; +wire \Add7~14_combout ; +wire \Add7~13_combout ; +wire \Add7~12_combout ; +wire \Add7~11_combout ; +wire \Add5~30_combout ; +wire \Add7~10_combout ; +wire \Add7~9_combout ; +wire \Add7~8_combout ; +wire \Add5~14_combout ; +wire \Add5~16_combout ; +wire \Add7~1_combout ; +wire \Add5~12_combout ; +wire \Add5~17_combout ; +wire \Add7~2_combout ; +wire \Add5~10_combout ; +wire \Add5~18_combout ; +wire \Add7~3_combout ; +wire \Add5~8_combout ; +wire \Add5~19_combout ; +wire \Add5~6_combout ; +wire \Add5~20_combout ; +wire \Add7~4_combout ; +wire \Add7~5_combout ; +wire \Add5~4_combout ; +wire \Add5~21_combout ; +wire \Add7~6_combout ; +wire \Add5~2_combout ; +wire \Add5~22_combout ; +wire \Add5~0_combout ; +wire \Add5~23_combout ; +wire \Add7~7_combout ; +wire \Vout[0]~15_cout ; +wire \Vout[0]~17_cout ; +wire \Vout[0]~19_cout ; +wire \Vout[0]~21_cout ; +wire \Vout[0]~23_cout ; +wire \Vout[0]~25_cout ; +wire \Vout[0]~27_cout ; +wire \Vout[0]~29 ; +wire \Vout[1]~30_combout ; +wire \Vout[1]~reg0_q ; +wire \Add5~24_combout ; +wire \Add5~26_combout ; +wire \Vout[1]~31 ; +wire \Vout[2]~32_combout ; +wire \Vout[2]~reg0_q ; +wire \Add5~27_combout ; +wire \Add5~29_combout ; +wire \Vout[2]~33 ; +wire \Vout[3]~34_combout ; +wire \Vout[3]~reg0_q ; +wire \Add5~32_combout ; +wire \Vout[3]~35 ; +wire \Vout[4]~36_combout ; +wire \Vout[4]~reg0_q ; +wire \Add5~33_combout ; +wire \Add5~35_combout ; +wire \Vout[4]~37 ; +wire \Vout[5]~38_combout ; +wire \Vout[5]~reg0_q ; +wire \Add5~36_combout ; +wire \Add5~38_combout ; +wire \Vout[5]~39 ; +wire \Vout[6]~40_combout ; +wire \Vout[6]~reg0_q ; +wire \Add5~39_combout ; +wire \Add5~41_combout ; +wire \Vout[6]~41 ; +wire \Vout[7]~42_combout ; +wire \Vout[7]~reg0_q ; +wire \Add5~42_combout ; +wire \Add5~44_combout ; +wire \Vout[7]~43 ; +wire \Vout[8]~44_combout ; +wire \Vout[8]~reg0_q ; +wire \Add5~45_combout ; +wire \Add5~47_combout ; +wire \Vout[8]~45 ; +wire \Vout[9]~46_combout ; +wire \Vout[9]~reg0_q ; +wire \Add5~50_combout ; +wire \Vout[9]~47 ; +wire \Vout[10]~48_combout ; +wire \Vout[10]~reg0_q ; +wire \Add5~51_combout ; +wire \Add5~53_combout ; +wire \Vout[10]~49 ; +wire \Vout[11]~50_combout ; +wire \Vout[11]~reg0_q ; +wire \Add5~54_combout ; +wire \Add5~56_combout ; +wire \Vout[11]~51 ; +wire \Vout[12]~52_combout ; +wire \Vout[12]~reg0_q ; +wire \Add5~57_combout ; +wire \Add5~59_combout ; +wire \Vout[12]~53 ; +wire \Vout[13]~54_combout ; +wire \Vout[13]~reg0_q ; +wire \Add7~0_combout ; +wire \Vout[0]~28_combout ; +wire \Vout[0]~reg0_q ; +wire [21:0] Kd_Out; +wire [21:0] Ki_Out; +wire [21:0] Kp_Out; +wire [13:0] EE2; +wire [13:0] EE1; +wire [10:0] period; + +wire [35:0] \Mult2|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult1|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult0|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult2|auto_generated|mac_mult1_DATAOUT_bus ; +wire [35:0] \Mult1|auto_generated|mac_mult1_DATAOUT_bus ; +wire [35:0] \Mult0|auto_generated|mac_mult1_DATAOUT_bus ; + +assign \Mult2|auto_generated|mac_out2~0 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult2|auto_generated|mac_out2~1 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult2|auto_generated|mac_out2~2 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult2|auto_generated|mac_out2~3 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult2|auto_generated|mac_out2~4 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult2|auto_generated|mac_out2~5 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult2|auto_generated|mac_out2~6 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult2|auto_generated|mac_out2~7 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult2|auto_generated|mac_out2~8 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult2|auto_generated|mac_out2~9 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult2|auto_generated|mac_out2~10 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult2|auto_generated|mac_out2~11 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult2|auto_generated|mac_out2~12 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult2|auto_generated|mac_out2~13 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult2|auto_generated|mac_out2~14 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult2|auto_generated|mac_out2~15 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult2|auto_generated|mac_out2~dataout = \Mult2|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult2|auto_generated|mac_out2~DATAOUT1 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult2|auto_generated|mac_out2~DATAOUT2 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult2|auto_generated|mac_out2~DATAOUT3 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult2|auto_generated|mac_out2~DATAOUT4 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult2|auto_generated|mac_out2~DATAOUT5 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult2|auto_generated|mac_out2~DATAOUT6 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult2|auto_generated|mac_out2~DATAOUT7 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult2|auto_generated|mac_out2~DATAOUT8 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult2|auto_generated|mac_out2~DATAOUT9 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult2|auto_generated|mac_out2~DATAOUT10 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult2|auto_generated|mac_out2~DATAOUT11 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult2|auto_generated|mac_out2~DATAOUT12 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult2|auto_generated|mac_out2~DATAOUT13 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult2|auto_generated|mac_out2~DATAOUT14 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult2|auto_generated|mac_out2~DATAOUT15 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult2|auto_generated|mac_out2~DATAOUT16 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult2|auto_generated|mac_out2~DATAOUT17 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult2|auto_generated|mac_out2~DATAOUT18 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult2|auto_generated|mac_out2~DATAOUT19 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult1|auto_generated|mac_out2~0 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult1|auto_generated|mac_out2~1 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult1|auto_generated|mac_out2~2 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult1|auto_generated|mac_out2~3 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult1|auto_generated|mac_out2~4 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult1|auto_generated|mac_out2~5 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult1|auto_generated|mac_out2~6 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult1|auto_generated|mac_out2~7 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult1|auto_generated|mac_out2~8 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult1|auto_generated|mac_out2~9 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult1|auto_generated|mac_out2~10 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult1|auto_generated|mac_out2~11 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult1|auto_generated|mac_out2~12 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult1|auto_generated|mac_out2~13 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult1|auto_generated|mac_out2~14 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult1|auto_generated|mac_out2~15 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult1|auto_generated|mac_out2~dataout = \Mult1|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult1|auto_generated|mac_out2~DATAOUT1 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult1|auto_generated|mac_out2~DATAOUT2 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult1|auto_generated|mac_out2~DATAOUT3 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult1|auto_generated|mac_out2~DATAOUT4 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult1|auto_generated|mac_out2~DATAOUT5 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult1|auto_generated|mac_out2~DATAOUT6 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult1|auto_generated|mac_out2~DATAOUT7 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult1|auto_generated|mac_out2~DATAOUT8 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult1|auto_generated|mac_out2~DATAOUT9 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult1|auto_generated|mac_out2~DATAOUT10 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult1|auto_generated|mac_out2~DATAOUT11 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult1|auto_generated|mac_out2~DATAOUT12 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult1|auto_generated|mac_out2~DATAOUT13 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult1|auto_generated|mac_out2~DATAOUT14 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult1|auto_generated|mac_out2~DATAOUT15 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult1|auto_generated|mac_out2~DATAOUT16 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult1|auto_generated|mac_out2~DATAOUT17 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult1|auto_generated|mac_out2~DATAOUT18 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult1|auto_generated|mac_out2~DATAOUT19 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult0|auto_generated|mac_out2~0 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult0|auto_generated|mac_out2~1 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult0|auto_generated|mac_out2~2 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult0|auto_generated|mac_out2~3 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult0|auto_generated|mac_out2~4 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult0|auto_generated|mac_out2~5 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult0|auto_generated|mac_out2~6 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult0|auto_generated|mac_out2~7 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult0|auto_generated|mac_out2~8 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult0|auto_generated|mac_out2~9 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult0|auto_generated|mac_out2~10 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult0|auto_generated|mac_out2~11 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult0|auto_generated|mac_out2~12 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult0|auto_generated|mac_out2~13 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult0|auto_generated|mac_out2~dataout = \Mult0|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult0|auto_generated|mac_out2~DATAOUT1 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult0|auto_generated|mac_out2~DATAOUT2 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult0|auto_generated|mac_out2~DATAOUT3 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult0|auto_generated|mac_out2~DATAOUT4 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult0|auto_generated|mac_out2~DATAOUT5 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult0|auto_generated|mac_out2~DATAOUT6 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult0|auto_generated|mac_out2~DATAOUT7 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult0|auto_generated|mac_out2~DATAOUT8 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult0|auto_generated|mac_out2~DATAOUT9 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult0|auto_generated|mac_out2~DATAOUT10 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult0|auto_generated|mac_out2~DATAOUT11 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult0|auto_generated|mac_out2~DATAOUT12 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult0|auto_generated|mac_out2~DATAOUT13 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult0|auto_generated|mac_out2~DATAOUT14 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult0|auto_generated|mac_out2~DATAOUT15 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult0|auto_generated|mac_out2~DATAOUT16 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult0|auto_generated|mac_out2~DATAOUT17 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult0|auto_generated|mac_out2~DATAOUT18 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult0|auto_generated|mac_out2~DATAOUT19 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult0|auto_generated|mac_out2~DATAOUT20 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult0|auto_generated|mac_out2~DATAOUT21 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult2|auto_generated|mac_mult1~0 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult2|auto_generated|mac_mult1~1 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult2|auto_generated|mac_mult1~2 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult2|auto_generated|mac_mult1~3 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult2|auto_generated|mac_mult1~4 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult2|auto_generated|mac_mult1~5 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult2|auto_generated|mac_mult1~6 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult2|auto_generated|mac_mult1~7 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult2|auto_generated|mac_mult1~8 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult2|auto_generated|mac_mult1~9 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult2|auto_generated|mac_mult1~10 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult2|auto_generated|mac_mult1~11 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult2|auto_generated|mac_mult1~12 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult2|auto_generated|mac_mult1~13 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult2|auto_generated|mac_mult1~14 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult2|auto_generated|mac_mult1~15 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult2|auto_generated|mac_mult1~dataout = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT1 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT2 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT3 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT4 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT5 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT6 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT7 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT8 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT9 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT10 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT11 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT12 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT13 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT14 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT15 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT16 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT17 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT18 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT19 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [35]; + +assign \Mult1|auto_generated|mac_mult1~0 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult1|auto_generated|mac_mult1~1 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult1|auto_generated|mac_mult1~2 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult1|auto_generated|mac_mult1~3 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult1|auto_generated|mac_mult1~4 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult1|auto_generated|mac_mult1~5 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult1|auto_generated|mac_mult1~6 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult1|auto_generated|mac_mult1~7 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult1|auto_generated|mac_mult1~8 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult1|auto_generated|mac_mult1~9 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult1|auto_generated|mac_mult1~10 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult1|auto_generated|mac_mult1~11 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult1|auto_generated|mac_mult1~12 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult1|auto_generated|mac_mult1~13 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult1|auto_generated|mac_mult1~14 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult1|auto_generated|mac_mult1~15 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult1|auto_generated|mac_mult1~dataout = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT1 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT2 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT3 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT4 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT5 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT6 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT7 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT8 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT9 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT10 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT11 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT12 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT13 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT14 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT15 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT16 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT17 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT18 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT19 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [35]; + +assign \Mult0|auto_generated|mac_mult1~0 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult0|auto_generated|mac_mult1~1 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult0|auto_generated|mac_mult1~2 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult0|auto_generated|mac_mult1~3 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult0|auto_generated|mac_mult1~4 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult0|auto_generated|mac_mult1~5 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult0|auto_generated|mac_mult1~6 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult0|auto_generated|mac_mult1~7 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult0|auto_generated|mac_mult1~8 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult0|auto_generated|mac_mult1~9 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult0|auto_generated|mac_mult1~10 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult0|auto_generated|mac_mult1~11 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult0|auto_generated|mac_mult1~12 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult0|auto_generated|mac_mult1~13 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult0|auto_generated|mac_mult1~dataout = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT1 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT2 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT3 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT4 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT5 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT6 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT7 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT8 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT9 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT10 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT11 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT12 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT13 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT14 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT15 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT16 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT17 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT18 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT19 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT20 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT21 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [35]; + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: IOOBUF_X7_Y24_N16 +cycloneive_io_obuf \Vout[0]~output ( + .i(\Vout[0]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[0]~output .bus_hold = "false"; +defparam \Vout[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N9 +cycloneive_io_obuf \Vout[1]~output ( + .i(\Vout[1]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[1]~output .bus_hold = "false"; +defparam \Vout[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N23 +cycloneive_io_obuf \Vout[2]~output ( + .i(\Vout[2]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[2]~output .bus_hold = "false"; +defparam \Vout[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N16 +cycloneive_io_obuf \Vout[3]~output ( + .i(\Vout[3]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[3]~output .bus_hold = "false"; +defparam \Vout[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N2 +cycloneive_io_obuf \Vout[4]~output ( + .i(\Vout[4]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[4]~output .bus_hold = "false"; +defparam \Vout[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y24_N2 +cycloneive_io_obuf \Vout[5]~output ( + .i(\Vout[5]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[5]~output .bus_hold = "false"; +defparam \Vout[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N16 +cycloneive_io_obuf \Vout[6]~output ( + .i(\Vout[6]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[6]~output .bus_hold = "false"; +defparam \Vout[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y24_N16 +cycloneive_io_obuf \Vout[7]~output ( + .i(\Vout[7]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[7]~output .bus_hold = "false"; +defparam \Vout[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N2 +cycloneive_io_obuf \Vout[8]~output ( + .i(\Vout[8]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[8]~output .bus_hold = "false"; +defparam \Vout[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N2 +cycloneive_io_obuf \Vout[9]~output ( + .i(\Vout[9]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[9]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[9]~output .bus_hold = "false"; +defparam \Vout[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N23 +cycloneive_io_obuf \Vout[10]~output ( + .i(\Vout[10]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[10]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[10]~output .bus_hold = "false"; +defparam \Vout[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y19_N16 +cycloneive_io_obuf \Vout[11]~output ( + .i(\Vout[11]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[11]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[11]~output .bus_hold = "false"; +defparam \Vout[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y24_N9 +cycloneive_io_obuf \Vout[12]~output ( + .i(\Vout[12]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[12]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[12]~output .bus_hold = "false"; +defparam \Vout[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N9 +cycloneive_io_obuf \Vout[13]~output ( + .i(\Vout[13]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[13]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[13]~output .bus_hold = "false"; +defparam \Vout[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk~inputclkctrl .clock_type = "global clock"; +defparam \clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N12 +cycloneive_lcell_comb \Kd_Out[0]~21 ( +// Equation(s): +// \Kd_Out[0]~21_combout = Kd_Out[0] $ (GND) +// \Kd_Out[0]~22 = CARRY(!Kd_Out[0]) + + .dataa(Kd_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Kd_Out[0]~21_combout ), + .cout(\Kd_Out[0]~22 )); +// synopsys translate_off +defparam \Kd_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Kd_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 +cycloneive_lcell_comb \EE2[0]~14 ( +// Equation(s): +// \EE2[0]~14_combout = EE2[0] $ (GND) +// \EE2[0]~15 = CARRY(!EE2[0]) + + .dataa(gnd), + .datab(EE2[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\EE2[0]~14_combout ), + .cout(\EE2[0]~15 )); +// synopsys translate_off +defparam \EE2[0]~14 .lut_mask = 16'hCC33; +defparam \EE2[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N2 +cycloneive_lcell_comb \EE1[0]~14 ( +// Equation(s): +// \EE1[0]~14_combout = EE1[0] $ (GND) +// \EE1[0]~15 = CARRY(!EE1[0]) + + .dataa(gnd), + .datab(EE1[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\EE1[0]~14_combout ), + .cout(\EE1[0]~15 )); +// synopsys translate_off +defparam \EE1[0]~14 .lut_mask = 16'hCC33; +defparam \EE1[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y0_N1 +cycloneive_io_ibuf \SetPoint[0]~input ( + .i(SetPoint[0]), + .ibar(gnd), + .o(\SetPoint[0]~input_o )); +// synopsys translate_off +defparam \SetPoint[0]~input .bus_hold = "false"; +defparam \SetPoint[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N8 +cycloneive_io_ibuf \Sample[13]~input ( + .i(Sample[13]), + .ibar(gnd), + .o(\Sample[13]~input_o )); +// synopsys translate_off +defparam \Sample[13]~input .bus_hold = "false"; +defparam \Sample[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N2 +cycloneive_lcell_comb \Add1~1 ( +// Equation(s): +// \Add1~1_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[13]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[13]~input_o ), + .cin(gnd), + .combout(\Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~1 .lut_mask = 16'hFFF0; +defparam \Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N22 +cycloneive_io_ibuf \SetPoint[13]~input ( + .i(SetPoint[13]), + .ibar(gnd), + .o(\SetPoint[13]~input_o )); +// synopsys translate_off +defparam \SetPoint[13]~input .bus_hold = "false"; +defparam \SetPoint[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N0 +cycloneive_lcell_comb \Add1~0 ( +// Equation(s): +// \Add1~0_combout = (!\EE0[13]~_Duplicate_1_q & \SetPoint[13]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\SetPoint[13]~input_o ), + .cin(gnd), + .combout(\Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~0 .lut_mask = 16'h0F00; +defparam \Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N1 +cycloneive_io_ibuf \Sample[12]~input ( + .i(Sample[12]), + .ibar(gnd), + .o(\Sample[12]~input_o )); +// synopsys translate_off +defparam \Sample[12]~input .bus_hold = "false"; +defparam \Sample[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N8 +cycloneive_lcell_comb \Add1~2 ( +// Equation(s): +// \Add1~2_combout = (\Sample[12]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[12]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~2_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~2 .lut_mask = 16'hFFF0; +defparam \Add1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N8 +cycloneive_io_ibuf \SetPoint[12]~input ( + .i(SetPoint[12]), + .ibar(gnd), + .o(\SetPoint[12]~input_o )); +// synopsys translate_off +defparam \SetPoint[12]~input .bus_hold = "false"; +defparam \SetPoint[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N22 +cycloneive_io_ibuf \Sample[11]~input ( + .i(Sample[11]), + .ibar(gnd), + .o(\Sample[11]~input_o )); +// synopsys translate_off +defparam \Sample[11]~input .bus_hold = "false"; +defparam \Sample[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N24 +cycloneive_lcell_comb \Add1~4 ( +// Equation(s): +// \Add1~4_combout = (\Sample[11]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(\Sample[11]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(gnd), + .cin(gnd), + .combout(\Add1~4_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~4 .lut_mask = 16'hFAFA; +defparam \Add1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N8 +cycloneive_io_ibuf \SetPoint[11]~input ( + .i(SetPoint[11]), + .ibar(gnd), + .o(\SetPoint[11]~input_o )); +// synopsys translate_off +defparam \SetPoint[11]~input .bus_hold = "false"; +defparam \SetPoint[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N1 +cycloneive_io_ibuf \SetPoint[10]~input ( + .i(SetPoint[10]), + .ibar(gnd), + .o(\SetPoint[10]~input_o )); +// synopsys translate_off +defparam \SetPoint[10]~input .bus_hold = "false"; +defparam \SetPoint[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N1 +cycloneive_io_ibuf \Sample[10]~input ( + .i(Sample[10]), + .ibar(gnd), + .o(\Sample[10]~input_o )); +// synopsys translate_off +defparam \Sample[10]~input .bus_hold = "false"; +defparam \Sample[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N10 +cycloneive_lcell_comb \Add1~6 ( +// Equation(s): +// \Add1~6_combout = (\Sample[10]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[10]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~6 .lut_mask = 16'hFFF0; +defparam \Add1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N8 +cycloneive_io_ibuf \Sample[9]~input ( + .i(Sample[9]), + .ibar(gnd), + .o(\Sample[9]~input_o )); +// synopsys translate_off +defparam \Sample[9]~input .bus_hold = "false"; +defparam \Sample[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N18 +cycloneive_lcell_comb \Add1~8 ( +// Equation(s): +// \Add1~8_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[9]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[9]~input_o ), + .cin(gnd), + .combout(\Add1~8_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~8 .lut_mask = 16'hFFF0; +defparam \Add1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N15 +cycloneive_io_ibuf \SetPoint[9]~input ( + .i(SetPoint[9]), + .ibar(gnd), + .o(\SetPoint[9]~input_o )); +// synopsys translate_off +defparam \SetPoint[9]~input .bus_hold = "false"; +defparam \SetPoint[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N22 +cycloneive_io_ibuf \SetPoint[8]~input ( + .i(SetPoint[8]), + .ibar(gnd), + .o(\SetPoint[8]~input_o )); +// synopsys translate_off +defparam \SetPoint[8]~input .bus_hold = "false"; +defparam \SetPoint[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N1 +cycloneive_io_ibuf \Sample[8]~input ( + .i(Sample[8]), + .ibar(gnd), + .o(\Sample[8]~input_o )); +// synopsys translate_off +defparam \Sample[8]~input .bus_hold = "false"; +defparam \Sample[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N20 +cycloneive_lcell_comb \Add1~10 ( +// Equation(s): +// \Add1~10_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[8]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[8]~input_o ), + .cin(gnd), + .combout(\Add1~10_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~10 .lut_mask = 16'hFFF0; +defparam \Add1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N15 +cycloneive_io_ibuf \Sample[7]~input ( + .i(Sample[7]), + .ibar(gnd), + .o(\Sample[7]~input_o )); +// synopsys translate_off +defparam \Sample[7]~input .bus_hold = "false"; +defparam \Sample[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N6 +cycloneive_lcell_comb \Add1~12 ( +// Equation(s): +// \Add1~12_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[7]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[7]~input_o ), + .cin(gnd), + .combout(\Add1~12_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~12 .lut_mask = 16'hFFF0; +defparam \Add1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N8 +cycloneive_io_ibuf \SetPoint[7]~input ( + .i(SetPoint[7]), + .ibar(gnd), + .o(\SetPoint[7]~input_o )); +// synopsys translate_off +defparam \SetPoint[7]~input .bus_hold = "false"; +defparam \SetPoint[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N15 +cycloneive_io_ibuf \SetPoint[6]~input ( + .i(SetPoint[6]), + .ibar(gnd), + .o(\SetPoint[6]~input_o )); +// synopsys translate_off +defparam \SetPoint[6]~input .bus_hold = "false"; +defparam \SetPoint[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N15 +cycloneive_io_ibuf \Sample[6]~input ( + .i(Sample[6]), + .ibar(gnd), + .o(\Sample[6]~input_o )); +// synopsys translate_off +defparam \Sample[6]~input .bus_hold = "false"; +defparam \Sample[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N22 +cycloneive_lcell_comb \Add1~14 ( +// Equation(s): +// \Add1~14_combout = (\Sample[6]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\Sample[6]~input_o ), + .datac(gnd), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~14_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~14 .lut_mask = 16'hFFCC; +defparam \Add1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N22 +cycloneive_io_ibuf \Sample[5]~input ( + .i(Sample[5]), + .ibar(gnd), + .o(\Sample[5]~input_o )); +// synopsys translate_off +defparam \Sample[5]~input .bus_hold = "false"; +defparam \Sample[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N12 +cycloneive_lcell_comb \Add1~16 ( +// Equation(s): +// \Add1~16_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[5]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[5]~input_o ), + .cin(gnd), + .combout(\Add1~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~16 .lut_mask = 16'hFFF0; +defparam \Add1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N15 +cycloneive_io_ibuf \SetPoint[4]~input ( + .i(SetPoint[4]), + .ibar(gnd), + .o(\SetPoint[4]~input_o )); +// synopsys translate_off +defparam \SetPoint[4]~input .bus_hold = "false"; +defparam \SetPoint[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N15 +cycloneive_io_ibuf \Sample[4]~input ( + .i(Sample[4]), + .ibar(gnd), + .o(\Sample[4]~input_o )); +// synopsys translate_off +defparam \Sample[4]~input .bus_hold = "false"; +defparam \Sample[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N16 +cycloneive_lcell_comb \Add1~18 ( +// Equation(s): +// \Add1~18_combout = (\Sample[4]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\Sample[4]~input_o ), + .datac(gnd), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~18 .lut_mask = 16'hFFCC; +defparam \Add1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N22 +cycloneive_io_ibuf \Sample[3]~input ( + .i(Sample[3]), + .ibar(gnd), + .o(\Sample[3]~input_o )); +// synopsys translate_off +defparam \Sample[3]~input .bus_hold = "false"; +defparam \Sample[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N6 +cycloneive_lcell_comb \Add1~20 ( +// Equation(s): +// \Add1~20_combout = (\Sample[3]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[3]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~20 .lut_mask = 16'hFFF0; +defparam \Add1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N1 +cycloneive_io_ibuf \SetPoint[2]~input ( + .i(SetPoint[2]), + .ibar(gnd), + .o(\SetPoint[2]~input_o )); +// synopsys translate_off +defparam \SetPoint[2]~input .bus_hold = "false"; +defparam \SetPoint[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N22 +cycloneive_io_ibuf \Sample[2]~input ( + .i(Sample[2]), + .ibar(gnd), + .o(\Sample[2]~input_o )); +// synopsys translate_off +defparam \Sample[2]~input .bus_hold = "false"; +defparam \Sample[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N14 +cycloneive_lcell_comb \Add1~22 ( +// Equation(s): +// \Add1~22_combout = (\Sample[2]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[2]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~22_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~22 .lut_mask = 16'hFFF0; +defparam \Add1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N8 +cycloneive_io_ibuf \Sample[1]~input ( + .i(Sample[1]), + .ibar(gnd), + .o(\Sample[1]~input_o )); +// synopsys translate_off +defparam \Sample[1]~input .bus_hold = "false"; +defparam \Sample[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N4 +cycloneive_lcell_comb \Add1~24 ( +// Equation(s): +// \Add1~24_combout = (\Sample[1]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[1]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~24_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~24 .lut_mask = 16'hFFF0; +defparam \Add1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N1 +cycloneive_io_ibuf \SetPoint[1]~input ( + .i(SetPoint[1]), + .ibar(gnd), + .o(\SetPoint[1]~input_o )); +// synopsys translate_off +defparam \SetPoint[1]~input .bus_hold = "false"; +defparam \SetPoint[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \Sample[0]~input ( + .i(Sample[0]), + .ibar(gnd), + .o(\Sample[0]~input_o )); +// synopsys translate_off +defparam \Sample[0]~input .bus_hold = "false"; +defparam \Sample[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N12 +cycloneive_lcell_comb \Add1~26 ( +// Equation(s): +// \Add1~26_combout = (\EE0[13]~_Duplicate_1_q ) # (!\Sample[0]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[0]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~26_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~26 .lut_mask = 16'hFF0F; +defparam \Add1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N0 +cycloneive_lcell_comb \EE0[0]~15 ( +// Equation(s): +// \EE0[0]~15_cout = CARRY(!\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\EE0[0]~15_cout )); +// synopsys translate_off +defparam \EE0[0]~15 .lut_mask = 16'h0033; +defparam \EE0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N2 +cycloneive_lcell_comb \EE0[0]~16 ( +// Equation(s): +// \EE0[0]~16_combout = (\Add1~27_combout & ((\Add1~26_combout & (\EE0[0]~15_cout & VCC)) # (!\Add1~26_combout & (!\EE0[0]~15_cout )))) # (!\Add1~27_combout & ((\Add1~26_combout & (!\EE0[0]~15_cout )) # (!\Add1~26_combout & ((\EE0[0]~15_cout ) # +// (GND))))) +// \EE0[0]~17 = CARRY((\Add1~27_combout & (!\Add1~26_combout & !\EE0[0]~15_cout )) # (!\Add1~27_combout & ((!\EE0[0]~15_cout ) # (!\Add1~26_combout )))) + + .dataa(\Add1~27_combout ), + .datab(\Add1~26_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[0]~15_cout ), + .combout(\EE0[0]~16_combout ), + .cout(\EE0[0]~17 )); +// synopsys translate_off +defparam \EE0[0]~16 .lut_mask = 16'h9617; +defparam \EE0[0]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N4 +cycloneive_lcell_comb \EE0[1]~18 ( +// Equation(s): +// \EE0[1]~18_combout = ((\Add1~24_combout $ (\Add1~25_combout $ (\EE0[0]~17 )))) # (GND) +// \EE0[1]~19 = CARRY((\Add1~24_combout & (\Add1~25_combout & !\EE0[0]~17 )) # (!\Add1~24_combout & ((\Add1~25_combout ) # (!\EE0[0]~17 )))) + + .dataa(\Add1~24_combout ), + .datab(\Add1~25_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[0]~17 ), + .combout(\EE0[1]~18_combout ), + .cout(\EE0[1]~19 )); +// synopsys translate_off +defparam \EE0[1]~18 .lut_mask = 16'h964D; +defparam \EE0[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \Add0~0 ( +// Equation(s): +// \Add0~0_combout = period[0] $ (VCC) +// \Add0~1 = CARRY(period[0]) + + .dataa(gnd), + .datab(period[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add0~0_combout ), + .cout(\Add0~1 )); +// synopsys translate_off +defparam \Add0~0 .lut_mask = 16'h33CC; +defparam \Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N6 +cycloneive_lcell_comb \period~3 ( +// Equation(s): +// \period~3_combout = (\Add0~0_combout & (((!\Equal0~2_combout ) # (!\Equal0~0_combout )) # (!\Equal0~1_combout ))) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~0_combout ), + .datac(\Add0~0_combout ), + .datad(\Equal0~2_combout ), + .cin(gnd), + .combout(\period~3_combout ), + .cout()); +// synopsys translate_off +defparam \period~3 .lut_mask = 16'h70F0; +defparam \period~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y13_N7 +dffeas \period[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~3_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[0]), + .prn(vcc)); +// synopsys translate_off +defparam \period[0] .is_wysiwyg = "true"; +defparam \period[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \Add0~2 ( +// Equation(s): +// \Add0~2_combout = (period[1] & (!\Add0~1 )) # (!period[1] & ((\Add0~1 ) # (GND))) +// \Add0~3 = CARRY((!\Add0~1 ) # (!period[1])) + + .dataa(period[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~1 ), + .combout(\Add0~2_combout ), + .cout(\Add0~3 )); +// synopsys translate_off +defparam \Add0~2 .lut_mask = 16'h5A5F; +defparam \Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N7 +dffeas \period[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~2_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[1]), + .prn(vcc)); +// synopsys translate_off +defparam \period[1] .is_wysiwyg = "true"; +defparam \period[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N8 +cycloneive_lcell_comb \Add0~4 ( +// Equation(s): +// \Add0~4_combout = (period[2] & (\Add0~3 $ (GND))) # (!period[2] & (!\Add0~3 & VCC)) +// \Add0~5 = CARRY((period[2] & !\Add0~3 )) + + .dataa(gnd), + .datab(period[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~3 ), + .combout(\Add0~4_combout ), + .cout(\Add0~5 )); +// synopsys translate_off +defparam \Add0~4 .lut_mask = 16'hC30C; +defparam \Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N9 +dffeas \period[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~4_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[2]), + .prn(vcc)); +// synopsys translate_off +defparam \period[2] .is_wysiwyg = "true"; +defparam \period[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N16 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!period[0] & (!period[2] & !period[1])) + + .dataa(period[0]), + .datab(gnd), + .datac(period[2]), + .datad(period[1]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0005; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \Add0~6 ( +// Equation(s): +// \Add0~6_combout = (period[3] & (!\Add0~5 )) # (!period[3] & ((\Add0~5 ) # (GND))) +// \Add0~7 = CARRY((!\Add0~5 ) # (!period[3])) + + .dataa(gnd), + .datab(period[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~5 ), + .combout(\Add0~6_combout ), + .cout(\Add0~7 )); +// synopsys translate_off +defparam \Add0~6 .lut_mask = 16'h3C3F; +defparam \Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N0 +cycloneive_lcell_comb \period~2 ( +// Equation(s): +// \period~2_combout = (\Add0~6_combout & (((!\Equal0~0_combout ) # (!\Equal0~1_combout )) # (!\Equal0~2_combout ))) + + .dataa(\Equal0~2_combout ), + .datab(\Equal0~1_combout ), + .datac(\Equal0~0_combout ), + .datad(\Add0~6_combout ), + .cin(gnd), + .combout(\period~2_combout ), + .cout()); +// synopsys translate_off +defparam \period~2 .lut_mask = 16'h7F00; +defparam \period~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N1 +dffeas \period[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~2_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[3]), + .prn(vcc)); +// synopsys translate_off +defparam \period[3] .is_wysiwyg = "true"; +defparam \period[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \Add0~8 ( +// Equation(s): +// \Add0~8_combout = (period[4] & (\Add0~7 $ (GND))) # (!period[4] & (!\Add0~7 & VCC)) +// \Add0~9 = CARRY((period[4] & !\Add0~7 )) + + .dataa(period[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~7 ), + .combout(\Add0~8_combout ), + .cout(\Add0~9 )); +// synopsys translate_off +defparam \Add0~8 .lut_mask = 16'hA50A; +defparam \Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N13 +dffeas \period[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~8_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[4]), + .prn(vcc)); +// synopsys translate_off +defparam \period[4] .is_wysiwyg = "true"; +defparam \period[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N14 +cycloneive_lcell_comb \Add0~10 ( +// Equation(s): +// \Add0~10_combout = (period[5] & (!\Add0~9 )) # (!period[5] & ((\Add0~9 ) # (GND))) +// \Add0~11 = CARRY((!\Add0~9 ) # (!period[5])) + + .dataa(gnd), + .datab(period[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~9 ), + .combout(\Add0~10_combout ), + .cout(\Add0~11 )); +// synopsys translate_off +defparam \Add0~10 .lut_mask = 16'h3C3F; +defparam \Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N15 +dffeas \period[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~10_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[5]), + .prn(vcc)); +// synopsys translate_off +defparam \period[5] .is_wysiwyg = "true"; +defparam \period[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \Add0~12 ( +// Equation(s): +// \Add0~12_combout = (period[6] & (\Add0~11 $ (GND))) # (!period[6] & (!\Add0~11 & VCC)) +// \Add0~13 = CARRY((period[6] & !\Add0~11 )) + + .dataa(period[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~11 ), + .combout(\Add0~12_combout ), + .cout(\Add0~13 )); +// synopsys translate_off +defparam \Add0~12 .lut_mask = 16'hA50A; +defparam \Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \Add0~14 ( +// Equation(s): +// \Add0~14_combout = (period[7] & (!\Add0~13 )) # (!period[7] & ((\Add0~13 ) # (GND))) +// \Add0~15 = CARRY((!\Add0~13 ) # (!period[7])) + + .dataa(gnd), + .datab(period[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~13 ), + .combout(\Add0~14_combout ), + .cout(\Add0~15 )); +// synopsys translate_off +defparam \Add0~14 .lut_mask = 16'h3C3F; +defparam \Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \period~0 ( +// Equation(s): +// \period~0_combout = (\Add0~14_combout & (((!\Equal0~1_combout ) # (!\Equal0~2_combout )) # (!\Equal0~0_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Add0~14_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\period~0_combout ), + .cout()); +// synopsys translate_off +defparam \period~0 .lut_mask = 16'h4CCC; +defparam \period~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N29 +dffeas \period[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~0_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[7]), + .prn(vcc)); +// synopsys translate_off +defparam \period[7] .is_wysiwyg = "true"; +defparam \period[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N20 +cycloneive_lcell_comb \Add0~16 ( +// Equation(s): +// \Add0~16_combout = (period[8] & (\Add0~15 $ (GND))) # (!period[8] & (!\Add0~15 & VCC)) +// \Add0~17 = CARRY((period[8] & !\Add0~15 )) + + .dataa(gnd), + .datab(period[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~15 ), + .combout(\Add0~16_combout ), + .cout(\Add0~17 )); +// synopsys translate_off +defparam \Add0~16 .lut_mask = 16'hC30C; +defparam \Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N21 +dffeas \period[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~16_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[8]), + .prn(vcc)); +// synopsys translate_off +defparam \period[8] .is_wysiwyg = "true"; +defparam \period[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \Add0~18 ( +// Equation(s): +// \Add0~18_combout = (period[9] & (!\Add0~17 )) # (!period[9] & ((\Add0~17 ) # (GND))) +// \Add0~19 = CARRY((!\Add0~17 ) # (!period[9])) + + .dataa(period[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~17 ), + .combout(\Add0~18_combout ), + .cout(\Add0~19 )); +// synopsys translate_off +defparam \Add0~18 .lut_mask = 16'h5A5F; +defparam \Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N23 +dffeas \period[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~18_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[9]), + .prn(vcc)); +// synopsys translate_off +defparam \period[9] .is_wysiwyg = "true"; +defparam \period[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \Add0~20 ( +// Equation(s): +// \Add0~20_combout = \Add0~19 $ (!period[10]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(period[10]), + .cin(\Add0~19 ), + .combout(\Add0~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add0~20 .lut_mask = 16'hF00F; +defparam \Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N25 +dffeas \period[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~20_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[10]), + .prn(vcc)); +// synopsys translate_off +defparam \period[10] .is_wysiwyg = "true"; +defparam \period[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!period[10] & (!period[8] & (!period[9] & period[7]))) + + .dataa(period[10]), + .datab(period[8]), + .datac(period[9]), + .datad(period[7]), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0100; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \period~1 ( +// Equation(s): +// \period~1_combout = (\Add0~12_combout & (((!\Equal0~1_combout ) # (!\Equal0~2_combout )) # (!\Equal0~0_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Add0~12_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\period~1_combout ), + .cout()); +// synopsys translate_off +defparam \period~1 .lut_mask = 16'h4CCC; +defparam \period~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N31 +dffeas \period[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~1_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[6]), + .prn(vcc)); +// synopsys translate_off +defparam \period[6] .is_wysiwyg = "true"; +defparam \period[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N2 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (period[6] & (period[3] & (!period[5] & !period[4]))) + + .dataa(period[6]), + .datab(period[3]), + .datac(period[5]), + .datad(period[4]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0008; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N0 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~0_combout )) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~2_combout ), + .datac(gnd), + .datad(\Equal0~0_combout ), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h8800; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y13_N1 +dffeas Clk_Ctrl( + .clk(\clk~inputclkctrl_outclk ), + .d(\Equal0~3_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\Clk_Ctrl~q ), + .prn(vcc)); +// synopsys translate_off +defparam Clk_Ctrl.is_wysiwyg = "true"; +defparam Clk_Ctrl.power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y18_N5 +dffeas \EE0[1]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[1]~18_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[1]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[1]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[1]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N10 +cycloneive_lcell_comb \Add1~25 ( +// Equation(s): +// \Add1~25_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[1]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[1]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[1]~input_o ), + .datac(\EE0[1]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~25_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~25 .lut_mask = 16'h0FCC; +defparam \Add1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N6 +cycloneive_lcell_comb \EE0[2]~20 ( +// Equation(s): +// \EE0[2]~20_combout = (\Add1~23_combout & ((\Add1~22_combout & (!\EE0[1]~19 )) # (!\Add1~22_combout & (\EE0[1]~19 & VCC)))) # (!\Add1~23_combout & ((\Add1~22_combout & ((\EE0[1]~19 ) # (GND))) # (!\Add1~22_combout & (!\EE0[1]~19 )))) +// \EE0[2]~21 = CARRY((\Add1~23_combout & (\Add1~22_combout & !\EE0[1]~19 )) # (!\Add1~23_combout & ((\Add1~22_combout ) # (!\EE0[1]~19 )))) + + .dataa(\Add1~23_combout ), + .datab(\Add1~22_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[1]~19 ), + .combout(\EE0[2]~20_combout ), + .cout(\EE0[2]~21 )); +// synopsys translate_off +defparam \EE0[2]~20 .lut_mask = 16'h694D; +defparam \EE0[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N7 +dffeas \EE0[2]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[2]~20_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[2]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[2]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[2]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N30 +cycloneive_lcell_comb \Add1~23 ( +// Equation(s): +// \Add1~23_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[2]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[2]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[2]~input_o ), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[2]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~23_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~23 .lut_mask = 16'h0CFC; +defparam \Add1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N8 +cycloneive_lcell_comb \EE0[3]~22 ( +// Equation(s): +// \EE0[3]~22_combout = ((\Add1~20_combout $ (\Add1~21_combout $ (\EE0[2]~21 )))) # (GND) +// \EE0[3]~23 = CARRY((\Add1~20_combout & (\Add1~21_combout & !\EE0[2]~21 )) # (!\Add1~20_combout & ((\Add1~21_combout ) # (!\EE0[2]~21 )))) + + .dataa(\Add1~20_combout ), + .datab(\Add1~21_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[2]~21 ), + .combout(\EE0[3]~22_combout ), + .cout(\EE0[3]~23 )); +// synopsys translate_off +defparam \EE0[3]~22 .lut_mask = 16'h964D; +defparam \EE0[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N9 +dffeas \EE0[3]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[3]~22_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[3]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[3]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[3]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N15 +cycloneive_io_ibuf \SetPoint[3]~input ( + .i(SetPoint[3]), + .ibar(gnd), + .o(\SetPoint[3]~input_o )); +// synopsys translate_off +defparam \SetPoint[3]~input .bus_hold = "false"; +defparam \SetPoint[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N28 +cycloneive_lcell_comb \Add1~21 ( +// Equation(s): +// \Add1~21_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[3]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[3]~input_o ))) + + .dataa(\EE0[3]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[3]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~21_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~21 .lut_mask = 16'h55F0; +defparam \Add1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N10 +cycloneive_lcell_comb \EE0[4]~24 ( +// Equation(s): +// \EE0[4]~24_combout = (\Add1~19_combout & ((\Add1~18_combout & (!\EE0[3]~23 )) # (!\Add1~18_combout & (\EE0[3]~23 & VCC)))) # (!\Add1~19_combout & ((\Add1~18_combout & ((\EE0[3]~23 ) # (GND))) # (!\Add1~18_combout & (!\EE0[3]~23 )))) +// \EE0[4]~25 = CARRY((\Add1~19_combout & (\Add1~18_combout & !\EE0[3]~23 )) # (!\Add1~19_combout & ((\Add1~18_combout ) # (!\EE0[3]~23 )))) + + .dataa(\Add1~19_combout ), + .datab(\Add1~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[3]~23 ), + .combout(\EE0[4]~24_combout ), + .cout(\EE0[4]~25 )); +// synopsys translate_off +defparam \EE0[4]~24 .lut_mask = 16'h694D; +defparam \EE0[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N11 +dffeas \EE0[4]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[4]~24_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[4]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[4]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[4]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N22 +cycloneive_lcell_comb \Add1~19 ( +// Equation(s): +// \Add1~19_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[4]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[4]~input_o )) + + .dataa(\SetPoint[4]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[4]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~19 .lut_mask = 16'h0AFA; +defparam \Add1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N12 +cycloneive_lcell_comb \EE0[5]~26 ( +// Equation(s): +// \EE0[5]~26_combout = ((\Add1~16_combout $ (\Add1~17_combout $ (\EE0[4]~25 )))) # (GND) +// \EE0[5]~27 = CARRY((\Add1~16_combout & (\Add1~17_combout & !\EE0[4]~25 )) # (!\Add1~16_combout & ((\Add1~17_combout ) # (!\EE0[4]~25 )))) + + .dataa(\Add1~16_combout ), + .datab(\Add1~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[4]~25 ), + .combout(\EE0[5]~26_combout ), + .cout(\EE0[5]~27 )); +// synopsys translate_off +defparam \EE0[5]~26 .lut_mask = 16'h964D; +defparam \EE0[5]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N13 +dffeas \EE0[5]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[5]~26_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[5]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[5]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[5]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N8 +cycloneive_io_ibuf \SetPoint[5]~input ( + .i(SetPoint[5]), + .ibar(gnd), + .o(\SetPoint[5]~input_o )); +// synopsys translate_off +defparam \SetPoint[5]~input .bus_hold = "false"; +defparam \SetPoint[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N18 +cycloneive_lcell_comb \Add1~17 ( +// Equation(s): +// \Add1~17_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[5]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[5]~input_o ))) + + .dataa(\EE0[5]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[5]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~17 .lut_mask = 16'h55F0; +defparam \Add1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N14 +cycloneive_lcell_comb \EE0[6]~28 ( +// Equation(s): +// \EE0[6]~28_combout = (\Add1~15_combout & ((\Add1~14_combout & (!\EE0[5]~27 )) # (!\Add1~14_combout & (\EE0[5]~27 & VCC)))) # (!\Add1~15_combout & ((\Add1~14_combout & ((\EE0[5]~27 ) # (GND))) # (!\Add1~14_combout & (!\EE0[5]~27 )))) +// \EE0[6]~29 = CARRY((\Add1~15_combout & (\Add1~14_combout & !\EE0[5]~27 )) # (!\Add1~15_combout & ((\Add1~14_combout ) # (!\EE0[5]~27 )))) + + .dataa(\Add1~15_combout ), + .datab(\Add1~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[5]~27 ), + .combout(\EE0[6]~28_combout ), + .cout(\EE0[6]~29 )); +// synopsys translate_off +defparam \EE0[6]~28 .lut_mask = 16'h694D; +defparam \EE0[6]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N15 +dffeas \EE0[6]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[6]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[6]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[6]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[6]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N20 +cycloneive_lcell_comb \Add1~15 ( +// Equation(s): +// \Add1~15_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[6]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[6]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[6]~input_o ), + .datad(\EE0[6]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~15_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~15 .lut_mask = 16'h30FC; +defparam \Add1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N16 +cycloneive_lcell_comb \EE0[7]~30 ( +// Equation(s): +// \EE0[7]~30_combout = ((\Add1~12_combout $ (\Add1~13_combout $ (\EE0[6]~29 )))) # (GND) +// \EE0[7]~31 = CARRY((\Add1~12_combout & (\Add1~13_combout & !\EE0[6]~29 )) # (!\Add1~12_combout & ((\Add1~13_combout ) # (!\EE0[6]~29 )))) + + .dataa(\Add1~12_combout ), + .datab(\Add1~13_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[6]~29 ), + .combout(\EE0[7]~30_combout ), + .cout(\EE0[7]~31 )); +// synopsys translate_off +defparam \EE0[7]~30 .lut_mask = 16'h964D; +defparam \EE0[7]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N17 +dffeas \EE0[7]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[7]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[7]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[7]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[7]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N24 +cycloneive_lcell_comb \Add1~13 ( +// Equation(s): +// \Add1~13_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[7]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[7]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[7]~input_o ), + .datac(\EE0[7]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~13_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~13 .lut_mask = 16'h0FCC; +defparam \Add1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N18 +cycloneive_lcell_comb \EE0[8]~32 ( +// Equation(s): +// \EE0[8]~32_combout = (\Add1~11_combout & ((\Add1~10_combout & (!\EE0[7]~31 )) # (!\Add1~10_combout & (\EE0[7]~31 & VCC)))) # (!\Add1~11_combout & ((\Add1~10_combout & ((\EE0[7]~31 ) # (GND))) # (!\Add1~10_combout & (!\EE0[7]~31 )))) +// \EE0[8]~33 = CARRY((\Add1~11_combout & (\Add1~10_combout & !\EE0[7]~31 )) # (!\Add1~11_combout & ((\Add1~10_combout ) # (!\EE0[7]~31 )))) + + .dataa(\Add1~11_combout ), + .datab(\Add1~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[7]~31 ), + .combout(\EE0[8]~32_combout ), + .cout(\EE0[8]~33 )); +// synopsys translate_off +defparam \EE0[8]~32 .lut_mask = 16'h694D; +defparam \EE0[8]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N19 +dffeas \EE0[8]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[8]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[8]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[8]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[8]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N30 +cycloneive_lcell_comb \Add1~11 ( +// Equation(s): +// \Add1~11_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[8]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[8]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[8]~input_o ), + .datad(\EE0[8]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~11_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~11 .lut_mask = 16'h30FC; +defparam \Add1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N20 +cycloneive_lcell_comb \EE0[9]~34 ( +// Equation(s): +// \EE0[9]~34_combout = ((\Add1~8_combout $ (\Add1~9_combout $ (\EE0[8]~33 )))) # (GND) +// \EE0[9]~35 = CARRY((\Add1~8_combout & (\Add1~9_combout & !\EE0[8]~33 )) # (!\Add1~8_combout & ((\Add1~9_combout ) # (!\EE0[8]~33 )))) + + .dataa(\Add1~8_combout ), + .datab(\Add1~9_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[8]~33 ), + .combout(\EE0[9]~34_combout ), + .cout(\EE0[9]~35 )); +// synopsys translate_off +defparam \EE0[9]~34 .lut_mask = 16'h964D; +defparam \EE0[9]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N21 +dffeas \EE0[9]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[9]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[9]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[9]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[9]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N8 +cycloneive_lcell_comb \Add1~9 ( +// Equation(s): +// \Add1~9_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[9]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[9]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[9]~input_o ), + .datad(\EE0[9]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~9_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~9 .lut_mask = 16'h30FC; +defparam \Add1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N22 +cycloneive_lcell_comb \EE0[10]~36 ( +// Equation(s): +// \EE0[10]~36_combout = (\Add1~7_combout & ((\Add1~6_combout & (!\EE0[9]~35 )) # (!\Add1~6_combout & (\EE0[9]~35 & VCC)))) # (!\Add1~7_combout & ((\Add1~6_combout & ((\EE0[9]~35 ) # (GND))) # (!\Add1~6_combout & (!\EE0[9]~35 )))) +// \EE0[10]~37 = CARRY((\Add1~7_combout & (\Add1~6_combout & !\EE0[9]~35 )) # (!\Add1~7_combout & ((\Add1~6_combout ) # (!\EE0[9]~35 )))) + + .dataa(\Add1~7_combout ), + .datab(\Add1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[9]~35 ), + .combout(\EE0[10]~36_combout ), + .cout(\EE0[10]~37 )); +// synopsys translate_off +defparam \EE0[10]~36 .lut_mask = 16'h694D; +defparam \EE0[10]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N23 +dffeas \EE0[10]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[10]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[10]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[10]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[10]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N26 +cycloneive_lcell_comb \Add1~7 ( +// Equation(s): +// \Add1~7_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[10]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[10]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[10]~input_o ), + .datad(\EE0[10]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~7_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~7 .lut_mask = 16'h30FC; +defparam \Add1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N24 +cycloneive_lcell_comb \EE0[11]~38 ( +// Equation(s): +// \EE0[11]~38_combout = ((\Add1~4_combout $ (\Add1~5_combout $ (\EE0[10]~37 )))) # (GND) +// \EE0[11]~39 = CARRY((\Add1~4_combout & (\Add1~5_combout & !\EE0[10]~37 )) # (!\Add1~4_combout & ((\Add1~5_combout ) # (!\EE0[10]~37 )))) + + .dataa(\Add1~4_combout ), + .datab(\Add1~5_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[10]~37 ), + .combout(\EE0[11]~38_combout ), + .cout(\EE0[11]~39 )); +// synopsys translate_off +defparam \EE0[11]~38 .lut_mask = 16'h964D; +defparam \EE0[11]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N25 +dffeas \EE0[11]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[11]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[11]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[11]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[11]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \Add1~5 ( +// Equation(s): +// \Add1~5_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[11]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[11]~input_o )) + + .dataa(\SetPoint[11]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[11]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~5_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~5 .lut_mask = 16'h0AFA; +defparam \Add1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N26 +cycloneive_lcell_comb \EE0[12]~40 ( +// Equation(s): +// \EE0[12]~40_combout = (\Add1~2_combout & ((\Add1~3_combout & (!\EE0[11]~39 )) # (!\Add1~3_combout & ((\EE0[11]~39 ) # (GND))))) # (!\Add1~2_combout & ((\Add1~3_combout & (\EE0[11]~39 & VCC)) # (!\Add1~3_combout & (!\EE0[11]~39 )))) +// \EE0[12]~41 = CARRY((\Add1~2_combout & ((!\EE0[11]~39 ) # (!\Add1~3_combout ))) # (!\Add1~2_combout & (!\Add1~3_combout & !\EE0[11]~39 ))) + + .dataa(\Add1~2_combout ), + .datab(\Add1~3_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[11]~39 ), + .combout(\EE0[12]~40_combout ), + .cout(\EE0[12]~41 )); +// synopsys translate_off +defparam \EE0[12]~40 .lut_mask = 16'h692B; +defparam \EE0[12]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N27 +dffeas \EE0[12]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[12]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[12]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[12]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[12]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N0 +cycloneive_lcell_comb \Add1~3 ( +// Equation(s): +// \Add1~3_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[12]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[12]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[12]~input_o ), + .datac(\EE0[12]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~3_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~3 .lut_mask = 16'h0FCC; +defparam \Add1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N28 +cycloneive_lcell_comb \EE0[13]~42 ( +// Equation(s): +// \EE0[13]~42_combout = \Add1~1_combout $ (\EE0[12]~41 $ (\Add1~0_combout )) + + .dataa(gnd), + .datab(\Add1~1_combout ), + .datac(gnd), + .datad(\Add1~0_combout ), + .cin(\EE0[12]~41 ), + .combout(\EE0[13]~42_combout ), + .cout()); +// synopsys translate_off +defparam \EE0[13]~42 .lut_mask = 16'hC33C; +defparam \EE0[13]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N31 +dffeas \EE0[13]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\EE0[13]~42_combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[13]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[13]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[13]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N2 +cycloneive_lcell_comb \Add1~27 ( +// Equation(s): +// \Add1~27_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[0]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[0]~input_o ))) + + .dataa(\EE0[0]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[0]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~27_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~27 .lut_mask = 16'h55F0; +defparam \Add1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y18_N3 +dffeas \EE0[0]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[0]~16_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[0]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[0]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[0]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N4 +cycloneive_lcell_comb \EE1[1]~16 ( +// Equation(s): +// \EE1[1]~16_combout = (EE1[1] & ((\EE1[0]~15 ) # (GND))) # (!EE1[1] & (!\EE1[0]~15 )) +// \EE1[1]~17 = CARRY((EE1[1]) # (!\EE1[0]~15 )) + + .dataa(gnd), + .datab(EE1[1]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[0]~15 ), + .combout(\EE1[1]~16_combout ), + .cout(\EE1[1]~17 )); +// synopsys translate_off +defparam \EE1[1]~16 .lut_mask = 16'hC3CF; +defparam \EE1[1]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N5 +dffeas \EE1[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[1]~16_combout ), + .asdata(\EE0[1]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[1]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[1] .is_wysiwyg = "true"; +defparam \EE1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N6 +cycloneive_lcell_comb \EE1[2]~18 ( +// Equation(s): +// \EE1[2]~18_combout = (EE1[2] & (!\EE1[1]~17 & VCC)) # (!EE1[2] & (\EE1[1]~17 $ (GND))) +// \EE1[2]~19 = CARRY((!EE1[2] & !\EE1[1]~17 )) + + .dataa(EE1[2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[1]~17 ), + .combout(\EE1[2]~18_combout ), + .cout(\EE1[2]~19 )); +// synopsys translate_off +defparam \EE1[2]~18 .lut_mask = 16'h5A05; +defparam \EE1[2]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N7 +dffeas \EE1[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[2]~18_combout ), + .asdata(\EE0[2]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[2]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[2] .is_wysiwyg = "true"; +defparam \EE1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N8 +cycloneive_lcell_comb \EE1[3]~20 ( +// Equation(s): +// \EE1[3]~20_combout = (EE1[3] & ((\EE1[2]~19 ) # (GND))) # (!EE1[3] & (!\EE1[2]~19 )) +// \EE1[3]~21 = CARRY((EE1[3]) # (!\EE1[2]~19 )) + + .dataa(gnd), + .datab(EE1[3]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[2]~19 ), + .combout(\EE1[3]~20_combout ), + .cout(\EE1[3]~21 )); +// synopsys translate_off +defparam \EE1[3]~20 .lut_mask = 16'hC3CF; +defparam \EE1[3]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N9 +dffeas \EE1[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[3]~20_combout ), + .asdata(\EE0[3]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[3]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[3] .is_wysiwyg = "true"; +defparam \EE1[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N10 +cycloneive_lcell_comb \EE1[4]~22 ( +// Equation(s): +// \EE1[4]~22_combout = (EE1[4] & (!\EE1[3]~21 & VCC)) # (!EE1[4] & (\EE1[3]~21 $ (GND))) +// \EE1[4]~23 = CARRY((!EE1[4] & !\EE1[3]~21 )) + + .dataa(EE1[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[3]~21 ), + .combout(\EE1[4]~22_combout ), + .cout(\EE1[4]~23 )); +// synopsys translate_off +defparam \EE1[4]~22 .lut_mask = 16'h5A05; +defparam \EE1[4]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N11 +dffeas \EE1[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[4]~22_combout ), + .asdata(\EE0[4]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[4]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[4] .is_wysiwyg = "true"; +defparam \EE1[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N12 +cycloneive_lcell_comb \EE1[5]~24 ( +// Equation(s): +// \EE1[5]~24_combout = (EE1[5] & ((\EE1[4]~23 ) # (GND))) # (!EE1[5] & (!\EE1[4]~23 )) +// \EE1[5]~25 = CARRY((EE1[5]) # (!\EE1[4]~23 )) + + .dataa(EE1[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[4]~23 ), + .combout(\EE1[5]~24_combout ), + .cout(\EE1[5]~25 )); +// synopsys translate_off +defparam \EE1[5]~24 .lut_mask = 16'hA5AF; +defparam \EE1[5]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N13 +dffeas \EE1[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[5]~24_combout ), + .asdata(\EE0[5]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[5]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[5] .is_wysiwyg = "true"; +defparam \EE1[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N14 +cycloneive_lcell_comb \EE1[6]~26 ( +// Equation(s): +// \EE1[6]~26_combout = (EE1[6] & (!\EE1[5]~25 & VCC)) # (!EE1[6] & (\EE1[5]~25 $ (GND))) +// \EE1[6]~27 = CARRY((!EE1[6] & !\EE1[5]~25 )) + + .dataa(gnd), + .datab(EE1[6]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[5]~25 ), + .combout(\EE1[6]~26_combout ), + .cout(\EE1[6]~27 )); +// synopsys translate_off +defparam \EE1[6]~26 .lut_mask = 16'h3C03; +defparam \EE1[6]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N15 +dffeas \EE1[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[6]~26_combout ), + .asdata(\EE0[6]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[6]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[6] .is_wysiwyg = "true"; +defparam \EE1[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N16 +cycloneive_lcell_comb \EE1[7]~28 ( +// Equation(s): +// \EE1[7]~28_combout = (EE1[7] & ((\EE1[6]~27 ) # (GND))) # (!EE1[7] & (!\EE1[6]~27 )) +// \EE1[7]~29 = CARRY((EE1[7]) # (!\EE1[6]~27 )) + + .dataa(gnd), + .datab(EE1[7]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[6]~27 ), + .combout(\EE1[7]~28_combout ), + .cout(\EE1[7]~29 )); +// synopsys translate_off +defparam \EE1[7]~28 .lut_mask = 16'hC3CF; +defparam \EE1[7]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N17 +dffeas \EE1[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[7]~28_combout ), + .asdata(\EE0[7]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[7]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[7] .is_wysiwyg = "true"; +defparam \EE1[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N18 +cycloneive_lcell_comb \EE1[8]~30 ( +// Equation(s): +// \EE1[8]~30_combout = (EE1[8] & (!\EE1[7]~29 & VCC)) # (!EE1[8] & (\EE1[7]~29 $ (GND))) +// \EE1[8]~31 = CARRY((!EE1[8] & !\EE1[7]~29 )) + + .dataa(gnd), + .datab(EE1[8]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[7]~29 ), + .combout(\EE1[8]~30_combout ), + .cout(\EE1[8]~31 )); +// synopsys translate_off +defparam \EE1[8]~30 .lut_mask = 16'h3C03; +defparam \EE1[8]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N19 +dffeas \EE1[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[8]~30_combout ), + .asdata(\EE0[8]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[8]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[8] .is_wysiwyg = "true"; +defparam \EE1[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N20 +cycloneive_lcell_comb \EE1[9]~32 ( +// Equation(s): +// \EE1[9]~32_combout = (EE1[9] & ((\EE1[8]~31 ) # (GND))) # (!EE1[9] & (!\EE1[8]~31 )) +// \EE1[9]~33 = CARRY((EE1[9]) # (!\EE1[8]~31 )) + + .dataa(gnd), + .datab(EE1[9]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[8]~31 ), + .combout(\EE1[9]~32_combout ), + .cout(\EE1[9]~33 )); +// synopsys translate_off +defparam \EE1[9]~32 .lut_mask = 16'hC3CF; +defparam \EE1[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N21 +dffeas \EE1[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[9]~32_combout ), + .asdata(\EE0[9]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[9]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[9] .is_wysiwyg = "true"; +defparam \EE1[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N22 +cycloneive_lcell_comb \EE1[10]~34 ( +// Equation(s): +// \EE1[10]~34_combout = (EE1[10] & (!\EE1[9]~33 & VCC)) # (!EE1[10] & (\EE1[9]~33 $ (GND))) +// \EE1[10]~35 = CARRY((!EE1[10] & !\EE1[9]~33 )) + + .dataa(EE1[10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[9]~33 ), + .combout(\EE1[10]~34_combout ), + .cout(\EE1[10]~35 )); +// synopsys translate_off +defparam \EE1[10]~34 .lut_mask = 16'h5A05; +defparam \EE1[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N23 +dffeas \EE1[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[10]~34_combout ), + .asdata(\EE0[10]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[10]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[10] .is_wysiwyg = "true"; +defparam \EE1[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N24 +cycloneive_lcell_comb \EE1[11]~36 ( +// Equation(s): +// \EE1[11]~36_combout = (EE1[11] & ((\EE1[10]~35 ) # (GND))) # (!EE1[11] & (!\EE1[10]~35 )) +// \EE1[11]~37 = CARRY((EE1[11]) # (!\EE1[10]~35 )) + + .dataa(gnd), + .datab(EE1[11]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[10]~35 ), + .combout(\EE1[11]~36_combout ), + .cout(\EE1[11]~37 )); +// synopsys translate_off +defparam \EE1[11]~36 .lut_mask = 16'hC3CF; +defparam \EE1[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N25 +dffeas \EE1[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[11]~36_combout ), + .asdata(\EE0[11]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[11]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[11] .is_wysiwyg = "true"; +defparam \EE1[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N26 +cycloneive_lcell_comb \EE1[12]~38 ( +// Equation(s): +// \EE1[12]~38_combout = (EE1[12] & (!\EE1[11]~37 & VCC)) # (!EE1[12] & (\EE1[11]~37 $ (GND))) +// \EE1[12]~39 = CARRY((!EE1[12] & !\EE1[11]~37 )) + + .dataa(EE1[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[11]~37 ), + .combout(\EE1[12]~38_combout ), + .cout(\EE1[12]~39 )); +// synopsys translate_off +defparam \EE1[12]~38 .lut_mask = 16'h5A05; +defparam \EE1[12]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N27 +dffeas \EE1[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[12]~38_combout ), + .asdata(\EE0[12]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[12]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[12] .is_wysiwyg = "true"; +defparam \EE1[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N28 +cycloneive_lcell_comb \EE1[13]~40 ( +// Equation(s): +// \EE1[13]~40_combout = \EE1[12]~39 $ (!EE1[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(EE1[13]), + .cin(\EE1[12]~39 ), + .combout(\EE1[13]~40_combout ), + .cout()); +// synopsys translate_off +defparam \EE1[13]~40 .lut_mask = 16'hF00F; +defparam \EE1[13]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N29 +dffeas \EE1[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[13]~40_combout ), + .asdata(\EE0[13]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[13]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[13] .is_wysiwyg = "true"; +defparam \EE1[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y17_N3 +dffeas \EE1[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[0]~14_combout ), + .asdata(\EE0[0]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[0]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[0] .is_wysiwyg = "true"; +defparam \EE1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N6 +cycloneive_lcell_comb \EE2[1]~16 ( +// Equation(s): +// \EE2[1]~16_combout = (EE2[1] & ((\EE2[0]~15 ) # (GND))) # (!EE2[1] & (!\EE2[0]~15 )) +// \EE2[1]~17 = CARRY((EE2[1]) # (!\EE2[0]~15 )) + + .dataa(EE2[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[0]~15 ), + .combout(\EE2[1]~16_combout ), + .cout(\EE2[1]~17 )); +// synopsys translate_off +defparam \EE2[1]~16 .lut_mask = 16'hA5AF; +defparam \EE2[1]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N7 +dffeas \EE2[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[1]~16_combout ), + .asdata(EE1[1]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[1]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[1] .is_wysiwyg = "true"; +defparam \EE2[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \EE2[2]~18 ( +// Equation(s): +// \EE2[2]~18_combout = (EE2[2] & (!\EE2[1]~17 & VCC)) # (!EE2[2] & (\EE2[1]~17 $ (GND))) +// \EE2[2]~19 = CARRY((!EE2[2] & !\EE2[1]~17 )) + + .dataa(gnd), + .datab(EE2[2]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[1]~17 ), + .combout(\EE2[2]~18_combout ), + .cout(\EE2[2]~19 )); +// synopsys translate_off +defparam \EE2[2]~18 .lut_mask = 16'h3C03; +defparam \EE2[2]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N9 +dffeas \EE2[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[2]~18_combout ), + .asdata(EE1[2]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[2]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[2] .is_wysiwyg = "true"; +defparam \EE2[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 +cycloneive_lcell_comb \EE2[3]~20 ( +// Equation(s): +// \EE2[3]~20_combout = (EE2[3] & ((\EE2[2]~19 ) # (GND))) # (!EE2[3] & (!\EE2[2]~19 )) +// \EE2[3]~21 = CARRY((EE2[3]) # (!\EE2[2]~19 )) + + .dataa(EE2[3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[2]~19 ), + .combout(\EE2[3]~20_combout ), + .cout(\EE2[3]~21 )); +// synopsys translate_off +defparam \EE2[3]~20 .lut_mask = 16'hA5AF; +defparam \EE2[3]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N11 +dffeas \EE2[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[3]~20_combout ), + .asdata(EE1[3]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[3]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[3] .is_wysiwyg = "true"; +defparam \EE2[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N12 +cycloneive_lcell_comb \EE2[4]~22 ( +// Equation(s): +// \EE2[4]~22_combout = (EE2[4] & (!\EE2[3]~21 & VCC)) # (!EE2[4] & (\EE2[3]~21 $ (GND))) +// \EE2[4]~23 = CARRY((!EE2[4] & !\EE2[3]~21 )) + + .dataa(EE2[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[3]~21 ), + .combout(\EE2[4]~22_combout ), + .cout(\EE2[4]~23 )); +// synopsys translate_off +defparam \EE2[4]~22 .lut_mask = 16'h5A05; +defparam \EE2[4]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N13 +dffeas \EE2[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[4]~22_combout ), + .asdata(EE1[4]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[4]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[4] .is_wysiwyg = "true"; +defparam \EE2[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \EE2[5]~24 ( +// Equation(s): +// \EE2[5]~24_combout = (EE2[5] & ((\EE2[4]~23 ) # (GND))) # (!EE2[5] & (!\EE2[4]~23 )) +// \EE2[5]~25 = CARRY((EE2[5]) # (!\EE2[4]~23 )) + + .dataa(gnd), + .datab(EE2[5]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[4]~23 ), + .combout(\EE2[5]~24_combout ), + .cout(\EE2[5]~25 )); +// synopsys translate_off +defparam \EE2[5]~24 .lut_mask = 16'hC3CF; +defparam \EE2[5]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N15 +dffeas \EE2[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[5]~24_combout ), + .asdata(EE1[5]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[5]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[5] .is_wysiwyg = "true"; +defparam \EE2[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \EE2[6]~26 ( +// Equation(s): +// \EE2[6]~26_combout = (EE2[6] & (!\EE2[5]~25 & VCC)) # (!EE2[6] & (\EE2[5]~25 $ (GND))) +// \EE2[6]~27 = CARRY((!EE2[6] & !\EE2[5]~25 )) + + .dataa(gnd), + .datab(EE2[6]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[5]~25 ), + .combout(\EE2[6]~26_combout ), + .cout(\EE2[6]~27 )); +// synopsys translate_off +defparam \EE2[6]~26 .lut_mask = 16'h3C03; +defparam \EE2[6]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N17 +dffeas \EE2[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[6]~26_combout ), + .asdata(EE1[6]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[6]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[6] .is_wysiwyg = "true"; +defparam \EE2[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \EE2[7]~28 ( +// Equation(s): +// \EE2[7]~28_combout = (EE2[7] & ((\EE2[6]~27 ) # (GND))) # (!EE2[7] & (!\EE2[6]~27 )) +// \EE2[7]~29 = CARRY((EE2[7]) # (!\EE2[6]~27 )) + + .dataa(gnd), + .datab(EE2[7]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[6]~27 ), + .combout(\EE2[7]~28_combout ), + .cout(\EE2[7]~29 )); +// synopsys translate_off +defparam \EE2[7]~28 .lut_mask = 16'hC3CF; +defparam \EE2[7]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N19 +dffeas \EE2[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[7]~28_combout ), + .asdata(EE1[7]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[7]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[7] .is_wysiwyg = "true"; +defparam \EE2[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \EE2[8]~30 ( +// Equation(s): +// \EE2[8]~30_combout = (EE2[8] & (!\EE2[7]~29 & VCC)) # (!EE2[8] & (\EE2[7]~29 $ (GND))) +// \EE2[8]~31 = CARRY((!EE2[8] & !\EE2[7]~29 )) + + .dataa(gnd), + .datab(EE2[8]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[7]~29 ), + .combout(\EE2[8]~30_combout ), + .cout(\EE2[8]~31 )); +// synopsys translate_off +defparam \EE2[8]~30 .lut_mask = 16'h3C03; +defparam \EE2[8]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N21 +dffeas \EE2[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[8]~30_combout ), + .asdata(EE1[8]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[8]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[8] .is_wysiwyg = "true"; +defparam \EE2[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N22 +cycloneive_lcell_comb \EE2[9]~32 ( +// Equation(s): +// \EE2[9]~32_combout = (EE2[9] & ((\EE2[8]~31 ) # (GND))) # (!EE2[9] & (!\EE2[8]~31 )) +// \EE2[9]~33 = CARRY((EE2[9]) # (!\EE2[8]~31 )) + + .dataa(EE2[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[8]~31 ), + .combout(\EE2[9]~32_combout ), + .cout(\EE2[9]~33 )); +// synopsys translate_off +defparam \EE2[9]~32 .lut_mask = 16'hA5AF; +defparam \EE2[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N23 +dffeas \EE2[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[9]~32_combout ), + .asdata(EE1[9]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[9]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[9] .is_wysiwyg = "true"; +defparam \EE2[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \EE2[10]~34 ( +// Equation(s): +// \EE2[10]~34_combout = (EE2[10] & (!\EE2[9]~33 & VCC)) # (!EE2[10] & (\EE2[9]~33 $ (GND))) +// \EE2[10]~35 = CARRY((!EE2[10] & !\EE2[9]~33 )) + + .dataa(gnd), + .datab(EE2[10]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[9]~33 ), + .combout(\EE2[10]~34_combout ), + .cout(\EE2[10]~35 )); +// synopsys translate_off +defparam \EE2[10]~34 .lut_mask = 16'h3C03; +defparam \EE2[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N25 +dffeas \EE2[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[10]~34_combout ), + .asdata(EE1[10]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[10]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[10] .is_wysiwyg = "true"; +defparam \EE2[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \EE2[11]~36 ( +// Equation(s): +// \EE2[11]~36_combout = (EE2[11] & ((\EE2[10]~35 ) # (GND))) # (!EE2[11] & (!\EE2[10]~35 )) +// \EE2[11]~37 = CARRY((EE2[11]) # (!\EE2[10]~35 )) + + .dataa(EE2[11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[10]~35 ), + .combout(\EE2[11]~36_combout ), + .cout(\EE2[11]~37 )); +// synopsys translate_off +defparam \EE2[11]~36 .lut_mask = 16'hA5AF; +defparam \EE2[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N27 +dffeas \EE2[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[11]~36_combout ), + .asdata(EE1[11]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[11]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[11] .is_wysiwyg = "true"; +defparam \EE2[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \EE2[12]~38 ( +// Equation(s): +// \EE2[12]~38_combout = (EE2[12] & (!\EE2[11]~37 & VCC)) # (!EE2[12] & (\EE2[11]~37 $ (GND))) +// \EE2[12]~39 = CARRY((!EE2[12] & !\EE2[11]~37 )) + + .dataa(gnd), + .datab(EE2[12]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[11]~37 ), + .combout(\EE2[12]~38_combout ), + .cout(\EE2[12]~39 )); +// synopsys translate_off +defparam \EE2[12]~38 .lut_mask = 16'h3C03; +defparam \EE2[12]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N29 +dffeas \EE2[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[12]~38_combout ), + .asdata(EE1[12]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[12]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[12] .is_wysiwyg = "true"; +defparam \EE2[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 +cycloneive_lcell_comb \EE2[13]~40 ( +// Equation(s): +// \EE2[13]~40_combout = EE2[13] $ (!\EE2[12]~39 ) + + .dataa(EE2[13]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\EE2[12]~39 ), + .combout(\EE2[13]~40_combout ), + .cout()); +// synopsys translate_off +defparam \EE2[13]~40 .lut_mask = 16'hA5A5; +defparam \EE2[13]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N31 +dffeas \EE2[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[13]~40_combout ), + .asdata(EE1[13]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[13]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[13] .is_wysiwyg = "true"; +defparam \EE2[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y14_N5 +dffeas \EE2[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[0]~14_combout ), + .asdata(EE1[0]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[0]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[0] .is_wysiwyg = "true"; +defparam \EE2[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N15 +cycloneive_io_ibuf \Kd[0]~input ( + .i(Kd[0]), + .ibar(gnd), + .o(\Kd[0]~input_o )); +// synopsys translate_off +defparam \Kd[0]~input .bus_hold = "false"; +defparam \Kd[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N8 +cycloneive_io_ibuf \Kd[1]~input ( + .i(Kd[1]), + .ibar(gnd), + .o(\Kd[1]~input_o )); +// synopsys translate_off +defparam \Kd[1]~input .bus_hold = "false"; +defparam \Kd[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N1 +cycloneive_io_ibuf \Kd[2]~input ( + .i(Kd[2]), + .ibar(gnd), + .o(\Kd[2]~input_o )); +// synopsys translate_off +defparam \Kd[2]~input .bus_hold = "false"; +defparam \Kd[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N15 +cycloneive_io_ibuf \Kd[3]~input ( + .i(Kd[3]), + .ibar(gnd), + .o(\Kd[3]~input_o )); +// synopsys translate_off +defparam \Kd[3]~input .bus_hold = "false"; +defparam \Kd[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N8 +cycloneive_io_ibuf \Kd[4]~input ( + .i(Kd[4]), + .ibar(gnd), + .o(\Kd[4]~input_o )); +// synopsys translate_off +defparam \Kd[4]~input .bus_hold = "false"; +defparam \Kd[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N8 +cycloneive_io_ibuf \Kd[5]~input ( + .i(Kd[5]), + .ibar(gnd), + .o(\Kd[5]~input_o )); +// synopsys translate_off +defparam \Kd[5]~input .bus_hold = "false"; +defparam \Kd[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N1 +cycloneive_io_ibuf \Kd[6]~input ( + .i(Kd[6]), + .ibar(gnd), + .o(\Kd[6]~input_o )); +// synopsys translate_off +defparam \Kd[6]~input .bus_hold = "false"; +defparam \Kd[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N22 +cycloneive_io_ibuf \Kd[7]~input ( + .i(Kd[7]), + .ibar(gnd), + .o(\Kd[7]~input_o )); +// synopsys translate_off +defparam \Kd[7]~input .bus_hold = "false"; +defparam \Kd[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y14_N0 +cycloneive_mac_mult \Mult2|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({EE2[11],EE2[10],EE2[9],EE2[8],EE2[7],EE2[6],EE2[5],EE2[4],EE2[3],EE2[2],EE2[1],EE2[0],gnd,gnd,gnd,gnd,gnd,gnd}), + .datab({\Kd[7]~input_o ,\Kd[6]~input_o ,\Kd[5]~input_o ,\Kd[4]~input_o ,\Kd[3]~input_o ,\Kd[2]~input_o ,\Kd[1]~input_o ,\Kd[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult2|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult2|auto_generated|mac_mult1 .dataa_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult2|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult2|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y14_N2 +cycloneive_mac_out \Mult2|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult2|auto_generated|mac_mult1~DATAOUT19 ,\Mult2|auto_generated|mac_mult1~DATAOUT18 ,\Mult2|auto_generated|mac_mult1~DATAOUT17 ,\Mult2|auto_generated|mac_mult1~DATAOUT16 ,\Mult2|auto_generated|mac_mult1~DATAOUT15 ,\Mult2|auto_generated|mac_mult1~DATAOUT14 , +\Mult2|auto_generated|mac_mult1~DATAOUT13 ,\Mult2|auto_generated|mac_mult1~DATAOUT12 ,\Mult2|auto_generated|mac_mult1~DATAOUT11 ,\Mult2|auto_generated|mac_mult1~DATAOUT10 ,\Mult2|auto_generated|mac_mult1~DATAOUT9 ,\Mult2|auto_generated|mac_mult1~DATAOUT8 , +\Mult2|auto_generated|mac_mult1~DATAOUT7 ,\Mult2|auto_generated|mac_mult1~DATAOUT6 ,\Mult2|auto_generated|mac_mult1~DATAOUT5 ,\Mult2|auto_generated|mac_mult1~DATAOUT4 ,\Mult2|auto_generated|mac_mult1~DATAOUT3 ,\Mult2|auto_generated|mac_mult1~DATAOUT2 , +\Mult2|auto_generated|mac_mult1~DATAOUT1 ,\Mult2|auto_generated|mac_mult1~dataout ,\Mult2|auto_generated|mac_mult1~15 ,\Mult2|auto_generated|mac_mult1~14 ,\Mult2|auto_generated|mac_mult1~13 ,\Mult2|auto_generated|mac_mult1~12 ,\Mult2|auto_generated|mac_mult1~11 , +\Mult2|auto_generated|mac_mult1~10 ,\Mult2|auto_generated|mac_mult1~9 ,\Mult2|auto_generated|mac_mult1~8 ,\Mult2|auto_generated|mac_mult1~7 ,\Mult2|auto_generated|mac_mult1~6 ,\Mult2|auto_generated|mac_mult1~5 ,\Mult2|auto_generated|mac_mult1~4 , +\Mult2|auto_generated|mac_mult1~3 ,\Mult2|auto_generated|mac_mult1~2 ,\Mult2|auto_generated|mac_mult1~1 ,\Mult2|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult2|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult2|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult2|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y14_N13 +dffeas \Kd_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[0]~21_combout ), + .asdata(\Mult2|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[0] .is_wysiwyg = "true"; +defparam \Kd_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N14 +cycloneive_lcell_comb \Kd_Out[1]~23 ( +// Equation(s): +// \Kd_Out[1]~23_combout = (Kd_Out[1] & ((\Kd_Out[0]~22 ) # (GND))) # (!Kd_Out[1] & (!\Kd_Out[0]~22 )) +// \Kd_Out[1]~24 = CARRY((Kd_Out[1]) # (!\Kd_Out[0]~22 )) + + .dataa(gnd), + .datab(Kd_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[0]~22 ), + .combout(\Kd_Out[1]~23_combout ), + .cout(\Kd_Out[1]~24 )); +// synopsys translate_off +defparam \Kd_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Kd_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N15 +dffeas \Kd_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[1]~23_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[1] .is_wysiwyg = "true"; +defparam \Kd_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N16 +cycloneive_lcell_comb \Kd_Out[2]~25 ( +// Equation(s): +// \Kd_Out[2]~25_combout = (Kd_Out[2] & (!\Kd_Out[1]~24 & VCC)) # (!Kd_Out[2] & (\Kd_Out[1]~24 $ (GND))) +// \Kd_Out[2]~26 = CARRY((!Kd_Out[2] & !\Kd_Out[1]~24 )) + + .dataa(gnd), + .datab(Kd_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[1]~24 ), + .combout(\Kd_Out[2]~25_combout ), + .cout(\Kd_Out[2]~26 )); +// synopsys translate_off +defparam \Kd_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Kd_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N17 +dffeas \Kd_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[2]~25_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[2] .is_wysiwyg = "true"; +defparam \Kd_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N18 +cycloneive_lcell_comb \Kd_Out[3]~27 ( +// Equation(s): +// \Kd_Out[3]~27_combout = (Kd_Out[3] & ((\Kd_Out[2]~26 ) # (GND))) # (!Kd_Out[3] & (!\Kd_Out[2]~26 )) +// \Kd_Out[3]~28 = CARRY((Kd_Out[3]) # (!\Kd_Out[2]~26 )) + + .dataa(gnd), + .datab(Kd_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[2]~26 ), + .combout(\Kd_Out[3]~27_combout ), + .cout(\Kd_Out[3]~28 )); +// synopsys translate_off +defparam \Kd_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Kd_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N19 +dffeas \Kd_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[3]~27_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[3] .is_wysiwyg = "true"; +defparam \Kd_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N20 +cycloneive_lcell_comb \Kd_Out[4]~29 ( +// Equation(s): +// \Kd_Out[4]~29_combout = (Kd_Out[4] & (!\Kd_Out[3]~28 & VCC)) # (!Kd_Out[4] & (\Kd_Out[3]~28 $ (GND))) +// \Kd_Out[4]~30 = CARRY((!Kd_Out[4] & !\Kd_Out[3]~28 )) + + .dataa(gnd), + .datab(Kd_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[3]~28 ), + .combout(\Kd_Out[4]~29_combout ), + .cout(\Kd_Out[4]~30 )); +// synopsys translate_off +defparam \Kd_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Kd_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N21 +dffeas \Kd_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[4]~29_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[4] .is_wysiwyg = "true"; +defparam \Kd_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N22 +cycloneive_lcell_comb \Kd_Out[5]~31 ( +// Equation(s): +// \Kd_Out[5]~31_combout = (Kd_Out[5] & ((\Kd_Out[4]~30 ) # (GND))) # (!Kd_Out[5] & (!\Kd_Out[4]~30 )) +// \Kd_Out[5]~32 = CARRY((Kd_Out[5]) # (!\Kd_Out[4]~30 )) + + .dataa(Kd_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[4]~30 ), + .combout(\Kd_Out[5]~31_combout ), + .cout(\Kd_Out[5]~32 )); +// synopsys translate_off +defparam \Kd_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Kd_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N23 +dffeas \Kd_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[5]~31_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[5] .is_wysiwyg = "true"; +defparam \Kd_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N24 +cycloneive_lcell_comb \Kd_Out[6]~33 ( +// Equation(s): +// \Kd_Out[6]~33_combout = (Kd_Out[6] & (!\Kd_Out[5]~32 & VCC)) # (!Kd_Out[6] & (\Kd_Out[5]~32 $ (GND))) +// \Kd_Out[6]~34 = CARRY((!Kd_Out[6] & !\Kd_Out[5]~32 )) + + .dataa(gnd), + .datab(Kd_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[5]~32 ), + .combout(\Kd_Out[6]~33_combout ), + .cout(\Kd_Out[6]~34 )); +// synopsys translate_off +defparam \Kd_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Kd_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N25 +dffeas \Kd_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[6]~33_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[6] .is_wysiwyg = "true"; +defparam \Kd_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N26 +cycloneive_lcell_comb \Kd_Out[7]~35 ( +// Equation(s): +// \Kd_Out[7]~35_combout = (Kd_Out[7] & ((\Kd_Out[6]~34 ) # (GND))) # (!Kd_Out[7] & (!\Kd_Out[6]~34 )) +// \Kd_Out[7]~36 = CARRY((Kd_Out[7]) # (!\Kd_Out[6]~34 )) + + .dataa(Kd_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[6]~34 ), + .combout(\Kd_Out[7]~35_combout ), + .cout(\Kd_Out[7]~36 )); +// synopsys translate_off +defparam \Kd_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Kd_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N27 +dffeas \Kd_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[7]~35_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[7] .is_wysiwyg = "true"; +defparam \Kd_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N28 +cycloneive_lcell_comb \Kd_Out[8]~37 ( +// Equation(s): +// \Kd_Out[8]~37_combout = (Kd_Out[8] & (!\Kd_Out[7]~36 & VCC)) # (!Kd_Out[8] & (\Kd_Out[7]~36 $ (GND))) +// \Kd_Out[8]~38 = CARRY((!Kd_Out[8] & !\Kd_Out[7]~36 )) + + .dataa(gnd), + .datab(Kd_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[7]~36 ), + .combout(\Kd_Out[8]~37_combout ), + .cout(\Kd_Out[8]~38 )); +// synopsys translate_off +defparam \Kd_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Kd_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N29 +dffeas \Kd_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[8]~37_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[8] .is_wysiwyg = "true"; +defparam \Kd_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N30 +cycloneive_lcell_comb \Kd_Out[9]~39 ( +// Equation(s): +// \Kd_Out[9]~39_combout = (Kd_Out[9] & ((\Kd_Out[8]~38 ) # (GND))) # (!Kd_Out[9] & (!\Kd_Out[8]~38 )) +// \Kd_Out[9]~40 = CARRY((Kd_Out[9]) # (!\Kd_Out[8]~38 )) + + .dataa(Kd_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[8]~38 ), + .combout(\Kd_Out[9]~39_combout ), + .cout(\Kd_Out[9]~40 )); +// synopsys translate_off +defparam \Kd_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Kd_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N31 +dffeas \Kd_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[9]~39_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[9] .is_wysiwyg = "true"; +defparam \Kd_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N0 +cycloneive_lcell_comb \Kd_Out[10]~41 ( +// Equation(s): +// \Kd_Out[10]~41_combout = (Kd_Out[10] & (!\Kd_Out[9]~40 & VCC)) # (!Kd_Out[10] & (\Kd_Out[9]~40 $ (GND))) +// \Kd_Out[10]~42 = CARRY((!Kd_Out[10] & !\Kd_Out[9]~40 )) + + .dataa(gnd), + .datab(Kd_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[9]~40 ), + .combout(\Kd_Out[10]~41_combout ), + .cout(\Kd_Out[10]~42 )); +// synopsys translate_off +defparam \Kd_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Kd_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N1 +dffeas \Kd_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[10]~41_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[10] .is_wysiwyg = "true"; +defparam \Kd_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N2 +cycloneive_lcell_comb \Kd_Out[11]~43 ( +// Equation(s): +// \Kd_Out[11]~43_combout = (Kd_Out[11] & ((\Kd_Out[10]~42 ) # (GND))) # (!Kd_Out[11] & (!\Kd_Out[10]~42 )) +// \Kd_Out[11]~44 = CARRY((Kd_Out[11]) # (!\Kd_Out[10]~42 )) + + .dataa(gnd), + .datab(Kd_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[10]~42 ), + .combout(\Kd_Out[11]~43_combout ), + .cout(\Kd_Out[11]~44 )); +// synopsys translate_off +defparam \Kd_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Kd_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N0 +cycloneive_lcell_comb \Kd_Out[11]~feeder ( +// Equation(s): +// \Kd_Out[11]~feeder_combout = \Kd_Out[11]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[11]~43_combout ), + .cin(gnd), + .combout(\Kd_Out[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[11]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N1 +dffeas \Kd_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[11]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[11] .is_wysiwyg = "true"; +defparam \Kd_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N4 +cycloneive_lcell_comb \Kd_Out[12]~45 ( +// Equation(s): +// \Kd_Out[12]~45_combout = (Kd_Out[12] & (!\Kd_Out[11]~44 & VCC)) # (!Kd_Out[12] & (\Kd_Out[11]~44 $ (GND))) +// \Kd_Out[12]~46 = CARRY((!Kd_Out[12] & !\Kd_Out[11]~44 )) + + .dataa(gnd), + .datab(Kd_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[11]~44 ), + .combout(\Kd_Out[12]~45_combout ), + .cout(\Kd_Out[12]~46 )); +// synopsys translate_off +defparam \Kd_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Kd_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N5 +dffeas \Kd_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[12]~45_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[12] .is_wysiwyg = "true"; +defparam \Kd_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N6 +cycloneive_lcell_comb \Kd_Out[13]~47 ( +// Equation(s): +// \Kd_Out[13]~47_combout = (Kd_Out[13] & ((\Kd_Out[12]~46 ) # (GND))) # (!Kd_Out[13] & (!\Kd_Out[12]~46 )) +// \Kd_Out[13]~48 = CARRY((Kd_Out[13]) # (!\Kd_Out[12]~46 )) + + .dataa(Kd_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[12]~46 ), + .combout(\Kd_Out[13]~47_combout ), + .cout(\Kd_Out[13]~48 )); +// synopsys translate_off +defparam \Kd_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Kd_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N7 +dffeas \Kd_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[13]~47_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[13] .is_wysiwyg = "true"; +defparam \Kd_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N8 +cycloneive_lcell_comb \Kd_Out[14]~49 ( +// Equation(s): +// \Kd_Out[14]~49_combout = (Kd_Out[14] & (!\Kd_Out[13]~48 & VCC)) # (!Kd_Out[14] & (\Kd_Out[13]~48 $ (GND))) +// \Kd_Out[14]~50 = CARRY((!Kd_Out[14] & !\Kd_Out[13]~48 )) + + .dataa(gnd), + .datab(Kd_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[13]~48 ), + .combout(\Kd_Out[14]~49_combout ), + .cout(\Kd_Out[14]~50 )); +// synopsys translate_off +defparam \Kd_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Kd_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N6 +cycloneive_lcell_comb \Kd_Out[14]~feeder ( +// Equation(s): +// \Kd_Out[14]~feeder_combout = \Kd_Out[14]~49_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[14]~49_combout ), + .cin(gnd), + .combout(\Kd_Out[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[14]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N7 +dffeas \Kd_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[14]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[14] .is_wysiwyg = "true"; +defparam \Kd_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N10 +cycloneive_lcell_comb \Kd_Out[15]~51 ( +// Equation(s): +// \Kd_Out[15]~51_combout = (Kd_Out[15] & ((\Kd_Out[14]~50 ) # (GND))) # (!Kd_Out[15] & (!\Kd_Out[14]~50 )) +// \Kd_Out[15]~52 = CARRY((Kd_Out[15]) # (!\Kd_Out[14]~50 )) + + .dataa(Kd_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[14]~50 ), + .combout(\Kd_Out[15]~51_combout ), + .cout(\Kd_Out[15]~52 )); +// synopsys translate_off +defparam \Kd_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Kd_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N4 +cycloneive_lcell_comb \Kd_Out[15]~feeder ( +// Equation(s): +// \Kd_Out[15]~feeder_combout = \Kd_Out[15]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[15]~51_combout ), + .cin(gnd), + .combout(\Kd_Out[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[15]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N5 +dffeas \Kd_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[15]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[15] .is_wysiwyg = "true"; +defparam \Kd_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N12 +cycloneive_lcell_comb \Kd_Out[16]~53 ( +// Equation(s): +// \Kd_Out[16]~53_combout = (Kd_Out[16] & (!\Kd_Out[15]~52 & VCC)) # (!Kd_Out[16] & (\Kd_Out[15]~52 $ (GND))) +// \Kd_Out[16]~54 = CARRY((!Kd_Out[16] & !\Kd_Out[15]~52 )) + + .dataa(Kd_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[15]~52 ), + .combout(\Kd_Out[16]~53_combout ), + .cout(\Kd_Out[16]~54 )); +// synopsys translate_off +defparam \Kd_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Kd_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N13 +dffeas \Kd_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[16]~53_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[16] .is_wysiwyg = "true"; +defparam \Kd_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N14 +cycloneive_lcell_comb \Kd_Out[17]~55 ( +// Equation(s): +// \Kd_Out[17]~55_combout = (Kd_Out[17] & ((\Kd_Out[16]~54 ) # (GND))) # (!Kd_Out[17] & (!\Kd_Out[16]~54 )) +// \Kd_Out[17]~56 = CARRY((Kd_Out[17]) # (!\Kd_Out[16]~54 )) + + .dataa(Kd_Out[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[16]~54 ), + .combout(\Kd_Out[17]~55_combout ), + .cout(\Kd_Out[17]~56 )); +// synopsys translate_off +defparam \Kd_Out[17]~55 .lut_mask = 16'hA5AF; +defparam \Kd_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N10 +cycloneive_lcell_comb \Kd_Out[17]~feeder ( +// Equation(s): +// \Kd_Out[17]~feeder_combout = \Kd_Out[17]~55_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[17]~55_combout ), + .cin(gnd), + .combout(\Kd_Out[17]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[17]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[17]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N11 +dffeas \Kd_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[17]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[17] .is_wysiwyg = "true"; +defparam \Kd_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N16 +cycloneive_lcell_comb \Kd_Out[18]~57 ( +// Equation(s): +// \Kd_Out[18]~57_combout = (Kd_Out[18] & (!\Kd_Out[17]~56 & VCC)) # (!Kd_Out[18] & (\Kd_Out[17]~56 $ (GND))) +// \Kd_Out[18]~58 = CARRY((!Kd_Out[18] & !\Kd_Out[17]~56 )) + + .dataa(gnd), + .datab(Kd_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[17]~56 ), + .combout(\Kd_Out[18]~57_combout ), + .cout(\Kd_Out[18]~58 )); +// synopsys translate_off +defparam \Kd_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Kd_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N8 +cycloneive_lcell_comb \Kd_Out[18]~feeder ( +// Equation(s): +// \Kd_Out[18]~feeder_combout = \Kd_Out[18]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[18]~57_combout ), + .cin(gnd), + .combout(\Kd_Out[18]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[18]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[18]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N9 +dffeas \Kd_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[18]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[18] .is_wysiwyg = "true"; +defparam \Kd_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N18 +cycloneive_lcell_comb \Kd_Out[19]~59 ( +// Equation(s): +// \Kd_Out[19]~59_combout = (Kd_Out[19] & ((\Kd_Out[18]~58 ) # (GND))) # (!Kd_Out[19] & (!\Kd_Out[18]~58 )) +// \Kd_Out[19]~60 = CARRY((Kd_Out[19]) # (!\Kd_Out[18]~58 )) + + .dataa(gnd), + .datab(Kd_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[18]~58 ), + .combout(\Kd_Out[19]~59_combout ), + .cout(\Kd_Out[19]~60 )); +// synopsys translate_off +defparam \Kd_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Kd_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N2 +cycloneive_lcell_comb \Kd_Out[19]~feeder ( +// Equation(s): +// \Kd_Out[19]~feeder_combout = \Kd_Out[19]~59_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[19]~59_combout ), + .cin(gnd), + .combout(\Kd_Out[19]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[19]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[19]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N3 +dffeas \Kd_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[19]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[19] .is_wysiwyg = "true"; +defparam \Kd_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N20 +cycloneive_lcell_comb \Kd_Out[20]~61 ( +// Equation(s): +// \Kd_Out[20]~61_combout = \Kd_Out[19]~60 $ (Kd_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[20]), + .cin(\Kd_Out[19]~60 ), + .combout(\Kd_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Kd_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N26 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y13_N21 +dffeas \Kd_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[20]~61_combout ), + .asdata(\~GND~combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[20] .is_wysiwyg = "true"; +defparam \Kd_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N30 +cycloneive_lcell_comb \Add7~20 ( +// Equation(s): +// \Add7~20_combout = (Kd_Out[20] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[20]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~20 .lut_mask = 16'h00F0; +defparam \Add7~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N12 +cycloneive_lcell_comb \Ki_Out[0]~21 ( +// Equation(s): +// \Ki_Out[0]~21_combout = Ki_Out[0] $ (GND) +// \Ki_Out[0]~22 = CARRY(!Ki_Out[0]) + + .dataa(Ki_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Ki_Out[0]~21_combout ), + .cout(\Ki_Out[0]~22 )); +// synopsys translate_off +defparam \Ki_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Ki_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y17_N22 +cycloneive_io_ibuf \Ki[0]~input ( + .i(Ki[0]), + .ibar(gnd), + .o(\Ki[0]~input_o )); +// synopsys translate_off +defparam \Ki[0]~input .bus_hold = "false"; +defparam \Ki[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N1 +cycloneive_io_ibuf \Ki[1]~input ( + .i(Ki[1]), + .ibar(gnd), + .o(\Ki[1]~input_o )); +// synopsys translate_off +defparam \Ki[1]~input .bus_hold = "false"; +defparam \Ki[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N22 +cycloneive_io_ibuf \Ki[2]~input ( + .i(Ki[2]), + .ibar(gnd), + .o(\Ki[2]~input_o )); +// synopsys translate_off +defparam \Ki[2]~input .bus_hold = "false"; +defparam \Ki[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N15 +cycloneive_io_ibuf \Ki[3]~input ( + .i(Ki[3]), + .ibar(gnd), + .o(\Ki[3]~input_o )); +// synopsys translate_off +defparam \Ki[3]~input .bus_hold = "false"; +defparam \Ki[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N15 +cycloneive_io_ibuf \Ki[4]~input ( + .i(Ki[4]), + .ibar(gnd), + .o(\Ki[4]~input_o )); +// synopsys translate_off +defparam \Ki[4]~input .bus_hold = "false"; +defparam \Ki[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N8 +cycloneive_io_ibuf \Ki[5]~input ( + .i(Ki[5]), + .ibar(gnd), + .o(\Ki[5]~input_o )); +// synopsys translate_off +defparam \Ki[5]~input .bus_hold = "false"; +defparam \Ki[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N1 +cycloneive_io_ibuf \Ki[6]~input ( + .i(Ki[6]), + .ibar(gnd), + .o(\Ki[6]~input_o )); +// synopsys translate_off +defparam \Ki[6]~input .bus_hold = "false"; +defparam \Ki[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N8 +cycloneive_io_ibuf \Ki[7]~input ( + .i(Ki[7]), + .ibar(gnd), + .o(\Ki[7]~input_o )); +// synopsys translate_off +defparam \Ki[7]~input .bus_hold = "false"; +defparam \Ki[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y17_N0 +cycloneive_mac_mult \Mult1|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({EE1[11],EE1[10],EE1[9],EE1[8],EE1[7],EE1[6],EE1[5],EE1[4],EE1[3],EE1[2],EE1[1],EE1[0],gnd,gnd,gnd,gnd,gnd,gnd}), + .datab({\Ki[7]~input_o ,\Ki[6]~input_o ,\Ki[5]~input_o ,\Ki[4]~input_o ,\Ki[3]~input_o ,\Ki[2]~input_o ,\Ki[1]~input_o ,\Ki[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult1|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult1|auto_generated|mac_mult1 .dataa_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult1|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult1|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y17_N2 +cycloneive_mac_out \Mult1|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult1|auto_generated|mac_mult1~DATAOUT19 ,\Mult1|auto_generated|mac_mult1~DATAOUT18 ,\Mult1|auto_generated|mac_mult1~DATAOUT17 ,\Mult1|auto_generated|mac_mult1~DATAOUT16 ,\Mult1|auto_generated|mac_mult1~DATAOUT15 ,\Mult1|auto_generated|mac_mult1~DATAOUT14 , +\Mult1|auto_generated|mac_mult1~DATAOUT13 ,\Mult1|auto_generated|mac_mult1~DATAOUT12 ,\Mult1|auto_generated|mac_mult1~DATAOUT11 ,\Mult1|auto_generated|mac_mult1~DATAOUT10 ,\Mult1|auto_generated|mac_mult1~DATAOUT9 ,\Mult1|auto_generated|mac_mult1~DATAOUT8 , +\Mult1|auto_generated|mac_mult1~DATAOUT7 ,\Mult1|auto_generated|mac_mult1~DATAOUT6 ,\Mult1|auto_generated|mac_mult1~DATAOUT5 ,\Mult1|auto_generated|mac_mult1~DATAOUT4 ,\Mult1|auto_generated|mac_mult1~DATAOUT3 ,\Mult1|auto_generated|mac_mult1~DATAOUT2 , +\Mult1|auto_generated|mac_mult1~DATAOUT1 ,\Mult1|auto_generated|mac_mult1~dataout ,\Mult1|auto_generated|mac_mult1~15 ,\Mult1|auto_generated|mac_mult1~14 ,\Mult1|auto_generated|mac_mult1~13 ,\Mult1|auto_generated|mac_mult1~12 ,\Mult1|auto_generated|mac_mult1~11 , +\Mult1|auto_generated|mac_mult1~10 ,\Mult1|auto_generated|mac_mult1~9 ,\Mult1|auto_generated|mac_mult1~8 ,\Mult1|auto_generated|mac_mult1~7 ,\Mult1|auto_generated|mac_mult1~6 ,\Mult1|auto_generated|mac_mult1~5 ,\Mult1|auto_generated|mac_mult1~4 , +\Mult1|auto_generated|mac_mult1~3 ,\Mult1|auto_generated|mac_mult1~2 ,\Mult1|auto_generated|mac_mult1~1 ,\Mult1|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult1|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult1|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult1|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y18_N13 +dffeas \Ki_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[0]~21_combout ), + .asdata(\Mult1|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[0] .is_wysiwyg = "true"; +defparam \Ki_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N14 +cycloneive_lcell_comb \Ki_Out[1]~23 ( +// Equation(s): +// \Ki_Out[1]~23_combout = (Ki_Out[1] & ((\Ki_Out[0]~22 ) # (GND))) # (!Ki_Out[1] & (!\Ki_Out[0]~22 )) +// \Ki_Out[1]~24 = CARRY((Ki_Out[1]) # (!\Ki_Out[0]~22 )) + + .dataa(gnd), + .datab(Ki_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[0]~22 ), + .combout(\Ki_Out[1]~23_combout ), + .cout(\Ki_Out[1]~24 )); +// synopsys translate_off +defparam \Ki_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Ki_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N15 +dffeas \Ki_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[1]~23_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[1] .is_wysiwyg = "true"; +defparam \Ki_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N16 +cycloneive_lcell_comb \Ki_Out[2]~25 ( +// Equation(s): +// \Ki_Out[2]~25_combout = (Ki_Out[2] & (!\Ki_Out[1]~24 & VCC)) # (!Ki_Out[2] & (\Ki_Out[1]~24 $ (GND))) +// \Ki_Out[2]~26 = CARRY((!Ki_Out[2] & !\Ki_Out[1]~24 )) + + .dataa(gnd), + .datab(Ki_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[1]~24 ), + .combout(\Ki_Out[2]~25_combout ), + .cout(\Ki_Out[2]~26 )); +// synopsys translate_off +defparam \Ki_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Ki_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N17 +dffeas \Ki_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[2]~25_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[2] .is_wysiwyg = "true"; +defparam \Ki_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N18 +cycloneive_lcell_comb \Ki_Out[3]~27 ( +// Equation(s): +// \Ki_Out[3]~27_combout = (Ki_Out[3] & ((\Ki_Out[2]~26 ) # (GND))) # (!Ki_Out[3] & (!\Ki_Out[2]~26 )) +// \Ki_Out[3]~28 = CARRY((Ki_Out[3]) # (!\Ki_Out[2]~26 )) + + .dataa(gnd), + .datab(Ki_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[2]~26 ), + .combout(\Ki_Out[3]~27_combout ), + .cout(\Ki_Out[3]~28 )); +// synopsys translate_off +defparam \Ki_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Ki_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N19 +dffeas \Ki_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[3]~27_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[3] .is_wysiwyg = "true"; +defparam \Ki_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N20 +cycloneive_lcell_comb \Ki_Out[4]~29 ( +// Equation(s): +// \Ki_Out[4]~29_combout = (Ki_Out[4] & (!\Ki_Out[3]~28 & VCC)) # (!Ki_Out[4] & (\Ki_Out[3]~28 $ (GND))) +// \Ki_Out[4]~30 = CARRY((!Ki_Out[4] & !\Ki_Out[3]~28 )) + + .dataa(gnd), + .datab(Ki_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[3]~28 ), + .combout(\Ki_Out[4]~29_combout ), + .cout(\Ki_Out[4]~30 )); +// synopsys translate_off +defparam \Ki_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Ki_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N21 +dffeas \Ki_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[4]~29_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[4] .is_wysiwyg = "true"; +defparam \Ki_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N22 +cycloneive_lcell_comb \Ki_Out[5]~31 ( +// Equation(s): +// \Ki_Out[5]~31_combout = (Ki_Out[5] & ((\Ki_Out[4]~30 ) # (GND))) # (!Ki_Out[5] & (!\Ki_Out[4]~30 )) +// \Ki_Out[5]~32 = CARRY((Ki_Out[5]) # (!\Ki_Out[4]~30 )) + + .dataa(Ki_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[4]~30 ), + .combout(\Ki_Out[5]~31_combout ), + .cout(\Ki_Out[5]~32 )); +// synopsys translate_off +defparam \Ki_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Ki_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N23 +dffeas \Ki_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[5]~31_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[5] .is_wysiwyg = "true"; +defparam \Ki_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N24 +cycloneive_lcell_comb \Ki_Out[6]~33 ( +// Equation(s): +// \Ki_Out[6]~33_combout = (Ki_Out[6] & (!\Ki_Out[5]~32 & VCC)) # (!Ki_Out[6] & (\Ki_Out[5]~32 $ (GND))) +// \Ki_Out[6]~34 = CARRY((!Ki_Out[6] & !\Ki_Out[5]~32 )) + + .dataa(gnd), + .datab(Ki_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[5]~32 ), + .combout(\Ki_Out[6]~33_combout ), + .cout(\Ki_Out[6]~34 )); +// synopsys translate_off +defparam \Ki_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Ki_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N25 +dffeas \Ki_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[6]~33_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[6] .is_wysiwyg = "true"; +defparam \Ki_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N26 +cycloneive_lcell_comb \Ki_Out[7]~35 ( +// Equation(s): +// \Ki_Out[7]~35_combout = (Ki_Out[7] & ((\Ki_Out[6]~34 ) # (GND))) # (!Ki_Out[7] & (!\Ki_Out[6]~34 )) +// \Ki_Out[7]~36 = CARRY((Ki_Out[7]) # (!\Ki_Out[6]~34 )) + + .dataa(Ki_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[6]~34 ), + .combout(\Ki_Out[7]~35_combout ), + .cout(\Ki_Out[7]~36 )); +// synopsys translate_off +defparam \Ki_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Ki_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N27 +dffeas \Ki_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[7]~35_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[7] .is_wysiwyg = "true"; +defparam \Ki_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N28 +cycloneive_lcell_comb \Ki_Out[8]~37 ( +// Equation(s): +// \Ki_Out[8]~37_combout = (Ki_Out[8] & (!\Ki_Out[7]~36 & VCC)) # (!Ki_Out[8] & (\Ki_Out[7]~36 $ (GND))) +// \Ki_Out[8]~38 = CARRY((!Ki_Out[8] & !\Ki_Out[7]~36 )) + + .dataa(gnd), + .datab(Ki_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[7]~36 ), + .combout(\Ki_Out[8]~37_combout ), + .cout(\Ki_Out[8]~38 )); +// synopsys translate_off +defparam \Ki_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Ki_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N29 +dffeas \Ki_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[8]~37_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[8] .is_wysiwyg = "true"; +defparam \Ki_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N30 +cycloneive_lcell_comb \Ki_Out[9]~39 ( +// Equation(s): +// \Ki_Out[9]~39_combout = (Ki_Out[9] & ((\Ki_Out[8]~38 ) # (GND))) # (!Ki_Out[9] & (!\Ki_Out[8]~38 )) +// \Ki_Out[9]~40 = CARRY((Ki_Out[9]) # (!\Ki_Out[8]~38 )) + + .dataa(Ki_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[8]~38 ), + .combout(\Ki_Out[9]~39_combout ), + .cout(\Ki_Out[9]~40 )); +// synopsys translate_off +defparam \Ki_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Ki_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N31 +dffeas \Ki_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[9]~39_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[9] .is_wysiwyg = "true"; +defparam \Ki_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N0 +cycloneive_lcell_comb \Ki_Out[10]~41 ( +// Equation(s): +// \Ki_Out[10]~41_combout = (Ki_Out[10] & (!\Ki_Out[9]~40 & VCC)) # (!Ki_Out[10] & (\Ki_Out[9]~40 $ (GND))) +// \Ki_Out[10]~42 = CARRY((!Ki_Out[10] & !\Ki_Out[9]~40 )) + + .dataa(gnd), + .datab(Ki_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[9]~40 ), + .combout(\Ki_Out[10]~41_combout ), + .cout(\Ki_Out[10]~42 )); +// synopsys translate_off +defparam \Ki_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Ki_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N1 +dffeas \Ki_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[10]~41_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[10] .is_wysiwyg = "true"; +defparam \Ki_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N2 +cycloneive_lcell_comb \Ki_Out[11]~43 ( +// Equation(s): +// \Ki_Out[11]~43_combout = (Ki_Out[11] & ((\Ki_Out[10]~42 ) # (GND))) # (!Ki_Out[11] & (!\Ki_Out[10]~42 )) +// \Ki_Out[11]~44 = CARRY((Ki_Out[11]) # (!\Ki_Out[10]~42 )) + + .dataa(gnd), + .datab(Ki_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[10]~42 ), + .combout(\Ki_Out[11]~43_combout ), + .cout(\Ki_Out[11]~44 )); +// synopsys translate_off +defparam \Ki_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Ki_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N3 +dffeas \Ki_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[11]~43_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[11] .is_wysiwyg = "true"; +defparam \Ki_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N4 +cycloneive_lcell_comb \Ki_Out[12]~45 ( +// Equation(s): +// \Ki_Out[12]~45_combout = (Ki_Out[12] & (!\Ki_Out[11]~44 & VCC)) # (!Ki_Out[12] & (\Ki_Out[11]~44 $ (GND))) +// \Ki_Out[12]~46 = CARRY((!Ki_Out[12] & !\Ki_Out[11]~44 )) + + .dataa(gnd), + .datab(Ki_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[11]~44 ), + .combout(\Ki_Out[12]~45_combout ), + .cout(\Ki_Out[12]~46 )); +// synopsys translate_off +defparam \Ki_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Ki_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N5 +dffeas \Ki_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[12]~45_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[12] .is_wysiwyg = "true"; +defparam \Ki_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N6 +cycloneive_lcell_comb \Ki_Out[13]~47 ( +// Equation(s): +// \Ki_Out[13]~47_combout = (Ki_Out[13] & ((\Ki_Out[12]~46 ) # (GND))) # (!Ki_Out[13] & (!\Ki_Out[12]~46 )) +// \Ki_Out[13]~48 = CARRY((Ki_Out[13]) # (!\Ki_Out[12]~46 )) + + .dataa(Ki_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[12]~46 ), + .combout(\Ki_Out[13]~47_combout ), + .cout(\Ki_Out[13]~48 )); +// synopsys translate_off +defparam \Ki_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Ki_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N7 +dffeas \Ki_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[13]~47_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[13] .is_wysiwyg = "true"; +defparam \Ki_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N8 +cycloneive_lcell_comb \Ki_Out[14]~49 ( +// Equation(s): +// \Ki_Out[14]~49_combout = (Ki_Out[14] & (!\Ki_Out[13]~48 & VCC)) # (!Ki_Out[14] & (\Ki_Out[13]~48 $ (GND))) +// \Ki_Out[14]~50 = CARRY((!Ki_Out[14] & !\Ki_Out[13]~48 )) + + .dataa(gnd), + .datab(Ki_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[13]~48 ), + .combout(\Ki_Out[14]~49_combout ), + .cout(\Ki_Out[14]~50 )); +// synopsys translate_off +defparam \Ki_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Ki_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N9 +dffeas \Ki_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[14]~49_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[14] .is_wysiwyg = "true"; +defparam \Ki_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N10 +cycloneive_lcell_comb \Ki_Out[15]~51 ( +// Equation(s): +// \Ki_Out[15]~51_combout = (Ki_Out[15] & ((\Ki_Out[14]~50 ) # (GND))) # (!Ki_Out[15] & (!\Ki_Out[14]~50 )) +// \Ki_Out[15]~52 = CARRY((Ki_Out[15]) # (!\Ki_Out[14]~50 )) + + .dataa(Ki_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[14]~50 ), + .combout(\Ki_Out[15]~51_combout ), + .cout(\Ki_Out[15]~52 )); +// synopsys translate_off +defparam \Ki_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Ki_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N11 +dffeas \Ki_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[15]~51_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[15] .is_wysiwyg = "true"; +defparam \Ki_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N12 +cycloneive_lcell_comb \Ki_Out[16]~53 ( +// Equation(s): +// \Ki_Out[16]~53_combout = (Ki_Out[16] & (!\Ki_Out[15]~52 & VCC)) # (!Ki_Out[16] & (\Ki_Out[15]~52 $ (GND))) +// \Ki_Out[16]~54 = CARRY((!Ki_Out[16] & !\Ki_Out[15]~52 )) + + .dataa(Ki_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[15]~52 ), + .combout(\Ki_Out[16]~53_combout ), + .cout(\Ki_Out[16]~54 )); +// synopsys translate_off +defparam \Ki_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Ki_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N13 +dffeas \Ki_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[16]~53_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[16] .is_wysiwyg = "true"; +defparam \Ki_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N14 +cycloneive_lcell_comb \Ki_Out[17]~55 ( +// Equation(s): +// \Ki_Out[17]~55_combout = (Ki_Out[17] & ((\Ki_Out[16]~54 ) # (GND))) # (!Ki_Out[17] & (!\Ki_Out[16]~54 )) +// \Ki_Out[17]~56 = CARRY((Ki_Out[17]) # (!\Ki_Out[16]~54 )) + + .dataa(gnd), + .datab(Ki_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[16]~54 ), + .combout(\Ki_Out[17]~55_combout ), + .cout(\Ki_Out[17]~56 )); +// synopsys translate_off +defparam \Ki_Out[17]~55 .lut_mask = 16'hC3CF; +defparam \Ki_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N15 +dffeas \Ki_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[17]~55_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[17] .is_wysiwyg = "true"; +defparam \Ki_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N16 +cycloneive_lcell_comb \Ki_Out[18]~57 ( +// Equation(s): +// \Ki_Out[18]~57_combout = (Ki_Out[18] & (!\Ki_Out[17]~56 & VCC)) # (!Ki_Out[18] & (\Ki_Out[17]~56 $ (GND))) +// \Ki_Out[18]~58 = CARRY((!Ki_Out[18] & !\Ki_Out[17]~56 )) + + .dataa(gnd), + .datab(Ki_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[17]~56 ), + .combout(\Ki_Out[18]~57_combout ), + .cout(\Ki_Out[18]~58 )); +// synopsys translate_off +defparam \Ki_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Ki_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N17 +dffeas \Ki_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[18]~57_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[18] .is_wysiwyg = "true"; +defparam \Ki_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N18 +cycloneive_lcell_comb \Ki_Out[19]~59 ( +// Equation(s): +// \Ki_Out[19]~59_combout = (Ki_Out[19] & ((\Ki_Out[18]~58 ) # (GND))) # (!Ki_Out[19] & (!\Ki_Out[18]~58 )) +// \Ki_Out[19]~60 = CARRY((Ki_Out[19]) # (!\Ki_Out[18]~58 )) + + .dataa(gnd), + .datab(Ki_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[18]~58 ), + .combout(\Ki_Out[19]~59_combout ), + .cout(\Ki_Out[19]~60 )); +// synopsys translate_off +defparam \Ki_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Ki_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N19 +dffeas \Ki_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[19]~59_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[19] .is_wysiwyg = "true"; +defparam \Ki_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N20 +cycloneive_lcell_comb \Ki_Out[20]~61 ( +// Equation(s): +// \Ki_Out[20]~61_combout = \Ki_Out[19]~60 $ (Ki_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Ki_Out[20]), + .cin(\Ki_Out[19]~60 ), + .combout(\Ki_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Ki_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Ki_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N21 +dffeas \Ki_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[20]~61_combout ), + .asdata(\~GND~combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[20] .is_wysiwyg = "true"; +defparam \Ki_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N12 +cycloneive_lcell_comb \Kp_Out[0]~21 ( +// Equation(s): +// \Kp_Out[0]~21_combout = Kp_Out[0] $ (GND) +// \Kp_Out[0]~22 = CARRY(!Kp_Out[0]) + + .dataa(Kp_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Kp_Out[0]~21_combout ), + .cout(\Kp_Out[0]~22 )); +// synopsys translate_off +defparam \Kp_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Kp_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \Kp[0]~input ( + .i(Kp[0]), + .ibar(gnd), + .o(\Kp[0]~input_o )); +// synopsys translate_off +defparam \Kp[0]~input .bus_hold = "false"; +defparam \Kp[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N22 +cycloneive_io_ibuf \Kp[1]~input ( + .i(Kp[1]), + .ibar(gnd), + .o(\Kp[1]~input_o )); +// synopsys translate_off +defparam \Kp[1]~input .bus_hold = "false"; +defparam \Kp[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N22 +cycloneive_io_ibuf \Kp[2]~input ( + .i(Kp[2]), + .ibar(gnd), + .o(\Kp[2]~input_o )); +// synopsys translate_off +defparam \Kp[2]~input .bus_hold = "false"; +defparam \Kp[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N22 +cycloneive_io_ibuf \Kp[3]~input ( + .i(Kp[3]), + .ibar(gnd), + .o(\Kp[3]~input_o )); +// synopsys translate_off +defparam \Kp[3]~input .bus_hold = "false"; +defparam \Kp[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N15 +cycloneive_io_ibuf \Kp[4]~input ( + .i(Kp[4]), + .ibar(gnd), + .o(\Kp[4]~input_o )); +// synopsys translate_off +defparam \Kp[4]~input .bus_hold = "false"; +defparam \Kp[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N15 +cycloneive_io_ibuf \Kp[5]~input ( + .i(Kp[5]), + .ibar(gnd), + .o(\Kp[5]~input_o )); +// synopsys translate_off +defparam \Kp[5]~input .bus_hold = "false"; +defparam \Kp[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N1 +cycloneive_io_ibuf \Kp[6]~input ( + .i(Kp[6]), + .ibar(gnd), + .o(\Kp[6]~input_o )); +// synopsys translate_off +defparam \Kp[6]~input .bus_hold = "false"; +defparam \Kp[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N22 +cycloneive_io_ibuf \Kp[7]~input ( + .i(Kp[7]), + .ibar(gnd), + .o(\Kp[7]~input_o )); +// synopsys translate_off +defparam \Kp[7]~input .bus_hold = "false"; +defparam \Kp[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y18_N0 +cycloneive_mac_mult \Mult0|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(\clk~inputclkctrl_outclk ), + .aclr(!\rst_n~inputclkctrl_outclk ), + .ena(\Clk_Ctrl~q ), + .dataa({\EE0[13]~42_combout ,\EE0[12]~40_combout ,\EE0[11]~38_combout ,\EE0[10]~36_combout ,\EE0[9]~34_combout ,\EE0[8]~32_combout ,\EE0[7]~30_combout ,\EE0[6]~28_combout ,\EE0[5]~26_combout ,\EE0[4]~24_combout ,\EE0[3]~22_combout ,\EE0[2]~20_combout ,\EE0[1]~18_combout , +\EE0[0]~16_combout ,gnd,gnd,gnd,gnd}), + .datab({\Kp[7]~input_o ,\Kp[6]~input_o ,\Kp[5]~input_o ,\Kp[4]~input_o ,\Kp[3]~input_o ,\Kp[2]~input_o ,\Kp[1]~input_o ,\Kp[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult0|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult0|auto_generated|mac_mult1 .dataa_clock = "0"; +defparam \Mult0|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult0|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult0|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult0|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult0|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y18_N2 +cycloneive_mac_out \Mult0|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult0|auto_generated|mac_mult1~DATAOUT21 ,\Mult0|auto_generated|mac_mult1~DATAOUT20 ,\Mult0|auto_generated|mac_mult1~DATAOUT19 ,\Mult0|auto_generated|mac_mult1~DATAOUT18 ,\Mult0|auto_generated|mac_mult1~DATAOUT17 ,\Mult0|auto_generated|mac_mult1~DATAOUT16 , +\Mult0|auto_generated|mac_mult1~DATAOUT15 ,\Mult0|auto_generated|mac_mult1~DATAOUT14 ,\Mult0|auto_generated|mac_mult1~DATAOUT13 ,\Mult0|auto_generated|mac_mult1~DATAOUT12 ,\Mult0|auto_generated|mac_mult1~DATAOUT11 ,\Mult0|auto_generated|mac_mult1~DATAOUT10 , +\Mult0|auto_generated|mac_mult1~DATAOUT9 ,\Mult0|auto_generated|mac_mult1~DATAOUT8 ,\Mult0|auto_generated|mac_mult1~DATAOUT7 ,\Mult0|auto_generated|mac_mult1~DATAOUT6 ,\Mult0|auto_generated|mac_mult1~DATAOUT5 ,\Mult0|auto_generated|mac_mult1~DATAOUT4 , +\Mult0|auto_generated|mac_mult1~DATAOUT3 ,\Mult0|auto_generated|mac_mult1~DATAOUT2 ,\Mult0|auto_generated|mac_mult1~DATAOUT1 ,\Mult0|auto_generated|mac_mult1~dataout ,\Mult0|auto_generated|mac_mult1~13 ,\Mult0|auto_generated|mac_mult1~12 , +\Mult0|auto_generated|mac_mult1~11 ,\Mult0|auto_generated|mac_mult1~10 ,\Mult0|auto_generated|mac_mult1~9 ,\Mult0|auto_generated|mac_mult1~8 ,\Mult0|auto_generated|mac_mult1~7 ,\Mult0|auto_generated|mac_mult1~6 ,\Mult0|auto_generated|mac_mult1~5 , +\Mult0|auto_generated|mac_mult1~4 ,\Mult0|auto_generated|mac_mult1~3 ,\Mult0|auto_generated|mac_mult1~2 ,\Mult0|auto_generated|mac_mult1~1 ,\Mult0|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult0|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult0|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult0|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y16_N13 +dffeas \Kp_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[0]~21_combout ), + .asdata(\Mult0|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[0] .is_wysiwyg = "true"; +defparam \Kp_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N14 +cycloneive_lcell_comb \Kp_Out[1]~23 ( +// Equation(s): +// \Kp_Out[1]~23_combout = (Kp_Out[1] & ((\Kp_Out[0]~22 ) # (GND))) # (!Kp_Out[1] & (!\Kp_Out[0]~22 )) +// \Kp_Out[1]~24 = CARRY((Kp_Out[1]) # (!\Kp_Out[0]~22 )) + + .dataa(gnd), + .datab(Kp_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[0]~22 ), + .combout(\Kp_Out[1]~23_combout ), + .cout(\Kp_Out[1]~24 )); +// synopsys translate_off +defparam \Kp_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Kp_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N15 +dffeas \Kp_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[1]~23_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[1] .is_wysiwyg = "true"; +defparam \Kp_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N16 +cycloneive_lcell_comb \Kp_Out[2]~25 ( +// Equation(s): +// \Kp_Out[2]~25_combout = (Kp_Out[2] & (!\Kp_Out[1]~24 & VCC)) # (!Kp_Out[2] & (\Kp_Out[1]~24 $ (GND))) +// \Kp_Out[2]~26 = CARRY((!Kp_Out[2] & !\Kp_Out[1]~24 )) + + .dataa(gnd), + .datab(Kp_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[1]~24 ), + .combout(\Kp_Out[2]~25_combout ), + .cout(\Kp_Out[2]~26 )); +// synopsys translate_off +defparam \Kp_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Kp_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N17 +dffeas \Kp_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[2]~25_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[2] .is_wysiwyg = "true"; +defparam \Kp_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N18 +cycloneive_lcell_comb \Kp_Out[3]~27 ( +// Equation(s): +// \Kp_Out[3]~27_combout = (Kp_Out[3] & ((\Kp_Out[2]~26 ) # (GND))) # (!Kp_Out[3] & (!\Kp_Out[2]~26 )) +// \Kp_Out[3]~28 = CARRY((Kp_Out[3]) # (!\Kp_Out[2]~26 )) + + .dataa(gnd), + .datab(Kp_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[2]~26 ), + .combout(\Kp_Out[3]~27_combout ), + .cout(\Kp_Out[3]~28 )); +// synopsys translate_off +defparam \Kp_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Kp_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N19 +dffeas \Kp_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[3]~27_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[3] .is_wysiwyg = "true"; +defparam \Kp_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N20 +cycloneive_lcell_comb \Kp_Out[4]~29 ( +// Equation(s): +// \Kp_Out[4]~29_combout = (Kp_Out[4] & (!\Kp_Out[3]~28 & VCC)) # (!Kp_Out[4] & (\Kp_Out[3]~28 $ (GND))) +// \Kp_Out[4]~30 = CARRY((!Kp_Out[4] & !\Kp_Out[3]~28 )) + + .dataa(gnd), + .datab(Kp_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[3]~28 ), + .combout(\Kp_Out[4]~29_combout ), + .cout(\Kp_Out[4]~30 )); +// synopsys translate_off +defparam \Kp_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Kp_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N21 +dffeas \Kp_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[4]~29_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[4] .is_wysiwyg = "true"; +defparam \Kp_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N22 +cycloneive_lcell_comb \Kp_Out[5]~31 ( +// Equation(s): +// \Kp_Out[5]~31_combout = (Kp_Out[5] & ((\Kp_Out[4]~30 ) # (GND))) # (!Kp_Out[5] & (!\Kp_Out[4]~30 )) +// \Kp_Out[5]~32 = CARRY((Kp_Out[5]) # (!\Kp_Out[4]~30 )) + + .dataa(Kp_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[4]~30 ), + .combout(\Kp_Out[5]~31_combout ), + .cout(\Kp_Out[5]~32 )); +// synopsys translate_off +defparam \Kp_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Kp_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N23 +dffeas \Kp_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[5]~31_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[5] .is_wysiwyg = "true"; +defparam \Kp_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N24 +cycloneive_lcell_comb \Kp_Out[6]~33 ( +// Equation(s): +// \Kp_Out[6]~33_combout = (Kp_Out[6] & (!\Kp_Out[5]~32 & VCC)) # (!Kp_Out[6] & (\Kp_Out[5]~32 $ (GND))) +// \Kp_Out[6]~34 = CARRY((!Kp_Out[6] & !\Kp_Out[5]~32 )) + + .dataa(gnd), + .datab(Kp_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[5]~32 ), + .combout(\Kp_Out[6]~33_combout ), + .cout(\Kp_Out[6]~34 )); +// synopsys translate_off +defparam \Kp_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Kp_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N25 +dffeas \Kp_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[6]~33_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[6] .is_wysiwyg = "true"; +defparam \Kp_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N26 +cycloneive_lcell_comb \Kp_Out[7]~35 ( +// Equation(s): +// \Kp_Out[7]~35_combout = (Kp_Out[7] & ((\Kp_Out[6]~34 ) # (GND))) # (!Kp_Out[7] & (!\Kp_Out[6]~34 )) +// \Kp_Out[7]~36 = CARRY((Kp_Out[7]) # (!\Kp_Out[6]~34 )) + + .dataa(Kp_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[6]~34 ), + .combout(\Kp_Out[7]~35_combout ), + .cout(\Kp_Out[7]~36 )); +// synopsys translate_off +defparam \Kp_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Kp_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N27 +dffeas \Kp_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[7]~35_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[7] .is_wysiwyg = "true"; +defparam \Kp_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N28 +cycloneive_lcell_comb \Kp_Out[8]~37 ( +// Equation(s): +// \Kp_Out[8]~37_combout = (Kp_Out[8] & (!\Kp_Out[7]~36 & VCC)) # (!Kp_Out[8] & (\Kp_Out[7]~36 $ (GND))) +// \Kp_Out[8]~38 = CARRY((!Kp_Out[8] & !\Kp_Out[7]~36 )) + + .dataa(gnd), + .datab(Kp_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[7]~36 ), + .combout(\Kp_Out[8]~37_combout ), + .cout(\Kp_Out[8]~38 )); +// synopsys translate_off +defparam \Kp_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Kp_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N29 +dffeas \Kp_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[8]~37_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[8] .is_wysiwyg = "true"; +defparam \Kp_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N30 +cycloneive_lcell_comb \Kp_Out[9]~39 ( +// Equation(s): +// \Kp_Out[9]~39_combout = (Kp_Out[9] & ((\Kp_Out[8]~38 ) # (GND))) # (!Kp_Out[9] & (!\Kp_Out[8]~38 )) +// \Kp_Out[9]~40 = CARRY((Kp_Out[9]) # (!\Kp_Out[8]~38 )) + + .dataa(Kp_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[8]~38 ), + .combout(\Kp_Out[9]~39_combout ), + .cout(\Kp_Out[9]~40 )); +// synopsys translate_off +defparam \Kp_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Kp_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N31 +dffeas \Kp_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[9]~39_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[9] .is_wysiwyg = "true"; +defparam \Kp_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \Kp_Out[10]~41 ( +// Equation(s): +// \Kp_Out[10]~41_combout = (Kp_Out[10] & (!\Kp_Out[9]~40 & VCC)) # (!Kp_Out[10] & (\Kp_Out[9]~40 $ (GND))) +// \Kp_Out[10]~42 = CARRY((!Kp_Out[10] & !\Kp_Out[9]~40 )) + + .dataa(gnd), + .datab(Kp_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[9]~40 ), + .combout(\Kp_Out[10]~41_combout ), + .cout(\Kp_Out[10]~42 )); +// synopsys translate_off +defparam \Kp_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Kp_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N1 +dffeas \Kp_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[10]~41_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[10] .is_wysiwyg = "true"; +defparam \Kp_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \Kp_Out[11]~43 ( +// Equation(s): +// \Kp_Out[11]~43_combout = (Kp_Out[11] & ((\Kp_Out[10]~42 ) # (GND))) # (!Kp_Out[11] & (!\Kp_Out[10]~42 )) +// \Kp_Out[11]~44 = CARRY((Kp_Out[11]) # (!\Kp_Out[10]~42 )) + + .dataa(gnd), + .datab(Kp_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[10]~42 ), + .combout(\Kp_Out[11]~43_combout ), + .cout(\Kp_Out[11]~44 )); +// synopsys translate_off +defparam \Kp_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Kp_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N3 +dffeas \Kp_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[11]~43_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[11] .is_wysiwyg = "true"; +defparam \Kp_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \Kp_Out[12]~45 ( +// Equation(s): +// \Kp_Out[12]~45_combout = (Kp_Out[12] & (!\Kp_Out[11]~44 & VCC)) # (!Kp_Out[12] & (\Kp_Out[11]~44 $ (GND))) +// \Kp_Out[12]~46 = CARRY((!Kp_Out[12] & !\Kp_Out[11]~44 )) + + .dataa(gnd), + .datab(Kp_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[11]~44 ), + .combout(\Kp_Out[12]~45_combout ), + .cout(\Kp_Out[12]~46 )); +// synopsys translate_off +defparam \Kp_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Kp_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N5 +dffeas \Kp_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[12]~45_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[12] .is_wysiwyg = "true"; +defparam \Kp_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \Kp_Out[13]~47 ( +// Equation(s): +// \Kp_Out[13]~47_combout = (Kp_Out[13] & ((\Kp_Out[12]~46 ) # (GND))) # (!Kp_Out[13] & (!\Kp_Out[12]~46 )) +// \Kp_Out[13]~48 = CARRY((Kp_Out[13]) # (!\Kp_Out[12]~46 )) + + .dataa(Kp_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[12]~46 ), + .combout(\Kp_Out[13]~47_combout ), + .cout(\Kp_Out[13]~48 )); +// synopsys translate_off +defparam \Kp_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Kp_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N7 +dffeas \Kp_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[13]~47_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[13] .is_wysiwyg = "true"; +defparam \Kp_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \Kp_Out[14]~49 ( +// Equation(s): +// \Kp_Out[14]~49_combout = (Kp_Out[14] & (!\Kp_Out[13]~48 & VCC)) # (!Kp_Out[14] & (\Kp_Out[13]~48 $ (GND))) +// \Kp_Out[14]~50 = CARRY((!Kp_Out[14] & !\Kp_Out[13]~48 )) + + .dataa(gnd), + .datab(Kp_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[13]~48 ), + .combout(\Kp_Out[14]~49_combout ), + .cout(\Kp_Out[14]~50 )); +// synopsys translate_off +defparam \Kp_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Kp_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N9 +dffeas \Kp_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[14]~49_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[14] .is_wysiwyg = "true"; +defparam \Kp_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \Kp_Out[15]~51 ( +// Equation(s): +// \Kp_Out[15]~51_combout = (Kp_Out[15] & ((\Kp_Out[14]~50 ) # (GND))) # (!Kp_Out[15] & (!\Kp_Out[14]~50 )) +// \Kp_Out[15]~52 = CARRY((Kp_Out[15]) # (!\Kp_Out[14]~50 )) + + .dataa(Kp_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[14]~50 ), + .combout(\Kp_Out[15]~51_combout ), + .cout(\Kp_Out[15]~52 )); +// synopsys translate_off +defparam \Kp_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Kp_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N11 +dffeas \Kp_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[15]~51_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[15] .is_wysiwyg = "true"; +defparam \Kp_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \Kp_Out[16]~53 ( +// Equation(s): +// \Kp_Out[16]~53_combout = (Kp_Out[16] & (!\Kp_Out[15]~52 & VCC)) # (!Kp_Out[16] & (\Kp_Out[15]~52 $ (GND))) +// \Kp_Out[16]~54 = CARRY((!Kp_Out[16] & !\Kp_Out[15]~52 )) + + .dataa(Kp_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[15]~52 ), + .combout(\Kp_Out[16]~53_combout ), + .cout(\Kp_Out[16]~54 )); +// synopsys translate_off +defparam \Kp_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Kp_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N13 +dffeas \Kp_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[16]~53_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[16] .is_wysiwyg = "true"; +defparam \Kp_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \Kp_Out[17]~55 ( +// Equation(s): +// \Kp_Out[17]~55_combout = (Kp_Out[17] & ((\Kp_Out[16]~54 ) # (GND))) # (!Kp_Out[17] & (!\Kp_Out[16]~54 )) +// \Kp_Out[17]~56 = CARRY((Kp_Out[17]) # (!\Kp_Out[16]~54 )) + + .dataa(gnd), + .datab(Kp_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[16]~54 ), + .combout(\Kp_Out[17]~55_combout ), + .cout(\Kp_Out[17]~56 )); +// synopsys translate_off +defparam \Kp_Out[17]~55 .lut_mask = 16'hC3CF; +defparam \Kp_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N15 +dffeas \Kp_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[17]~55_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[17] .is_wysiwyg = "true"; +defparam \Kp_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \Kp_Out[18]~57 ( +// Equation(s): +// \Kp_Out[18]~57_combout = (Kp_Out[18] & (!\Kp_Out[17]~56 & VCC)) # (!Kp_Out[18] & (\Kp_Out[17]~56 $ (GND))) +// \Kp_Out[18]~58 = CARRY((!Kp_Out[18] & !\Kp_Out[17]~56 )) + + .dataa(gnd), + .datab(Kp_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[17]~56 ), + .combout(\Kp_Out[18]~57_combout ), + .cout(\Kp_Out[18]~58 )); +// synopsys translate_off +defparam \Kp_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Kp_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N17 +dffeas \Kp_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[18]~57_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[18] .is_wysiwyg = "true"; +defparam \Kp_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \Kp_Out[19]~59 ( +// Equation(s): +// \Kp_Out[19]~59_combout = (Kp_Out[19] & ((\Kp_Out[18]~58 ) # (GND))) # (!Kp_Out[19] & (!\Kp_Out[18]~58 )) +// \Kp_Out[19]~60 = CARRY((Kp_Out[19]) # (!\Kp_Out[18]~58 )) + + .dataa(gnd), + .datab(Kp_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[18]~58 ), + .combout(\Kp_Out[19]~59_combout ), + .cout(\Kp_Out[19]~60 )); +// synopsys translate_off +defparam \Kp_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Kp_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N19 +dffeas \Kp_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[19]~59_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[19] .is_wysiwyg = "true"; +defparam \Kp_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \Kp_Out[20]~61 ( +// Equation(s): +// \Kp_Out[20]~61_combout = \Kp_Out[19]~60 $ (Kp_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Kp_Out[20]), + .cin(\Kp_Out[19]~60 ), + .combout(\Kp_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Kp_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Kp_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \Kp_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[20]~61_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT20 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[20] .is_wysiwyg = "true"; +defparam \Kp_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N12 +cycloneive_lcell_comb \Add5~0 ( +// Equation(s): +// \Add5~0_combout = (Kp_Out[0] & ((GND) # (!Ki_Out[0]))) # (!Kp_Out[0] & (Ki_Out[0] $ (GND))) +// \Add5~1 = CARRY((Kp_Out[0]) # (!Ki_Out[0])) + + .dataa(Kp_Out[0]), + .datab(Ki_Out[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add5~0_combout ), + .cout(\Add5~1 )); +// synopsys translate_off +defparam \Add5~0 .lut_mask = 16'h66BB; +defparam \Add5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N14 +cycloneive_lcell_comb \Add5~2 ( +// Equation(s): +// \Add5~2_combout = (Ki_Out[1] & ((Kp_Out[1] & (!\Add5~1 )) # (!Kp_Out[1] & ((\Add5~1 ) # (GND))))) # (!Ki_Out[1] & ((Kp_Out[1] & (\Add5~1 & VCC)) # (!Kp_Out[1] & (!\Add5~1 )))) +// \Add5~3 = CARRY((Ki_Out[1] & ((!\Add5~1 ) # (!Kp_Out[1]))) # (!Ki_Out[1] & (!Kp_Out[1] & !\Add5~1 ))) + + .dataa(Ki_Out[1]), + .datab(Kp_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~1 ), + .combout(\Add5~2_combout ), + .cout(\Add5~3 )); +// synopsys translate_off +defparam \Add5~2 .lut_mask = 16'h692B; +defparam \Add5~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N16 +cycloneive_lcell_comb \Add5~4 ( +// Equation(s): +// \Add5~4_combout = ((Kp_Out[2] $ (Ki_Out[2] $ (\Add5~3 )))) # (GND) +// \Add5~5 = CARRY((Kp_Out[2] & ((!\Add5~3 ) # (!Ki_Out[2]))) # (!Kp_Out[2] & (!Ki_Out[2] & !\Add5~3 ))) + + .dataa(Kp_Out[2]), + .datab(Ki_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~3 ), + .combout(\Add5~4_combout ), + .cout(\Add5~5 )); +// synopsys translate_off +defparam \Add5~4 .lut_mask = 16'h962B; +defparam \Add5~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N18 +cycloneive_lcell_comb \Add5~6 ( +// Equation(s): +// \Add5~6_combout = (Kp_Out[3] & ((Ki_Out[3] & (!\Add5~5 )) # (!Ki_Out[3] & (\Add5~5 & VCC)))) # (!Kp_Out[3] & ((Ki_Out[3] & ((\Add5~5 ) # (GND))) # (!Ki_Out[3] & (!\Add5~5 )))) +// \Add5~7 = CARRY((Kp_Out[3] & (Ki_Out[3] & !\Add5~5 )) # (!Kp_Out[3] & ((Ki_Out[3]) # (!\Add5~5 )))) + + .dataa(Kp_Out[3]), + .datab(Ki_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~5 ), + .combout(\Add5~6_combout ), + .cout(\Add5~7 )); +// synopsys translate_off +defparam \Add5~6 .lut_mask = 16'h694D; +defparam \Add5~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N20 +cycloneive_lcell_comb \Add5~8 ( +// Equation(s): +// \Add5~8_combout = ((Ki_Out[4] $ (Kp_Out[4] $ (\Add5~7 )))) # (GND) +// \Add5~9 = CARRY((Ki_Out[4] & (Kp_Out[4] & !\Add5~7 )) # (!Ki_Out[4] & ((Kp_Out[4]) # (!\Add5~7 )))) + + .dataa(Ki_Out[4]), + .datab(Kp_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~7 ), + .combout(\Add5~8_combout ), + .cout(\Add5~9 )); +// synopsys translate_off +defparam \Add5~8 .lut_mask = 16'h964D; +defparam \Add5~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N22 +cycloneive_lcell_comb \Add5~10 ( +// Equation(s): +// \Add5~10_combout = (Ki_Out[5] & ((Kp_Out[5] & (!\Add5~9 )) # (!Kp_Out[5] & ((\Add5~9 ) # (GND))))) # (!Ki_Out[5] & ((Kp_Out[5] & (\Add5~9 & VCC)) # (!Kp_Out[5] & (!\Add5~9 )))) +// \Add5~11 = CARRY((Ki_Out[5] & ((!\Add5~9 ) # (!Kp_Out[5]))) # (!Ki_Out[5] & (!Kp_Out[5] & !\Add5~9 ))) + + .dataa(Ki_Out[5]), + .datab(Kp_Out[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~9 ), + .combout(\Add5~10_combout ), + .cout(\Add5~11 )); +// synopsys translate_off +defparam \Add5~10 .lut_mask = 16'h692B; +defparam \Add5~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N24 +cycloneive_lcell_comb \Add5~12 ( +// Equation(s): +// \Add5~12_combout = ((Ki_Out[6] $ (Kp_Out[6] $ (\Add5~11 )))) # (GND) +// \Add5~13 = CARRY((Ki_Out[6] & (Kp_Out[6] & !\Add5~11 )) # (!Ki_Out[6] & ((Kp_Out[6]) # (!\Add5~11 )))) + + .dataa(Ki_Out[6]), + .datab(Kp_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~11 ), + .combout(\Add5~12_combout ), + .cout(\Add5~13 )); +// synopsys translate_off +defparam \Add5~12 .lut_mask = 16'h964D; +defparam \Add5~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N26 +cycloneive_lcell_comb \Add5~14 ( +// Equation(s): +// \Add5~14_combout = (Kp_Out[7] & ((Ki_Out[7] & (!\Add5~13 )) # (!Ki_Out[7] & (\Add5~13 & VCC)))) # (!Kp_Out[7] & ((Ki_Out[7] & ((\Add5~13 ) # (GND))) # (!Ki_Out[7] & (!\Add5~13 )))) +// \Add5~15 = CARRY((Kp_Out[7] & (Ki_Out[7] & !\Add5~13 )) # (!Kp_Out[7] & ((Ki_Out[7]) # (!\Add5~13 )))) + + .dataa(Kp_Out[7]), + .datab(Ki_Out[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~13 ), + .combout(\Add5~14_combout ), + .cout(\Add5~15 )); +// synopsys translate_off +defparam \Add5~14 .lut_mask = 16'h694D; +defparam \Add5~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N28 +cycloneive_lcell_comb \Add5~24 ( +// Equation(s): +// \Add5~24_combout = ((Kp_Out[8] $ (Ki_Out[8] $ (\Add5~15 )))) # (GND) +// \Add5~25 = CARRY((Kp_Out[8] & ((!\Add5~15 ) # (!Ki_Out[8]))) # (!Kp_Out[8] & (!Ki_Out[8] & !\Add5~15 ))) + + .dataa(Kp_Out[8]), + .datab(Ki_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~15 ), + .combout(\Add5~24_combout ), + .cout(\Add5~25 )); +// synopsys translate_off +defparam \Add5~24 .lut_mask = 16'h962B; +defparam \Add5~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N30 +cycloneive_lcell_comb \Add5~27 ( +// Equation(s): +// \Add5~27_combout = (Ki_Out[9] & ((Kp_Out[9] & (!\Add5~25 )) # (!Kp_Out[9] & ((\Add5~25 ) # (GND))))) # (!Ki_Out[9] & ((Kp_Out[9] & (\Add5~25 & VCC)) # (!Kp_Out[9] & (!\Add5~25 )))) +// \Add5~28 = CARRY((Ki_Out[9] & ((!\Add5~25 ) # (!Kp_Out[9]))) # (!Ki_Out[9] & (!Kp_Out[9] & !\Add5~25 ))) + + .dataa(Ki_Out[9]), + .datab(Kp_Out[9]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~25 ), + .combout(\Add5~27_combout ), + .cout(\Add5~28 )); +// synopsys translate_off +defparam \Add5~27 .lut_mask = 16'h692B; +defparam \Add5~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N0 +cycloneive_lcell_comb \Add5~30 ( +// Equation(s): +// \Add5~30_combout = ((Kp_Out[10] $ (Ki_Out[10] $ (\Add5~28 )))) # (GND) +// \Add5~31 = CARRY((Kp_Out[10] & ((!\Add5~28 ) # (!Ki_Out[10]))) # (!Kp_Out[10] & (!Ki_Out[10] & !\Add5~28 ))) + + .dataa(Kp_Out[10]), + .datab(Ki_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~28 ), + .combout(\Add5~30_combout ), + .cout(\Add5~31 )); +// synopsys translate_off +defparam \Add5~30 .lut_mask = 16'h962B; +defparam \Add5~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N2 +cycloneive_lcell_comb \Add5~33 ( +// Equation(s): +// \Add5~33_combout = (Ki_Out[11] & ((Kp_Out[11] & (!\Add5~31 )) # (!Kp_Out[11] & ((\Add5~31 ) # (GND))))) # (!Ki_Out[11] & ((Kp_Out[11] & (\Add5~31 & VCC)) # (!Kp_Out[11] & (!\Add5~31 )))) +// \Add5~34 = CARRY((Ki_Out[11] & ((!\Add5~31 ) # (!Kp_Out[11]))) # (!Ki_Out[11] & (!Kp_Out[11] & !\Add5~31 ))) + + .dataa(Ki_Out[11]), + .datab(Kp_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~31 ), + .combout(\Add5~33_combout ), + .cout(\Add5~34 )); +// synopsys translate_off +defparam \Add5~33 .lut_mask = 16'h692B; +defparam \Add5~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N4 +cycloneive_lcell_comb \Add5~36 ( +// Equation(s): +// \Add5~36_combout = ((Ki_Out[12] $ (Kp_Out[12] $ (\Add5~34 )))) # (GND) +// \Add5~37 = CARRY((Ki_Out[12] & (Kp_Out[12] & !\Add5~34 )) # (!Ki_Out[12] & ((Kp_Out[12]) # (!\Add5~34 )))) + + .dataa(Ki_Out[12]), + .datab(Kp_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~34 ), + .combout(\Add5~36_combout ), + .cout(\Add5~37 )); +// synopsys translate_off +defparam \Add5~36 .lut_mask = 16'h964D; +defparam \Add5~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N6 +cycloneive_lcell_comb \Add5~39 ( +// Equation(s): +// \Add5~39_combout = (Ki_Out[13] & ((Kp_Out[13] & (!\Add5~37 )) # (!Kp_Out[13] & ((\Add5~37 ) # (GND))))) # (!Ki_Out[13] & ((Kp_Out[13] & (\Add5~37 & VCC)) # (!Kp_Out[13] & (!\Add5~37 )))) +// \Add5~40 = CARRY((Ki_Out[13] & ((!\Add5~37 ) # (!Kp_Out[13]))) # (!Ki_Out[13] & (!Kp_Out[13] & !\Add5~37 ))) + + .dataa(Ki_Out[13]), + .datab(Kp_Out[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~37 ), + .combout(\Add5~39_combout ), + .cout(\Add5~40 )); +// synopsys translate_off +defparam \Add5~39 .lut_mask = 16'h692B; +defparam \Add5~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N8 +cycloneive_lcell_comb \Add5~42 ( +// Equation(s): +// \Add5~42_combout = ((Kp_Out[14] $ (Ki_Out[14] $ (\Add5~40 )))) # (GND) +// \Add5~43 = CARRY((Kp_Out[14] & ((!\Add5~40 ) # (!Ki_Out[14]))) # (!Kp_Out[14] & (!Ki_Out[14] & !\Add5~40 ))) + + .dataa(Kp_Out[14]), + .datab(Ki_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~40 ), + .combout(\Add5~42_combout ), + .cout(\Add5~43 )); +// synopsys translate_off +defparam \Add5~42 .lut_mask = 16'h962B; +defparam \Add5~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N10 +cycloneive_lcell_comb \Add5~45 ( +// Equation(s): +// \Add5~45_combout = (Ki_Out[15] & ((Kp_Out[15] & (!\Add5~43 )) # (!Kp_Out[15] & ((\Add5~43 ) # (GND))))) # (!Ki_Out[15] & ((Kp_Out[15] & (\Add5~43 & VCC)) # (!Kp_Out[15] & (!\Add5~43 )))) +// \Add5~46 = CARRY((Ki_Out[15] & ((!\Add5~43 ) # (!Kp_Out[15]))) # (!Ki_Out[15] & (!Kp_Out[15] & !\Add5~43 ))) + + .dataa(Ki_Out[15]), + .datab(Kp_Out[15]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~43 ), + .combout(\Add5~45_combout ), + .cout(\Add5~46 )); +// synopsys translate_off +defparam \Add5~45 .lut_mask = 16'h692B; +defparam \Add5~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N12 +cycloneive_lcell_comb \Add5~48 ( +// Equation(s): +// \Add5~48_combout = ((Ki_Out[16] $ (Kp_Out[16] $ (\Add5~46 )))) # (GND) +// \Add5~49 = CARRY((Ki_Out[16] & (Kp_Out[16] & !\Add5~46 )) # (!Ki_Out[16] & ((Kp_Out[16]) # (!\Add5~46 )))) + + .dataa(Ki_Out[16]), + .datab(Kp_Out[16]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~46 ), + .combout(\Add5~48_combout ), + .cout(\Add5~49 )); +// synopsys translate_off +defparam \Add5~48 .lut_mask = 16'h964D; +defparam \Add5~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N14 +cycloneive_lcell_comb \Add5~51 ( +// Equation(s): +// \Add5~51_combout = (Kp_Out[17] & ((Ki_Out[17] & (!\Add5~49 )) # (!Ki_Out[17] & (\Add5~49 & VCC)))) # (!Kp_Out[17] & ((Ki_Out[17] & ((\Add5~49 ) # (GND))) # (!Ki_Out[17] & (!\Add5~49 )))) +// \Add5~52 = CARRY((Kp_Out[17] & (Ki_Out[17] & !\Add5~49 )) # (!Kp_Out[17] & ((Ki_Out[17]) # (!\Add5~49 )))) + + .dataa(Kp_Out[17]), + .datab(Ki_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~49 ), + .combout(\Add5~51_combout ), + .cout(\Add5~52 )); +// synopsys translate_off +defparam \Add5~51 .lut_mask = 16'h694D; +defparam \Add5~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N16 +cycloneive_lcell_comb \Add5~54 ( +// Equation(s): +// \Add5~54_combout = ((Kp_Out[18] $ (Ki_Out[18] $ (\Add5~52 )))) # (GND) +// \Add5~55 = CARRY((Kp_Out[18] & ((!\Add5~52 ) # (!Ki_Out[18]))) # (!Kp_Out[18] & (!Ki_Out[18] & !\Add5~52 ))) + + .dataa(Kp_Out[18]), + .datab(Ki_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~52 ), + .combout(\Add5~54_combout ), + .cout(\Add5~55 )); +// synopsys translate_off +defparam \Add5~54 .lut_mask = 16'h962B; +defparam \Add5~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N18 +cycloneive_lcell_comb \Add5~57 ( +// Equation(s): +// \Add5~57_combout = (Kp_Out[19] & ((Ki_Out[19] & (!\Add5~55 )) # (!Ki_Out[19] & (\Add5~55 & VCC)))) # (!Kp_Out[19] & ((Ki_Out[19] & ((\Add5~55 ) # (GND))) # (!Ki_Out[19] & (!\Add5~55 )))) +// \Add5~58 = CARRY((Kp_Out[19] & (Ki_Out[19] & !\Add5~55 )) # (!Kp_Out[19] & ((Ki_Out[19]) # (!\Add5~55 )))) + + .dataa(Kp_Out[19]), + .datab(Ki_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~55 ), + .combout(\Add5~57_combout ), + .cout(\Add5~58 )); +// synopsys translate_off +defparam \Add5~57 .lut_mask = 16'h694D; +defparam \Add5~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N20 +cycloneive_lcell_comb \Add5~60 ( +// Equation(s): +// \Add5~60_combout = Ki_Out[20] $ (\Add5~58 $ (Kp_Out[20])) + + .dataa(Ki_Out[20]), + .datab(gnd), + .datac(gnd), + .datad(Kp_Out[20]), + .cin(\Add5~58 ), + .combout(\Add5~60_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~60 .lut_mask = 16'hA55A; +defparam \Add5~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N12 +cycloneive_lcell_comb \Add5~62 ( +// Equation(s): +// \Add5~62_combout = (!\Vout[13]~reg0_q & \Add5~60_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~60_combout ), + .cin(gnd), + .combout(\Add5~62_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~62 .lut_mask = 16'h0F00; +defparam \Add5~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N10 +cycloneive_lcell_comb \Add7~19 ( +// Equation(s): +// \Add7~19_combout = (!\Vout[13]~reg0_q & Kd_Out[19]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[19]), + .cin(gnd), + .combout(\Add7~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~19 .lut_mask = 16'h0F00; +defparam \Add7~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N16 +cycloneive_lcell_comb \Add7~18 ( +// Equation(s): +// \Add7~18_combout = (!\Vout[13]~reg0_q & Kd_Out[18]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[18]), + .cin(gnd), + .combout(\Add7~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~18 .lut_mask = 16'h0F00; +defparam \Add7~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N10 +cycloneive_lcell_comb \Add7~17 ( +// Equation(s): +// \Add7~17_combout = (Kd_Out[17] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[17]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~17 .lut_mask = 16'h00F0; +defparam \Add7~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N20 +cycloneive_lcell_comb \Add7~16 ( +// Equation(s): +// \Add7~16_combout = (Kd_Out[16] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[16]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~16 .lut_mask = 16'h00F0; +defparam \Add7~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N26 +cycloneive_lcell_comb \Add7~15 ( +// Equation(s): +// \Add7~15_combout = (!\Vout[13]~reg0_q & Kd_Out[15]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[15]), + .cin(gnd), + .combout(\Add7~15_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~15 .lut_mask = 16'h0F00; +defparam \Add7~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N4 +cycloneive_lcell_comb \Add7~14 ( +// Equation(s): +// \Add7~14_combout = (!\Vout[13]~reg0_q & Kd_Out[14]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[14]), + .cin(gnd), + .combout(\Add7~14_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~14 .lut_mask = 16'h0F00; +defparam \Add7~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N2 +cycloneive_lcell_comb \Add7~13 ( +// Equation(s): +// \Add7~13_combout = (Kd_Out[13] & !\Vout[13]~reg0_q ) + + .dataa(Kd_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~13_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~13 .lut_mask = 16'h00AA; +defparam \Add7~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N14 +cycloneive_lcell_comb \Add7~12 ( +// Equation(s): +// \Add7~12_combout = (Kd_Out[12] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(Kd_Out[12]), + .datac(\Vout[13]~reg0_q ), + .datad(gnd), + .cin(gnd), + .combout(\Add7~12_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~12 .lut_mask = 16'h0C0C; +defparam \Add7~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N20 +cycloneive_lcell_comb \Add7~11 ( +// Equation(s): +// \Add7~11_combout = (!\Vout[13]~reg0_q & Kd_Out[11]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[11]), + .cin(gnd), + .combout(\Add7~11_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~11 .lut_mask = 16'h0F00; +defparam \Add7~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N16 +cycloneive_lcell_comb \Add7~10 ( +// Equation(s): +// \Add7~10_combout = (Kd_Out[10] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[10]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~10_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~10 .lut_mask = 16'h00F0; +defparam \Add7~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N12 +cycloneive_lcell_comb \Add7~9 ( +// Equation(s): +// \Add7~9_combout = (Kd_Out[9] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[9]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~9_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~9 .lut_mask = 16'h00F0; +defparam \Add7~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N16 +cycloneive_lcell_comb \Add7~8 ( +// Equation(s): +// \Add7~8_combout = (!\Vout[13]~reg0_q & Kd_Out[8]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[8]), + .cin(gnd), + .combout(\Add7~8_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~8 .lut_mask = 16'h5500; +defparam \Add7~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N8 +cycloneive_lcell_comb \Add5~16 ( +// Equation(s): +// \Add5~16_combout = (\Vout[13]~reg0_q & (!\Vout[0]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~14_combout ))) + + .dataa(\Vout[0]~reg0_q ), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~14_combout ), + .cin(gnd), + .combout(\Add5~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~16 .lut_mask = 16'h5F50; +defparam \Add5~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y14_N0 +cycloneive_lcell_comb \Add7~1 ( +// Equation(s): +// \Add7~1_combout = (!\Vout[13]~reg0_q & Kd_Out[6]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[6]), + .cin(gnd), + .combout(\Add7~1_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~1 .lut_mask = 16'h0F00; +defparam \Add7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N0 +cycloneive_lcell_comb \Add5~17 ( +// Equation(s): +// \Add5~17_combout = (!\Vout[13]~reg0_q & \Add5~12_combout ) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\Add5~12_combout ), + .cin(gnd), + .combout(\Add5~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~17 .lut_mask = 16'h5500; +defparam \Add5~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N8 +cycloneive_lcell_comb \Add7~2 ( +// Equation(s): +// \Add7~2_combout = (!\Vout[13]~reg0_q & Kd_Out[5]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[5]), + .cin(gnd), + .combout(\Add7~2_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~2 .lut_mask = 16'h5500; +defparam \Add7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N10 +cycloneive_lcell_comb \Add5~18 ( +// Equation(s): +// \Add5~18_combout = (\Add5~10_combout & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Add5~10_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~18 .lut_mask = 16'h00F0; +defparam \Add5~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N4 +cycloneive_lcell_comb \Add7~3 ( +// Equation(s): +// \Add7~3_combout = (Kd_Out[4] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(Kd_Out[4]), + .datac(gnd), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~3_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~3 .lut_mask = 16'h00CC; +defparam \Add7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N2 +cycloneive_lcell_comb \Add5~19 ( +// Equation(s): +// \Add5~19_combout = (!\Vout[13]~reg0_q & \Add5~8_combout ) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~19 .lut_mask = 16'h3030; +defparam \Add5~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N2 +cycloneive_lcell_comb \Add5~20 ( +// Equation(s): +// \Add5~20_combout = (!\Vout[13]~reg0_q & \Add5~6_combout ) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\Add5~6_combout ), + .cin(gnd), + .combout(\Add5~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~20 .lut_mask = 16'h5500; +defparam \Add5~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N8 +cycloneive_lcell_comb \Add7~4 ( +// Equation(s): +// \Add7~4_combout = (!\Vout[13]~reg0_q & Kd_Out[3]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[3]), + .cin(gnd), + .combout(\Add7~4_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~4 .lut_mask = 16'h5500; +defparam \Add7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N14 +cycloneive_lcell_comb \Add7~5 ( +// Equation(s): +// \Add7~5_combout = (Kd_Out[2] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[2]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~5_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~5 .lut_mask = 16'h00F0; +defparam \Add7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N0 +cycloneive_lcell_comb \Add5~21 ( +// Equation(s): +// \Add5~21_combout = (!\Vout[13]~reg0_q & \Add5~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~4_combout ), + .cin(gnd), + .combout(\Add5~21_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~21 .lut_mask = 16'h0F00; +defparam \Add5~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N6 +cycloneive_lcell_comb \Add7~6 ( +// Equation(s): +// \Add7~6_combout = (Kd_Out[1] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[1]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~6_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~6 .lut_mask = 16'h00F0; +defparam \Add7~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N8 +cycloneive_lcell_comb \Add5~22 ( +// Equation(s): +// \Add5~22_combout = (\Add5~2_combout & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Add5~2_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~22_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~22 .lut_mask = 16'h00F0; +defparam \Add5~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N10 +cycloneive_lcell_comb \Add5~23 ( +// Equation(s): +// \Add5~23_combout = (!\Vout[13]~reg0_q & \Add5~0_combout ) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~23_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~23 .lut_mask = 16'h3030; +defparam \Add5~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N22 +cycloneive_lcell_comb \Add7~7 ( +// Equation(s): +// \Add7~7_combout = (Kd_Out[0] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[0]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~7_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~7 .lut_mask = 16'h00F0; +defparam \Add7~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N12 +cycloneive_lcell_comb \Vout[0]~15 ( +// Equation(s): +// \Vout[0]~15_cout = CARRY((\Add5~23_combout & \Add7~7_combout )) + + .dataa(\Add5~23_combout ), + .datab(\Add7~7_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\Vout[0]~15_cout )); +// synopsys translate_off +defparam \Vout[0]~15 .lut_mask = 16'h0088; +defparam \Vout[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N14 +cycloneive_lcell_comb \Vout[0]~17 ( +// Equation(s): +// \Vout[0]~17_cout = CARRY((\Add7~6_combout & (!\Add5~22_combout & !\Vout[0]~15_cout )) # (!\Add7~6_combout & ((!\Vout[0]~15_cout ) # (!\Add5~22_combout )))) + + .dataa(\Add7~6_combout ), + .datab(\Add5~22_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~15_cout ), + .combout(), + .cout(\Vout[0]~17_cout )); +// synopsys translate_off +defparam \Vout[0]~17 .lut_mask = 16'h0017; +defparam \Vout[0]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N16 +cycloneive_lcell_comb \Vout[0]~19 ( +// Equation(s): +// \Vout[0]~19_cout = CARRY((\Add7~5_combout & ((\Add5~21_combout ) # (!\Vout[0]~17_cout ))) # (!\Add7~5_combout & (\Add5~21_combout & !\Vout[0]~17_cout ))) + + .dataa(\Add7~5_combout ), + .datab(\Add5~21_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~17_cout ), + .combout(), + .cout(\Vout[0]~19_cout )); +// synopsys translate_off +defparam \Vout[0]~19 .lut_mask = 16'h008E; +defparam \Vout[0]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N18 +cycloneive_lcell_comb \Vout[0]~21 ( +// Equation(s): +// \Vout[0]~21_cout = CARRY((\Add5~20_combout & (!\Add7~4_combout & !\Vout[0]~19_cout )) # (!\Add5~20_combout & ((!\Vout[0]~19_cout ) # (!\Add7~4_combout )))) + + .dataa(\Add5~20_combout ), + .datab(\Add7~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~19_cout ), + .combout(), + .cout(\Vout[0]~21_cout )); +// synopsys translate_off +defparam \Vout[0]~21 .lut_mask = 16'h0017; +defparam \Vout[0]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N20 +cycloneive_lcell_comb \Vout[0]~23 ( +// Equation(s): +// \Vout[0]~23_cout = CARRY((\Add7~3_combout & ((\Add5~19_combout ) # (!\Vout[0]~21_cout ))) # (!\Add7~3_combout & (\Add5~19_combout & !\Vout[0]~21_cout ))) + + .dataa(\Add7~3_combout ), + .datab(\Add5~19_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~21_cout ), + .combout(), + .cout(\Vout[0]~23_cout )); +// synopsys translate_off +defparam \Vout[0]~23 .lut_mask = 16'h008E; +defparam \Vout[0]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N22 +cycloneive_lcell_comb \Vout[0]~25 ( +// Equation(s): +// \Vout[0]~25_cout = CARRY((\Add7~2_combout & (!\Add5~18_combout & !\Vout[0]~23_cout )) # (!\Add7~2_combout & ((!\Vout[0]~23_cout ) # (!\Add5~18_combout )))) + + .dataa(\Add7~2_combout ), + .datab(\Add5~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~23_cout ), + .combout(), + .cout(\Vout[0]~25_cout )); +// synopsys translate_off +defparam \Vout[0]~25 .lut_mask = 16'h0017; +defparam \Vout[0]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N24 +cycloneive_lcell_comb \Vout[0]~27 ( +// Equation(s): +// \Vout[0]~27_cout = CARRY((\Add7~1_combout & ((\Add5~17_combout ) # (!\Vout[0]~25_cout ))) # (!\Add7~1_combout & (\Add5~17_combout & !\Vout[0]~25_cout ))) + + .dataa(\Add7~1_combout ), + .datab(\Add5~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~25_cout ), + .combout(), + .cout(\Vout[0]~27_cout )); +// synopsys translate_off +defparam \Vout[0]~27 .lut_mask = 16'h008E; +defparam \Vout[0]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N26 +cycloneive_lcell_comb \Vout[0]~28 ( +// Equation(s): +// \Vout[0]~28_combout = (\Add7~0_combout & ((\Add5~16_combout & (\Vout[0]~27_cout & VCC)) # (!\Add5~16_combout & (!\Vout[0]~27_cout )))) # (!\Add7~0_combout & ((\Add5~16_combout & (!\Vout[0]~27_cout )) # (!\Add5~16_combout & ((\Vout[0]~27_cout ) # +// (GND))))) +// \Vout[0]~29 = CARRY((\Add7~0_combout & (!\Add5~16_combout & !\Vout[0]~27_cout )) # (!\Add7~0_combout & ((!\Vout[0]~27_cout ) # (!\Add5~16_combout )))) + + .dataa(\Add7~0_combout ), + .datab(\Add5~16_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~27_cout ), + .combout(\Vout[0]~28_combout ), + .cout(\Vout[0]~29 )); +// synopsys translate_off +defparam \Vout[0]~28 .lut_mask = 16'h9617; +defparam \Vout[0]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N28 +cycloneive_lcell_comb \Vout[1]~30 ( +// Equation(s): +// \Vout[1]~30_combout = ((\Add7~8_combout $ (\Add5~26_combout $ (!\Vout[0]~29 )))) # (GND) +// \Vout[1]~31 = CARRY((\Add7~8_combout & ((\Add5~26_combout ) # (!\Vout[0]~29 ))) # (!\Add7~8_combout & (\Add5~26_combout & !\Vout[0]~29 ))) + + .dataa(\Add7~8_combout ), + .datab(\Add5~26_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~29 ), + .combout(\Vout[1]~30_combout ), + .cout(\Vout[1]~31 )); +// synopsys translate_off +defparam \Vout[1]~30 .lut_mask = 16'h698E; +defparam \Vout[1]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y18_N29 +dffeas \Vout[1]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[1]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[1]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[1]~reg0 .is_wysiwyg = "true"; +defparam \Vout[1]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N4 +cycloneive_lcell_comb \Add5~26 ( +// Equation(s): +// \Add5~26_combout = (\Vout[13]~reg0_q & (!\Vout[1]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~24_combout ))) + + .dataa(gnd), + .datab(\Vout[1]~reg0_q ), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~24_combout ), + .cin(gnd), + .combout(\Add5~26_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~26 .lut_mask = 16'h3F30; +defparam \Add5~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N30 +cycloneive_lcell_comb \Vout[2]~32 ( +// Equation(s): +// \Vout[2]~32_combout = (\Add5~29_combout & ((\Add7~9_combout & (\Vout[1]~31 & VCC)) # (!\Add7~9_combout & (!\Vout[1]~31 )))) # (!\Add5~29_combout & ((\Add7~9_combout & (!\Vout[1]~31 )) # (!\Add7~9_combout & ((\Vout[1]~31 ) # (GND))))) +// \Vout[2]~33 = CARRY((\Add5~29_combout & (!\Add7~9_combout & !\Vout[1]~31 )) # (!\Add5~29_combout & ((!\Vout[1]~31 ) # (!\Add7~9_combout )))) + + .dataa(\Add5~29_combout ), + .datab(\Add7~9_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[1]~31 ), + .combout(\Vout[2]~32_combout ), + .cout(\Vout[2]~33 )); +// synopsys translate_off +defparam \Vout[2]~32 .lut_mask = 16'h9617; +defparam \Vout[2]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y18_N31 +dffeas \Vout[2]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[2]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[2]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[2]~reg0 .is_wysiwyg = "true"; +defparam \Vout[2]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N6 +cycloneive_lcell_comb \Add5~29 ( +// Equation(s): +// \Add5~29_combout = (\Vout[13]~reg0_q & (!\Vout[2]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~27_combout ))) + + .dataa(\Vout[2]~reg0_q ), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~27_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~29_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~29 .lut_mask = 16'h7474; +defparam \Add5~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N0 +cycloneive_lcell_comb \Vout[3]~34 ( +// Equation(s): +// \Vout[3]~34_combout = ((\Add5~32_combout $ (\Add7~10_combout $ (!\Vout[2]~33 )))) # (GND) +// \Vout[3]~35 = CARRY((\Add5~32_combout & ((\Add7~10_combout ) # (!\Vout[2]~33 ))) # (!\Add5~32_combout & (\Add7~10_combout & !\Vout[2]~33 ))) + + .dataa(\Add5~32_combout ), + .datab(\Add7~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[2]~33 ), + .combout(\Vout[3]~34_combout ), + .cout(\Vout[3]~35 )); +// synopsys translate_off +defparam \Vout[3]~34 .lut_mask = 16'h698E; +defparam \Vout[3]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N1 +dffeas \Vout[3]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[3]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[3]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[3]~reg0 .is_wysiwyg = "true"; +defparam \Vout[3]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N26 +cycloneive_lcell_comb \Add5~32 ( +// Equation(s): +// \Add5~32_combout = (\Vout[13]~reg0_q & ((!\Vout[3]~reg0_q ))) # (!\Vout[13]~reg0_q & (\Add5~30_combout )) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~30_combout ), + .datad(\Vout[3]~reg0_q ), + .cin(gnd), + .combout(\Add5~32_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~32 .lut_mask = 16'h30FC; +defparam \Add5~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N2 +cycloneive_lcell_comb \Vout[4]~36 ( +// Equation(s): +// \Vout[4]~36_combout = (\Add5~35_combout & ((\Add7~11_combout & (\Vout[3]~35 & VCC)) # (!\Add7~11_combout & (!\Vout[3]~35 )))) # (!\Add5~35_combout & ((\Add7~11_combout & (!\Vout[3]~35 )) # (!\Add7~11_combout & ((\Vout[3]~35 ) # (GND))))) +// \Vout[4]~37 = CARRY((\Add5~35_combout & (!\Add7~11_combout & !\Vout[3]~35 )) # (!\Add5~35_combout & ((!\Vout[3]~35 ) # (!\Add7~11_combout )))) + + .dataa(\Add5~35_combout ), + .datab(\Add7~11_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[3]~35 ), + .combout(\Vout[4]~36_combout ), + .cout(\Vout[4]~37 )); +// synopsys translate_off +defparam \Vout[4]~36 .lut_mask = 16'h9617; +defparam \Vout[4]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N3 +dffeas \Vout[4]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[4]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[4]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[4]~reg0 .is_wysiwyg = "true"; +defparam \Vout[4]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N30 +cycloneive_lcell_comb \Add5~35 ( +// Equation(s): +// \Add5~35_combout = (\Vout[13]~reg0_q & (!\Vout[4]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~33_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[4]~reg0_q ), + .datad(\Add5~33_combout ), + .cin(gnd), + .combout(\Add5~35_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~35 .lut_mask = 16'h3F0C; +defparam \Add5~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N4 +cycloneive_lcell_comb \Vout[5]~38 ( +// Equation(s): +// \Vout[5]~38_combout = ((\Add7~12_combout $ (\Add5~38_combout $ (!\Vout[4]~37 )))) # (GND) +// \Vout[5]~39 = CARRY((\Add7~12_combout & ((\Add5~38_combout ) # (!\Vout[4]~37 ))) # (!\Add7~12_combout & (\Add5~38_combout & !\Vout[4]~37 ))) + + .dataa(\Add7~12_combout ), + .datab(\Add5~38_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[4]~37 ), + .combout(\Vout[5]~38_combout ), + .cout(\Vout[5]~39 )); +// synopsys translate_off +defparam \Vout[5]~38 .lut_mask = 16'h698E; +defparam \Vout[5]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N5 +dffeas \Vout[5]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[5]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[5]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[5]~reg0 .is_wysiwyg = "true"; +defparam \Vout[5]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N28 +cycloneive_lcell_comb \Add5~38 ( +// Equation(s): +// \Add5~38_combout = (\Vout[13]~reg0_q & (!\Vout[5]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~36_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[5]~reg0_q ), + .datad(\Add5~36_combout ), + .cin(gnd), + .combout(\Add5~38_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~38 .lut_mask = 16'h3F0C; +defparam \Add5~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N6 +cycloneive_lcell_comb \Vout[6]~40 ( +// Equation(s): +// \Vout[6]~40_combout = (\Add7~13_combout & ((\Add5~41_combout & (\Vout[5]~39 & VCC)) # (!\Add5~41_combout & (!\Vout[5]~39 )))) # (!\Add7~13_combout & ((\Add5~41_combout & (!\Vout[5]~39 )) # (!\Add5~41_combout & ((\Vout[5]~39 ) # (GND))))) +// \Vout[6]~41 = CARRY((\Add7~13_combout & (!\Add5~41_combout & !\Vout[5]~39 )) # (!\Add7~13_combout & ((!\Vout[5]~39 ) # (!\Add5~41_combout )))) + + .dataa(\Add7~13_combout ), + .datab(\Add5~41_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[5]~39 ), + .combout(\Vout[6]~40_combout ), + .cout(\Vout[6]~41 )); +// synopsys translate_off +defparam \Vout[6]~40 .lut_mask = 16'h9617; +defparam \Vout[6]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N7 +dffeas \Vout[6]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[6]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[6]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[6]~reg0 .is_wysiwyg = "true"; +defparam \Vout[6]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N24 +cycloneive_lcell_comb \Add5~41 ( +// Equation(s): +// \Add5~41_combout = (\Vout[13]~reg0_q & (!\Vout[6]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~39_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[6]~reg0_q ), + .datad(\Add5~39_combout ), + .cin(gnd), + .combout(\Add5~41_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~41 .lut_mask = 16'h3F0C; +defparam \Add5~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N8 +cycloneive_lcell_comb \Vout[7]~42 ( +// Equation(s): +// \Vout[7]~42_combout = ((\Add5~44_combout $ (\Add7~14_combout $ (!\Vout[6]~41 )))) # (GND) +// \Vout[7]~43 = CARRY((\Add5~44_combout & ((\Add7~14_combout ) # (!\Vout[6]~41 ))) # (!\Add5~44_combout & (\Add7~14_combout & !\Vout[6]~41 ))) + + .dataa(\Add5~44_combout ), + .datab(\Add7~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[6]~41 ), + .combout(\Vout[7]~42_combout ), + .cout(\Vout[7]~43 )); +// synopsys translate_off +defparam \Vout[7]~42 .lut_mask = 16'h698E; +defparam \Vout[7]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N9 +dffeas \Vout[7]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[7]~42_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[7]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[7]~reg0 .is_wysiwyg = "true"; +defparam \Vout[7]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N30 +cycloneive_lcell_comb \Add5~44 ( +// Equation(s): +// \Add5~44_combout = (\Vout[13]~reg0_q & (!\Vout[7]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~42_combout ))) + + .dataa(gnd), + .datab(\Vout[7]~reg0_q ), + .datac(\Add5~42_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~44_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~44 .lut_mask = 16'h33F0; +defparam \Add5~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N10 +cycloneive_lcell_comb \Vout[8]~44 ( +// Equation(s): +// \Vout[8]~44_combout = (\Add7~15_combout & ((\Add5~47_combout & (\Vout[7]~43 & VCC)) # (!\Add5~47_combout & (!\Vout[7]~43 )))) # (!\Add7~15_combout & ((\Add5~47_combout & (!\Vout[7]~43 )) # (!\Add5~47_combout & ((\Vout[7]~43 ) # (GND))))) +// \Vout[8]~45 = CARRY((\Add7~15_combout & (!\Add5~47_combout & !\Vout[7]~43 )) # (!\Add7~15_combout & ((!\Vout[7]~43 ) # (!\Add5~47_combout )))) + + .dataa(\Add7~15_combout ), + .datab(\Add5~47_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[7]~43 ), + .combout(\Vout[8]~44_combout ), + .cout(\Vout[8]~45 )); +// synopsys translate_off +defparam \Vout[8]~44 .lut_mask = 16'h9617; +defparam \Vout[8]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N11 +dffeas \Vout[8]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[8]~44_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[8]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[8]~reg0 .is_wysiwyg = "true"; +defparam \Vout[8]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N26 +cycloneive_lcell_comb \Add5~47 ( +// Equation(s): +// \Add5~47_combout = (\Vout[13]~reg0_q & (!\Vout[8]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~45_combout ))) + + .dataa(\Vout[8]~reg0_q ), + .datab(\Vout[13]~reg0_q ), + .datac(gnd), + .datad(\Add5~45_combout ), + .cin(gnd), + .combout(\Add5~47_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~47 .lut_mask = 16'h7744; +defparam \Add5~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N12 +cycloneive_lcell_comb \Vout[9]~46 ( +// Equation(s): +// \Vout[9]~46_combout = ((\Add7~16_combout $ (\Add5~50_combout $ (!\Vout[8]~45 )))) # (GND) +// \Vout[9]~47 = CARRY((\Add7~16_combout & ((\Add5~50_combout ) # (!\Vout[8]~45 ))) # (!\Add7~16_combout & (\Add5~50_combout & !\Vout[8]~45 ))) + + .dataa(\Add7~16_combout ), + .datab(\Add5~50_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[8]~45 ), + .combout(\Vout[9]~46_combout ), + .cout(\Vout[9]~47 )); +// synopsys translate_off +defparam \Vout[9]~46 .lut_mask = 16'h698E; +defparam \Vout[9]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N13 +dffeas \Vout[9]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[9]~46_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[9]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[9]~reg0 .is_wysiwyg = "true"; +defparam \Vout[9]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N24 +cycloneive_lcell_comb \Add5~50 ( +// Equation(s): +// \Add5~50_combout = (\Vout[13]~reg0_q & ((!\Vout[9]~reg0_q ))) # (!\Vout[13]~reg0_q & (\Add5~48_combout )) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~48_combout ), + .datad(\Vout[9]~reg0_q ), + .cin(gnd), + .combout(\Add5~50_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~50 .lut_mask = 16'h30FC; +defparam \Add5~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N14 +cycloneive_lcell_comb \Vout[10]~48 ( +// Equation(s): +// \Vout[10]~48_combout = (\Add5~53_combout & ((\Add7~17_combout & (\Vout[9]~47 & VCC)) # (!\Add7~17_combout & (!\Vout[9]~47 )))) # (!\Add5~53_combout & ((\Add7~17_combout & (!\Vout[9]~47 )) # (!\Add7~17_combout & ((\Vout[9]~47 ) # (GND))))) +// \Vout[10]~49 = CARRY((\Add5~53_combout & (!\Add7~17_combout & !\Vout[9]~47 )) # (!\Add5~53_combout & ((!\Vout[9]~47 ) # (!\Add7~17_combout )))) + + .dataa(\Add5~53_combout ), + .datab(\Add7~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[9]~47 ), + .combout(\Vout[10]~48_combout ), + .cout(\Vout[10]~49 )); +// synopsys translate_off +defparam \Vout[10]~48 .lut_mask = 16'h9617; +defparam \Vout[10]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N15 +dffeas \Vout[10]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[10]~48_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[10]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[10]~reg0 .is_wysiwyg = "true"; +defparam \Vout[10]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N22 +cycloneive_lcell_comb \Add5~53 ( +// Equation(s): +// \Add5~53_combout = (\Vout[13]~reg0_q & (!\Vout[10]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~51_combout ))) + + .dataa(gnd), + .datab(\Vout[10]~reg0_q ), + .datac(\Add5~51_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~53_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~53 .lut_mask = 16'h33F0; +defparam \Add5~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N16 +cycloneive_lcell_comb \Vout[11]~50 ( +// Equation(s): +// \Vout[11]~50_combout = ((\Add7~18_combout $ (\Add5~56_combout $ (!\Vout[10]~49 )))) # (GND) +// \Vout[11]~51 = CARRY((\Add7~18_combout & ((\Add5~56_combout ) # (!\Vout[10]~49 ))) # (!\Add7~18_combout & (\Add5~56_combout & !\Vout[10]~49 ))) + + .dataa(\Add7~18_combout ), + .datab(\Add5~56_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[10]~49 ), + .combout(\Vout[11]~50_combout ), + .cout(\Vout[11]~51 )); +// synopsys translate_off +defparam \Vout[11]~50 .lut_mask = 16'h698E; +defparam \Vout[11]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N17 +dffeas \Vout[11]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[11]~50_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[11]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[11]~reg0 .is_wysiwyg = "true"; +defparam \Vout[11]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N28 +cycloneive_lcell_comb \Add5~56 ( +// Equation(s): +// \Add5~56_combout = (\Vout[13]~reg0_q & (!\Vout[11]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~54_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[11]~reg0_q ), + .datad(\Add5~54_combout ), + .cin(gnd), + .combout(\Add5~56_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~56 .lut_mask = 16'h3F0C; +defparam \Add5~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N18 +cycloneive_lcell_comb \Vout[12]~52 ( +// Equation(s): +// \Vout[12]~52_combout = (\Add7~19_combout & ((\Add5~59_combout & (\Vout[11]~51 & VCC)) # (!\Add5~59_combout & (!\Vout[11]~51 )))) # (!\Add7~19_combout & ((\Add5~59_combout & (!\Vout[11]~51 )) # (!\Add5~59_combout & ((\Vout[11]~51 ) # (GND))))) +// \Vout[12]~53 = CARRY((\Add7~19_combout & (!\Add5~59_combout & !\Vout[11]~51 )) # (!\Add7~19_combout & ((!\Vout[11]~51 ) # (!\Add5~59_combout )))) + + .dataa(\Add7~19_combout ), + .datab(\Add5~59_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[11]~51 ), + .combout(\Vout[12]~52_combout ), + .cout(\Vout[12]~53 )); +// synopsys translate_off +defparam \Vout[12]~52 .lut_mask = 16'h9617; +defparam \Vout[12]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N19 +dffeas \Vout[12]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[12]~52_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[12]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[12]~reg0 .is_wysiwyg = "true"; +defparam \Vout[12]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N22 +cycloneive_lcell_comb \Add5~59 ( +// Equation(s): +// \Add5~59_combout = (\Vout[13]~reg0_q & (!\Vout[12]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~57_combout ))) + + .dataa(gnd), + .datab(\Vout[12]~reg0_q ), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~57_combout ), + .cin(gnd), + .combout(\Add5~59_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~59 .lut_mask = 16'h3F30; +defparam \Add5~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N20 +cycloneive_lcell_comb \Vout[13]~54 ( +// Equation(s): +// \Vout[13]~54_combout = \Add7~20_combout $ (\Vout[12]~53 $ (!\Add5~62_combout )) + + .dataa(gnd), + .datab(\Add7~20_combout ), + .datac(gnd), + .datad(\Add5~62_combout ), + .cin(\Vout[12]~53 ), + .combout(\Vout[13]~54_combout ), + .cout()); +// synopsys translate_off +defparam \Vout[13]~54 .lut_mask = 16'h3CC3; +defparam \Vout[13]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N21 +dffeas \Vout[13]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[13]~54_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[13]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[13]~reg0 .is_wysiwyg = "true"; +defparam \Vout[13]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N20 +cycloneive_lcell_comb \Add7~0 ( +// Equation(s): +// \Add7~0_combout = (\Vout[13]~reg0_q ) # (Kd_Out[7]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[7]), + .cin(gnd), + .combout(\Add7~0_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~0 .lut_mask = 16'hFFF0; +defparam \Add7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y18_N27 +dffeas \Vout[0]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[0]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[0]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[0]~reg0 .is_wysiwyg = "true"; +defparam \Vout[0]~reg0 .power_up = "low"; +// synopsys translate_on + +assign Vout[0] = \Vout[0]~output_o ; + +assign Vout[1] = \Vout[1]~output_o ; + +assign Vout[2] = \Vout[2]~output_o ; + +assign Vout[3] = \Vout[3]~output_o ; + +assign Vout[4] = \Vout[4]~output_o ; + +assign Vout[5] = \Vout[5]~output_o ; + +assign Vout[6] = \Vout[6]~output_o ; + +assign Vout[7] = \Vout[7]~output_o ; + +assign Vout[8] = \Vout[8]~output_o ; + +assign Vout[9] = \Vout[9]~output_o ; + +assign Vout[10] = \Vout[10]~output_o ; + +assign Vout[11] = \Vout[11]~output_o ; + +assign Vout[12] = \Vout[12]~output_o ; + +assign Vout[13] = \Vout[13]~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_DATA0~~ibuf_o ; + + +endmodule diff --git a/pid/simulation/modelsim/pid_8_1200mv_0c_slow.vo b/pid/simulation/modelsim/pid_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..60ed3fc --- /dev/null +++ b/pid/simulation/modelsim/pid_8_1200mv_0c_slow.vo @@ -0,0 +1,8790 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" + +// DATE "12/04/2018 14:36:38" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module pid ( + clk, + rst_n, + Sample, + SetPoint, + Kp, + Ki, + Kd, + Vout); +input clk; +input rst_n; +input [13:0] Sample; +input [13:0] SetPoint; +input [7:0] Kp; +input [7:0] Ki; +input [7:0] Kd; +output [13:0] Vout; + +// Design Ports Information +// Vout[0] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// Vout[1] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[2] => Location: PIN_N8, I/O Standard: 2.5 V, Current Strength: Default +// Vout[3] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default +// Vout[4] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[5] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[6] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default +// Vout[7] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// Vout[8] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// Vout[9] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default +// Vout[10] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[11] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// Vout[12] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +// Vout[13] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[13] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default +// Sample[13] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default +// Sample[12] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[12] => Location: PIN_F10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[11] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[11] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default +// Sample[10] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[10] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[9] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[9] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default +// Sample[8] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[8] => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// Sample[7] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[7] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default +// Sample[6] => Location: PIN_F14, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[6] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default +// Sample[5] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[5] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[4] => Location: PIN_G11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[4] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[3] => Location: PIN_F11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[3] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default +// Sample[2] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[2] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default +// Sample[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[1] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default +// Sample[0] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[0] => Location: PIN_R12, I/O Standard: 2.5 V, Current Strength: Default +// Kd[0] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[1] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default +// Kd[2] => Location: PIN_J14, I/O Standard: 2.5 V, Current Strength: Default +// Kd[3] => Location: PIN_N9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[4] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default +// Kd[5] => Location: PIN_K9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[6] => Location: PIN_L9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[7] => Location: PIN_R9, I/O Standard: 2.5 V, Current Strength: Default +// Ki[0] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default +// Ki[1] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// Ki[2] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// Ki[3] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default +// Ki[4] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// Ki[5] => Location: PIN_J12, I/O Standard: 2.5 V, Current Strength: Default +// Ki[6] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default +// Ki[7] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[0] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// Kp[1] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default +// Kp[2] => Location: PIN_M9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[3] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default +// Kp[4] => Location: PIN_D9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[5] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// Kp[6] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// Kp[7] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("pid_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \Mult2|auto_generated|mac_out2~0 ; +wire \Mult2|auto_generated|mac_out2~1 ; +wire \Mult2|auto_generated|mac_out2~2 ; +wire \Mult2|auto_generated|mac_out2~3 ; +wire \Mult2|auto_generated|mac_out2~4 ; +wire \Mult2|auto_generated|mac_out2~5 ; +wire \Mult2|auto_generated|mac_out2~6 ; +wire \Mult2|auto_generated|mac_out2~7 ; +wire \Mult2|auto_generated|mac_out2~8 ; +wire \Mult2|auto_generated|mac_out2~9 ; +wire \Mult2|auto_generated|mac_out2~10 ; +wire \Mult2|auto_generated|mac_out2~11 ; +wire \Mult2|auto_generated|mac_out2~12 ; +wire \Mult2|auto_generated|mac_out2~13 ; +wire \Mult2|auto_generated|mac_out2~14 ; +wire \Mult2|auto_generated|mac_out2~15 ; +wire \Mult1|auto_generated|mac_out2~0 ; +wire \Mult1|auto_generated|mac_out2~1 ; +wire \Mult1|auto_generated|mac_out2~2 ; +wire \Mult1|auto_generated|mac_out2~3 ; +wire \Mult1|auto_generated|mac_out2~4 ; +wire \Mult1|auto_generated|mac_out2~5 ; +wire \Mult1|auto_generated|mac_out2~6 ; +wire \Mult1|auto_generated|mac_out2~7 ; +wire \Mult1|auto_generated|mac_out2~8 ; +wire \Mult1|auto_generated|mac_out2~9 ; +wire \Mult1|auto_generated|mac_out2~10 ; +wire \Mult1|auto_generated|mac_out2~11 ; +wire \Mult1|auto_generated|mac_out2~12 ; +wire \Mult1|auto_generated|mac_out2~13 ; +wire \Mult1|auto_generated|mac_out2~14 ; +wire \Mult1|auto_generated|mac_out2~15 ; +wire \Mult0|auto_generated|mac_out2~DATAOUT21 ; +wire \Mult0|auto_generated|mac_out2~0 ; +wire \Mult0|auto_generated|mac_out2~1 ; +wire \Mult0|auto_generated|mac_out2~2 ; +wire \Mult0|auto_generated|mac_out2~3 ; +wire \Mult0|auto_generated|mac_out2~4 ; +wire \Mult0|auto_generated|mac_out2~5 ; +wire \Mult0|auto_generated|mac_out2~6 ; +wire \Mult0|auto_generated|mac_out2~7 ; +wire \Mult0|auto_generated|mac_out2~8 ; +wire \Mult0|auto_generated|mac_out2~9 ; +wire \Mult0|auto_generated|mac_out2~10 ; +wire \Mult0|auto_generated|mac_out2~11 ; +wire \Mult0|auto_generated|mac_out2~12 ; +wire \Mult0|auto_generated|mac_out2~13 ; +wire \Vout[0]~output_o ; +wire \Vout[1]~output_o ; +wire \Vout[2]~output_o ; +wire \Vout[3]~output_o ; +wire \Vout[4]~output_o ; +wire \Vout[5]~output_o ; +wire \Vout[6]~output_o ; +wire \Vout[7]~output_o ; +wire \Vout[8]~output_o ; +wire \Vout[9]~output_o ; +wire \Vout[10]~output_o ; +wire \Vout[11]~output_o ; +wire \Vout[12]~output_o ; +wire \Vout[13]~output_o ; +wire \clk~input_o ; +wire \clk~inputclkctrl_outclk ; +wire \Kd_Out[0]~21_combout ; +wire \EE2[0]~14_combout ; +wire \EE1[0]~14_combout ; +wire \SetPoint[0]~input_o ; +wire \Sample[13]~input_o ; +wire \Add1~1_combout ; +wire \SetPoint[13]~input_o ; +wire \Add1~0_combout ; +wire \Sample[12]~input_o ; +wire \Add1~2_combout ; +wire \SetPoint[12]~input_o ; +wire \Sample[11]~input_o ; +wire \Add1~4_combout ; +wire \SetPoint[11]~input_o ; +wire \SetPoint[10]~input_o ; +wire \Sample[10]~input_o ; +wire \Add1~6_combout ; +wire \Sample[9]~input_o ; +wire \Add1~8_combout ; +wire \SetPoint[9]~input_o ; +wire \SetPoint[8]~input_o ; +wire \Sample[8]~input_o ; +wire \Add1~10_combout ; +wire \Sample[7]~input_o ; +wire \Add1~12_combout ; +wire \SetPoint[7]~input_o ; +wire \SetPoint[6]~input_o ; +wire \Sample[6]~input_o ; +wire \Add1~14_combout ; +wire \Sample[5]~input_o ; +wire \Add1~16_combout ; +wire \SetPoint[4]~input_o ; +wire \Sample[4]~input_o ; +wire \Add1~18_combout ; +wire \Sample[3]~input_o ; +wire \Add1~20_combout ; +wire \SetPoint[2]~input_o ; +wire \Sample[2]~input_o ; +wire \Add1~22_combout ; +wire \Sample[1]~input_o ; +wire \Add1~24_combout ; +wire \SetPoint[1]~input_o ; +wire \Sample[0]~input_o ; +wire \Add1~26_combout ; +wire \EE0[0]~15_cout ; +wire \EE0[0]~17 ; +wire \EE0[1]~18_combout ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \Add0~0_combout ; +wire \period~3_combout ; +wire \Add0~1 ; +wire \Add0~2_combout ; +wire \Add0~3 ; +wire \Add0~4_combout ; +wire \Equal0~2_combout ; +wire \Add0~5 ; +wire \Add0~6_combout ; +wire \period~2_combout ; +wire \Add0~7 ; +wire \Add0~8_combout ; +wire \Add0~9 ; +wire \Add0~10_combout ; +wire \Add0~11 ; +wire \Add0~13 ; +wire \Add0~14_combout ; +wire \period~0_combout ; +wire \Add0~15 ; +wire \Add0~16_combout ; +wire \Add0~17 ; +wire \Add0~18_combout ; +wire \Add0~19 ; +wire \Add0~20_combout ; +wire \Equal0~0_combout ; +wire \Add0~12_combout ; +wire \period~1_combout ; +wire \Equal0~1_combout ; +wire \Equal0~3_combout ; +wire \Clk_Ctrl~q ; +wire \EE0[1]~_Duplicate_1_q ; +wire \Add1~25_combout ; +wire \EE0[1]~19 ; +wire \EE0[2]~20_combout ; +wire \EE0[2]~_Duplicate_1_q ; +wire \Add1~23_combout ; +wire \EE0[2]~21 ; +wire \EE0[3]~22_combout ; +wire \EE0[3]~_Duplicate_1_q ; +wire \SetPoint[3]~input_o ; +wire \Add1~21_combout ; +wire \EE0[3]~23 ; +wire \EE0[4]~24_combout ; +wire \EE0[4]~_Duplicate_1_q ; +wire \Add1~19_combout ; +wire \EE0[4]~25 ; +wire \EE0[5]~26_combout ; +wire \EE0[5]~_Duplicate_1_q ; +wire \SetPoint[5]~input_o ; +wire \Add1~17_combout ; +wire \EE0[5]~27 ; +wire \EE0[6]~28_combout ; +wire \EE0[6]~_Duplicate_1_q ; +wire \Add1~15_combout ; +wire \EE0[6]~29 ; +wire \EE0[7]~30_combout ; +wire \EE0[7]~_Duplicate_1_q ; +wire \Add1~13_combout ; +wire \EE0[7]~31 ; +wire \EE0[8]~32_combout ; +wire \EE0[8]~_Duplicate_1_q ; +wire \Add1~11_combout ; +wire \EE0[8]~33 ; +wire \EE0[9]~34_combout ; +wire \EE0[9]~_Duplicate_1_q ; +wire \Add1~9_combout ; +wire \EE0[9]~35 ; +wire \EE0[10]~36_combout ; +wire \EE0[10]~_Duplicate_1_q ; +wire \Add1~7_combout ; +wire \EE0[10]~37 ; +wire \EE0[11]~38_combout ; +wire \EE0[11]~_Duplicate_1_q ; +wire \Add1~5_combout ; +wire \EE0[11]~39 ; +wire \EE0[12]~40_combout ; +wire \EE0[12]~_Duplicate_1_q ; +wire \Add1~3_combout ; +wire \EE0[12]~41 ; +wire \EE0[13]~42_combout ; +wire \EE0[13]~_Duplicate_1_q ; +wire \Add1~27_combout ; +wire \EE0[0]~16_combout ; +wire \EE0[0]~_Duplicate_1_q ; +wire \EE1[0]~15 ; +wire \EE1[1]~16_combout ; +wire \EE1[1]~17 ; +wire \EE1[2]~18_combout ; +wire \EE1[2]~19 ; +wire \EE1[3]~20_combout ; +wire \EE1[3]~21 ; +wire \EE1[4]~22_combout ; +wire \EE1[4]~23 ; +wire \EE1[5]~24_combout ; +wire \EE1[5]~25 ; +wire \EE1[6]~26_combout ; +wire \EE1[6]~27 ; +wire \EE1[7]~28_combout ; +wire \EE1[7]~29 ; +wire \EE1[8]~30_combout ; +wire \EE1[8]~31 ; +wire \EE1[9]~32_combout ; +wire \EE1[9]~33 ; +wire \EE1[10]~34_combout ; +wire \EE1[10]~35 ; +wire \EE1[11]~36_combout ; +wire \EE1[11]~37 ; +wire \EE1[12]~38_combout ; +wire \EE1[12]~39 ; +wire \EE1[13]~40_combout ; +wire \EE2[0]~15 ; +wire \EE2[1]~16_combout ; +wire \EE2[1]~17 ; +wire \EE2[2]~18_combout ; +wire \EE2[2]~19 ; +wire \EE2[3]~20_combout ; +wire \EE2[3]~21 ; +wire \EE2[4]~22_combout ; +wire \EE2[4]~23 ; +wire \EE2[5]~24_combout ; +wire \EE2[5]~25 ; +wire \EE2[6]~26_combout ; +wire \EE2[6]~27 ; +wire \EE2[7]~28_combout ; +wire \EE2[7]~29 ; +wire \EE2[8]~30_combout ; +wire \EE2[8]~31 ; +wire \EE2[9]~32_combout ; +wire \EE2[9]~33 ; +wire \EE2[10]~34_combout ; +wire \EE2[10]~35 ; +wire \EE2[11]~36_combout ; +wire \EE2[11]~37 ; +wire \EE2[12]~38_combout ; +wire \EE2[12]~39 ; +wire \EE2[13]~40_combout ; +wire \Kd[0]~input_o ; +wire \Kd[1]~input_o ; +wire \Kd[2]~input_o ; +wire \Kd[3]~input_o ; +wire \Kd[4]~input_o ; +wire \Kd[5]~input_o ; +wire \Kd[6]~input_o ; +wire \Kd[7]~input_o ; +wire \Mult2|auto_generated|mac_mult1~dataout ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult2|auto_generated|mac_mult1~0 ; +wire \Mult2|auto_generated|mac_mult1~1 ; +wire \Mult2|auto_generated|mac_mult1~2 ; +wire \Mult2|auto_generated|mac_mult1~3 ; +wire \Mult2|auto_generated|mac_mult1~4 ; +wire \Mult2|auto_generated|mac_mult1~5 ; +wire \Mult2|auto_generated|mac_mult1~6 ; +wire \Mult2|auto_generated|mac_mult1~7 ; +wire \Mult2|auto_generated|mac_mult1~8 ; +wire \Mult2|auto_generated|mac_mult1~9 ; +wire \Mult2|auto_generated|mac_mult1~10 ; +wire \Mult2|auto_generated|mac_mult1~11 ; +wire \Mult2|auto_generated|mac_mult1~12 ; +wire \Mult2|auto_generated|mac_mult1~13 ; +wire \Mult2|auto_generated|mac_mult1~14 ; +wire \Mult2|auto_generated|mac_mult1~15 ; +wire \Mult2|auto_generated|mac_out2~dataout ; +wire \Kd_Out[0]~22 ; +wire \Kd_Out[1]~23_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT1 ; +wire \Kd_Out[1]~24 ; +wire \Kd_Out[2]~25_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT2 ; +wire \Kd_Out[2]~26 ; +wire \Kd_Out[3]~27_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT3 ; +wire \Kd_Out[3]~28 ; +wire \Kd_Out[4]~29_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT4 ; +wire \Kd_Out[4]~30 ; +wire \Kd_Out[5]~31_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT5 ; +wire \Kd_Out[5]~32 ; +wire \Kd_Out[6]~33_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT6 ; +wire \Kd_Out[6]~34 ; +wire \Kd_Out[7]~35_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT7 ; +wire \Kd_Out[7]~36 ; +wire \Kd_Out[8]~37_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT8 ; +wire \Kd_Out[8]~38 ; +wire \Kd_Out[9]~39_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT9 ; +wire \Kd_Out[9]~40 ; +wire \Kd_Out[10]~41_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT10 ; +wire \Kd_Out[10]~42 ; +wire \Kd_Out[11]~43_combout ; +wire \Kd_Out[11]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT11 ; +wire \Kd_Out[11]~44 ; +wire \Kd_Out[12]~45_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT12 ; +wire \Kd_Out[12]~46 ; +wire \Kd_Out[13]~47_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT13 ; +wire \Kd_Out[13]~48 ; +wire \Kd_Out[14]~49_combout ; +wire \Kd_Out[14]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT14 ; +wire \Kd_Out[14]~50 ; +wire \Kd_Out[15]~51_combout ; +wire \Kd_Out[15]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT15 ; +wire \Kd_Out[15]~52 ; +wire \Kd_Out[16]~53_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT16 ; +wire \Kd_Out[16]~54 ; +wire \Kd_Out[17]~55_combout ; +wire \Kd_Out[17]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT17 ; +wire \Kd_Out[17]~56 ; +wire \Kd_Out[18]~57_combout ; +wire \Kd_Out[18]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT18 ; +wire \Kd_Out[18]~58 ; +wire \Kd_Out[19]~59_combout ; +wire \Kd_Out[19]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT19 ; +wire \Kd_Out[19]~60 ; +wire \Kd_Out[20]~61_combout ; +wire \~GND~combout ; +wire \Add7~20_combout ; +wire \Ki_Out[0]~21_combout ; +wire \Ki[0]~input_o ; +wire \Ki[1]~input_o ; +wire \Ki[2]~input_o ; +wire \Ki[3]~input_o ; +wire \Ki[4]~input_o ; +wire \Ki[5]~input_o ; +wire \Ki[6]~input_o ; +wire \Ki[7]~input_o ; +wire \Mult1|auto_generated|mac_mult1~dataout ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult1|auto_generated|mac_mult1~0 ; +wire \Mult1|auto_generated|mac_mult1~1 ; +wire \Mult1|auto_generated|mac_mult1~2 ; +wire \Mult1|auto_generated|mac_mult1~3 ; +wire \Mult1|auto_generated|mac_mult1~4 ; +wire \Mult1|auto_generated|mac_mult1~5 ; +wire \Mult1|auto_generated|mac_mult1~6 ; +wire \Mult1|auto_generated|mac_mult1~7 ; +wire \Mult1|auto_generated|mac_mult1~8 ; +wire \Mult1|auto_generated|mac_mult1~9 ; +wire \Mult1|auto_generated|mac_mult1~10 ; +wire \Mult1|auto_generated|mac_mult1~11 ; +wire \Mult1|auto_generated|mac_mult1~12 ; +wire \Mult1|auto_generated|mac_mult1~13 ; +wire \Mult1|auto_generated|mac_mult1~14 ; +wire \Mult1|auto_generated|mac_mult1~15 ; +wire \Mult1|auto_generated|mac_out2~dataout ; +wire \Ki_Out[0]~22 ; +wire \Ki_Out[1]~23_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT1 ; +wire \Ki_Out[1]~24 ; +wire \Ki_Out[2]~25_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT2 ; +wire \Ki_Out[2]~26 ; +wire \Ki_Out[3]~27_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT3 ; +wire \Ki_Out[3]~28 ; +wire \Ki_Out[4]~29_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT4 ; +wire \Ki_Out[4]~30 ; +wire \Ki_Out[5]~31_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT5 ; +wire \Ki_Out[5]~32 ; +wire \Ki_Out[6]~33_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT6 ; +wire \Ki_Out[6]~34 ; +wire \Ki_Out[7]~35_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT7 ; +wire \Ki_Out[7]~36 ; +wire \Ki_Out[8]~37_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT8 ; +wire \Ki_Out[8]~38 ; +wire \Ki_Out[9]~39_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT9 ; +wire \Ki_Out[9]~40 ; +wire \Ki_Out[10]~41_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT10 ; +wire \Ki_Out[10]~42 ; +wire \Ki_Out[11]~43_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT11 ; +wire \Ki_Out[11]~44 ; +wire \Ki_Out[12]~45_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT12 ; +wire \Ki_Out[12]~46 ; +wire \Ki_Out[13]~47_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT13 ; +wire \Ki_Out[13]~48 ; +wire \Ki_Out[14]~49_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT14 ; +wire \Ki_Out[14]~50 ; +wire \Ki_Out[15]~51_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT15 ; +wire \Ki_Out[15]~52 ; +wire \Ki_Out[16]~53_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT16 ; +wire \Ki_Out[16]~54 ; +wire \Ki_Out[17]~55_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT17 ; +wire \Ki_Out[17]~56 ; +wire \Ki_Out[18]~57_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT18 ; +wire \Ki_Out[18]~58 ; +wire \Ki_Out[19]~59_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT19 ; +wire \Ki_Out[19]~60 ; +wire \Ki_Out[20]~61_combout ; +wire \Kp_Out[0]~21_combout ; +wire \Kp[0]~input_o ; +wire \Kp[1]~input_o ; +wire \Kp[2]~input_o ; +wire \Kp[3]~input_o ; +wire \Kp[4]~input_o ; +wire \Kp[5]~input_o ; +wire \Kp[6]~input_o ; +wire \Kp[7]~input_o ; +wire \Mult0|auto_generated|mac_mult1~dataout ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT20 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT21 ; +wire \Mult0|auto_generated|mac_mult1~0 ; +wire \Mult0|auto_generated|mac_mult1~1 ; +wire \Mult0|auto_generated|mac_mult1~2 ; +wire \Mult0|auto_generated|mac_mult1~3 ; +wire \Mult0|auto_generated|mac_mult1~4 ; +wire \Mult0|auto_generated|mac_mult1~5 ; +wire \Mult0|auto_generated|mac_mult1~6 ; +wire \Mult0|auto_generated|mac_mult1~7 ; +wire \Mult0|auto_generated|mac_mult1~8 ; +wire \Mult0|auto_generated|mac_mult1~9 ; +wire \Mult0|auto_generated|mac_mult1~10 ; +wire \Mult0|auto_generated|mac_mult1~11 ; +wire \Mult0|auto_generated|mac_mult1~12 ; +wire \Mult0|auto_generated|mac_mult1~13 ; +wire \Mult0|auto_generated|mac_out2~dataout ; +wire \Kp_Out[0]~22 ; +wire \Kp_Out[1]~23_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT1 ; +wire \Kp_Out[1]~24 ; +wire \Kp_Out[2]~25_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT2 ; +wire \Kp_Out[2]~26 ; +wire \Kp_Out[3]~27_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT3 ; +wire \Kp_Out[3]~28 ; +wire \Kp_Out[4]~29_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT4 ; +wire \Kp_Out[4]~30 ; +wire \Kp_Out[5]~31_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT5 ; +wire \Kp_Out[5]~32 ; +wire \Kp_Out[6]~33_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT6 ; +wire \Kp_Out[6]~34 ; +wire \Kp_Out[7]~35_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT7 ; +wire \Kp_Out[7]~36 ; +wire \Kp_Out[8]~37_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT8 ; +wire \Kp_Out[8]~38 ; +wire \Kp_Out[9]~39_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT9 ; +wire \Kp_Out[9]~40 ; +wire \Kp_Out[10]~41_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT10 ; +wire \Kp_Out[10]~42 ; +wire \Kp_Out[11]~43_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT11 ; +wire \Kp_Out[11]~44 ; +wire \Kp_Out[12]~45_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT12 ; +wire \Kp_Out[12]~46 ; +wire \Kp_Out[13]~47_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT13 ; +wire \Kp_Out[13]~48 ; +wire \Kp_Out[14]~49_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT14 ; +wire \Kp_Out[14]~50 ; +wire \Kp_Out[15]~51_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT15 ; +wire \Kp_Out[15]~52 ; +wire \Kp_Out[16]~53_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT16 ; +wire \Kp_Out[16]~54 ; +wire \Kp_Out[17]~55_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT17 ; +wire \Kp_Out[17]~56 ; +wire \Kp_Out[18]~57_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT18 ; +wire \Kp_Out[18]~58 ; +wire \Kp_Out[19]~59_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT19 ; +wire \Kp_Out[19]~60 ; +wire \Kp_Out[20]~61_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT20 ; +wire \Add5~1 ; +wire \Add5~3 ; +wire \Add5~5 ; +wire \Add5~7 ; +wire \Add5~9 ; +wire \Add5~11 ; +wire \Add5~13 ; +wire \Add5~15 ; +wire \Add5~25 ; +wire \Add5~28 ; +wire \Add5~31 ; +wire \Add5~34 ; +wire \Add5~37 ; +wire \Add5~40 ; +wire \Add5~43 ; +wire \Add5~46 ; +wire \Add5~49 ; +wire \Add5~52 ; +wire \Add5~55 ; +wire \Add5~58 ; +wire \Add5~60_combout ; +wire \Add5~62_combout ; +wire \Add7~19_combout ; +wire \Add7~18_combout ; +wire \Add7~17_combout ; +wire \Add7~16_combout ; +wire \Add5~48_combout ; +wire \Add7~15_combout ; +wire \Add7~14_combout ; +wire \Add7~13_combout ; +wire \Add7~12_combout ; +wire \Add7~11_combout ; +wire \Add5~30_combout ; +wire \Add7~10_combout ; +wire \Add7~9_combout ; +wire \Add7~8_combout ; +wire \Add5~14_combout ; +wire \Add5~16_combout ; +wire \Add7~1_combout ; +wire \Add5~12_combout ; +wire \Add5~17_combout ; +wire \Add7~2_combout ; +wire \Add5~10_combout ; +wire \Add5~18_combout ; +wire \Add7~3_combout ; +wire \Add5~8_combout ; +wire \Add5~19_combout ; +wire \Add5~6_combout ; +wire \Add5~20_combout ; +wire \Add7~4_combout ; +wire \Add7~5_combout ; +wire \Add5~4_combout ; +wire \Add5~21_combout ; +wire \Add7~6_combout ; +wire \Add5~2_combout ; +wire \Add5~22_combout ; +wire \Add5~0_combout ; +wire \Add5~23_combout ; +wire \Add7~7_combout ; +wire \Vout[0]~15_cout ; +wire \Vout[0]~17_cout ; +wire \Vout[0]~19_cout ; +wire \Vout[0]~21_cout ; +wire \Vout[0]~23_cout ; +wire \Vout[0]~25_cout ; +wire \Vout[0]~27_cout ; +wire \Vout[0]~29 ; +wire \Vout[1]~30_combout ; +wire \Vout[1]~reg0_q ; +wire \Add5~24_combout ; +wire \Add5~26_combout ; +wire \Vout[1]~31 ; +wire \Vout[2]~32_combout ; +wire \Vout[2]~reg0_q ; +wire \Add5~27_combout ; +wire \Add5~29_combout ; +wire \Vout[2]~33 ; +wire \Vout[3]~34_combout ; +wire \Vout[3]~reg0_q ; +wire \Add5~32_combout ; +wire \Vout[3]~35 ; +wire \Vout[4]~36_combout ; +wire \Vout[4]~reg0_q ; +wire \Add5~33_combout ; +wire \Add5~35_combout ; +wire \Vout[4]~37 ; +wire \Vout[5]~38_combout ; +wire \Vout[5]~reg0_q ; +wire \Add5~36_combout ; +wire \Add5~38_combout ; +wire \Vout[5]~39 ; +wire \Vout[6]~40_combout ; +wire \Vout[6]~reg0_q ; +wire \Add5~39_combout ; +wire \Add5~41_combout ; +wire \Vout[6]~41 ; +wire \Vout[7]~42_combout ; +wire \Vout[7]~reg0_q ; +wire \Add5~42_combout ; +wire \Add5~44_combout ; +wire \Vout[7]~43 ; +wire \Vout[8]~44_combout ; +wire \Vout[8]~reg0_q ; +wire \Add5~45_combout ; +wire \Add5~47_combout ; +wire \Vout[8]~45 ; +wire \Vout[9]~46_combout ; +wire \Vout[9]~reg0_q ; +wire \Add5~50_combout ; +wire \Vout[9]~47 ; +wire \Vout[10]~48_combout ; +wire \Vout[10]~reg0_q ; +wire \Add5~51_combout ; +wire \Add5~53_combout ; +wire \Vout[10]~49 ; +wire \Vout[11]~50_combout ; +wire \Vout[11]~reg0_q ; +wire \Add5~54_combout ; +wire \Add5~56_combout ; +wire \Vout[11]~51 ; +wire \Vout[12]~52_combout ; +wire \Vout[12]~reg0_q ; +wire \Add5~57_combout ; +wire \Add5~59_combout ; +wire \Vout[12]~53 ; +wire \Vout[13]~54_combout ; +wire \Vout[13]~reg0_q ; +wire \Add7~0_combout ; +wire \Vout[0]~28_combout ; +wire \Vout[0]~reg0_q ; +wire [21:0] Kd_Out; +wire [21:0] Ki_Out; +wire [21:0] Kp_Out; +wire [13:0] EE2; +wire [13:0] EE1; +wire [10:0] period; + +wire [35:0] \Mult2|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult1|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult0|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult2|auto_generated|mac_mult1_DATAOUT_bus ; +wire [35:0] \Mult1|auto_generated|mac_mult1_DATAOUT_bus ; +wire [35:0] \Mult0|auto_generated|mac_mult1_DATAOUT_bus ; + +assign \Mult2|auto_generated|mac_out2~0 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult2|auto_generated|mac_out2~1 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult2|auto_generated|mac_out2~2 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult2|auto_generated|mac_out2~3 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult2|auto_generated|mac_out2~4 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult2|auto_generated|mac_out2~5 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult2|auto_generated|mac_out2~6 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult2|auto_generated|mac_out2~7 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult2|auto_generated|mac_out2~8 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult2|auto_generated|mac_out2~9 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult2|auto_generated|mac_out2~10 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult2|auto_generated|mac_out2~11 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult2|auto_generated|mac_out2~12 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult2|auto_generated|mac_out2~13 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult2|auto_generated|mac_out2~14 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult2|auto_generated|mac_out2~15 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult2|auto_generated|mac_out2~dataout = \Mult2|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult2|auto_generated|mac_out2~DATAOUT1 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult2|auto_generated|mac_out2~DATAOUT2 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult2|auto_generated|mac_out2~DATAOUT3 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult2|auto_generated|mac_out2~DATAOUT4 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult2|auto_generated|mac_out2~DATAOUT5 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult2|auto_generated|mac_out2~DATAOUT6 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult2|auto_generated|mac_out2~DATAOUT7 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult2|auto_generated|mac_out2~DATAOUT8 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult2|auto_generated|mac_out2~DATAOUT9 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult2|auto_generated|mac_out2~DATAOUT10 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult2|auto_generated|mac_out2~DATAOUT11 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult2|auto_generated|mac_out2~DATAOUT12 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult2|auto_generated|mac_out2~DATAOUT13 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult2|auto_generated|mac_out2~DATAOUT14 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult2|auto_generated|mac_out2~DATAOUT15 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult2|auto_generated|mac_out2~DATAOUT16 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult2|auto_generated|mac_out2~DATAOUT17 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult2|auto_generated|mac_out2~DATAOUT18 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult2|auto_generated|mac_out2~DATAOUT19 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult1|auto_generated|mac_out2~0 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult1|auto_generated|mac_out2~1 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult1|auto_generated|mac_out2~2 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult1|auto_generated|mac_out2~3 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult1|auto_generated|mac_out2~4 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult1|auto_generated|mac_out2~5 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult1|auto_generated|mac_out2~6 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult1|auto_generated|mac_out2~7 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult1|auto_generated|mac_out2~8 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult1|auto_generated|mac_out2~9 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult1|auto_generated|mac_out2~10 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult1|auto_generated|mac_out2~11 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult1|auto_generated|mac_out2~12 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult1|auto_generated|mac_out2~13 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult1|auto_generated|mac_out2~14 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult1|auto_generated|mac_out2~15 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult1|auto_generated|mac_out2~dataout = \Mult1|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult1|auto_generated|mac_out2~DATAOUT1 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult1|auto_generated|mac_out2~DATAOUT2 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult1|auto_generated|mac_out2~DATAOUT3 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult1|auto_generated|mac_out2~DATAOUT4 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult1|auto_generated|mac_out2~DATAOUT5 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult1|auto_generated|mac_out2~DATAOUT6 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult1|auto_generated|mac_out2~DATAOUT7 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult1|auto_generated|mac_out2~DATAOUT8 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult1|auto_generated|mac_out2~DATAOUT9 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult1|auto_generated|mac_out2~DATAOUT10 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult1|auto_generated|mac_out2~DATAOUT11 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult1|auto_generated|mac_out2~DATAOUT12 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult1|auto_generated|mac_out2~DATAOUT13 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult1|auto_generated|mac_out2~DATAOUT14 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult1|auto_generated|mac_out2~DATAOUT15 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult1|auto_generated|mac_out2~DATAOUT16 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult1|auto_generated|mac_out2~DATAOUT17 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult1|auto_generated|mac_out2~DATAOUT18 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult1|auto_generated|mac_out2~DATAOUT19 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult0|auto_generated|mac_out2~0 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult0|auto_generated|mac_out2~1 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult0|auto_generated|mac_out2~2 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult0|auto_generated|mac_out2~3 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult0|auto_generated|mac_out2~4 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult0|auto_generated|mac_out2~5 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult0|auto_generated|mac_out2~6 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult0|auto_generated|mac_out2~7 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult0|auto_generated|mac_out2~8 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult0|auto_generated|mac_out2~9 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult0|auto_generated|mac_out2~10 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult0|auto_generated|mac_out2~11 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult0|auto_generated|mac_out2~12 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult0|auto_generated|mac_out2~13 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult0|auto_generated|mac_out2~dataout = \Mult0|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult0|auto_generated|mac_out2~DATAOUT1 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult0|auto_generated|mac_out2~DATAOUT2 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult0|auto_generated|mac_out2~DATAOUT3 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult0|auto_generated|mac_out2~DATAOUT4 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult0|auto_generated|mac_out2~DATAOUT5 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult0|auto_generated|mac_out2~DATAOUT6 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult0|auto_generated|mac_out2~DATAOUT7 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult0|auto_generated|mac_out2~DATAOUT8 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult0|auto_generated|mac_out2~DATAOUT9 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult0|auto_generated|mac_out2~DATAOUT10 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult0|auto_generated|mac_out2~DATAOUT11 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult0|auto_generated|mac_out2~DATAOUT12 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult0|auto_generated|mac_out2~DATAOUT13 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult0|auto_generated|mac_out2~DATAOUT14 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult0|auto_generated|mac_out2~DATAOUT15 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult0|auto_generated|mac_out2~DATAOUT16 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult0|auto_generated|mac_out2~DATAOUT17 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult0|auto_generated|mac_out2~DATAOUT18 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult0|auto_generated|mac_out2~DATAOUT19 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult0|auto_generated|mac_out2~DATAOUT20 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult0|auto_generated|mac_out2~DATAOUT21 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult2|auto_generated|mac_mult1~0 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult2|auto_generated|mac_mult1~1 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult2|auto_generated|mac_mult1~2 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult2|auto_generated|mac_mult1~3 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult2|auto_generated|mac_mult1~4 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult2|auto_generated|mac_mult1~5 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult2|auto_generated|mac_mult1~6 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult2|auto_generated|mac_mult1~7 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult2|auto_generated|mac_mult1~8 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult2|auto_generated|mac_mult1~9 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult2|auto_generated|mac_mult1~10 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult2|auto_generated|mac_mult1~11 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult2|auto_generated|mac_mult1~12 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult2|auto_generated|mac_mult1~13 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult2|auto_generated|mac_mult1~14 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult2|auto_generated|mac_mult1~15 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult2|auto_generated|mac_mult1~dataout = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT1 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT2 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT3 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT4 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT5 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT6 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT7 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT8 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT9 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT10 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT11 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT12 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT13 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT14 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT15 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT16 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT17 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT18 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT19 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [35]; + +assign \Mult1|auto_generated|mac_mult1~0 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult1|auto_generated|mac_mult1~1 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult1|auto_generated|mac_mult1~2 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult1|auto_generated|mac_mult1~3 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult1|auto_generated|mac_mult1~4 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult1|auto_generated|mac_mult1~5 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult1|auto_generated|mac_mult1~6 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult1|auto_generated|mac_mult1~7 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult1|auto_generated|mac_mult1~8 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult1|auto_generated|mac_mult1~9 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult1|auto_generated|mac_mult1~10 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult1|auto_generated|mac_mult1~11 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult1|auto_generated|mac_mult1~12 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult1|auto_generated|mac_mult1~13 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult1|auto_generated|mac_mult1~14 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult1|auto_generated|mac_mult1~15 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult1|auto_generated|mac_mult1~dataout = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT1 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT2 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT3 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT4 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT5 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT6 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT7 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT8 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT9 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT10 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT11 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT12 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT13 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT14 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT15 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT16 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT17 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT18 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT19 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [35]; + +assign \Mult0|auto_generated|mac_mult1~0 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult0|auto_generated|mac_mult1~1 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult0|auto_generated|mac_mult1~2 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult0|auto_generated|mac_mult1~3 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult0|auto_generated|mac_mult1~4 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult0|auto_generated|mac_mult1~5 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult0|auto_generated|mac_mult1~6 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult0|auto_generated|mac_mult1~7 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult0|auto_generated|mac_mult1~8 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult0|auto_generated|mac_mult1~9 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult0|auto_generated|mac_mult1~10 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult0|auto_generated|mac_mult1~11 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult0|auto_generated|mac_mult1~12 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult0|auto_generated|mac_mult1~13 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult0|auto_generated|mac_mult1~dataout = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT1 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT2 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT3 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT4 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT5 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT6 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT7 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT8 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT9 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT10 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT11 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT12 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT13 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT14 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT15 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT16 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT17 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT18 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT19 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT20 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT21 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [35]; + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: IOOBUF_X7_Y24_N16 +cycloneive_io_obuf \Vout[0]~output ( + .i(\Vout[0]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[0]~output .bus_hold = "false"; +defparam \Vout[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N9 +cycloneive_io_obuf \Vout[1]~output ( + .i(\Vout[1]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[1]~output .bus_hold = "false"; +defparam \Vout[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N23 +cycloneive_io_obuf \Vout[2]~output ( + .i(\Vout[2]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[2]~output .bus_hold = "false"; +defparam \Vout[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N16 +cycloneive_io_obuf \Vout[3]~output ( + .i(\Vout[3]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[3]~output .bus_hold = "false"; +defparam \Vout[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N2 +cycloneive_io_obuf \Vout[4]~output ( + .i(\Vout[4]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[4]~output .bus_hold = "false"; +defparam \Vout[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y24_N2 +cycloneive_io_obuf \Vout[5]~output ( + .i(\Vout[5]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[5]~output .bus_hold = "false"; +defparam \Vout[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N16 +cycloneive_io_obuf \Vout[6]~output ( + .i(\Vout[6]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[6]~output .bus_hold = "false"; +defparam \Vout[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y24_N16 +cycloneive_io_obuf \Vout[7]~output ( + .i(\Vout[7]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[7]~output .bus_hold = "false"; +defparam \Vout[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N2 +cycloneive_io_obuf \Vout[8]~output ( + .i(\Vout[8]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[8]~output .bus_hold = "false"; +defparam \Vout[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N2 +cycloneive_io_obuf \Vout[9]~output ( + .i(\Vout[9]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[9]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[9]~output .bus_hold = "false"; +defparam \Vout[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N23 +cycloneive_io_obuf \Vout[10]~output ( + .i(\Vout[10]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[10]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[10]~output .bus_hold = "false"; +defparam \Vout[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y19_N16 +cycloneive_io_obuf \Vout[11]~output ( + .i(\Vout[11]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[11]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[11]~output .bus_hold = "false"; +defparam \Vout[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y24_N9 +cycloneive_io_obuf \Vout[12]~output ( + .i(\Vout[12]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[12]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[12]~output .bus_hold = "false"; +defparam \Vout[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N9 +cycloneive_io_obuf \Vout[13]~output ( + .i(\Vout[13]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[13]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[13]~output .bus_hold = "false"; +defparam \Vout[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk~inputclkctrl .clock_type = "global clock"; +defparam \clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N12 +cycloneive_lcell_comb \Kd_Out[0]~21 ( +// Equation(s): +// \Kd_Out[0]~21_combout = Kd_Out[0] $ (GND) +// \Kd_Out[0]~22 = CARRY(!Kd_Out[0]) + + .dataa(Kd_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Kd_Out[0]~21_combout ), + .cout(\Kd_Out[0]~22 )); +// synopsys translate_off +defparam \Kd_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Kd_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 +cycloneive_lcell_comb \EE2[0]~14 ( +// Equation(s): +// \EE2[0]~14_combout = EE2[0] $ (GND) +// \EE2[0]~15 = CARRY(!EE2[0]) + + .dataa(gnd), + .datab(EE2[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\EE2[0]~14_combout ), + .cout(\EE2[0]~15 )); +// synopsys translate_off +defparam \EE2[0]~14 .lut_mask = 16'hCC33; +defparam \EE2[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N2 +cycloneive_lcell_comb \EE1[0]~14 ( +// Equation(s): +// \EE1[0]~14_combout = EE1[0] $ (GND) +// \EE1[0]~15 = CARRY(!EE1[0]) + + .dataa(gnd), + .datab(EE1[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\EE1[0]~14_combout ), + .cout(\EE1[0]~15 )); +// synopsys translate_off +defparam \EE1[0]~14 .lut_mask = 16'hCC33; +defparam \EE1[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y0_N1 +cycloneive_io_ibuf \SetPoint[0]~input ( + .i(SetPoint[0]), + .ibar(gnd), + .o(\SetPoint[0]~input_o )); +// synopsys translate_off +defparam \SetPoint[0]~input .bus_hold = "false"; +defparam \SetPoint[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N8 +cycloneive_io_ibuf \Sample[13]~input ( + .i(Sample[13]), + .ibar(gnd), + .o(\Sample[13]~input_o )); +// synopsys translate_off +defparam \Sample[13]~input .bus_hold = "false"; +defparam \Sample[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N2 +cycloneive_lcell_comb \Add1~1 ( +// Equation(s): +// \Add1~1_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[13]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[13]~input_o ), + .cin(gnd), + .combout(\Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~1 .lut_mask = 16'hFFF0; +defparam \Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N22 +cycloneive_io_ibuf \SetPoint[13]~input ( + .i(SetPoint[13]), + .ibar(gnd), + .o(\SetPoint[13]~input_o )); +// synopsys translate_off +defparam \SetPoint[13]~input .bus_hold = "false"; +defparam \SetPoint[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N0 +cycloneive_lcell_comb \Add1~0 ( +// Equation(s): +// \Add1~0_combout = (!\EE0[13]~_Duplicate_1_q & \SetPoint[13]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\SetPoint[13]~input_o ), + .cin(gnd), + .combout(\Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~0 .lut_mask = 16'h0F00; +defparam \Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N1 +cycloneive_io_ibuf \Sample[12]~input ( + .i(Sample[12]), + .ibar(gnd), + .o(\Sample[12]~input_o )); +// synopsys translate_off +defparam \Sample[12]~input .bus_hold = "false"; +defparam \Sample[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N8 +cycloneive_lcell_comb \Add1~2 ( +// Equation(s): +// \Add1~2_combout = (\Sample[12]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[12]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~2_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~2 .lut_mask = 16'hFFF0; +defparam \Add1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N8 +cycloneive_io_ibuf \SetPoint[12]~input ( + .i(SetPoint[12]), + .ibar(gnd), + .o(\SetPoint[12]~input_o )); +// synopsys translate_off +defparam \SetPoint[12]~input .bus_hold = "false"; +defparam \SetPoint[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N22 +cycloneive_io_ibuf \Sample[11]~input ( + .i(Sample[11]), + .ibar(gnd), + .o(\Sample[11]~input_o )); +// synopsys translate_off +defparam \Sample[11]~input .bus_hold = "false"; +defparam \Sample[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N24 +cycloneive_lcell_comb \Add1~4 ( +// Equation(s): +// \Add1~4_combout = (\Sample[11]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(\Sample[11]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(gnd), + .cin(gnd), + .combout(\Add1~4_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~4 .lut_mask = 16'hFAFA; +defparam \Add1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N8 +cycloneive_io_ibuf \SetPoint[11]~input ( + .i(SetPoint[11]), + .ibar(gnd), + .o(\SetPoint[11]~input_o )); +// synopsys translate_off +defparam \SetPoint[11]~input .bus_hold = "false"; +defparam \SetPoint[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N1 +cycloneive_io_ibuf \SetPoint[10]~input ( + .i(SetPoint[10]), + .ibar(gnd), + .o(\SetPoint[10]~input_o )); +// synopsys translate_off +defparam \SetPoint[10]~input .bus_hold = "false"; +defparam \SetPoint[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N1 +cycloneive_io_ibuf \Sample[10]~input ( + .i(Sample[10]), + .ibar(gnd), + .o(\Sample[10]~input_o )); +// synopsys translate_off +defparam \Sample[10]~input .bus_hold = "false"; +defparam \Sample[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N10 +cycloneive_lcell_comb \Add1~6 ( +// Equation(s): +// \Add1~6_combout = (\Sample[10]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[10]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~6 .lut_mask = 16'hFFF0; +defparam \Add1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N8 +cycloneive_io_ibuf \Sample[9]~input ( + .i(Sample[9]), + .ibar(gnd), + .o(\Sample[9]~input_o )); +// synopsys translate_off +defparam \Sample[9]~input .bus_hold = "false"; +defparam \Sample[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N18 +cycloneive_lcell_comb \Add1~8 ( +// Equation(s): +// \Add1~8_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[9]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[9]~input_o ), + .cin(gnd), + .combout(\Add1~8_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~8 .lut_mask = 16'hFFF0; +defparam \Add1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N15 +cycloneive_io_ibuf \SetPoint[9]~input ( + .i(SetPoint[9]), + .ibar(gnd), + .o(\SetPoint[9]~input_o )); +// synopsys translate_off +defparam \SetPoint[9]~input .bus_hold = "false"; +defparam \SetPoint[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N22 +cycloneive_io_ibuf \SetPoint[8]~input ( + .i(SetPoint[8]), + .ibar(gnd), + .o(\SetPoint[8]~input_o )); +// synopsys translate_off +defparam \SetPoint[8]~input .bus_hold = "false"; +defparam \SetPoint[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N1 +cycloneive_io_ibuf \Sample[8]~input ( + .i(Sample[8]), + .ibar(gnd), + .o(\Sample[8]~input_o )); +// synopsys translate_off +defparam \Sample[8]~input .bus_hold = "false"; +defparam \Sample[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N20 +cycloneive_lcell_comb \Add1~10 ( +// Equation(s): +// \Add1~10_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[8]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[8]~input_o ), + .cin(gnd), + .combout(\Add1~10_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~10 .lut_mask = 16'hFFF0; +defparam \Add1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N15 +cycloneive_io_ibuf \Sample[7]~input ( + .i(Sample[7]), + .ibar(gnd), + .o(\Sample[7]~input_o )); +// synopsys translate_off +defparam \Sample[7]~input .bus_hold = "false"; +defparam \Sample[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N6 +cycloneive_lcell_comb \Add1~12 ( +// Equation(s): +// \Add1~12_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[7]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[7]~input_o ), + .cin(gnd), + .combout(\Add1~12_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~12 .lut_mask = 16'hFFF0; +defparam \Add1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N8 +cycloneive_io_ibuf \SetPoint[7]~input ( + .i(SetPoint[7]), + .ibar(gnd), + .o(\SetPoint[7]~input_o )); +// synopsys translate_off +defparam \SetPoint[7]~input .bus_hold = "false"; +defparam \SetPoint[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N15 +cycloneive_io_ibuf \SetPoint[6]~input ( + .i(SetPoint[6]), + .ibar(gnd), + .o(\SetPoint[6]~input_o )); +// synopsys translate_off +defparam \SetPoint[6]~input .bus_hold = "false"; +defparam \SetPoint[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N15 +cycloneive_io_ibuf \Sample[6]~input ( + .i(Sample[6]), + .ibar(gnd), + .o(\Sample[6]~input_o )); +// synopsys translate_off +defparam \Sample[6]~input .bus_hold = "false"; +defparam \Sample[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N22 +cycloneive_lcell_comb \Add1~14 ( +// Equation(s): +// \Add1~14_combout = (\Sample[6]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\Sample[6]~input_o ), + .datac(gnd), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~14_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~14 .lut_mask = 16'hFFCC; +defparam \Add1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N22 +cycloneive_io_ibuf \Sample[5]~input ( + .i(Sample[5]), + .ibar(gnd), + .o(\Sample[5]~input_o )); +// synopsys translate_off +defparam \Sample[5]~input .bus_hold = "false"; +defparam \Sample[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N12 +cycloneive_lcell_comb \Add1~16 ( +// Equation(s): +// \Add1~16_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[5]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[5]~input_o ), + .cin(gnd), + .combout(\Add1~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~16 .lut_mask = 16'hFFF0; +defparam \Add1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N15 +cycloneive_io_ibuf \SetPoint[4]~input ( + .i(SetPoint[4]), + .ibar(gnd), + .o(\SetPoint[4]~input_o )); +// synopsys translate_off +defparam \SetPoint[4]~input .bus_hold = "false"; +defparam \SetPoint[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N15 +cycloneive_io_ibuf \Sample[4]~input ( + .i(Sample[4]), + .ibar(gnd), + .o(\Sample[4]~input_o )); +// synopsys translate_off +defparam \Sample[4]~input .bus_hold = "false"; +defparam \Sample[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N16 +cycloneive_lcell_comb \Add1~18 ( +// Equation(s): +// \Add1~18_combout = (\Sample[4]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\Sample[4]~input_o ), + .datac(gnd), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~18 .lut_mask = 16'hFFCC; +defparam \Add1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N22 +cycloneive_io_ibuf \Sample[3]~input ( + .i(Sample[3]), + .ibar(gnd), + .o(\Sample[3]~input_o )); +// synopsys translate_off +defparam \Sample[3]~input .bus_hold = "false"; +defparam \Sample[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N6 +cycloneive_lcell_comb \Add1~20 ( +// Equation(s): +// \Add1~20_combout = (\Sample[3]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[3]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~20 .lut_mask = 16'hFFF0; +defparam \Add1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N1 +cycloneive_io_ibuf \SetPoint[2]~input ( + .i(SetPoint[2]), + .ibar(gnd), + .o(\SetPoint[2]~input_o )); +// synopsys translate_off +defparam \SetPoint[2]~input .bus_hold = "false"; +defparam \SetPoint[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N22 +cycloneive_io_ibuf \Sample[2]~input ( + .i(Sample[2]), + .ibar(gnd), + .o(\Sample[2]~input_o )); +// synopsys translate_off +defparam \Sample[2]~input .bus_hold = "false"; +defparam \Sample[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N14 +cycloneive_lcell_comb \Add1~22 ( +// Equation(s): +// \Add1~22_combout = (\Sample[2]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[2]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~22_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~22 .lut_mask = 16'hFFF0; +defparam \Add1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N8 +cycloneive_io_ibuf \Sample[1]~input ( + .i(Sample[1]), + .ibar(gnd), + .o(\Sample[1]~input_o )); +// synopsys translate_off +defparam \Sample[1]~input .bus_hold = "false"; +defparam \Sample[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N4 +cycloneive_lcell_comb \Add1~24 ( +// Equation(s): +// \Add1~24_combout = (\Sample[1]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[1]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~24_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~24 .lut_mask = 16'hFFF0; +defparam \Add1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N1 +cycloneive_io_ibuf \SetPoint[1]~input ( + .i(SetPoint[1]), + .ibar(gnd), + .o(\SetPoint[1]~input_o )); +// synopsys translate_off +defparam \SetPoint[1]~input .bus_hold = "false"; +defparam \SetPoint[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \Sample[0]~input ( + .i(Sample[0]), + .ibar(gnd), + .o(\Sample[0]~input_o )); +// synopsys translate_off +defparam \Sample[0]~input .bus_hold = "false"; +defparam \Sample[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N12 +cycloneive_lcell_comb \Add1~26 ( +// Equation(s): +// \Add1~26_combout = (\EE0[13]~_Duplicate_1_q ) # (!\Sample[0]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[0]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~26_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~26 .lut_mask = 16'hFF0F; +defparam \Add1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N0 +cycloneive_lcell_comb \EE0[0]~15 ( +// Equation(s): +// \EE0[0]~15_cout = CARRY(!\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\EE0[0]~15_cout )); +// synopsys translate_off +defparam \EE0[0]~15 .lut_mask = 16'h0033; +defparam \EE0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N2 +cycloneive_lcell_comb \EE0[0]~16 ( +// Equation(s): +// \EE0[0]~16_combout = (\Add1~27_combout & ((\Add1~26_combout & (\EE0[0]~15_cout & VCC)) # (!\Add1~26_combout & (!\EE0[0]~15_cout )))) # (!\Add1~27_combout & ((\Add1~26_combout & (!\EE0[0]~15_cout )) # (!\Add1~26_combout & ((\EE0[0]~15_cout ) # +// (GND))))) +// \EE0[0]~17 = CARRY((\Add1~27_combout & (!\Add1~26_combout & !\EE0[0]~15_cout )) # (!\Add1~27_combout & ((!\EE0[0]~15_cout ) # (!\Add1~26_combout )))) + + .dataa(\Add1~27_combout ), + .datab(\Add1~26_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[0]~15_cout ), + .combout(\EE0[0]~16_combout ), + .cout(\EE0[0]~17 )); +// synopsys translate_off +defparam \EE0[0]~16 .lut_mask = 16'h9617; +defparam \EE0[0]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N4 +cycloneive_lcell_comb \EE0[1]~18 ( +// Equation(s): +// \EE0[1]~18_combout = ((\Add1~24_combout $ (\Add1~25_combout $ (\EE0[0]~17 )))) # (GND) +// \EE0[1]~19 = CARRY((\Add1~24_combout & (\Add1~25_combout & !\EE0[0]~17 )) # (!\Add1~24_combout & ((\Add1~25_combout ) # (!\EE0[0]~17 )))) + + .dataa(\Add1~24_combout ), + .datab(\Add1~25_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[0]~17 ), + .combout(\EE0[1]~18_combout ), + .cout(\EE0[1]~19 )); +// synopsys translate_off +defparam \EE0[1]~18 .lut_mask = 16'h964D; +defparam \EE0[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \Add0~0 ( +// Equation(s): +// \Add0~0_combout = period[0] $ (VCC) +// \Add0~1 = CARRY(period[0]) + + .dataa(gnd), + .datab(period[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add0~0_combout ), + .cout(\Add0~1 )); +// synopsys translate_off +defparam \Add0~0 .lut_mask = 16'h33CC; +defparam \Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N6 +cycloneive_lcell_comb \period~3 ( +// Equation(s): +// \period~3_combout = (\Add0~0_combout & (((!\Equal0~2_combout ) # (!\Equal0~0_combout )) # (!\Equal0~1_combout ))) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~0_combout ), + .datac(\Add0~0_combout ), + .datad(\Equal0~2_combout ), + .cin(gnd), + .combout(\period~3_combout ), + .cout()); +// synopsys translate_off +defparam \period~3 .lut_mask = 16'h70F0; +defparam \period~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y13_N7 +dffeas \period[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~3_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[0]), + .prn(vcc)); +// synopsys translate_off +defparam \period[0] .is_wysiwyg = "true"; +defparam \period[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \Add0~2 ( +// Equation(s): +// \Add0~2_combout = (period[1] & (!\Add0~1 )) # (!period[1] & ((\Add0~1 ) # (GND))) +// \Add0~3 = CARRY((!\Add0~1 ) # (!period[1])) + + .dataa(period[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~1 ), + .combout(\Add0~2_combout ), + .cout(\Add0~3 )); +// synopsys translate_off +defparam \Add0~2 .lut_mask = 16'h5A5F; +defparam \Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N7 +dffeas \period[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~2_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[1]), + .prn(vcc)); +// synopsys translate_off +defparam \period[1] .is_wysiwyg = "true"; +defparam \period[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N8 +cycloneive_lcell_comb \Add0~4 ( +// Equation(s): +// \Add0~4_combout = (period[2] & (\Add0~3 $ (GND))) # (!period[2] & (!\Add0~3 & VCC)) +// \Add0~5 = CARRY((period[2] & !\Add0~3 )) + + .dataa(gnd), + .datab(period[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~3 ), + .combout(\Add0~4_combout ), + .cout(\Add0~5 )); +// synopsys translate_off +defparam \Add0~4 .lut_mask = 16'hC30C; +defparam \Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N9 +dffeas \period[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~4_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[2]), + .prn(vcc)); +// synopsys translate_off +defparam \period[2] .is_wysiwyg = "true"; +defparam \period[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N16 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!period[0] & (!period[2] & !period[1])) + + .dataa(period[0]), + .datab(gnd), + .datac(period[2]), + .datad(period[1]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0005; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \Add0~6 ( +// Equation(s): +// \Add0~6_combout = (period[3] & (!\Add0~5 )) # (!period[3] & ((\Add0~5 ) # (GND))) +// \Add0~7 = CARRY((!\Add0~5 ) # (!period[3])) + + .dataa(gnd), + .datab(period[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~5 ), + .combout(\Add0~6_combout ), + .cout(\Add0~7 )); +// synopsys translate_off +defparam \Add0~6 .lut_mask = 16'h3C3F; +defparam \Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N0 +cycloneive_lcell_comb \period~2 ( +// Equation(s): +// \period~2_combout = (\Add0~6_combout & (((!\Equal0~0_combout ) # (!\Equal0~1_combout )) # (!\Equal0~2_combout ))) + + .dataa(\Equal0~2_combout ), + .datab(\Equal0~1_combout ), + .datac(\Equal0~0_combout ), + .datad(\Add0~6_combout ), + .cin(gnd), + .combout(\period~2_combout ), + .cout()); +// synopsys translate_off +defparam \period~2 .lut_mask = 16'h7F00; +defparam \period~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N1 +dffeas \period[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~2_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[3]), + .prn(vcc)); +// synopsys translate_off +defparam \period[3] .is_wysiwyg = "true"; +defparam \period[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \Add0~8 ( +// Equation(s): +// \Add0~8_combout = (period[4] & (\Add0~7 $ (GND))) # (!period[4] & (!\Add0~7 & VCC)) +// \Add0~9 = CARRY((period[4] & !\Add0~7 )) + + .dataa(period[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~7 ), + .combout(\Add0~8_combout ), + .cout(\Add0~9 )); +// synopsys translate_off +defparam \Add0~8 .lut_mask = 16'hA50A; +defparam \Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N13 +dffeas \period[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~8_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[4]), + .prn(vcc)); +// synopsys translate_off +defparam \period[4] .is_wysiwyg = "true"; +defparam \period[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N14 +cycloneive_lcell_comb \Add0~10 ( +// Equation(s): +// \Add0~10_combout = (period[5] & (!\Add0~9 )) # (!period[5] & ((\Add0~9 ) # (GND))) +// \Add0~11 = CARRY((!\Add0~9 ) # (!period[5])) + + .dataa(gnd), + .datab(period[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~9 ), + .combout(\Add0~10_combout ), + .cout(\Add0~11 )); +// synopsys translate_off +defparam \Add0~10 .lut_mask = 16'h3C3F; +defparam \Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N15 +dffeas \period[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~10_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[5]), + .prn(vcc)); +// synopsys translate_off +defparam \period[5] .is_wysiwyg = "true"; +defparam \period[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \Add0~12 ( +// Equation(s): +// \Add0~12_combout = (period[6] & (\Add0~11 $ (GND))) # (!period[6] & (!\Add0~11 & VCC)) +// \Add0~13 = CARRY((period[6] & !\Add0~11 )) + + .dataa(period[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~11 ), + .combout(\Add0~12_combout ), + .cout(\Add0~13 )); +// synopsys translate_off +defparam \Add0~12 .lut_mask = 16'hA50A; +defparam \Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \Add0~14 ( +// Equation(s): +// \Add0~14_combout = (period[7] & (!\Add0~13 )) # (!period[7] & ((\Add0~13 ) # (GND))) +// \Add0~15 = CARRY((!\Add0~13 ) # (!period[7])) + + .dataa(gnd), + .datab(period[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~13 ), + .combout(\Add0~14_combout ), + .cout(\Add0~15 )); +// synopsys translate_off +defparam \Add0~14 .lut_mask = 16'h3C3F; +defparam \Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \period~0 ( +// Equation(s): +// \period~0_combout = (\Add0~14_combout & (((!\Equal0~1_combout ) # (!\Equal0~2_combout )) # (!\Equal0~0_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Add0~14_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\period~0_combout ), + .cout()); +// synopsys translate_off +defparam \period~0 .lut_mask = 16'h4CCC; +defparam \period~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N29 +dffeas \period[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~0_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[7]), + .prn(vcc)); +// synopsys translate_off +defparam \period[7] .is_wysiwyg = "true"; +defparam \period[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N20 +cycloneive_lcell_comb \Add0~16 ( +// Equation(s): +// \Add0~16_combout = (period[8] & (\Add0~15 $ (GND))) # (!period[8] & (!\Add0~15 & VCC)) +// \Add0~17 = CARRY((period[8] & !\Add0~15 )) + + .dataa(gnd), + .datab(period[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~15 ), + .combout(\Add0~16_combout ), + .cout(\Add0~17 )); +// synopsys translate_off +defparam \Add0~16 .lut_mask = 16'hC30C; +defparam \Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N21 +dffeas \period[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~16_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[8]), + .prn(vcc)); +// synopsys translate_off +defparam \period[8] .is_wysiwyg = "true"; +defparam \period[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \Add0~18 ( +// Equation(s): +// \Add0~18_combout = (period[9] & (!\Add0~17 )) # (!period[9] & ((\Add0~17 ) # (GND))) +// \Add0~19 = CARRY((!\Add0~17 ) # (!period[9])) + + .dataa(period[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~17 ), + .combout(\Add0~18_combout ), + .cout(\Add0~19 )); +// synopsys translate_off +defparam \Add0~18 .lut_mask = 16'h5A5F; +defparam \Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N23 +dffeas \period[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~18_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[9]), + .prn(vcc)); +// synopsys translate_off +defparam \period[9] .is_wysiwyg = "true"; +defparam \period[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \Add0~20 ( +// Equation(s): +// \Add0~20_combout = \Add0~19 $ (!period[10]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(period[10]), + .cin(\Add0~19 ), + .combout(\Add0~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add0~20 .lut_mask = 16'hF00F; +defparam \Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N25 +dffeas \period[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~20_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[10]), + .prn(vcc)); +// synopsys translate_off +defparam \period[10] .is_wysiwyg = "true"; +defparam \period[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!period[10] & (!period[8] & (!period[9] & period[7]))) + + .dataa(period[10]), + .datab(period[8]), + .datac(period[9]), + .datad(period[7]), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0100; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \period~1 ( +// Equation(s): +// \period~1_combout = (\Add0~12_combout & (((!\Equal0~1_combout ) # (!\Equal0~2_combout )) # (!\Equal0~0_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Add0~12_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\period~1_combout ), + .cout()); +// synopsys translate_off +defparam \period~1 .lut_mask = 16'h4CCC; +defparam \period~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N31 +dffeas \period[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~1_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[6]), + .prn(vcc)); +// synopsys translate_off +defparam \period[6] .is_wysiwyg = "true"; +defparam \period[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N2 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (period[6] & (period[3] & (!period[5] & !period[4]))) + + .dataa(period[6]), + .datab(period[3]), + .datac(period[5]), + .datad(period[4]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0008; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N0 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~0_combout )) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~2_combout ), + .datac(gnd), + .datad(\Equal0~0_combout ), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h8800; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y13_N1 +dffeas Clk_Ctrl( + .clk(\clk~inputclkctrl_outclk ), + .d(\Equal0~3_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\Clk_Ctrl~q ), + .prn(vcc)); +// synopsys translate_off +defparam Clk_Ctrl.is_wysiwyg = "true"; +defparam Clk_Ctrl.power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y18_N5 +dffeas \EE0[1]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[1]~18_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[1]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[1]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[1]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N10 +cycloneive_lcell_comb \Add1~25 ( +// Equation(s): +// \Add1~25_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[1]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[1]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[1]~input_o ), + .datac(\EE0[1]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~25_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~25 .lut_mask = 16'h0FCC; +defparam \Add1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N6 +cycloneive_lcell_comb \EE0[2]~20 ( +// Equation(s): +// \EE0[2]~20_combout = (\Add1~23_combout & ((\Add1~22_combout & (!\EE0[1]~19 )) # (!\Add1~22_combout & (\EE0[1]~19 & VCC)))) # (!\Add1~23_combout & ((\Add1~22_combout & ((\EE0[1]~19 ) # (GND))) # (!\Add1~22_combout & (!\EE0[1]~19 )))) +// \EE0[2]~21 = CARRY((\Add1~23_combout & (\Add1~22_combout & !\EE0[1]~19 )) # (!\Add1~23_combout & ((\Add1~22_combout ) # (!\EE0[1]~19 )))) + + .dataa(\Add1~23_combout ), + .datab(\Add1~22_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[1]~19 ), + .combout(\EE0[2]~20_combout ), + .cout(\EE0[2]~21 )); +// synopsys translate_off +defparam \EE0[2]~20 .lut_mask = 16'h694D; +defparam \EE0[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N7 +dffeas \EE0[2]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[2]~20_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[2]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[2]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[2]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N30 +cycloneive_lcell_comb \Add1~23 ( +// Equation(s): +// \Add1~23_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[2]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[2]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[2]~input_o ), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[2]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~23_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~23 .lut_mask = 16'h0CFC; +defparam \Add1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N8 +cycloneive_lcell_comb \EE0[3]~22 ( +// Equation(s): +// \EE0[3]~22_combout = ((\Add1~20_combout $ (\Add1~21_combout $ (\EE0[2]~21 )))) # (GND) +// \EE0[3]~23 = CARRY((\Add1~20_combout & (\Add1~21_combout & !\EE0[2]~21 )) # (!\Add1~20_combout & ((\Add1~21_combout ) # (!\EE0[2]~21 )))) + + .dataa(\Add1~20_combout ), + .datab(\Add1~21_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[2]~21 ), + .combout(\EE0[3]~22_combout ), + .cout(\EE0[3]~23 )); +// synopsys translate_off +defparam \EE0[3]~22 .lut_mask = 16'h964D; +defparam \EE0[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N9 +dffeas \EE0[3]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[3]~22_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[3]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[3]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[3]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N15 +cycloneive_io_ibuf \SetPoint[3]~input ( + .i(SetPoint[3]), + .ibar(gnd), + .o(\SetPoint[3]~input_o )); +// synopsys translate_off +defparam \SetPoint[3]~input .bus_hold = "false"; +defparam \SetPoint[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N28 +cycloneive_lcell_comb \Add1~21 ( +// Equation(s): +// \Add1~21_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[3]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[3]~input_o ))) + + .dataa(\EE0[3]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[3]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~21_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~21 .lut_mask = 16'h55F0; +defparam \Add1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N10 +cycloneive_lcell_comb \EE0[4]~24 ( +// Equation(s): +// \EE0[4]~24_combout = (\Add1~19_combout & ((\Add1~18_combout & (!\EE0[3]~23 )) # (!\Add1~18_combout & (\EE0[3]~23 & VCC)))) # (!\Add1~19_combout & ((\Add1~18_combout & ((\EE0[3]~23 ) # (GND))) # (!\Add1~18_combout & (!\EE0[3]~23 )))) +// \EE0[4]~25 = CARRY((\Add1~19_combout & (\Add1~18_combout & !\EE0[3]~23 )) # (!\Add1~19_combout & ((\Add1~18_combout ) # (!\EE0[3]~23 )))) + + .dataa(\Add1~19_combout ), + .datab(\Add1~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[3]~23 ), + .combout(\EE0[4]~24_combout ), + .cout(\EE0[4]~25 )); +// synopsys translate_off +defparam \EE0[4]~24 .lut_mask = 16'h694D; +defparam \EE0[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N11 +dffeas \EE0[4]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[4]~24_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[4]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[4]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[4]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N22 +cycloneive_lcell_comb \Add1~19 ( +// Equation(s): +// \Add1~19_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[4]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[4]~input_o )) + + .dataa(\SetPoint[4]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[4]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~19 .lut_mask = 16'h0AFA; +defparam \Add1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N12 +cycloneive_lcell_comb \EE0[5]~26 ( +// Equation(s): +// \EE0[5]~26_combout = ((\Add1~16_combout $ (\Add1~17_combout $ (\EE0[4]~25 )))) # (GND) +// \EE0[5]~27 = CARRY((\Add1~16_combout & (\Add1~17_combout & !\EE0[4]~25 )) # (!\Add1~16_combout & ((\Add1~17_combout ) # (!\EE0[4]~25 )))) + + .dataa(\Add1~16_combout ), + .datab(\Add1~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[4]~25 ), + .combout(\EE0[5]~26_combout ), + .cout(\EE0[5]~27 )); +// synopsys translate_off +defparam \EE0[5]~26 .lut_mask = 16'h964D; +defparam \EE0[5]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N13 +dffeas \EE0[5]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[5]~26_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[5]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[5]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[5]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N8 +cycloneive_io_ibuf \SetPoint[5]~input ( + .i(SetPoint[5]), + .ibar(gnd), + .o(\SetPoint[5]~input_o )); +// synopsys translate_off +defparam \SetPoint[5]~input .bus_hold = "false"; +defparam \SetPoint[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N18 +cycloneive_lcell_comb \Add1~17 ( +// Equation(s): +// \Add1~17_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[5]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[5]~input_o ))) + + .dataa(\EE0[5]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[5]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~17 .lut_mask = 16'h55F0; +defparam \Add1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N14 +cycloneive_lcell_comb \EE0[6]~28 ( +// Equation(s): +// \EE0[6]~28_combout = (\Add1~15_combout & ((\Add1~14_combout & (!\EE0[5]~27 )) # (!\Add1~14_combout & (\EE0[5]~27 & VCC)))) # (!\Add1~15_combout & ((\Add1~14_combout & ((\EE0[5]~27 ) # (GND))) # (!\Add1~14_combout & (!\EE0[5]~27 )))) +// \EE0[6]~29 = CARRY((\Add1~15_combout & (\Add1~14_combout & !\EE0[5]~27 )) # (!\Add1~15_combout & ((\Add1~14_combout ) # (!\EE0[5]~27 )))) + + .dataa(\Add1~15_combout ), + .datab(\Add1~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[5]~27 ), + .combout(\EE0[6]~28_combout ), + .cout(\EE0[6]~29 )); +// synopsys translate_off +defparam \EE0[6]~28 .lut_mask = 16'h694D; +defparam \EE0[6]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N15 +dffeas \EE0[6]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[6]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[6]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[6]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[6]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N20 +cycloneive_lcell_comb \Add1~15 ( +// Equation(s): +// \Add1~15_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[6]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[6]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[6]~input_o ), + .datad(\EE0[6]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~15_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~15 .lut_mask = 16'h30FC; +defparam \Add1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N16 +cycloneive_lcell_comb \EE0[7]~30 ( +// Equation(s): +// \EE0[7]~30_combout = ((\Add1~12_combout $ (\Add1~13_combout $ (\EE0[6]~29 )))) # (GND) +// \EE0[7]~31 = CARRY((\Add1~12_combout & (\Add1~13_combout & !\EE0[6]~29 )) # (!\Add1~12_combout & ((\Add1~13_combout ) # (!\EE0[6]~29 )))) + + .dataa(\Add1~12_combout ), + .datab(\Add1~13_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[6]~29 ), + .combout(\EE0[7]~30_combout ), + .cout(\EE0[7]~31 )); +// synopsys translate_off +defparam \EE0[7]~30 .lut_mask = 16'h964D; +defparam \EE0[7]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N17 +dffeas \EE0[7]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[7]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[7]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[7]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[7]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N24 +cycloneive_lcell_comb \Add1~13 ( +// Equation(s): +// \Add1~13_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[7]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[7]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[7]~input_o ), + .datac(\EE0[7]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~13_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~13 .lut_mask = 16'h0FCC; +defparam \Add1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N18 +cycloneive_lcell_comb \EE0[8]~32 ( +// Equation(s): +// \EE0[8]~32_combout = (\Add1~11_combout & ((\Add1~10_combout & (!\EE0[7]~31 )) # (!\Add1~10_combout & (\EE0[7]~31 & VCC)))) # (!\Add1~11_combout & ((\Add1~10_combout & ((\EE0[7]~31 ) # (GND))) # (!\Add1~10_combout & (!\EE0[7]~31 )))) +// \EE0[8]~33 = CARRY((\Add1~11_combout & (\Add1~10_combout & !\EE0[7]~31 )) # (!\Add1~11_combout & ((\Add1~10_combout ) # (!\EE0[7]~31 )))) + + .dataa(\Add1~11_combout ), + .datab(\Add1~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[7]~31 ), + .combout(\EE0[8]~32_combout ), + .cout(\EE0[8]~33 )); +// synopsys translate_off +defparam \EE0[8]~32 .lut_mask = 16'h694D; +defparam \EE0[8]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N19 +dffeas \EE0[8]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[8]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[8]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[8]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[8]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N30 +cycloneive_lcell_comb \Add1~11 ( +// Equation(s): +// \Add1~11_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[8]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[8]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[8]~input_o ), + .datad(\EE0[8]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~11_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~11 .lut_mask = 16'h30FC; +defparam \Add1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N20 +cycloneive_lcell_comb \EE0[9]~34 ( +// Equation(s): +// \EE0[9]~34_combout = ((\Add1~8_combout $ (\Add1~9_combout $ (\EE0[8]~33 )))) # (GND) +// \EE0[9]~35 = CARRY((\Add1~8_combout & (\Add1~9_combout & !\EE0[8]~33 )) # (!\Add1~8_combout & ((\Add1~9_combout ) # (!\EE0[8]~33 )))) + + .dataa(\Add1~8_combout ), + .datab(\Add1~9_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[8]~33 ), + .combout(\EE0[9]~34_combout ), + .cout(\EE0[9]~35 )); +// synopsys translate_off +defparam \EE0[9]~34 .lut_mask = 16'h964D; +defparam \EE0[9]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N21 +dffeas \EE0[9]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[9]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[9]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[9]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[9]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N8 +cycloneive_lcell_comb \Add1~9 ( +// Equation(s): +// \Add1~9_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[9]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[9]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[9]~input_o ), + .datad(\EE0[9]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~9_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~9 .lut_mask = 16'h30FC; +defparam \Add1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N22 +cycloneive_lcell_comb \EE0[10]~36 ( +// Equation(s): +// \EE0[10]~36_combout = (\Add1~7_combout & ((\Add1~6_combout & (!\EE0[9]~35 )) # (!\Add1~6_combout & (\EE0[9]~35 & VCC)))) # (!\Add1~7_combout & ((\Add1~6_combout & ((\EE0[9]~35 ) # (GND))) # (!\Add1~6_combout & (!\EE0[9]~35 )))) +// \EE0[10]~37 = CARRY((\Add1~7_combout & (\Add1~6_combout & !\EE0[9]~35 )) # (!\Add1~7_combout & ((\Add1~6_combout ) # (!\EE0[9]~35 )))) + + .dataa(\Add1~7_combout ), + .datab(\Add1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[9]~35 ), + .combout(\EE0[10]~36_combout ), + .cout(\EE0[10]~37 )); +// synopsys translate_off +defparam \EE0[10]~36 .lut_mask = 16'h694D; +defparam \EE0[10]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N23 +dffeas \EE0[10]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[10]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[10]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[10]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[10]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N26 +cycloneive_lcell_comb \Add1~7 ( +// Equation(s): +// \Add1~7_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[10]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[10]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[10]~input_o ), + .datad(\EE0[10]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~7_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~7 .lut_mask = 16'h30FC; +defparam \Add1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N24 +cycloneive_lcell_comb \EE0[11]~38 ( +// Equation(s): +// \EE0[11]~38_combout = ((\Add1~4_combout $ (\Add1~5_combout $ (\EE0[10]~37 )))) # (GND) +// \EE0[11]~39 = CARRY((\Add1~4_combout & (\Add1~5_combout & !\EE0[10]~37 )) # (!\Add1~4_combout & ((\Add1~5_combout ) # (!\EE0[10]~37 )))) + + .dataa(\Add1~4_combout ), + .datab(\Add1~5_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[10]~37 ), + .combout(\EE0[11]~38_combout ), + .cout(\EE0[11]~39 )); +// synopsys translate_off +defparam \EE0[11]~38 .lut_mask = 16'h964D; +defparam \EE0[11]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N25 +dffeas \EE0[11]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[11]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[11]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[11]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[11]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \Add1~5 ( +// Equation(s): +// \Add1~5_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[11]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[11]~input_o )) + + .dataa(\SetPoint[11]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[11]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~5_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~5 .lut_mask = 16'h0AFA; +defparam \Add1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N26 +cycloneive_lcell_comb \EE0[12]~40 ( +// Equation(s): +// \EE0[12]~40_combout = (\Add1~2_combout & ((\Add1~3_combout & (!\EE0[11]~39 )) # (!\Add1~3_combout & ((\EE0[11]~39 ) # (GND))))) # (!\Add1~2_combout & ((\Add1~3_combout & (\EE0[11]~39 & VCC)) # (!\Add1~3_combout & (!\EE0[11]~39 )))) +// \EE0[12]~41 = CARRY((\Add1~2_combout & ((!\EE0[11]~39 ) # (!\Add1~3_combout ))) # (!\Add1~2_combout & (!\Add1~3_combout & !\EE0[11]~39 ))) + + .dataa(\Add1~2_combout ), + .datab(\Add1~3_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[11]~39 ), + .combout(\EE0[12]~40_combout ), + .cout(\EE0[12]~41 )); +// synopsys translate_off +defparam \EE0[12]~40 .lut_mask = 16'h692B; +defparam \EE0[12]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N27 +dffeas \EE0[12]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[12]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[12]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[12]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[12]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N0 +cycloneive_lcell_comb \Add1~3 ( +// Equation(s): +// \Add1~3_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[12]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[12]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[12]~input_o ), + .datac(\EE0[12]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~3_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~3 .lut_mask = 16'h0FCC; +defparam \Add1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N28 +cycloneive_lcell_comb \EE0[13]~42 ( +// Equation(s): +// \EE0[13]~42_combout = \Add1~1_combout $ (\EE0[12]~41 $ (\Add1~0_combout )) + + .dataa(gnd), + .datab(\Add1~1_combout ), + .datac(gnd), + .datad(\Add1~0_combout ), + .cin(\EE0[12]~41 ), + .combout(\EE0[13]~42_combout ), + .cout()); +// synopsys translate_off +defparam \EE0[13]~42 .lut_mask = 16'hC33C; +defparam \EE0[13]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N31 +dffeas \EE0[13]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\EE0[13]~42_combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[13]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[13]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[13]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N2 +cycloneive_lcell_comb \Add1~27 ( +// Equation(s): +// \Add1~27_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[0]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[0]~input_o ))) + + .dataa(\EE0[0]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[0]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~27_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~27 .lut_mask = 16'h55F0; +defparam \Add1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y18_N3 +dffeas \EE0[0]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[0]~16_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[0]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[0]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[0]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N4 +cycloneive_lcell_comb \EE1[1]~16 ( +// Equation(s): +// \EE1[1]~16_combout = (EE1[1] & ((\EE1[0]~15 ) # (GND))) # (!EE1[1] & (!\EE1[0]~15 )) +// \EE1[1]~17 = CARRY((EE1[1]) # (!\EE1[0]~15 )) + + .dataa(gnd), + .datab(EE1[1]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[0]~15 ), + .combout(\EE1[1]~16_combout ), + .cout(\EE1[1]~17 )); +// synopsys translate_off +defparam \EE1[1]~16 .lut_mask = 16'hC3CF; +defparam \EE1[1]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N5 +dffeas \EE1[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[1]~16_combout ), + .asdata(\EE0[1]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[1]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[1] .is_wysiwyg = "true"; +defparam \EE1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N6 +cycloneive_lcell_comb \EE1[2]~18 ( +// Equation(s): +// \EE1[2]~18_combout = (EE1[2] & (!\EE1[1]~17 & VCC)) # (!EE1[2] & (\EE1[1]~17 $ (GND))) +// \EE1[2]~19 = CARRY((!EE1[2] & !\EE1[1]~17 )) + + .dataa(EE1[2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[1]~17 ), + .combout(\EE1[2]~18_combout ), + .cout(\EE1[2]~19 )); +// synopsys translate_off +defparam \EE1[2]~18 .lut_mask = 16'h5A05; +defparam \EE1[2]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N7 +dffeas \EE1[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[2]~18_combout ), + .asdata(\EE0[2]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[2]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[2] .is_wysiwyg = "true"; +defparam \EE1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N8 +cycloneive_lcell_comb \EE1[3]~20 ( +// Equation(s): +// \EE1[3]~20_combout = (EE1[3] & ((\EE1[2]~19 ) # (GND))) # (!EE1[3] & (!\EE1[2]~19 )) +// \EE1[3]~21 = CARRY((EE1[3]) # (!\EE1[2]~19 )) + + .dataa(gnd), + .datab(EE1[3]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[2]~19 ), + .combout(\EE1[3]~20_combout ), + .cout(\EE1[3]~21 )); +// synopsys translate_off +defparam \EE1[3]~20 .lut_mask = 16'hC3CF; +defparam \EE1[3]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N9 +dffeas \EE1[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[3]~20_combout ), + .asdata(\EE0[3]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[3]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[3] .is_wysiwyg = "true"; +defparam \EE1[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N10 +cycloneive_lcell_comb \EE1[4]~22 ( +// Equation(s): +// \EE1[4]~22_combout = (EE1[4] & (!\EE1[3]~21 & VCC)) # (!EE1[4] & (\EE1[3]~21 $ (GND))) +// \EE1[4]~23 = CARRY((!EE1[4] & !\EE1[3]~21 )) + + .dataa(EE1[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[3]~21 ), + .combout(\EE1[4]~22_combout ), + .cout(\EE1[4]~23 )); +// synopsys translate_off +defparam \EE1[4]~22 .lut_mask = 16'h5A05; +defparam \EE1[4]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N11 +dffeas \EE1[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[4]~22_combout ), + .asdata(\EE0[4]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[4]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[4] .is_wysiwyg = "true"; +defparam \EE1[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N12 +cycloneive_lcell_comb \EE1[5]~24 ( +// Equation(s): +// \EE1[5]~24_combout = (EE1[5] & ((\EE1[4]~23 ) # (GND))) # (!EE1[5] & (!\EE1[4]~23 )) +// \EE1[5]~25 = CARRY((EE1[5]) # (!\EE1[4]~23 )) + + .dataa(EE1[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[4]~23 ), + .combout(\EE1[5]~24_combout ), + .cout(\EE1[5]~25 )); +// synopsys translate_off +defparam \EE1[5]~24 .lut_mask = 16'hA5AF; +defparam \EE1[5]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N13 +dffeas \EE1[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[5]~24_combout ), + .asdata(\EE0[5]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[5]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[5] .is_wysiwyg = "true"; +defparam \EE1[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N14 +cycloneive_lcell_comb \EE1[6]~26 ( +// Equation(s): +// \EE1[6]~26_combout = (EE1[6] & (!\EE1[5]~25 & VCC)) # (!EE1[6] & (\EE1[5]~25 $ (GND))) +// \EE1[6]~27 = CARRY((!EE1[6] & !\EE1[5]~25 )) + + .dataa(gnd), + .datab(EE1[6]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[5]~25 ), + .combout(\EE1[6]~26_combout ), + .cout(\EE1[6]~27 )); +// synopsys translate_off +defparam \EE1[6]~26 .lut_mask = 16'h3C03; +defparam \EE1[6]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N15 +dffeas \EE1[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[6]~26_combout ), + .asdata(\EE0[6]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[6]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[6] .is_wysiwyg = "true"; +defparam \EE1[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N16 +cycloneive_lcell_comb \EE1[7]~28 ( +// Equation(s): +// \EE1[7]~28_combout = (EE1[7] & ((\EE1[6]~27 ) # (GND))) # (!EE1[7] & (!\EE1[6]~27 )) +// \EE1[7]~29 = CARRY((EE1[7]) # (!\EE1[6]~27 )) + + .dataa(gnd), + .datab(EE1[7]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[6]~27 ), + .combout(\EE1[7]~28_combout ), + .cout(\EE1[7]~29 )); +// synopsys translate_off +defparam \EE1[7]~28 .lut_mask = 16'hC3CF; +defparam \EE1[7]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N17 +dffeas \EE1[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[7]~28_combout ), + .asdata(\EE0[7]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[7]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[7] .is_wysiwyg = "true"; +defparam \EE1[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N18 +cycloneive_lcell_comb \EE1[8]~30 ( +// Equation(s): +// \EE1[8]~30_combout = (EE1[8] & (!\EE1[7]~29 & VCC)) # (!EE1[8] & (\EE1[7]~29 $ (GND))) +// \EE1[8]~31 = CARRY((!EE1[8] & !\EE1[7]~29 )) + + .dataa(gnd), + .datab(EE1[8]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[7]~29 ), + .combout(\EE1[8]~30_combout ), + .cout(\EE1[8]~31 )); +// synopsys translate_off +defparam \EE1[8]~30 .lut_mask = 16'h3C03; +defparam \EE1[8]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N19 +dffeas \EE1[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[8]~30_combout ), + .asdata(\EE0[8]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[8]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[8] .is_wysiwyg = "true"; +defparam \EE1[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N20 +cycloneive_lcell_comb \EE1[9]~32 ( +// Equation(s): +// \EE1[9]~32_combout = (EE1[9] & ((\EE1[8]~31 ) # (GND))) # (!EE1[9] & (!\EE1[8]~31 )) +// \EE1[9]~33 = CARRY((EE1[9]) # (!\EE1[8]~31 )) + + .dataa(gnd), + .datab(EE1[9]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[8]~31 ), + .combout(\EE1[9]~32_combout ), + .cout(\EE1[9]~33 )); +// synopsys translate_off +defparam \EE1[9]~32 .lut_mask = 16'hC3CF; +defparam \EE1[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N21 +dffeas \EE1[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[9]~32_combout ), + .asdata(\EE0[9]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[9]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[9] .is_wysiwyg = "true"; +defparam \EE1[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N22 +cycloneive_lcell_comb \EE1[10]~34 ( +// Equation(s): +// \EE1[10]~34_combout = (EE1[10] & (!\EE1[9]~33 & VCC)) # (!EE1[10] & (\EE1[9]~33 $ (GND))) +// \EE1[10]~35 = CARRY((!EE1[10] & !\EE1[9]~33 )) + + .dataa(EE1[10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[9]~33 ), + .combout(\EE1[10]~34_combout ), + .cout(\EE1[10]~35 )); +// synopsys translate_off +defparam \EE1[10]~34 .lut_mask = 16'h5A05; +defparam \EE1[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N23 +dffeas \EE1[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[10]~34_combout ), + .asdata(\EE0[10]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[10]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[10] .is_wysiwyg = "true"; +defparam \EE1[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N24 +cycloneive_lcell_comb \EE1[11]~36 ( +// Equation(s): +// \EE1[11]~36_combout = (EE1[11] & ((\EE1[10]~35 ) # (GND))) # (!EE1[11] & (!\EE1[10]~35 )) +// \EE1[11]~37 = CARRY((EE1[11]) # (!\EE1[10]~35 )) + + .dataa(gnd), + .datab(EE1[11]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[10]~35 ), + .combout(\EE1[11]~36_combout ), + .cout(\EE1[11]~37 )); +// synopsys translate_off +defparam \EE1[11]~36 .lut_mask = 16'hC3CF; +defparam \EE1[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N25 +dffeas \EE1[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[11]~36_combout ), + .asdata(\EE0[11]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[11]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[11] .is_wysiwyg = "true"; +defparam \EE1[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N26 +cycloneive_lcell_comb \EE1[12]~38 ( +// Equation(s): +// \EE1[12]~38_combout = (EE1[12] & (!\EE1[11]~37 & VCC)) # (!EE1[12] & (\EE1[11]~37 $ (GND))) +// \EE1[12]~39 = CARRY((!EE1[12] & !\EE1[11]~37 )) + + .dataa(EE1[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[11]~37 ), + .combout(\EE1[12]~38_combout ), + .cout(\EE1[12]~39 )); +// synopsys translate_off +defparam \EE1[12]~38 .lut_mask = 16'h5A05; +defparam \EE1[12]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N27 +dffeas \EE1[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[12]~38_combout ), + .asdata(\EE0[12]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[12]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[12] .is_wysiwyg = "true"; +defparam \EE1[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N28 +cycloneive_lcell_comb \EE1[13]~40 ( +// Equation(s): +// \EE1[13]~40_combout = \EE1[12]~39 $ (!EE1[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(EE1[13]), + .cin(\EE1[12]~39 ), + .combout(\EE1[13]~40_combout ), + .cout()); +// synopsys translate_off +defparam \EE1[13]~40 .lut_mask = 16'hF00F; +defparam \EE1[13]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N29 +dffeas \EE1[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[13]~40_combout ), + .asdata(\EE0[13]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[13]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[13] .is_wysiwyg = "true"; +defparam \EE1[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y17_N3 +dffeas \EE1[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[0]~14_combout ), + .asdata(\EE0[0]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[0]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[0] .is_wysiwyg = "true"; +defparam \EE1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N6 +cycloneive_lcell_comb \EE2[1]~16 ( +// Equation(s): +// \EE2[1]~16_combout = (EE2[1] & ((\EE2[0]~15 ) # (GND))) # (!EE2[1] & (!\EE2[0]~15 )) +// \EE2[1]~17 = CARRY((EE2[1]) # (!\EE2[0]~15 )) + + .dataa(EE2[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[0]~15 ), + .combout(\EE2[1]~16_combout ), + .cout(\EE2[1]~17 )); +// synopsys translate_off +defparam \EE2[1]~16 .lut_mask = 16'hA5AF; +defparam \EE2[1]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N7 +dffeas \EE2[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[1]~16_combout ), + .asdata(EE1[1]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[1]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[1] .is_wysiwyg = "true"; +defparam \EE2[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \EE2[2]~18 ( +// Equation(s): +// \EE2[2]~18_combout = (EE2[2] & (!\EE2[1]~17 & VCC)) # (!EE2[2] & (\EE2[1]~17 $ (GND))) +// \EE2[2]~19 = CARRY((!EE2[2] & !\EE2[1]~17 )) + + .dataa(gnd), + .datab(EE2[2]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[1]~17 ), + .combout(\EE2[2]~18_combout ), + .cout(\EE2[2]~19 )); +// synopsys translate_off +defparam \EE2[2]~18 .lut_mask = 16'h3C03; +defparam \EE2[2]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N9 +dffeas \EE2[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[2]~18_combout ), + .asdata(EE1[2]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[2]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[2] .is_wysiwyg = "true"; +defparam \EE2[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 +cycloneive_lcell_comb \EE2[3]~20 ( +// Equation(s): +// \EE2[3]~20_combout = (EE2[3] & ((\EE2[2]~19 ) # (GND))) # (!EE2[3] & (!\EE2[2]~19 )) +// \EE2[3]~21 = CARRY((EE2[3]) # (!\EE2[2]~19 )) + + .dataa(EE2[3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[2]~19 ), + .combout(\EE2[3]~20_combout ), + .cout(\EE2[3]~21 )); +// synopsys translate_off +defparam \EE2[3]~20 .lut_mask = 16'hA5AF; +defparam \EE2[3]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N11 +dffeas \EE2[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[3]~20_combout ), + .asdata(EE1[3]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[3]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[3] .is_wysiwyg = "true"; +defparam \EE2[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N12 +cycloneive_lcell_comb \EE2[4]~22 ( +// Equation(s): +// \EE2[4]~22_combout = (EE2[4] & (!\EE2[3]~21 & VCC)) # (!EE2[4] & (\EE2[3]~21 $ (GND))) +// \EE2[4]~23 = CARRY((!EE2[4] & !\EE2[3]~21 )) + + .dataa(EE2[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[3]~21 ), + .combout(\EE2[4]~22_combout ), + .cout(\EE2[4]~23 )); +// synopsys translate_off +defparam \EE2[4]~22 .lut_mask = 16'h5A05; +defparam \EE2[4]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N13 +dffeas \EE2[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[4]~22_combout ), + .asdata(EE1[4]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[4]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[4] .is_wysiwyg = "true"; +defparam \EE2[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \EE2[5]~24 ( +// Equation(s): +// \EE2[5]~24_combout = (EE2[5] & ((\EE2[4]~23 ) # (GND))) # (!EE2[5] & (!\EE2[4]~23 )) +// \EE2[5]~25 = CARRY((EE2[5]) # (!\EE2[4]~23 )) + + .dataa(gnd), + .datab(EE2[5]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[4]~23 ), + .combout(\EE2[5]~24_combout ), + .cout(\EE2[5]~25 )); +// synopsys translate_off +defparam \EE2[5]~24 .lut_mask = 16'hC3CF; +defparam \EE2[5]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N15 +dffeas \EE2[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[5]~24_combout ), + .asdata(EE1[5]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[5]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[5] .is_wysiwyg = "true"; +defparam \EE2[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \EE2[6]~26 ( +// Equation(s): +// \EE2[6]~26_combout = (EE2[6] & (!\EE2[5]~25 & VCC)) # (!EE2[6] & (\EE2[5]~25 $ (GND))) +// \EE2[6]~27 = CARRY((!EE2[6] & !\EE2[5]~25 )) + + .dataa(gnd), + .datab(EE2[6]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[5]~25 ), + .combout(\EE2[6]~26_combout ), + .cout(\EE2[6]~27 )); +// synopsys translate_off +defparam \EE2[6]~26 .lut_mask = 16'h3C03; +defparam \EE2[6]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N17 +dffeas \EE2[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[6]~26_combout ), + .asdata(EE1[6]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[6]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[6] .is_wysiwyg = "true"; +defparam \EE2[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \EE2[7]~28 ( +// Equation(s): +// \EE2[7]~28_combout = (EE2[7] & ((\EE2[6]~27 ) # (GND))) # (!EE2[7] & (!\EE2[6]~27 )) +// \EE2[7]~29 = CARRY((EE2[7]) # (!\EE2[6]~27 )) + + .dataa(gnd), + .datab(EE2[7]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[6]~27 ), + .combout(\EE2[7]~28_combout ), + .cout(\EE2[7]~29 )); +// synopsys translate_off +defparam \EE2[7]~28 .lut_mask = 16'hC3CF; +defparam \EE2[7]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N19 +dffeas \EE2[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[7]~28_combout ), + .asdata(EE1[7]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[7]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[7] .is_wysiwyg = "true"; +defparam \EE2[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \EE2[8]~30 ( +// Equation(s): +// \EE2[8]~30_combout = (EE2[8] & (!\EE2[7]~29 & VCC)) # (!EE2[8] & (\EE2[7]~29 $ (GND))) +// \EE2[8]~31 = CARRY((!EE2[8] & !\EE2[7]~29 )) + + .dataa(gnd), + .datab(EE2[8]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[7]~29 ), + .combout(\EE2[8]~30_combout ), + .cout(\EE2[8]~31 )); +// synopsys translate_off +defparam \EE2[8]~30 .lut_mask = 16'h3C03; +defparam \EE2[8]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N21 +dffeas \EE2[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[8]~30_combout ), + .asdata(EE1[8]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[8]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[8] .is_wysiwyg = "true"; +defparam \EE2[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N22 +cycloneive_lcell_comb \EE2[9]~32 ( +// Equation(s): +// \EE2[9]~32_combout = (EE2[9] & ((\EE2[8]~31 ) # (GND))) # (!EE2[9] & (!\EE2[8]~31 )) +// \EE2[9]~33 = CARRY((EE2[9]) # (!\EE2[8]~31 )) + + .dataa(EE2[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[8]~31 ), + .combout(\EE2[9]~32_combout ), + .cout(\EE2[9]~33 )); +// synopsys translate_off +defparam \EE2[9]~32 .lut_mask = 16'hA5AF; +defparam \EE2[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N23 +dffeas \EE2[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[9]~32_combout ), + .asdata(EE1[9]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[9]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[9] .is_wysiwyg = "true"; +defparam \EE2[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \EE2[10]~34 ( +// Equation(s): +// \EE2[10]~34_combout = (EE2[10] & (!\EE2[9]~33 & VCC)) # (!EE2[10] & (\EE2[9]~33 $ (GND))) +// \EE2[10]~35 = CARRY((!EE2[10] & !\EE2[9]~33 )) + + .dataa(gnd), + .datab(EE2[10]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[9]~33 ), + .combout(\EE2[10]~34_combout ), + .cout(\EE2[10]~35 )); +// synopsys translate_off +defparam \EE2[10]~34 .lut_mask = 16'h3C03; +defparam \EE2[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N25 +dffeas \EE2[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[10]~34_combout ), + .asdata(EE1[10]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[10]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[10] .is_wysiwyg = "true"; +defparam \EE2[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \EE2[11]~36 ( +// Equation(s): +// \EE2[11]~36_combout = (EE2[11] & ((\EE2[10]~35 ) # (GND))) # (!EE2[11] & (!\EE2[10]~35 )) +// \EE2[11]~37 = CARRY((EE2[11]) # (!\EE2[10]~35 )) + + .dataa(EE2[11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[10]~35 ), + .combout(\EE2[11]~36_combout ), + .cout(\EE2[11]~37 )); +// synopsys translate_off +defparam \EE2[11]~36 .lut_mask = 16'hA5AF; +defparam \EE2[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N27 +dffeas \EE2[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[11]~36_combout ), + .asdata(EE1[11]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[11]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[11] .is_wysiwyg = "true"; +defparam \EE2[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \EE2[12]~38 ( +// Equation(s): +// \EE2[12]~38_combout = (EE2[12] & (!\EE2[11]~37 & VCC)) # (!EE2[12] & (\EE2[11]~37 $ (GND))) +// \EE2[12]~39 = CARRY((!EE2[12] & !\EE2[11]~37 )) + + .dataa(gnd), + .datab(EE2[12]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[11]~37 ), + .combout(\EE2[12]~38_combout ), + .cout(\EE2[12]~39 )); +// synopsys translate_off +defparam \EE2[12]~38 .lut_mask = 16'h3C03; +defparam \EE2[12]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N29 +dffeas \EE2[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[12]~38_combout ), + .asdata(EE1[12]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[12]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[12] .is_wysiwyg = "true"; +defparam \EE2[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 +cycloneive_lcell_comb \EE2[13]~40 ( +// Equation(s): +// \EE2[13]~40_combout = EE2[13] $ (!\EE2[12]~39 ) + + .dataa(EE2[13]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\EE2[12]~39 ), + .combout(\EE2[13]~40_combout ), + .cout()); +// synopsys translate_off +defparam \EE2[13]~40 .lut_mask = 16'hA5A5; +defparam \EE2[13]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N31 +dffeas \EE2[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[13]~40_combout ), + .asdata(EE1[13]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[13]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[13] .is_wysiwyg = "true"; +defparam \EE2[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y14_N5 +dffeas \EE2[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[0]~14_combout ), + .asdata(EE1[0]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[0]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[0] .is_wysiwyg = "true"; +defparam \EE2[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N15 +cycloneive_io_ibuf \Kd[0]~input ( + .i(Kd[0]), + .ibar(gnd), + .o(\Kd[0]~input_o )); +// synopsys translate_off +defparam \Kd[0]~input .bus_hold = "false"; +defparam \Kd[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N8 +cycloneive_io_ibuf \Kd[1]~input ( + .i(Kd[1]), + .ibar(gnd), + .o(\Kd[1]~input_o )); +// synopsys translate_off +defparam \Kd[1]~input .bus_hold = "false"; +defparam \Kd[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N1 +cycloneive_io_ibuf \Kd[2]~input ( + .i(Kd[2]), + .ibar(gnd), + .o(\Kd[2]~input_o )); +// synopsys translate_off +defparam \Kd[2]~input .bus_hold = "false"; +defparam \Kd[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N15 +cycloneive_io_ibuf \Kd[3]~input ( + .i(Kd[3]), + .ibar(gnd), + .o(\Kd[3]~input_o )); +// synopsys translate_off +defparam \Kd[3]~input .bus_hold = "false"; +defparam \Kd[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N8 +cycloneive_io_ibuf \Kd[4]~input ( + .i(Kd[4]), + .ibar(gnd), + .o(\Kd[4]~input_o )); +// synopsys translate_off +defparam \Kd[4]~input .bus_hold = "false"; +defparam \Kd[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N8 +cycloneive_io_ibuf \Kd[5]~input ( + .i(Kd[5]), + .ibar(gnd), + .o(\Kd[5]~input_o )); +// synopsys translate_off +defparam \Kd[5]~input .bus_hold = "false"; +defparam \Kd[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N1 +cycloneive_io_ibuf \Kd[6]~input ( + .i(Kd[6]), + .ibar(gnd), + .o(\Kd[6]~input_o )); +// synopsys translate_off +defparam \Kd[6]~input .bus_hold = "false"; +defparam \Kd[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N22 +cycloneive_io_ibuf \Kd[7]~input ( + .i(Kd[7]), + .ibar(gnd), + .o(\Kd[7]~input_o )); +// synopsys translate_off +defparam \Kd[7]~input .bus_hold = "false"; +defparam \Kd[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y14_N0 +cycloneive_mac_mult \Mult2|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({EE2[11],EE2[10],EE2[9],EE2[8],EE2[7],EE2[6],EE2[5],EE2[4],EE2[3],EE2[2],EE2[1],EE2[0],gnd,gnd,gnd,gnd,gnd,gnd}), + .datab({\Kd[7]~input_o ,\Kd[6]~input_o ,\Kd[5]~input_o ,\Kd[4]~input_o ,\Kd[3]~input_o ,\Kd[2]~input_o ,\Kd[1]~input_o ,\Kd[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult2|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult2|auto_generated|mac_mult1 .dataa_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult2|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult2|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y14_N2 +cycloneive_mac_out \Mult2|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult2|auto_generated|mac_mult1~DATAOUT19 ,\Mult2|auto_generated|mac_mult1~DATAOUT18 ,\Mult2|auto_generated|mac_mult1~DATAOUT17 ,\Mult2|auto_generated|mac_mult1~DATAOUT16 ,\Mult2|auto_generated|mac_mult1~DATAOUT15 ,\Mult2|auto_generated|mac_mult1~DATAOUT14 , +\Mult2|auto_generated|mac_mult1~DATAOUT13 ,\Mult2|auto_generated|mac_mult1~DATAOUT12 ,\Mult2|auto_generated|mac_mult1~DATAOUT11 ,\Mult2|auto_generated|mac_mult1~DATAOUT10 ,\Mult2|auto_generated|mac_mult1~DATAOUT9 ,\Mult2|auto_generated|mac_mult1~DATAOUT8 , +\Mult2|auto_generated|mac_mult1~DATAOUT7 ,\Mult2|auto_generated|mac_mult1~DATAOUT6 ,\Mult2|auto_generated|mac_mult1~DATAOUT5 ,\Mult2|auto_generated|mac_mult1~DATAOUT4 ,\Mult2|auto_generated|mac_mult1~DATAOUT3 ,\Mult2|auto_generated|mac_mult1~DATAOUT2 , +\Mult2|auto_generated|mac_mult1~DATAOUT1 ,\Mult2|auto_generated|mac_mult1~dataout ,\Mult2|auto_generated|mac_mult1~15 ,\Mult2|auto_generated|mac_mult1~14 ,\Mult2|auto_generated|mac_mult1~13 ,\Mult2|auto_generated|mac_mult1~12 ,\Mult2|auto_generated|mac_mult1~11 , +\Mult2|auto_generated|mac_mult1~10 ,\Mult2|auto_generated|mac_mult1~9 ,\Mult2|auto_generated|mac_mult1~8 ,\Mult2|auto_generated|mac_mult1~7 ,\Mult2|auto_generated|mac_mult1~6 ,\Mult2|auto_generated|mac_mult1~5 ,\Mult2|auto_generated|mac_mult1~4 , +\Mult2|auto_generated|mac_mult1~3 ,\Mult2|auto_generated|mac_mult1~2 ,\Mult2|auto_generated|mac_mult1~1 ,\Mult2|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult2|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult2|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult2|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y14_N13 +dffeas \Kd_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[0]~21_combout ), + .asdata(\Mult2|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[0] .is_wysiwyg = "true"; +defparam \Kd_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N14 +cycloneive_lcell_comb \Kd_Out[1]~23 ( +// Equation(s): +// \Kd_Out[1]~23_combout = (Kd_Out[1] & ((\Kd_Out[0]~22 ) # (GND))) # (!Kd_Out[1] & (!\Kd_Out[0]~22 )) +// \Kd_Out[1]~24 = CARRY((Kd_Out[1]) # (!\Kd_Out[0]~22 )) + + .dataa(gnd), + .datab(Kd_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[0]~22 ), + .combout(\Kd_Out[1]~23_combout ), + .cout(\Kd_Out[1]~24 )); +// synopsys translate_off +defparam \Kd_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Kd_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N15 +dffeas \Kd_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[1]~23_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[1] .is_wysiwyg = "true"; +defparam \Kd_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N16 +cycloneive_lcell_comb \Kd_Out[2]~25 ( +// Equation(s): +// \Kd_Out[2]~25_combout = (Kd_Out[2] & (!\Kd_Out[1]~24 & VCC)) # (!Kd_Out[2] & (\Kd_Out[1]~24 $ (GND))) +// \Kd_Out[2]~26 = CARRY((!Kd_Out[2] & !\Kd_Out[1]~24 )) + + .dataa(gnd), + .datab(Kd_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[1]~24 ), + .combout(\Kd_Out[2]~25_combout ), + .cout(\Kd_Out[2]~26 )); +// synopsys translate_off +defparam \Kd_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Kd_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N17 +dffeas \Kd_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[2]~25_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[2] .is_wysiwyg = "true"; +defparam \Kd_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N18 +cycloneive_lcell_comb \Kd_Out[3]~27 ( +// Equation(s): +// \Kd_Out[3]~27_combout = (Kd_Out[3] & ((\Kd_Out[2]~26 ) # (GND))) # (!Kd_Out[3] & (!\Kd_Out[2]~26 )) +// \Kd_Out[3]~28 = CARRY((Kd_Out[3]) # (!\Kd_Out[2]~26 )) + + .dataa(gnd), + .datab(Kd_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[2]~26 ), + .combout(\Kd_Out[3]~27_combout ), + .cout(\Kd_Out[3]~28 )); +// synopsys translate_off +defparam \Kd_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Kd_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N19 +dffeas \Kd_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[3]~27_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[3] .is_wysiwyg = "true"; +defparam \Kd_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N20 +cycloneive_lcell_comb \Kd_Out[4]~29 ( +// Equation(s): +// \Kd_Out[4]~29_combout = (Kd_Out[4] & (!\Kd_Out[3]~28 & VCC)) # (!Kd_Out[4] & (\Kd_Out[3]~28 $ (GND))) +// \Kd_Out[4]~30 = CARRY((!Kd_Out[4] & !\Kd_Out[3]~28 )) + + .dataa(gnd), + .datab(Kd_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[3]~28 ), + .combout(\Kd_Out[4]~29_combout ), + .cout(\Kd_Out[4]~30 )); +// synopsys translate_off +defparam \Kd_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Kd_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N21 +dffeas \Kd_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[4]~29_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[4] .is_wysiwyg = "true"; +defparam \Kd_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N22 +cycloneive_lcell_comb \Kd_Out[5]~31 ( +// Equation(s): +// \Kd_Out[5]~31_combout = (Kd_Out[5] & ((\Kd_Out[4]~30 ) # (GND))) # (!Kd_Out[5] & (!\Kd_Out[4]~30 )) +// \Kd_Out[5]~32 = CARRY((Kd_Out[5]) # (!\Kd_Out[4]~30 )) + + .dataa(Kd_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[4]~30 ), + .combout(\Kd_Out[5]~31_combout ), + .cout(\Kd_Out[5]~32 )); +// synopsys translate_off +defparam \Kd_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Kd_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N23 +dffeas \Kd_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[5]~31_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[5] .is_wysiwyg = "true"; +defparam \Kd_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N24 +cycloneive_lcell_comb \Kd_Out[6]~33 ( +// Equation(s): +// \Kd_Out[6]~33_combout = (Kd_Out[6] & (!\Kd_Out[5]~32 & VCC)) # (!Kd_Out[6] & (\Kd_Out[5]~32 $ (GND))) +// \Kd_Out[6]~34 = CARRY((!Kd_Out[6] & !\Kd_Out[5]~32 )) + + .dataa(gnd), + .datab(Kd_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[5]~32 ), + .combout(\Kd_Out[6]~33_combout ), + .cout(\Kd_Out[6]~34 )); +// synopsys translate_off +defparam \Kd_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Kd_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N25 +dffeas \Kd_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[6]~33_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[6] .is_wysiwyg = "true"; +defparam \Kd_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N26 +cycloneive_lcell_comb \Kd_Out[7]~35 ( +// Equation(s): +// \Kd_Out[7]~35_combout = (Kd_Out[7] & ((\Kd_Out[6]~34 ) # (GND))) # (!Kd_Out[7] & (!\Kd_Out[6]~34 )) +// \Kd_Out[7]~36 = CARRY((Kd_Out[7]) # (!\Kd_Out[6]~34 )) + + .dataa(Kd_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[6]~34 ), + .combout(\Kd_Out[7]~35_combout ), + .cout(\Kd_Out[7]~36 )); +// synopsys translate_off +defparam \Kd_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Kd_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N27 +dffeas \Kd_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[7]~35_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[7] .is_wysiwyg = "true"; +defparam \Kd_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N28 +cycloneive_lcell_comb \Kd_Out[8]~37 ( +// Equation(s): +// \Kd_Out[8]~37_combout = (Kd_Out[8] & (!\Kd_Out[7]~36 & VCC)) # (!Kd_Out[8] & (\Kd_Out[7]~36 $ (GND))) +// \Kd_Out[8]~38 = CARRY((!Kd_Out[8] & !\Kd_Out[7]~36 )) + + .dataa(gnd), + .datab(Kd_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[7]~36 ), + .combout(\Kd_Out[8]~37_combout ), + .cout(\Kd_Out[8]~38 )); +// synopsys translate_off +defparam \Kd_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Kd_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N29 +dffeas \Kd_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[8]~37_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[8] .is_wysiwyg = "true"; +defparam \Kd_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N30 +cycloneive_lcell_comb \Kd_Out[9]~39 ( +// Equation(s): +// \Kd_Out[9]~39_combout = (Kd_Out[9] & ((\Kd_Out[8]~38 ) # (GND))) # (!Kd_Out[9] & (!\Kd_Out[8]~38 )) +// \Kd_Out[9]~40 = CARRY((Kd_Out[9]) # (!\Kd_Out[8]~38 )) + + .dataa(Kd_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[8]~38 ), + .combout(\Kd_Out[9]~39_combout ), + .cout(\Kd_Out[9]~40 )); +// synopsys translate_off +defparam \Kd_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Kd_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N31 +dffeas \Kd_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[9]~39_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[9] .is_wysiwyg = "true"; +defparam \Kd_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N0 +cycloneive_lcell_comb \Kd_Out[10]~41 ( +// Equation(s): +// \Kd_Out[10]~41_combout = (Kd_Out[10] & (!\Kd_Out[9]~40 & VCC)) # (!Kd_Out[10] & (\Kd_Out[9]~40 $ (GND))) +// \Kd_Out[10]~42 = CARRY((!Kd_Out[10] & !\Kd_Out[9]~40 )) + + .dataa(gnd), + .datab(Kd_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[9]~40 ), + .combout(\Kd_Out[10]~41_combout ), + .cout(\Kd_Out[10]~42 )); +// synopsys translate_off +defparam \Kd_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Kd_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N1 +dffeas \Kd_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[10]~41_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[10] .is_wysiwyg = "true"; +defparam \Kd_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N2 +cycloneive_lcell_comb \Kd_Out[11]~43 ( +// Equation(s): +// \Kd_Out[11]~43_combout = (Kd_Out[11] & ((\Kd_Out[10]~42 ) # (GND))) # (!Kd_Out[11] & (!\Kd_Out[10]~42 )) +// \Kd_Out[11]~44 = CARRY((Kd_Out[11]) # (!\Kd_Out[10]~42 )) + + .dataa(gnd), + .datab(Kd_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[10]~42 ), + .combout(\Kd_Out[11]~43_combout ), + .cout(\Kd_Out[11]~44 )); +// synopsys translate_off +defparam \Kd_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Kd_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N0 +cycloneive_lcell_comb \Kd_Out[11]~feeder ( +// Equation(s): +// \Kd_Out[11]~feeder_combout = \Kd_Out[11]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[11]~43_combout ), + .cin(gnd), + .combout(\Kd_Out[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[11]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N1 +dffeas \Kd_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[11]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[11] .is_wysiwyg = "true"; +defparam \Kd_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N4 +cycloneive_lcell_comb \Kd_Out[12]~45 ( +// Equation(s): +// \Kd_Out[12]~45_combout = (Kd_Out[12] & (!\Kd_Out[11]~44 & VCC)) # (!Kd_Out[12] & (\Kd_Out[11]~44 $ (GND))) +// \Kd_Out[12]~46 = CARRY((!Kd_Out[12] & !\Kd_Out[11]~44 )) + + .dataa(gnd), + .datab(Kd_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[11]~44 ), + .combout(\Kd_Out[12]~45_combout ), + .cout(\Kd_Out[12]~46 )); +// synopsys translate_off +defparam \Kd_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Kd_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N5 +dffeas \Kd_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[12]~45_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[12] .is_wysiwyg = "true"; +defparam \Kd_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N6 +cycloneive_lcell_comb \Kd_Out[13]~47 ( +// Equation(s): +// \Kd_Out[13]~47_combout = (Kd_Out[13] & ((\Kd_Out[12]~46 ) # (GND))) # (!Kd_Out[13] & (!\Kd_Out[12]~46 )) +// \Kd_Out[13]~48 = CARRY((Kd_Out[13]) # (!\Kd_Out[12]~46 )) + + .dataa(Kd_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[12]~46 ), + .combout(\Kd_Out[13]~47_combout ), + .cout(\Kd_Out[13]~48 )); +// synopsys translate_off +defparam \Kd_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Kd_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N7 +dffeas \Kd_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[13]~47_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[13] .is_wysiwyg = "true"; +defparam \Kd_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N8 +cycloneive_lcell_comb \Kd_Out[14]~49 ( +// Equation(s): +// \Kd_Out[14]~49_combout = (Kd_Out[14] & (!\Kd_Out[13]~48 & VCC)) # (!Kd_Out[14] & (\Kd_Out[13]~48 $ (GND))) +// \Kd_Out[14]~50 = CARRY((!Kd_Out[14] & !\Kd_Out[13]~48 )) + + .dataa(gnd), + .datab(Kd_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[13]~48 ), + .combout(\Kd_Out[14]~49_combout ), + .cout(\Kd_Out[14]~50 )); +// synopsys translate_off +defparam \Kd_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Kd_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N6 +cycloneive_lcell_comb \Kd_Out[14]~feeder ( +// Equation(s): +// \Kd_Out[14]~feeder_combout = \Kd_Out[14]~49_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[14]~49_combout ), + .cin(gnd), + .combout(\Kd_Out[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[14]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N7 +dffeas \Kd_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[14]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[14] .is_wysiwyg = "true"; +defparam \Kd_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N10 +cycloneive_lcell_comb \Kd_Out[15]~51 ( +// Equation(s): +// \Kd_Out[15]~51_combout = (Kd_Out[15] & ((\Kd_Out[14]~50 ) # (GND))) # (!Kd_Out[15] & (!\Kd_Out[14]~50 )) +// \Kd_Out[15]~52 = CARRY((Kd_Out[15]) # (!\Kd_Out[14]~50 )) + + .dataa(Kd_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[14]~50 ), + .combout(\Kd_Out[15]~51_combout ), + .cout(\Kd_Out[15]~52 )); +// synopsys translate_off +defparam \Kd_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Kd_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N4 +cycloneive_lcell_comb \Kd_Out[15]~feeder ( +// Equation(s): +// \Kd_Out[15]~feeder_combout = \Kd_Out[15]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[15]~51_combout ), + .cin(gnd), + .combout(\Kd_Out[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[15]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N5 +dffeas \Kd_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[15]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[15] .is_wysiwyg = "true"; +defparam \Kd_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N12 +cycloneive_lcell_comb \Kd_Out[16]~53 ( +// Equation(s): +// \Kd_Out[16]~53_combout = (Kd_Out[16] & (!\Kd_Out[15]~52 & VCC)) # (!Kd_Out[16] & (\Kd_Out[15]~52 $ (GND))) +// \Kd_Out[16]~54 = CARRY((!Kd_Out[16] & !\Kd_Out[15]~52 )) + + .dataa(Kd_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[15]~52 ), + .combout(\Kd_Out[16]~53_combout ), + .cout(\Kd_Out[16]~54 )); +// synopsys translate_off +defparam \Kd_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Kd_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N13 +dffeas \Kd_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[16]~53_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[16] .is_wysiwyg = "true"; +defparam \Kd_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N14 +cycloneive_lcell_comb \Kd_Out[17]~55 ( +// Equation(s): +// \Kd_Out[17]~55_combout = (Kd_Out[17] & ((\Kd_Out[16]~54 ) # (GND))) # (!Kd_Out[17] & (!\Kd_Out[16]~54 )) +// \Kd_Out[17]~56 = CARRY((Kd_Out[17]) # (!\Kd_Out[16]~54 )) + + .dataa(Kd_Out[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[16]~54 ), + .combout(\Kd_Out[17]~55_combout ), + .cout(\Kd_Out[17]~56 )); +// synopsys translate_off +defparam \Kd_Out[17]~55 .lut_mask = 16'hA5AF; +defparam \Kd_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N10 +cycloneive_lcell_comb \Kd_Out[17]~feeder ( +// Equation(s): +// \Kd_Out[17]~feeder_combout = \Kd_Out[17]~55_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[17]~55_combout ), + .cin(gnd), + .combout(\Kd_Out[17]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[17]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[17]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N11 +dffeas \Kd_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[17]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[17] .is_wysiwyg = "true"; +defparam \Kd_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N16 +cycloneive_lcell_comb \Kd_Out[18]~57 ( +// Equation(s): +// \Kd_Out[18]~57_combout = (Kd_Out[18] & (!\Kd_Out[17]~56 & VCC)) # (!Kd_Out[18] & (\Kd_Out[17]~56 $ (GND))) +// \Kd_Out[18]~58 = CARRY((!Kd_Out[18] & !\Kd_Out[17]~56 )) + + .dataa(gnd), + .datab(Kd_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[17]~56 ), + .combout(\Kd_Out[18]~57_combout ), + .cout(\Kd_Out[18]~58 )); +// synopsys translate_off +defparam \Kd_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Kd_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N8 +cycloneive_lcell_comb \Kd_Out[18]~feeder ( +// Equation(s): +// \Kd_Out[18]~feeder_combout = \Kd_Out[18]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[18]~57_combout ), + .cin(gnd), + .combout(\Kd_Out[18]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[18]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[18]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N9 +dffeas \Kd_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[18]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[18] .is_wysiwyg = "true"; +defparam \Kd_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N18 +cycloneive_lcell_comb \Kd_Out[19]~59 ( +// Equation(s): +// \Kd_Out[19]~59_combout = (Kd_Out[19] & ((\Kd_Out[18]~58 ) # (GND))) # (!Kd_Out[19] & (!\Kd_Out[18]~58 )) +// \Kd_Out[19]~60 = CARRY((Kd_Out[19]) # (!\Kd_Out[18]~58 )) + + .dataa(gnd), + .datab(Kd_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[18]~58 ), + .combout(\Kd_Out[19]~59_combout ), + .cout(\Kd_Out[19]~60 )); +// synopsys translate_off +defparam \Kd_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Kd_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N2 +cycloneive_lcell_comb \Kd_Out[19]~feeder ( +// Equation(s): +// \Kd_Out[19]~feeder_combout = \Kd_Out[19]~59_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[19]~59_combout ), + .cin(gnd), + .combout(\Kd_Out[19]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[19]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[19]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N3 +dffeas \Kd_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[19]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[19] .is_wysiwyg = "true"; +defparam \Kd_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N20 +cycloneive_lcell_comb \Kd_Out[20]~61 ( +// Equation(s): +// \Kd_Out[20]~61_combout = \Kd_Out[19]~60 $ (Kd_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[20]), + .cin(\Kd_Out[19]~60 ), + .combout(\Kd_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Kd_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N26 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y13_N21 +dffeas \Kd_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[20]~61_combout ), + .asdata(\~GND~combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[20] .is_wysiwyg = "true"; +defparam \Kd_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N30 +cycloneive_lcell_comb \Add7~20 ( +// Equation(s): +// \Add7~20_combout = (Kd_Out[20] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[20]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~20 .lut_mask = 16'h00F0; +defparam \Add7~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N12 +cycloneive_lcell_comb \Ki_Out[0]~21 ( +// Equation(s): +// \Ki_Out[0]~21_combout = Ki_Out[0] $ (GND) +// \Ki_Out[0]~22 = CARRY(!Ki_Out[0]) + + .dataa(Ki_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Ki_Out[0]~21_combout ), + .cout(\Ki_Out[0]~22 )); +// synopsys translate_off +defparam \Ki_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Ki_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y17_N22 +cycloneive_io_ibuf \Ki[0]~input ( + .i(Ki[0]), + .ibar(gnd), + .o(\Ki[0]~input_o )); +// synopsys translate_off +defparam \Ki[0]~input .bus_hold = "false"; +defparam \Ki[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N1 +cycloneive_io_ibuf \Ki[1]~input ( + .i(Ki[1]), + .ibar(gnd), + .o(\Ki[1]~input_o )); +// synopsys translate_off +defparam \Ki[1]~input .bus_hold = "false"; +defparam \Ki[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N22 +cycloneive_io_ibuf \Ki[2]~input ( + .i(Ki[2]), + .ibar(gnd), + .o(\Ki[2]~input_o )); +// synopsys translate_off +defparam \Ki[2]~input .bus_hold = "false"; +defparam \Ki[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N15 +cycloneive_io_ibuf \Ki[3]~input ( + .i(Ki[3]), + .ibar(gnd), + .o(\Ki[3]~input_o )); +// synopsys translate_off +defparam \Ki[3]~input .bus_hold = "false"; +defparam \Ki[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N15 +cycloneive_io_ibuf \Ki[4]~input ( + .i(Ki[4]), + .ibar(gnd), + .o(\Ki[4]~input_o )); +// synopsys translate_off +defparam \Ki[4]~input .bus_hold = "false"; +defparam \Ki[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N8 +cycloneive_io_ibuf \Ki[5]~input ( + .i(Ki[5]), + .ibar(gnd), + .o(\Ki[5]~input_o )); +// synopsys translate_off +defparam \Ki[5]~input .bus_hold = "false"; +defparam \Ki[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N1 +cycloneive_io_ibuf \Ki[6]~input ( + .i(Ki[6]), + .ibar(gnd), + .o(\Ki[6]~input_o )); +// synopsys translate_off +defparam \Ki[6]~input .bus_hold = "false"; +defparam \Ki[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N8 +cycloneive_io_ibuf \Ki[7]~input ( + .i(Ki[7]), + .ibar(gnd), + .o(\Ki[7]~input_o )); +// synopsys translate_off +defparam \Ki[7]~input .bus_hold = "false"; +defparam \Ki[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y17_N0 +cycloneive_mac_mult \Mult1|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({EE1[11],EE1[10],EE1[9],EE1[8],EE1[7],EE1[6],EE1[5],EE1[4],EE1[3],EE1[2],EE1[1],EE1[0],gnd,gnd,gnd,gnd,gnd,gnd}), + .datab({\Ki[7]~input_o ,\Ki[6]~input_o ,\Ki[5]~input_o ,\Ki[4]~input_o ,\Ki[3]~input_o ,\Ki[2]~input_o ,\Ki[1]~input_o ,\Ki[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult1|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult1|auto_generated|mac_mult1 .dataa_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult1|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult1|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y17_N2 +cycloneive_mac_out \Mult1|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult1|auto_generated|mac_mult1~DATAOUT19 ,\Mult1|auto_generated|mac_mult1~DATAOUT18 ,\Mult1|auto_generated|mac_mult1~DATAOUT17 ,\Mult1|auto_generated|mac_mult1~DATAOUT16 ,\Mult1|auto_generated|mac_mult1~DATAOUT15 ,\Mult1|auto_generated|mac_mult1~DATAOUT14 , +\Mult1|auto_generated|mac_mult1~DATAOUT13 ,\Mult1|auto_generated|mac_mult1~DATAOUT12 ,\Mult1|auto_generated|mac_mult1~DATAOUT11 ,\Mult1|auto_generated|mac_mult1~DATAOUT10 ,\Mult1|auto_generated|mac_mult1~DATAOUT9 ,\Mult1|auto_generated|mac_mult1~DATAOUT8 , +\Mult1|auto_generated|mac_mult1~DATAOUT7 ,\Mult1|auto_generated|mac_mult1~DATAOUT6 ,\Mult1|auto_generated|mac_mult1~DATAOUT5 ,\Mult1|auto_generated|mac_mult1~DATAOUT4 ,\Mult1|auto_generated|mac_mult1~DATAOUT3 ,\Mult1|auto_generated|mac_mult1~DATAOUT2 , +\Mult1|auto_generated|mac_mult1~DATAOUT1 ,\Mult1|auto_generated|mac_mult1~dataout ,\Mult1|auto_generated|mac_mult1~15 ,\Mult1|auto_generated|mac_mult1~14 ,\Mult1|auto_generated|mac_mult1~13 ,\Mult1|auto_generated|mac_mult1~12 ,\Mult1|auto_generated|mac_mult1~11 , +\Mult1|auto_generated|mac_mult1~10 ,\Mult1|auto_generated|mac_mult1~9 ,\Mult1|auto_generated|mac_mult1~8 ,\Mult1|auto_generated|mac_mult1~7 ,\Mult1|auto_generated|mac_mult1~6 ,\Mult1|auto_generated|mac_mult1~5 ,\Mult1|auto_generated|mac_mult1~4 , +\Mult1|auto_generated|mac_mult1~3 ,\Mult1|auto_generated|mac_mult1~2 ,\Mult1|auto_generated|mac_mult1~1 ,\Mult1|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult1|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult1|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult1|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y18_N13 +dffeas \Ki_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[0]~21_combout ), + .asdata(\Mult1|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[0] .is_wysiwyg = "true"; +defparam \Ki_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N14 +cycloneive_lcell_comb \Ki_Out[1]~23 ( +// Equation(s): +// \Ki_Out[1]~23_combout = (Ki_Out[1] & ((\Ki_Out[0]~22 ) # (GND))) # (!Ki_Out[1] & (!\Ki_Out[0]~22 )) +// \Ki_Out[1]~24 = CARRY((Ki_Out[1]) # (!\Ki_Out[0]~22 )) + + .dataa(gnd), + .datab(Ki_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[0]~22 ), + .combout(\Ki_Out[1]~23_combout ), + .cout(\Ki_Out[1]~24 )); +// synopsys translate_off +defparam \Ki_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Ki_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N15 +dffeas \Ki_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[1]~23_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[1] .is_wysiwyg = "true"; +defparam \Ki_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N16 +cycloneive_lcell_comb \Ki_Out[2]~25 ( +// Equation(s): +// \Ki_Out[2]~25_combout = (Ki_Out[2] & (!\Ki_Out[1]~24 & VCC)) # (!Ki_Out[2] & (\Ki_Out[1]~24 $ (GND))) +// \Ki_Out[2]~26 = CARRY((!Ki_Out[2] & !\Ki_Out[1]~24 )) + + .dataa(gnd), + .datab(Ki_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[1]~24 ), + .combout(\Ki_Out[2]~25_combout ), + .cout(\Ki_Out[2]~26 )); +// synopsys translate_off +defparam \Ki_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Ki_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N17 +dffeas \Ki_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[2]~25_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[2] .is_wysiwyg = "true"; +defparam \Ki_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N18 +cycloneive_lcell_comb \Ki_Out[3]~27 ( +// Equation(s): +// \Ki_Out[3]~27_combout = (Ki_Out[3] & ((\Ki_Out[2]~26 ) # (GND))) # (!Ki_Out[3] & (!\Ki_Out[2]~26 )) +// \Ki_Out[3]~28 = CARRY((Ki_Out[3]) # (!\Ki_Out[2]~26 )) + + .dataa(gnd), + .datab(Ki_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[2]~26 ), + .combout(\Ki_Out[3]~27_combout ), + .cout(\Ki_Out[3]~28 )); +// synopsys translate_off +defparam \Ki_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Ki_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N19 +dffeas \Ki_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[3]~27_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[3] .is_wysiwyg = "true"; +defparam \Ki_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N20 +cycloneive_lcell_comb \Ki_Out[4]~29 ( +// Equation(s): +// \Ki_Out[4]~29_combout = (Ki_Out[4] & (!\Ki_Out[3]~28 & VCC)) # (!Ki_Out[4] & (\Ki_Out[3]~28 $ (GND))) +// \Ki_Out[4]~30 = CARRY((!Ki_Out[4] & !\Ki_Out[3]~28 )) + + .dataa(gnd), + .datab(Ki_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[3]~28 ), + .combout(\Ki_Out[4]~29_combout ), + .cout(\Ki_Out[4]~30 )); +// synopsys translate_off +defparam \Ki_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Ki_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N21 +dffeas \Ki_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[4]~29_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[4] .is_wysiwyg = "true"; +defparam \Ki_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N22 +cycloneive_lcell_comb \Ki_Out[5]~31 ( +// Equation(s): +// \Ki_Out[5]~31_combout = (Ki_Out[5] & ((\Ki_Out[4]~30 ) # (GND))) # (!Ki_Out[5] & (!\Ki_Out[4]~30 )) +// \Ki_Out[5]~32 = CARRY((Ki_Out[5]) # (!\Ki_Out[4]~30 )) + + .dataa(Ki_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[4]~30 ), + .combout(\Ki_Out[5]~31_combout ), + .cout(\Ki_Out[5]~32 )); +// synopsys translate_off +defparam \Ki_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Ki_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N23 +dffeas \Ki_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[5]~31_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[5] .is_wysiwyg = "true"; +defparam \Ki_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N24 +cycloneive_lcell_comb \Ki_Out[6]~33 ( +// Equation(s): +// \Ki_Out[6]~33_combout = (Ki_Out[6] & (!\Ki_Out[5]~32 & VCC)) # (!Ki_Out[6] & (\Ki_Out[5]~32 $ (GND))) +// \Ki_Out[6]~34 = CARRY((!Ki_Out[6] & !\Ki_Out[5]~32 )) + + .dataa(gnd), + .datab(Ki_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[5]~32 ), + .combout(\Ki_Out[6]~33_combout ), + .cout(\Ki_Out[6]~34 )); +// synopsys translate_off +defparam \Ki_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Ki_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N25 +dffeas \Ki_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[6]~33_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[6] .is_wysiwyg = "true"; +defparam \Ki_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N26 +cycloneive_lcell_comb \Ki_Out[7]~35 ( +// Equation(s): +// \Ki_Out[7]~35_combout = (Ki_Out[7] & ((\Ki_Out[6]~34 ) # (GND))) # (!Ki_Out[7] & (!\Ki_Out[6]~34 )) +// \Ki_Out[7]~36 = CARRY((Ki_Out[7]) # (!\Ki_Out[6]~34 )) + + .dataa(Ki_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[6]~34 ), + .combout(\Ki_Out[7]~35_combout ), + .cout(\Ki_Out[7]~36 )); +// synopsys translate_off +defparam \Ki_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Ki_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N27 +dffeas \Ki_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[7]~35_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[7] .is_wysiwyg = "true"; +defparam \Ki_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N28 +cycloneive_lcell_comb \Ki_Out[8]~37 ( +// Equation(s): +// \Ki_Out[8]~37_combout = (Ki_Out[8] & (!\Ki_Out[7]~36 & VCC)) # (!Ki_Out[8] & (\Ki_Out[7]~36 $ (GND))) +// \Ki_Out[8]~38 = CARRY((!Ki_Out[8] & !\Ki_Out[7]~36 )) + + .dataa(gnd), + .datab(Ki_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[7]~36 ), + .combout(\Ki_Out[8]~37_combout ), + .cout(\Ki_Out[8]~38 )); +// synopsys translate_off +defparam \Ki_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Ki_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N29 +dffeas \Ki_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[8]~37_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[8] .is_wysiwyg = "true"; +defparam \Ki_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N30 +cycloneive_lcell_comb \Ki_Out[9]~39 ( +// Equation(s): +// \Ki_Out[9]~39_combout = (Ki_Out[9] & ((\Ki_Out[8]~38 ) # (GND))) # (!Ki_Out[9] & (!\Ki_Out[8]~38 )) +// \Ki_Out[9]~40 = CARRY((Ki_Out[9]) # (!\Ki_Out[8]~38 )) + + .dataa(Ki_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[8]~38 ), + .combout(\Ki_Out[9]~39_combout ), + .cout(\Ki_Out[9]~40 )); +// synopsys translate_off +defparam \Ki_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Ki_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N31 +dffeas \Ki_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[9]~39_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[9] .is_wysiwyg = "true"; +defparam \Ki_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N0 +cycloneive_lcell_comb \Ki_Out[10]~41 ( +// Equation(s): +// \Ki_Out[10]~41_combout = (Ki_Out[10] & (!\Ki_Out[9]~40 & VCC)) # (!Ki_Out[10] & (\Ki_Out[9]~40 $ (GND))) +// \Ki_Out[10]~42 = CARRY((!Ki_Out[10] & !\Ki_Out[9]~40 )) + + .dataa(gnd), + .datab(Ki_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[9]~40 ), + .combout(\Ki_Out[10]~41_combout ), + .cout(\Ki_Out[10]~42 )); +// synopsys translate_off +defparam \Ki_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Ki_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N1 +dffeas \Ki_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[10]~41_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[10] .is_wysiwyg = "true"; +defparam \Ki_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N2 +cycloneive_lcell_comb \Ki_Out[11]~43 ( +// Equation(s): +// \Ki_Out[11]~43_combout = (Ki_Out[11] & ((\Ki_Out[10]~42 ) # (GND))) # (!Ki_Out[11] & (!\Ki_Out[10]~42 )) +// \Ki_Out[11]~44 = CARRY((Ki_Out[11]) # (!\Ki_Out[10]~42 )) + + .dataa(gnd), + .datab(Ki_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[10]~42 ), + .combout(\Ki_Out[11]~43_combout ), + .cout(\Ki_Out[11]~44 )); +// synopsys translate_off +defparam \Ki_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Ki_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N3 +dffeas \Ki_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[11]~43_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[11] .is_wysiwyg = "true"; +defparam \Ki_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N4 +cycloneive_lcell_comb \Ki_Out[12]~45 ( +// Equation(s): +// \Ki_Out[12]~45_combout = (Ki_Out[12] & (!\Ki_Out[11]~44 & VCC)) # (!Ki_Out[12] & (\Ki_Out[11]~44 $ (GND))) +// \Ki_Out[12]~46 = CARRY((!Ki_Out[12] & !\Ki_Out[11]~44 )) + + .dataa(gnd), + .datab(Ki_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[11]~44 ), + .combout(\Ki_Out[12]~45_combout ), + .cout(\Ki_Out[12]~46 )); +// synopsys translate_off +defparam \Ki_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Ki_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N5 +dffeas \Ki_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[12]~45_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[12] .is_wysiwyg = "true"; +defparam \Ki_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N6 +cycloneive_lcell_comb \Ki_Out[13]~47 ( +// Equation(s): +// \Ki_Out[13]~47_combout = (Ki_Out[13] & ((\Ki_Out[12]~46 ) # (GND))) # (!Ki_Out[13] & (!\Ki_Out[12]~46 )) +// \Ki_Out[13]~48 = CARRY((Ki_Out[13]) # (!\Ki_Out[12]~46 )) + + .dataa(Ki_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[12]~46 ), + .combout(\Ki_Out[13]~47_combout ), + .cout(\Ki_Out[13]~48 )); +// synopsys translate_off +defparam \Ki_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Ki_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N7 +dffeas \Ki_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[13]~47_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[13] .is_wysiwyg = "true"; +defparam \Ki_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N8 +cycloneive_lcell_comb \Ki_Out[14]~49 ( +// Equation(s): +// \Ki_Out[14]~49_combout = (Ki_Out[14] & (!\Ki_Out[13]~48 & VCC)) # (!Ki_Out[14] & (\Ki_Out[13]~48 $ (GND))) +// \Ki_Out[14]~50 = CARRY((!Ki_Out[14] & !\Ki_Out[13]~48 )) + + .dataa(gnd), + .datab(Ki_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[13]~48 ), + .combout(\Ki_Out[14]~49_combout ), + .cout(\Ki_Out[14]~50 )); +// synopsys translate_off +defparam \Ki_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Ki_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N9 +dffeas \Ki_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[14]~49_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[14] .is_wysiwyg = "true"; +defparam \Ki_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N10 +cycloneive_lcell_comb \Ki_Out[15]~51 ( +// Equation(s): +// \Ki_Out[15]~51_combout = (Ki_Out[15] & ((\Ki_Out[14]~50 ) # (GND))) # (!Ki_Out[15] & (!\Ki_Out[14]~50 )) +// \Ki_Out[15]~52 = CARRY((Ki_Out[15]) # (!\Ki_Out[14]~50 )) + + .dataa(Ki_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[14]~50 ), + .combout(\Ki_Out[15]~51_combout ), + .cout(\Ki_Out[15]~52 )); +// synopsys translate_off +defparam \Ki_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Ki_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N11 +dffeas \Ki_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[15]~51_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[15] .is_wysiwyg = "true"; +defparam \Ki_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N12 +cycloneive_lcell_comb \Ki_Out[16]~53 ( +// Equation(s): +// \Ki_Out[16]~53_combout = (Ki_Out[16] & (!\Ki_Out[15]~52 & VCC)) # (!Ki_Out[16] & (\Ki_Out[15]~52 $ (GND))) +// \Ki_Out[16]~54 = CARRY((!Ki_Out[16] & !\Ki_Out[15]~52 )) + + .dataa(Ki_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[15]~52 ), + .combout(\Ki_Out[16]~53_combout ), + .cout(\Ki_Out[16]~54 )); +// synopsys translate_off +defparam \Ki_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Ki_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N13 +dffeas \Ki_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[16]~53_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[16] .is_wysiwyg = "true"; +defparam \Ki_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N14 +cycloneive_lcell_comb \Ki_Out[17]~55 ( +// Equation(s): +// \Ki_Out[17]~55_combout = (Ki_Out[17] & ((\Ki_Out[16]~54 ) # (GND))) # (!Ki_Out[17] & (!\Ki_Out[16]~54 )) +// \Ki_Out[17]~56 = CARRY((Ki_Out[17]) # (!\Ki_Out[16]~54 )) + + .dataa(gnd), + .datab(Ki_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[16]~54 ), + .combout(\Ki_Out[17]~55_combout ), + .cout(\Ki_Out[17]~56 )); +// synopsys translate_off +defparam \Ki_Out[17]~55 .lut_mask = 16'hC3CF; +defparam \Ki_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N15 +dffeas \Ki_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[17]~55_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[17] .is_wysiwyg = "true"; +defparam \Ki_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N16 +cycloneive_lcell_comb \Ki_Out[18]~57 ( +// Equation(s): +// \Ki_Out[18]~57_combout = (Ki_Out[18] & (!\Ki_Out[17]~56 & VCC)) # (!Ki_Out[18] & (\Ki_Out[17]~56 $ (GND))) +// \Ki_Out[18]~58 = CARRY((!Ki_Out[18] & !\Ki_Out[17]~56 )) + + .dataa(gnd), + .datab(Ki_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[17]~56 ), + .combout(\Ki_Out[18]~57_combout ), + .cout(\Ki_Out[18]~58 )); +// synopsys translate_off +defparam \Ki_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Ki_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N17 +dffeas \Ki_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[18]~57_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[18] .is_wysiwyg = "true"; +defparam \Ki_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N18 +cycloneive_lcell_comb \Ki_Out[19]~59 ( +// Equation(s): +// \Ki_Out[19]~59_combout = (Ki_Out[19] & ((\Ki_Out[18]~58 ) # (GND))) # (!Ki_Out[19] & (!\Ki_Out[18]~58 )) +// \Ki_Out[19]~60 = CARRY((Ki_Out[19]) # (!\Ki_Out[18]~58 )) + + .dataa(gnd), + .datab(Ki_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[18]~58 ), + .combout(\Ki_Out[19]~59_combout ), + .cout(\Ki_Out[19]~60 )); +// synopsys translate_off +defparam \Ki_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Ki_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N19 +dffeas \Ki_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[19]~59_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[19] .is_wysiwyg = "true"; +defparam \Ki_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N20 +cycloneive_lcell_comb \Ki_Out[20]~61 ( +// Equation(s): +// \Ki_Out[20]~61_combout = \Ki_Out[19]~60 $ (Ki_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Ki_Out[20]), + .cin(\Ki_Out[19]~60 ), + .combout(\Ki_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Ki_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Ki_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N21 +dffeas \Ki_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[20]~61_combout ), + .asdata(\~GND~combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[20] .is_wysiwyg = "true"; +defparam \Ki_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N12 +cycloneive_lcell_comb \Kp_Out[0]~21 ( +// Equation(s): +// \Kp_Out[0]~21_combout = Kp_Out[0] $ (GND) +// \Kp_Out[0]~22 = CARRY(!Kp_Out[0]) + + .dataa(Kp_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Kp_Out[0]~21_combout ), + .cout(\Kp_Out[0]~22 )); +// synopsys translate_off +defparam \Kp_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Kp_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \Kp[0]~input ( + .i(Kp[0]), + .ibar(gnd), + .o(\Kp[0]~input_o )); +// synopsys translate_off +defparam \Kp[0]~input .bus_hold = "false"; +defparam \Kp[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N22 +cycloneive_io_ibuf \Kp[1]~input ( + .i(Kp[1]), + .ibar(gnd), + .o(\Kp[1]~input_o )); +// synopsys translate_off +defparam \Kp[1]~input .bus_hold = "false"; +defparam \Kp[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N22 +cycloneive_io_ibuf \Kp[2]~input ( + .i(Kp[2]), + .ibar(gnd), + .o(\Kp[2]~input_o )); +// synopsys translate_off +defparam \Kp[2]~input .bus_hold = "false"; +defparam \Kp[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N22 +cycloneive_io_ibuf \Kp[3]~input ( + .i(Kp[3]), + .ibar(gnd), + .o(\Kp[3]~input_o )); +// synopsys translate_off +defparam \Kp[3]~input .bus_hold = "false"; +defparam \Kp[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N15 +cycloneive_io_ibuf \Kp[4]~input ( + .i(Kp[4]), + .ibar(gnd), + .o(\Kp[4]~input_o )); +// synopsys translate_off +defparam \Kp[4]~input .bus_hold = "false"; +defparam \Kp[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N15 +cycloneive_io_ibuf \Kp[5]~input ( + .i(Kp[5]), + .ibar(gnd), + .o(\Kp[5]~input_o )); +// synopsys translate_off +defparam \Kp[5]~input .bus_hold = "false"; +defparam \Kp[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N1 +cycloneive_io_ibuf \Kp[6]~input ( + .i(Kp[6]), + .ibar(gnd), + .o(\Kp[6]~input_o )); +// synopsys translate_off +defparam \Kp[6]~input .bus_hold = "false"; +defparam \Kp[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N22 +cycloneive_io_ibuf \Kp[7]~input ( + .i(Kp[7]), + .ibar(gnd), + .o(\Kp[7]~input_o )); +// synopsys translate_off +defparam \Kp[7]~input .bus_hold = "false"; +defparam \Kp[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y18_N0 +cycloneive_mac_mult \Mult0|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(\clk~inputclkctrl_outclk ), + .aclr(!\rst_n~inputclkctrl_outclk ), + .ena(\Clk_Ctrl~q ), + .dataa({\EE0[13]~42_combout ,\EE0[12]~40_combout ,\EE0[11]~38_combout ,\EE0[10]~36_combout ,\EE0[9]~34_combout ,\EE0[8]~32_combout ,\EE0[7]~30_combout ,\EE0[6]~28_combout ,\EE0[5]~26_combout ,\EE0[4]~24_combout ,\EE0[3]~22_combout ,\EE0[2]~20_combout ,\EE0[1]~18_combout , +\EE0[0]~16_combout ,gnd,gnd,gnd,gnd}), + .datab({\Kp[7]~input_o ,\Kp[6]~input_o ,\Kp[5]~input_o ,\Kp[4]~input_o ,\Kp[3]~input_o ,\Kp[2]~input_o ,\Kp[1]~input_o ,\Kp[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult0|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult0|auto_generated|mac_mult1 .dataa_clock = "0"; +defparam \Mult0|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult0|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult0|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult0|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult0|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y18_N2 +cycloneive_mac_out \Mult0|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult0|auto_generated|mac_mult1~DATAOUT21 ,\Mult0|auto_generated|mac_mult1~DATAOUT20 ,\Mult0|auto_generated|mac_mult1~DATAOUT19 ,\Mult0|auto_generated|mac_mult1~DATAOUT18 ,\Mult0|auto_generated|mac_mult1~DATAOUT17 ,\Mult0|auto_generated|mac_mult1~DATAOUT16 , +\Mult0|auto_generated|mac_mult1~DATAOUT15 ,\Mult0|auto_generated|mac_mult1~DATAOUT14 ,\Mult0|auto_generated|mac_mult1~DATAOUT13 ,\Mult0|auto_generated|mac_mult1~DATAOUT12 ,\Mult0|auto_generated|mac_mult1~DATAOUT11 ,\Mult0|auto_generated|mac_mult1~DATAOUT10 , +\Mult0|auto_generated|mac_mult1~DATAOUT9 ,\Mult0|auto_generated|mac_mult1~DATAOUT8 ,\Mult0|auto_generated|mac_mult1~DATAOUT7 ,\Mult0|auto_generated|mac_mult1~DATAOUT6 ,\Mult0|auto_generated|mac_mult1~DATAOUT5 ,\Mult0|auto_generated|mac_mult1~DATAOUT4 , +\Mult0|auto_generated|mac_mult1~DATAOUT3 ,\Mult0|auto_generated|mac_mult1~DATAOUT2 ,\Mult0|auto_generated|mac_mult1~DATAOUT1 ,\Mult0|auto_generated|mac_mult1~dataout ,\Mult0|auto_generated|mac_mult1~13 ,\Mult0|auto_generated|mac_mult1~12 , +\Mult0|auto_generated|mac_mult1~11 ,\Mult0|auto_generated|mac_mult1~10 ,\Mult0|auto_generated|mac_mult1~9 ,\Mult0|auto_generated|mac_mult1~8 ,\Mult0|auto_generated|mac_mult1~7 ,\Mult0|auto_generated|mac_mult1~6 ,\Mult0|auto_generated|mac_mult1~5 , +\Mult0|auto_generated|mac_mult1~4 ,\Mult0|auto_generated|mac_mult1~3 ,\Mult0|auto_generated|mac_mult1~2 ,\Mult0|auto_generated|mac_mult1~1 ,\Mult0|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult0|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult0|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult0|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y16_N13 +dffeas \Kp_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[0]~21_combout ), + .asdata(\Mult0|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[0] .is_wysiwyg = "true"; +defparam \Kp_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N14 +cycloneive_lcell_comb \Kp_Out[1]~23 ( +// Equation(s): +// \Kp_Out[1]~23_combout = (Kp_Out[1] & ((\Kp_Out[0]~22 ) # (GND))) # (!Kp_Out[1] & (!\Kp_Out[0]~22 )) +// \Kp_Out[1]~24 = CARRY((Kp_Out[1]) # (!\Kp_Out[0]~22 )) + + .dataa(gnd), + .datab(Kp_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[0]~22 ), + .combout(\Kp_Out[1]~23_combout ), + .cout(\Kp_Out[1]~24 )); +// synopsys translate_off +defparam \Kp_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Kp_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N15 +dffeas \Kp_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[1]~23_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[1] .is_wysiwyg = "true"; +defparam \Kp_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N16 +cycloneive_lcell_comb \Kp_Out[2]~25 ( +// Equation(s): +// \Kp_Out[2]~25_combout = (Kp_Out[2] & (!\Kp_Out[1]~24 & VCC)) # (!Kp_Out[2] & (\Kp_Out[1]~24 $ (GND))) +// \Kp_Out[2]~26 = CARRY((!Kp_Out[2] & !\Kp_Out[1]~24 )) + + .dataa(gnd), + .datab(Kp_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[1]~24 ), + .combout(\Kp_Out[2]~25_combout ), + .cout(\Kp_Out[2]~26 )); +// synopsys translate_off +defparam \Kp_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Kp_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N17 +dffeas \Kp_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[2]~25_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[2] .is_wysiwyg = "true"; +defparam \Kp_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N18 +cycloneive_lcell_comb \Kp_Out[3]~27 ( +// Equation(s): +// \Kp_Out[3]~27_combout = (Kp_Out[3] & ((\Kp_Out[2]~26 ) # (GND))) # (!Kp_Out[3] & (!\Kp_Out[2]~26 )) +// \Kp_Out[3]~28 = CARRY((Kp_Out[3]) # (!\Kp_Out[2]~26 )) + + .dataa(gnd), + .datab(Kp_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[2]~26 ), + .combout(\Kp_Out[3]~27_combout ), + .cout(\Kp_Out[3]~28 )); +// synopsys translate_off +defparam \Kp_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Kp_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N19 +dffeas \Kp_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[3]~27_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[3] .is_wysiwyg = "true"; +defparam \Kp_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N20 +cycloneive_lcell_comb \Kp_Out[4]~29 ( +// Equation(s): +// \Kp_Out[4]~29_combout = (Kp_Out[4] & (!\Kp_Out[3]~28 & VCC)) # (!Kp_Out[4] & (\Kp_Out[3]~28 $ (GND))) +// \Kp_Out[4]~30 = CARRY((!Kp_Out[4] & !\Kp_Out[3]~28 )) + + .dataa(gnd), + .datab(Kp_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[3]~28 ), + .combout(\Kp_Out[4]~29_combout ), + .cout(\Kp_Out[4]~30 )); +// synopsys translate_off +defparam \Kp_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Kp_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N21 +dffeas \Kp_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[4]~29_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[4] .is_wysiwyg = "true"; +defparam \Kp_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N22 +cycloneive_lcell_comb \Kp_Out[5]~31 ( +// Equation(s): +// \Kp_Out[5]~31_combout = (Kp_Out[5] & ((\Kp_Out[4]~30 ) # (GND))) # (!Kp_Out[5] & (!\Kp_Out[4]~30 )) +// \Kp_Out[5]~32 = CARRY((Kp_Out[5]) # (!\Kp_Out[4]~30 )) + + .dataa(Kp_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[4]~30 ), + .combout(\Kp_Out[5]~31_combout ), + .cout(\Kp_Out[5]~32 )); +// synopsys translate_off +defparam \Kp_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Kp_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N23 +dffeas \Kp_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[5]~31_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[5] .is_wysiwyg = "true"; +defparam \Kp_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N24 +cycloneive_lcell_comb \Kp_Out[6]~33 ( +// Equation(s): +// \Kp_Out[6]~33_combout = (Kp_Out[6] & (!\Kp_Out[5]~32 & VCC)) # (!Kp_Out[6] & (\Kp_Out[5]~32 $ (GND))) +// \Kp_Out[6]~34 = CARRY((!Kp_Out[6] & !\Kp_Out[5]~32 )) + + .dataa(gnd), + .datab(Kp_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[5]~32 ), + .combout(\Kp_Out[6]~33_combout ), + .cout(\Kp_Out[6]~34 )); +// synopsys translate_off +defparam \Kp_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Kp_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N25 +dffeas \Kp_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[6]~33_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[6] .is_wysiwyg = "true"; +defparam \Kp_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N26 +cycloneive_lcell_comb \Kp_Out[7]~35 ( +// Equation(s): +// \Kp_Out[7]~35_combout = (Kp_Out[7] & ((\Kp_Out[6]~34 ) # (GND))) # (!Kp_Out[7] & (!\Kp_Out[6]~34 )) +// \Kp_Out[7]~36 = CARRY((Kp_Out[7]) # (!\Kp_Out[6]~34 )) + + .dataa(Kp_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[6]~34 ), + .combout(\Kp_Out[7]~35_combout ), + .cout(\Kp_Out[7]~36 )); +// synopsys translate_off +defparam \Kp_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Kp_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N27 +dffeas \Kp_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[7]~35_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[7] .is_wysiwyg = "true"; +defparam \Kp_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N28 +cycloneive_lcell_comb \Kp_Out[8]~37 ( +// Equation(s): +// \Kp_Out[8]~37_combout = (Kp_Out[8] & (!\Kp_Out[7]~36 & VCC)) # (!Kp_Out[8] & (\Kp_Out[7]~36 $ (GND))) +// \Kp_Out[8]~38 = CARRY((!Kp_Out[8] & !\Kp_Out[7]~36 )) + + .dataa(gnd), + .datab(Kp_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[7]~36 ), + .combout(\Kp_Out[8]~37_combout ), + .cout(\Kp_Out[8]~38 )); +// synopsys translate_off +defparam \Kp_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Kp_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N29 +dffeas \Kp_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[8]~37_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[8] .is_wysiwyg = "true"; +defparam \Kp_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N30 +cycloneive_lcell_comb \Kp_Out[9]~39 ( +// Equation(s): +// \Kp_Out[9]~39_combout = (Kp_Out[9] & ((\Kp_Out[8]~38 ) # (GND))) # (!Kp_Out[9] & (!\Kp_Out[8]~38 )) +// \Kp_Out[9]~40 = CARRY((Kp_Out[9]) # (!\Kp_Out[8]~38 )) + + .dataa(Kp_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[8]~38 ), + .combout(\Kp_Out[9]~39_combout ), + .cout(\Kp_Out[9]~40 )); +// synopsys translate_off +defparam \Kp_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Kp_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N31 +dffeas \Kp_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[9]~39_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[9] .is_wysiwyg = "true"; +defparam \Kp_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \Kp_Out[10]~41 ( +// Equation(s): +// \Kp_Out[10]~41_combout = (Kp_Out[10] & (!\Kp_Out[9]~40 & VCC)) # (!Kp_Out[10] & (\Kp_Out[9]~40 $ (GND))) +// \Kp_Out[10]~42 = CARRY((!Kp_Out[10] & !\Kp_Out[9]~40 )) + + .dataa(gnd), + .datab(Kp_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[9]~40 ), + .combout(\Kp_Out[10]~41_combout ), + .cout(\Kp_Out[10]~42 )); +// synopsys translate_off +defparam \Kp_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Kp_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N1 +dffeas \Kp_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[10]~41_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[10] .is_wysiwyg = "true"; +defparam \Kp_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \Kp_Out[11]~43 ( +// Equation(s): +// \Kp_Out[11]~43_combout = (Kp_Out[11] & ((\Kp_Out[10]~42 ) # (GND))) # (!Kp_Out[11] & (!\Kp_Out[10]~42 )) +// \Kp_Out[11]~44 = CARRY((Kp_Out[11]) # (!\Kp_Out[10]~42 )) + + .dataa(gnd), + .datab(Kp_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[10]~42 ), + .combout(\Kp_Out[11]~43_combout ), + .cout(\Kp_Out[11]~44 )); +// synopsys translate_off +defparam \Kp_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Kp_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N3 +dffeas \Kp_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[11]~43_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[11] .is_wysiwyg = "true"; +defparam \Kp_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \Kp_Out[12]~45 ( +// Equation(s): +// \Kp_Out[12]~45_combout = (Kp_Out[12] & (!\Kp_Out[11]~44 & VCC)) # (!Kp_Out[12] & (\Kp_Out[11]~44 $ (GND))) +// \Kp_Out[12]~46 = CARRY((!Kp_Out[12] & !\Kp_Out[11]~44 )) + + .dataa(gnd), + .datab(Kp_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[11]~44 ), + .combout(\Kp_Out[12]~45_combout ), + .cout(\Kp_Out[12]~46 )); +// synopsys translate_off +defparam \Kp_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Kp_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N5 +dffeas \Kp_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[12]~45_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[12] .is_wysiwyg = "true"; +defparam \Kp_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \Kp_Out[13]~47 ( +// Equation(s): +// \Kp_Out[13]~47_combout = (Kp_Out[13] & ((\Kp_Out[12]~46 ) # (GND))) # (!Kp_Out[13] & (!\Kp_Out[12]~46 )) +// \Kp_Out[13]~48 = CARRY((Kp_Out[13]) # (!\Kp_Out[12]~46 )) + + .dataa(Kp_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[12]~46 ), + .combout(\Kp_Out[13]~47_combout ), + .cout(\Kp_Out[13]~48 )); +// synopsys translate_off +defparam \Kp_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Kp_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N7 +dffeas \Kp_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[13]~47_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[13] .is_wysiwyg = "true"; +defparam \Kp_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \Kp_Out[14]~49 ( +// Equation(s): +// \Kp_Out[14]~49_combout = (Kp_Out[14] & (!\Kp_Out[13]~48 & VCC)) # (!Kp_Out[14] & (\Kp_Out[13]~48 $ (GND))) +// \Kp_Out[14]~50 = CARRY((!Kp_Out[14] & !\Kp_Out[13]~48 )) + + .dataa(gnd), + .datab(Kp_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[13]~48 ), + .combout(\Kp_Out[14]~49_combout ), + .cout(\Kp_Out[14]~50 )); +// synopsys translate_off +defparam \Kp_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Kp_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N9 +dffeas \Kp_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[14]~49_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[14] .is_wysiwyg = "true"; +defparam \Kp_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \Kp_Out[15]~51 ( +// Equation(s): +// \Kp_Out[15]~51_combout = (Kp_Out[15] & ((\Kp_Out[14]~50 ) # (GND))) # (!Kp_Out[15] & (!\Kp_Out[14]~50 )) +// \Kp_Out[15]~52 = CARRY((Kp_Out[15]) # (!\Kp_Out[14]~50 )) + + .dataa(Kp_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[14]~50 ), + .combout(\Kp_Out[15]~51_combout ), + .cout(\Kp_Out[15]~52 )); +// synopsys translate_off +defparam \Kp_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Kp_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N11 +dffeas \Kp_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[15]~51_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[15] .is_wysiwyg = "true"; +defparam \Kp_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \Kp_Out[16]~53 ( +// Equation(s): +// \Kp_Out[16]~53_combout = (Kp_Out[16] & (!\Kp_Out[15]~52 & VCC)) # (!Kp_Out[16] & (\Kp_Out[15]~52 $ (GND))) +// \Kp_Out[16]~54 = CARRY((!Kp_Out[16] & !\Kp_Out[15]~52 )) + + .dataa(Kp_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[15]~52 ), + .combout(\Kp_Out[16]~53_combout ), + .cout(\Kp_Out[16]~54 )); +// synopsys translate_off +defparam \Kp_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Kp_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N13 +dffeas \Kp_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[16]~53_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[16] .is_wysiwyg = "true"; +defparam \Kp_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \Kp_Out[17]~55 ( +// Equation(s): +// \Kp_Out[17]~55_combout = (Kp_Out[17] & ((\Kp_Out[16]~54 ) # (GND))) # (!Kp_Out[17] & (!\Kp_Out[16]~54 )) +// \Kp_Out[17]~56 = CARRY((Kp_Out[17]) # (!\Kp_Out[16]~54 )) + + .dataa(gnd), + .datab(Kp_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[16]~54 ), + .combout(\Kp_Out[17]~55_combout ), + .cout(\Kp_Out[17]~56 )); +// synopsys translate_off +defparam \Kp_Out[17]~55 .lut_mask = 16'hC3CF; +defparam \Kp_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N15 +dffeas \Kp_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[17]~55_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[17] .is_wysiwyg = "true"; +defparam \Kp_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \Kp_Out[18]~57 ( +// Equation(s): +// \Kp_Out[18]~57_combout = (Kp_Out[18] & (!\Kp_Out[17]~56 & VCC)) # (!Kp_Out[18] & (\Kp_Out[17]~56 $ (GND))) +// \Kp_Out[18]~58 = CARRY((!Kp_Out[18] & !\Kp_Out[17]~56 )) + + .dataa(gnd), + .datab(Kp_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[17]~56 ), + .combout(\Kp_Out[18]~57_combout ), + .cout(\Kp_Out[18]~58 )); +// synopsys translate_off +defparam \Kp_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Kp_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N17 +dffeas \Kp_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[18]~57_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[18] .is_wysiwyg = "true"; +defparam \Kp_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \Kp_Out[19]~59 ( +// Equation(s): +// \Kp_Out[19]~59_combout = (Kp_Out[19] & ((\Kp_Out[18]~58 ) # (GND))) # (!Kp_Out[19] & (!\Kp_Out[18]~58 )) +// \Kp_Out[19]~60 = CARRY((Kp_Out[19]) # (!\Kp_Out[18]~58 )) + + .dataa(gnd), + .datab(Kp_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[18]~58 ), + .combout(\Kp_Out[19]~59_combout ), + .cout(\Kp_Out[19]~60 )); +// synopsys translate_off +defparam \Kp_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Kp_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N19 +dffeas \Kp_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[19]~59_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[19] .is_wysiwyg = "true"; +defparam \Kp_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \Kp_Out[20]~61 ( +// Equation(s): +// \Kp_Out[20]~61_combout = \Kp_Out[19]~60 $ (Kp_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Kp_Out[20]), + .cin(\Kp_Out[19]~60 ), + .combout(\Kp_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Kp_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Kp_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \Kp_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[20]~61_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT20 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[20] .is_wysiwyg = "true"; +defparam \Kp_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N12 +cycloneive_lcell_comb \Add5~0 ( +// Equation(s): +// \Add5~0_combout = (Kp_Out[0] & ((GND) # (!Ki_Out[0]))) # (!Kp_Out[0] & (Ki_Out[0] $ (GND))) +// \Add5~1 = CARRY((Kp_Out[0]) # (!Ki_Out[0])) + + .dataa(Kp_Out[0]), + .datab(Ki_Out[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add5~0_combout ), + .cout(\Add5~1 )); +// synopsys translate_off +defparam \Add5~0 .lut_mask = 16'h66BB; +defparam \Add5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N14 +cycloneive_lcell_comb \Add5~2 ( +// Equation(s): +// \Add5~2_combout = (Ki_Out[1] & ((Kp_Out[1] & (!\Add5~1 )) # (!Kp_Out[1] & ((\Add5~1 ) # (GND))))) # (!Ki_Out[1] & ((Kp_Out[1] & (\Add5~1 & VCC)) # (!Kp_Out[1] & (!\Add5~1 )))) +// \Add5~3 = CARRY((Ki_Out[1] & ((!\Add5~1 ) # (!Kp_Out[1]))) # (!Ki_Out[1] & (!Kp_Out[1] & !\Add5~1 ))) + + .dataa(Ki_Out[1]), + .datab(Kp_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~1 ), + .combout(\Add5~2_combout ), + .cout(\Add5~3 )); +// synopsys translate_off +defparam \Add5~2 .lut_mask = 16'h692B; +defparam \Add5~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N16 +cycloneive_lcell_comb \Add5~4 ( +// Equation(s): +// \Add5~4_combout = ((Kp_Out[2] $ (Ki_Out[2] $ (\Add5~3 )))) # (GND) +// \Add5~5 = CARRY((Kp_Out[2] & ((!\Add5~3 ) # (!Ki_Out[2]))) # (!Kp_Out[2] & (!Ki_Out[2] & !\Add5~3 ))) + + .dataa(Kp_Out[2]), + .datab(Ki_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~3 ), + .combout(\Add5~4_combout ), + .cout(\Add5~5 )); +// synopsys translate_off +defparam \Add5~4 .lut_mask = 16'h962B; +defparam \Add5~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N18 +cycloneive_lcell_comb \Add5~6 ( +// Equation(s): +// \Add5~6_combout = (Kp_Out[3] & ((Ki_Out[3] & (!\Add5~5 )) # (!Ki_Out[3] & (\Add5~5 & VCC)))) # (!Kp_Out[3] & ((Ki_Out[3] & ((\Add5~5 ) # (GND))) # (!Ki_Out[3] & (!\Add5~5 )))) +// \Add5~7 = CARRY((Kp_Out[3] & (Ki_Out[3] & !\Add5~5 )) # (!Kp_Out[3] & ((Ki_Out[3]) # (!\Add5~5 )))) + + .dataa(Kp_Out[3]), + .datab(Ki_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~5 ), + .combout(\Add5~6_combout ), + .cout(\Add5~7 )); +// synopsys translate_off +defparam \Add5~6 .lut_mask = 16'h694D; +defparam \Add5~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N20 +cycloneive_lcell_comb \Add5~8 ( +// Equation(s): +// \Add5~8_combout = ((Ki_Out[4] $ (Kp_Out[4] $ (\Add5~7 )))) # (GND) +// \Add5~9 = CARRY((Ki_Out[4] & (Kp_Out[4] & !\Add5~7 )) # (!Ki_Out[4] & ((Kp_Out[4]) # (!\Add5~7 )))) + + .dataa(Ki_Out[4]), + .datab(Kp_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~7 ), + .combout(\Add5~8_combout ), + .cout(\Add5~9 )); +// synopsys translate_off +defparam \Add5~8 .lut_mask = 16'h964D; +defparam \Add5~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N22 +cycloneive_lcell_comb \Add5~10 ( +// Equation(s): +// \Add5~10_combout = (Ki_Out[5] & ((Kp_Out[5] & (!\Add5~9 )) # (!Kp_Out[5] & ((\Add5~9 ) # (GND))))) # (!Ki_Out[5] & ((Kp_Out[5] & (\Add5~9 & VCC)) # (!Kp_Out[5] & (!\Add5~9 )))) +// \Add5~11 = CARRY((Ki_Out[5] & ((!\Add5~9 ) # (!Kp_Out[5]))) # (!Ki_Out[5] & (!Kp_Out[5] & !\Add5~9 ))) + + .dataa(Ki_Out[5]), + .datab(Kp_Out[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~9 ), + .combout(\Add5~10_combout ), + .cout(\Add5~11 )); +// synopsys translate_off +defparam \Add5~10 .lut_mask = 16'h692B; +defparam \Add5~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N24 +cycloneive_lcell_comb \Add5~12 ( +// Equation(s): +// \Add5~12_combout = ((Ki_Out[6] $ (Kp_Out[6] $ (\Add5~11 )))) # (GND) +// \Add5~13 = CARRY((Ki_Out[6] & (Kp_Out[6] & !\Add5~11 )) # (!Ki_Out[6] & ((Kp_Out[6]) # (!\Add5~11 )))) + + .dataa(Ki_Out[6]), + .datab(Kp_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~11 ), + .combout(\Add5~12_combout ), + .cout(\Add5~13 )); +// synopsys translate_off +defparam \Add5~12 .lut_mask = 16'h964D; +defparam \Add5~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N26 +cycloneive_lcell_comb \Add5~14 ( +// Equation(s): +// \Add5~14_combout = (Kp_Out[7] & ((Ki_Out[7] & (!\Add5~13 )) # (!Ki_Out[7] & (\Add5~13 & VCC)))) # (!Kp_Out[7] & ((Ki_Out[7] & ((\Add5~13 ) # (GND))) # (!Ki_Out[7] & (!\Add5~13 )))) +// \Add5~15 = CARRY((Kp_Out[7] & (Ki_Out[7] & !\Add5~13 )) # (!Kp_Out[7] & ((Ki_Out[7]) # (!\Add5~13 )))) + + .dataa(Kp_Out[7]), + .datab(Ki_Out[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~13 ), + .combout(\Add5~14_combout ), + .cout(\Add5~15 )); +// synopsys translate_off +defparam \Add5~14 .lut_mask = 16'h694D; +defparam \Add5~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N28 +cycloneive_lcell_comb \Add5~24 ( +// Equation(s): +// \Add5~24_combout = ((Kp_Out[8] $ (Ki_Out[8] $ (\Add5~15 )))) # (GND) +// \Add5~25 = CARRY((Kp_Out[8] & ((!\Add5~15 ) # (!Ki_Out[8]))) # (!Kp_Out[8] & (!Ki_Out[8] & !\Add5~15 ))) + + .dataa(Kp_Out[8]), + .datab(Ki_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~15 ), + .combout(\Add5~24_combout ), + .cout(\Add5~25 )); +// synopsys translate_off +defparam \Add5~24 .lut_mask = 16'h962B; +defparam \Add5~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N30 +cycloneive_lcell_comb \Add5~27 ( +// Equation(s): +// \Add5~27_combout = (Ki_Out[9] & ((Kp_Out[9] & (!\Add5~25 )) # (!Kp_Out[9] & ((\Add5~25 ) # (GND))))) # (!Ki_Out[9] & ((Kp_Out[9] & (\Add5~25 & VCC)) # (!Kp_Out[9] & (!\Add5~25 )))) +// \Add5~28 = CARRY((Ki_Out[9] & ((!\Add5~25 ) # (!Kp_Out[9]))) # (!Ki_Out[9] & (!Kp_Out[9] & !\Add5~25 ))) + + .dataa(Ki_Out[9]), + .datab(Kp_Out[9]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~25 ), + .combout(\Add5~27_combout ), + .cout(\Add5~28 )); +// synopsys translate_off +defparam \Add5~27 .lut_mask = 16'h692B; +defparam \Add5~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N0 +cycloneive_lcell_comb \Add5~30 ( +// Equation(s): +// \Add5~30_combout = ((Kp_Out[10] $ (Ki_Out[10] $ (\Add5~28 )))) # (GND) +// \Add5~31 = CARRY((Kp_Out[10] & ((!\Add5~28 ) # (!Ki_Out[10]))) # (!Kp_Out[10] & (!Ki_Out[10] & !\Add5~28 ))) + + .dataa(Kp_Out[10]), + .datab(Ki_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~28 ), + .combout(\Add5~30_combout ), + .cout(\Add5~31 )); +// synopsys translate_off +defparam \Add5~30 .lut_mask = 16'h962B; +defparam \Add5~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N2 +cycloneive_lcell_comb \Add5~33 ( +// Equation(s): +// \Add5~33_combout = (Ki_Out[11] & ((Kp_Out[11] & (!\Add5~31 )) # (!Kp_Out[11] & ((\Add5~31 ) # (GND))))) # (!Ki_Out[11] & ((Kp_Out[11] & (\Add5~31 & VCC)) # (!Kp_Out[11] & (!\Add5~31 )))) +// \Add5~34 = CARRY((Ki_Out[11] & ((!\Add5~31 ) # (!Kp_Out[11]))) # (!Ki_Out[11] & (!Kp_Out[11] & !\Add5~31 ))) + + .dataa(Ki_Out[11]), + .datab(Kp_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~31 ), + .combout(\Add5~33_combout ), + .cout(\Add5~34 )); +// synopsys translate_off +defparam \Add5~33 .lut_mask = 16'h692B; +defparam \Add5~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N4 +cycloneive_lcell_comb \Add5~36 ( +// Equation(s): +// \Add5~36_combout = ((Ki_Out[12] $ (Kp_Out[12] $ (\Add5~34 )))) # (GND) +// \Add5~37 = CARRY((Ki_Out[12] & (Kp_Out[12] & !\Add5~34 )) # (!Ki_Out[12] & ((Kp_Out[12]) # (!\Add5~34 )))) + + .dataa(Ki_Out[12]), + .datab(Kp_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~34 ), + .combout(\Add5~36_combout ), + .cout(\Add5~37 )); +// synopsys translate_off +defparam \Add5~36 .lut_mask = 16'h964D; +defparam \Add5~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N6 +cycloneive_lcell_comb \Add5~39 ( +// Equation(s): +// \Add5~39_combout = (Ki_Out[13] & ((Kp_Out[13] & (!\Add5~37 )) # (!Kp_Out[13] & ((\Add5~37 ) # (GND))))) # (!Ki_Out[13] & ((Kp_Out[13] & (\Add5~37 & VCC)) # (!Kp_Out[13] & (!\Add5~37 )))) +// \Add5~40 = CARRY((Ki_Out[13] & ((!\Add5~37 ) # (!Kp_Out[13]))) # (!Ki_Out[13] & (!Kp_Out[13] & !\Add5~37 ))) + + .dataa(Ki_Out[13]), + .datab(Kp_Out[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~37 ), + .combout(\Add5~39_combout ), + .cout(\Add5~40 )); +// synopsys translate_off +defparam \Add5~39 .lut_mask = 16'h692B; +defparam \Add5~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N8 +cycloneive_lcell_comb \Add5~42 ( +// Equation(s): +// \Add5~42_combout = ((Kp_Out[14] $ (Ki_Out[14] $ (\Add5~40 )))) # (GND) +// \Add5~43 = CARRY((Kp_Out[14] & ((!\Add5~40 ) # (!Ki_Out[14]))) # (!Kp_Out[14] & (!Ki_Out[14] & !\Add5~40 ))) + + .dataa(Kp_Out[14]), + .datab(Ki_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~40 ), + .combout(\Add5~42_combout ), + .cout(\Add5~43 )); +// synopsys translate_off +defparam \Add5~42 .lut_mask = 16'h962B; +defparam \Add5~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N10 +cycloneive_lcell_comb \Add5~45 ( +// Equation(s): +// \Add5~45_combout = (Ki_Out[15] & ((Kp_Out[15] & (!\Add5~43 )) # (!Kp_Out[15] & ((\Add5~43 ) # (GND))))) # (!Ki_Out[15] & ((Kp_Out[15] & (\Add5~43 & VCC)) # (!Kp_Out[15] & (!\Add5~43 )))) +// \Add5~46 = CARRY((Ki_Out[15] & ((!\Add5~43 ) # (!Kp_Out[15]))) # (!Ki_Out[15] & (!Kp_Out[15] & !\Add5~43 ))) + + .dataa(Ki_Out[15]), + .datab(Kp_Out[15]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~43 ), + .combout(\Add5~45_combout ), + .cout(\Add5~46 )); +// synopsys translate_off +defparam \Add5~45 .lut_mask = 16'h692B; +defparam \Add5~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N12 +cycloneive_lcell_comb \Add5~48 ( +// Equation(s): +// \Add5~48_combout = ((Ki_Out[16] $ (Kp_Out[16] $ (\Add5~46 )))) # (GND) +// \Add5~49 = CARRY((Ki_Out[16] & (Kp_Out[16] & !\Add5~46 )) # (!Ki_Out[16] & ((Kp_Out[16]) # (!\Add5~46 )))) + + .dataa(Ki_Out[16]), + .datab(Kp_Out[16]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~46 ), + .combout(\Add5~48_combout ), + .cout(\Add5~49 )); +// synopsys translate_off +defparam \Add5~48 .lut_mask = 16'h964D; +defparam \Add5~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N14 +cycloneive_lcell_comb \Add5~51 ( +// Equation(s): +// \Add5~51_combout = (Kp_Out[17] & ((Ki_Out[17] & (!\Add5~49 )) # (!Ki_Out[17] & (\Add5~49 & VCC)))) # (!Kp_Out[17] & ((Ki_Out[17] & ((\Add5~49 ) # (GND))) # (!Ki_Out[17] & (!\Add5~49 )))) +// \Add5~52 = CARRY((Kp_Out[17] & (Ki_Out[17] & !\Add5~49 )) # (!Kp_Out[17] & ((Ki_Out[17]) # (!\Add5~49 )))) + + .dataa(Kp_Out[17]), + .datab(Ki_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~49 ), + .combout(\Add5~51_combout ), + .cout(\Add5~52 )); +// synopsys translate_off +defparam \Add5~51 .lut_mask = 16'h694D; +defparam \Add5~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N16 +cycloneive_lcell_comb \Add5~54 ( +// Equation(s): +// \Add5~54_combout = ((Kp_Out[18] $ (Ki_Out[18] $ (\Add5~52 )))) # (GND) +// \Add5~55 = CARRY((Kp_Out[18] & ((!\Add5~52 ) # (!Ki_Out[18]))) # (!Kp_Out[18] & (!Ki_Out[18] & !\Add5~52 ))) + + .dataa(Kp_Out[18]), + .datab(Ki_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~52 ), + .combout(\Add5~54_combout ), + .cout(\Add5~55 )); +// synopsys translate_off +defparam \Add5~54 .lut_mask = 16'h962B; +defparam \Add5~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N18 +cycloneive_lcell_comb \Add5~57 ( +// Equation(s): +// \Add5~57_combout = (Kp_Out[19] & ((Ki_Out[19] & (!\Add5~55 )) # (!Ki_Out[19] & (\Add5~55 & VCC)))) # (!Kp_Out[19] & ((Ki_Out[19] & ((\Add5~55 ) # (GND))) # (!Ki_Out[19] & (!\Add5~55 )))) +// \Add5~58 = CARRY((Kp_Out[19] & (Ki_Out[19] & !\Add5~55 )) # (!Kp_Out[19] & ((Ki_Out[19]) # (!\Add5~55 )))) + + .dataa(Kp_Out[19]), + .datab(Ki_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~55 ), + .combout(\Add5~57_combout ), + .cout(\Add5~58 )); +// synopsys translate_off +defparam \Add5~57 .lut_mask = 16'h694D; +defparam \Add5~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N20 +cycloneive_lcell_comb \Add5~60 ( +// Equation(s): +// \Add5~60_combout = Ki_Out[20] $ (\Add5~58 $ (Kp_Out[20])) + + .dataa(Ki_Out[20]), + .datab(gnd), + .datac(gnd), + .datad(Kp_Out[20]), + .cin(\Add5~58 ), + .combout(\Add5~60_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~60 .lut_mask = 16'hA55A; +defparam \Add5~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N12 +cycloneive_lcell_comb \Add5~62 ( +// Equation(s): +// \Add5~62_combout = (!\Vout[13]~reg0_q & \Add5~60_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~60_combout ), + .cin(gnd), + .combout(\Add5~62_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~62 .lut_mask = 16'h0F00; +defparam \Add5~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N10 +cycloneive_lcell_comb \Add7~19 ( +// Equation(s): +// \Add7~19_combout = (!\Vout[13]~reg0_q & Kd_Out[19]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[19]), + .cin(gnd), + .combout(\Add7~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~19 .lut_mask = 16'h0F00; +defparam \Add7~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N16 +cycloneive_lcell_comb \Add7~18 ( +// Equation(s): +// \Add7~18_combout = (!\Vout[13]~reg0_q & Kd_Out[18]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[18]), + .cin(gnd), + .combout(\Add7~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~18 .lut_mask = 16'h0F00; +defparam \Add7~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N10 +cycloneive_lcell_comb \Add7~17 ( +// Equation(s): +// \Add7~17_combout = (Kd_Out[17] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[17]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~17 .lut_mask = 16'h00F0; +defparam \Add7~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N20 +cycloneive_lcell_comb \Add7~16 ( +// Equation(s): +// \Add7~16_combout = (Kd_Out[16] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[16]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~16 .lut_mask = 16'h00F0; +defparam \Add7~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N26 +cycloneive_lcell_comb \Add7~15 ( +// Equation(s): +// \Add7~15_combout = (!\Vout[13]~reg0_q & Kd_Out[15]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[15]), + .cin(gnd), + .combout(\Add7~15_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~15 .lut_mask = 16'h0F00; +defparam \Add7~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N4 +cycloneive_lcell_comb \Add7~14 ( +// Equation(s): +// \Add7~14_combout = (!\Vout[13]~reg0_q & Kd_Out[14]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[14]), + .cin(gnd), + .combout(\Add7~14_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~14 .lut_mask = 16'h0F00; +defparam \Add7~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N2 +cycloneive_lcell_comb \Add7~13 ( +// Equation(s): +// \Add7~13_combout = (Kd_Out[13] & !\Vout[13]~reg0_q ) + + .dataa(Kd_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~13_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~13 .lut_mask = 16'h00AA; +defparam \Add7~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N14 +cycloneive_lcell_comb \Add7~12 ( +// Equation(s): +// \Add7~12_combout = (Kd_Out[12] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(Kd_Out[12]), + .datac(\Vout[13]~reg0_q ), + .datad(gnd), + .cin(gnd), + .combout(\Add7~12_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~12 .lut_mask = 16'h0C0C; +defparam \Add7~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N20 +cycloneive_lcell_comb \Add7~11 ( +// Equation(s): +// \Add7~11_combout = (!\Vout[13]~reg0_q & Kd_Out[11]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[11]), + .cin(gnd), + .combout(\Add7~11_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~11 .lut_mask = 16'h0F00; +defparam \Add7~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N16 +cycloneive_lcell_comb \Add7~10 ( +// Equation(s): +// \Add7~10_combout = (Kd_Out[10] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[10]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~10_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~10 .lut_mask = 16'h00F0; +defparam \Add7~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N12 +cycloneive_lcell_comb \Add7~9 ( +// Equation(s): +// \Add7~9_combout = (Kd_Out[9] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[9]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~9_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~9 .lut_mask = 16'h00F0; +defparam \Add7~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N16 +cycloneive_lcell_comb \Add7~8 ( +// Equation(s): +// \Add7~8_combout = (!\Vout[13]~reg0_q & Kd_Out[8]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[8]), + .cin(gnd), + .combout(\Add7~8_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~8 .lut_mask = 16'h5500; +defparam \Add7~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N8 +cycloneive_lcell_comb \Add5~16 ( +// Equation(s): +// \Add5~16_combout = (\Vout[13]~reg0_q & (!\Vout[0]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~14_combout ))) + + .dataa(\Vout[0]~reg0_q ), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~14_combout ), + .cin(gnd), + .combout(\Add5~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~16 .lut_mask = 16'h5F50; +defparam \Add5~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y14_N0 +cycloneive_lcell_comb \Add7~1 ( +// Equation(s): +// \Add7~1_combout = (!\Vout[13]~reg0_q & Kd_Out[6]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[6]), + .cin(gnd), + .combout(\Add7~1_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~1 .lut_mask = 16'h0F00; +defparam \Add7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N0 +cycloneive_lcell_comb \Add5~17 ( +// Equation(s): +// \Add5~17_combout = (!\Vout[13]~reg0_q & \Add5~12_combout ) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\Add5~12_combout ), + .cin(gnd), + .combout(\Add5~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~17 .lut_mask = 16'h5500; +defparam \Add5~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N8 +cycloneive_lcell_comb \Add7~2 ( +// Equation(s): +// \Add7~2_combout = (!\Vout[13]~reg0_q & Kd_Out[5]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[5]), + .cin(gnd), + .combout(\Add7~2_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~2 .lut_mask = 16'h5500; +defparam \Add7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N10 +cycloneive_lcell_comb \Add5~18 ( +// Equation(s): +// \Add5~18_combout = (\Add5~10_combout & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Add5~10_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~18 .lut_mask = 16'h00F0; +defparam \Add5~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N4 +cycloneive_lcell_comb \Add7~3 ( +// Equation(s): +// \Add7~3_combout = (Kd_Out[4] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(Kd_Out[4]), + .datac(gnd), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~3_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~3 .lut_mask = 16'h00CC; +defparam \Add7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N2 +cycloneive_lcell_comb \Add5~19 ( +// Equation(s): +// \Add5~19_combout = (!\Vout[13]~reg0_q & \Add5~8_combout ) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~19 .lut_mask = 16'h3030; +defparam \Add5~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N2 +cycloneive_lcell_comb \Add5~20 ( +// Equation(s): +// \Add5~20_combout = (!\Vout[13]~reg0_q & \Add5~6_combout ) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\Add5~6_combout ), + .cin(gnd), + .combout(\Add5~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~20 .lut_mask = 16'h5500; +defparam \Add5~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N8 +cycloneive_lcell_comb \Add7~4 ( +// Equation(s): +// \Add7~4_combout = (!\Vout[13]~reg0_q & Kd_Out[3]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[3]), + .cin(gnd), + .combout(\Add7~4_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~4 .lut_mask = 16'h5500; +defparam \Add7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N14 +cycloneive_lcell_comb \Add7~5 ( +// Equation(s): +// \Add7~5_combout = (Kd_Out[2] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[2]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~5_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~5 .lut_mask = 16'h00F0; +defparam \Add7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N0 +cycloneive_lcell_comb \Add5~21 ( +// Equation(s): +// \Add5~21_combout = (!\Vout[13]~reg0_q & \Add5~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~4_combout ), + .cin(gnd), + .combout(\Add5~21_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~21 .lut_mask = 16'h0F00; +defparam \Add5~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N6 +cycloneive_lcell_comb \Add7~6 ( +// Equation(s): +// \Add7~6_combout = (Kd_Out[1] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[1]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~6_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~6 .lut_mask = 16'h00F0; +defparam \Add7~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N8 +cycloneive_lcell_comb \Add5~22 ( +// Equation(s): +// \Add5~22_combout = (\Add5~2_combout & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Add5~2_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~22_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~22 .lut_mask = 16'h00F0; +defparam \Add5~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N10 +cycloneive_lcell_comb \Add5~23 ( +// Equation(s): +// \Add5~23_combout = (!\Vout[13]~reg0_q & \Add5~0_combout ) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~23_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~23 .lut_mask = 16'h3030; +defparam \Add5~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N22 +cycloneive_lcell_comb \Add7~7 ( +// Equation(s): +// \Add7~7_combout = (Kd_Out[0] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[0]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~7_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~7 .lut_mask = 16'h00F0; +defparam \Add7~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N12 +cycloneive_lcell_comb \Vout[0]~15 ( +// Equation(s): +// \Vout[0]~15_cout = CARRY((\Add5~23_combout & \Add7~7_combout )) + + .dataa(\Add5~23_combout ), + .datab(\Add7~7_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\Vout[0]~15_cout )); +// synopsys translate_off +defparam \Vout[0]~15 .lut_mask = 16'h0088; +defparam \Vout[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N14 +cycloneive_lcell_comb \Vout[0]~17 ( +// Equation(s): +// \Vout[0]~17_cout = CARRY((\Add7~6_combout & (!\Add5~22_combout & !\Vout[0]~15_cout )) # (!\Add7~6_combout & ((!\Vout[0]~15_cout ) # (!\Add5~22_combout )))) + + .dataa(\Add7~6_combout ), + .datab(\Add5~22_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~15_cout ), + .combout(), + .cout(\Vout[0]~17_cout )); +// synopsys translate_off +defparam \Vout[0]~17 .lut_mask = 16'h0017; +defparam \Vout[0]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N16 +cycloneive_lcell_comb \Vout[0]~19 ( +// Equation(s): +// \Vout[0]~19_cout = CARRY((\Add7~5_combout & ((\Add5~21_combout ) # (!\Vout[0]~17_cout ))) # (!\Add7~5_combout & (\Add5~21_combout & !\Vout[0]~17_cout ))) + + .dataa(\Add7~5_combout ), + .datab(\Add5~21_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~17_cout ), + .combout(), + .cout(\Vout[0]~19_cout )); +// synopsys translate_off +defparam \Vout[0]~19 .lut_mask = 16'h008E; +defparam \Vout[0]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N18 +cycloneive_lcell_comb \Vout[0]~21 ( +// Equation(s): +// \Vout[0]~21_cout = CARRY((\Add5~20_combout & (!\Add7~4_combout & !\Vout[0]~19_cout )) # (!\Add5~20_combout & ((!\Vout[0]~19_cout ) # (!\Add7~4_combout )))) + + .dataa(\Add5~20_combout ), + .datab(\Add7~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~19_cout ), + .combout(), + .cout(\Vout[0]~21_cout )); +// synopsys translate_off +defparam \Vout[0]~21 .lut_mask = 16'h0017; +defparam \Vout[0]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N20 +cycloneive_lcell_comb \Vout[0]~23 ( +// Equation(s): +// \Vout[0]~23_cout = CARRY((\Add7~3_combout & ((\Add5~19_combout ) # (!\Vout[0]~21_cout ))) # (!\Add7~3_combout & (\Add5~19_combout & !\Vout[0]~21_cout ))) + + .dataa(\Add7~3_combout ), + .datab(\Add5~19_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~21_cout ), + .combout(), + .cout(\Vout[0]~23_cout )); +// synopsys translate_off +defparam \Vout[0]~23 .lut_mask = 16'h008E; +defparam \Vout[0]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N22 +cycloneive_lcell_comb \Vout[0]~25 ( +// Equation(s): +// \Vout[0]~25_cout = CARRY((\Add7~2_combout & (!\Add5~18_combout & !\Vout[0]~23_cout )) # (!\Add7~2_combout & ((!\Vout[0]~23_cout ) # (!\Add5~18_combout )))) + + .dataa(\Add7~2_combout ), + .datab(\Add5~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~23_cout ), + .combout(), + .cout(\Vout[0]~25_cout )); +// synopsys translate_off +defparam \Vout[0]~25 .lut_mask = 16'h0017; +defparam \Vout[0]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N24 +cycloneive_lcell_comb \Vout[0]~27 ( +// Equation(s): +// \Vout[0]~27_cout = CARRY((\Add7~1_combout & ((\Add5~17_combout ) # (!\Vout[0]~25_cout ))) # (!\Add7~1_combout & (\Add5~17_combout & !\Vout[0]~25_cout ))) + + .dataa(\Add7~1_combout ), + .datab(\Add5~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~25_cout ), + .combout(), + .cout(\Vout[0]~27_cout )); +// synopsys translate_off +defparam \Vout[0]~27 .lut_mask = 16'h008E; +defparam \Vout[0]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N26 +cycloneive_lcell_comb \Vout[0]~28 ( +// Equation(s): +// \Vout[0]~28_combout = (\Add7~0_combout & ((\Add5~16_combout & (\Vout[0]~27_cout & VCC)) # (!\Add5~16_combout & (!\Vout[0]~27_cout )))) # (!\Add7~0_combout & ((\Add5~16_combout & (!\Vout[0]~27_cout )) # (!\Add5~16_combout & ((\Vout[0]~27_cout ) # +// (GND))))) +// \Vout[0]~29 = CARRY((\Add7~0_combout & (!\Add5~16_combout & !\Vout[0]~27_cout )) # (!\Add7~0_combout & ((!\Vout[0]~27_cout ) # (!\Add5~16_combout )))) + + .dataa(\Add7~0_combout ), + .datab(\Add5~16_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~27_cout ), + .combout(\Vout[0]~28_combout ), + .cout(\Vout[0]~29 )); +// synopsys translate_off +defparam \Vout[0]~28 .lut_mask = 16'h9617; +defparam \Vout[0]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N28 +cycloneive_lcell_comb \Vout[1]~30 ( +// Equation(s): +// \Vout[1]~30_combout = ((\Add7~8_combout $ (\Add5~26_combout $ (!\Vout[0]~29 )))) # (GND) +// \Vout[1]~31 = CARRY((\Add7~8_combout & ((\Add5~26_combout ) # (!\Vout[0]~29 ))) # (!\Add7~8_combout & (\Add5~26_combout & !\Vout[0]~29 ))) + + .dataa(\Add7~8_combout ), + .datab(\Add5~26_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~29 ), + .combout(\Vout[1]~30_combout ), + .cout(\Vout[1]~31 )); +// synopsys translate_off +defparam \Vout[1]~30 .lut_mask = 16'h698E; +defparam \Vout[1]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y18_N29 +dffeas \Vout[1]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[1]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[1]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[1]~reg0 .is_wysiwyg = "true"; +defparam \Vout[1]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N4 +cycloneive_lcell_comb \Add5~26 ( +// Equation(s): +// \Add5~26_combout = (\Vout[13]~reg0_q & (!\Vout[1]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~24_combout ))) + + .dataa(gnd), + .datab(\Vout[1]~reg0_q ), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~24_combout ), + .cin(gnd), + .combout(\Add5~26_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~26 .lut_mask = 16'h3F30; +defparam \Add5~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N30 +cycloneive_lcell_comb \Vout[2]~32 ( +// Equation(s): +// \Vout[2]~32_combout = (\Add5~29_combout & ((\Add7~9_combout & (\Vout[1]~31 & VCC)) # (!\Add7~9_combout & (!\Vout[1]~31 )))) # (!\Add5~29_combout & ((\Add7~9_combout & (!\Vout[1]~31 )) # (!\Add7~9_combout & ((\Vout[1]~31 ) # (GND))))) +// \Vout[2]~33 = CARRY((\Add5~29_combout & (!\Add7~9_combout & !\Vout[1]~31 )) # (!\Add5~29_combout & ((!\Vout[1]~31 ) # (!\Add7~9_combout )))) + + .dataa(\Add5~29_combout ), + .datab(\Add7~9_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[1]~31 ), + .combout(\Vout[2]~32_combout ), + .cout(\Vout[2]~33 )); +// synopsys translate_off +defparam \Vout[2]~32 .lut_mask = 16'h9617; +defparam \Vout[2]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y18_N31 +dffeas \Vout[2]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[2]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[2]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[2]~reg0 .is_wysiwyg = "true"; +defparam \Vout[2]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N6 +cycloneive_lcell_comb \Add5~29 ( +// Equation(s): +// \Add5~29_combout = (\Vout[13]~reg0_q & (!\Vout[2]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~27_combout ))) + + .dataa(\Vout[2]~reg0_q ), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~27_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~29_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~29 .lut_mask = 16'h7474; +defparam \Add5~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N0 +cycloneive_lcell_comb \Vout[3]~34 ( +// Equation(s): +// \Vout[3]~34_combout = ((\Add5~32_combout $ (\Add7~10_combout $ (!\Vout[2]~33 )))) # (GND) +// \Vout[3]~35 = CARRY((\Add5~32_combout & ((\Add7~10_combout ) # (!\Vout[2]~33 ))) # (!\Add5~32_combout & (\Add7~10_combout & !\Vout[2]~33 ))) + + .dataa(\Add5~32_combout ), + .datab(\Add7~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[2]~33 ), + .combout(\Vout[3]~34_combout ), + .cout(\Vout[3]~35 )); +// synopsys translate_off +defparam \Vout[3]~34 .lut_mask = 16'h698E; +defparam \Vout[3]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N1 +dffeas \Vout[3]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[3]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[3]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[3]~reg0 .is_wysiwyg = "true"; +defparam \Vout[3]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N26 +cycloneive_lcell_comb \Add5~32 ( +// Equation(s): +// \Add5~32_combout = (\Vout[13]~reg0_q & ((!\Vout[3]~reg0_q ))) # (!\Vout[13]~reg0_q & (\Add5~30_combout )) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~30_combout ), + .datad(\Vout[3]~reg0_q ), + .cin(gnd), + .combout(\Add5~32_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~32 .lut_mask = 16'h30FC; +defparam \Add5~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N2 +cycloneive_lcell_comb \Vout[4]~36 ( +// Equation(s): +// \Vout[4]~36_combout = (\Add5~35_combout & ((\Add7~11_combout & (\Vout[3]~35 & VCC)) # (!\Add7~11_combout & (!\Vout[3]~35 )))) # (!\Add5~35_combout & ((\Add7~11_combout & (!\Vout[3]~35 )) # (!\Add7~11_combout & ((\Vout[3]~35 ) # (GND))))) +// \Vout[4]~37 = CARRY((\Add5~35_combout & (!\Add7~11_combout & !\Vout[3]~35 )) # (!\Add5~35_combout & ((!\Vout[3]~35 ) # (!\Add7~11_combout )))) + + .dataa(\Add5~35_combout ), + .datab(\Add7~11_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[3]~35 ), + .combout(\Vout[4]~36_combout ), + .cout(\Vout[4]~37 )); +// synopsys translate_off +defparam \Vout[4]~36 .lut_mask = 16'h9617; +defparam \Vout[4]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N3 +dffeas \Vout[4]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[4]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[4]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[4]~reg0 .is_wysiwyg = "true"; +defparam \Vout[4]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N30 +cycloneive_lcell_comb \Add5~35 ( +// Equation(s): +// \Add5~35_combout = (\Vout[13]~reg0_q & (!\Vout[4]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~33_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[4]~reg0_q ), + .datad(\Add5~33_combout ), + .cin(gnd), + .combout(\Add5~35_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~35 .lut_mask = 16'h3F0C; +defparam \Add5~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N4 +cycloneive_lcell_comb \Vout[5]~38 ( +// Equation(s): +// \Vout[5]~38_combout = ((\Add7~12_combout $ (\Add5~38_combout $ (!\Vout[4]~37 )))) # (GND) +// \Vout[5]~39 = CARRY((\Add7~12_combout & ((\Add5~38_combout ) # (!\Vout[4]~37 ))) # (!\Add7~12_combout & (\Add5~38_combout & !\Vout[4]~37 ))) + + .dataa(\Add7~12_combout ), + .datab(\Add5~38_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[4]~37 ), + .combout(\Vout[5]~38_combout ), + .cout(\Vout[5]~39 )); +// synopsys translate_off +defparam \Vout[5]~38 .lut_mask = 16'h698E; +defparam \Vout[5]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N5 +dffeas \Vout[5]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[5]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[5]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[5]~reg0 .is_wysiwyg = "true"; +defparam \Vout[5]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N28 +cycloneive_lcell_comb \Add5~38 ( +// Equation(s): +// \Add5~38_combout = (\Vout[13]~reg0_q & (!\Vout[5]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~36_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[5]~reg0_q ), + .datad(\Add5~36_combout ), + .cin(gnd), + .combout(\Add5~38_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~38 .lut_mask = 16'h3F0C; +defparam \Add5~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N6 +cycloneive_lcell_comb \Vout[6]~40 ( +// Equation(s): +// \Vout[6]~40_combout = (\Add7~13_combout & ((\Add5~41_combout & (\Vout[5]~39 & VCC)) # (!\Add5~41_combout & (!\Vout[5]~39 )))) # (!\Add7~13_combout & ((\Add5~41_combout & (!\Vout[5]~39 )) # (!\Add5~41_combout & ((\Vout[5]~39 ) # (GND))))) +// \Vout[6]~41 = CARRY((\Add7~13_combout & (!\Add5~41_combout & !\Vout[5]~39 )) # (!\Add7~13_combout & ((!\Vout[5]~39 ) # (!\Add5~41_combout )))) + + .dataa(\Add7~13_combout ), + .datab(\Add5~41_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[5]~39 ), + .combout(\Vout[6]~40_combout ), + .cout(\Vout[6]~41 )); +// synopsys translate_off +defparam \Vout[6]~40 .lut_mask = 16'h9617; +defparam \Vout[6]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N7 +dffeas \Vout[6]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[6]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[6]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[6]~reg0 .is_wysiwyg = "true"; +defparam \Vout[6]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N24 +cycloneive_lcell_comb \Add5~41 ( +// Equation(s): +// \Add5~41_combout = (\Vout[13]~reg0_q & (!\Vout[6]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~39_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[6]~reg0_q ), + .datad(\Add5~39_combout ), + .cin(gnd), + .combout(\Add5~41_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~41 .lut_mask = 16'h3F0C; +defparam \Add5~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N8 +cycloneive_lcell_comb \Vout[7]~42 ( +// Equation(s): +// \Vout[7]~42_combout = ((\Add5~44_combout $ (\Add7~14_combout $ (!\Vout[6]~41 )))) # (GND) +// \Vout[7]~43 = CARRY((\Add5~44_combout & ((\Add7~14_combout ) # (!\Vout[6]~41 ))) # (!\Add5~44_combout & (\Add7~14_combout & !\Vout[6]~41 ))) + + .dataa(\Add5~44_combout ), + .datab(\Add7~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[6]~41 ), + .combout(\Vout[7]~42_combout ), + .cout(\Vout[7]~43 )); +// synopsys translate_off +defparam \Vout[7]~42 .lut_mask = 16'h698E; +defparam \Vout[7]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N9 +dffeas \Vout[7]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[7]~42_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[7]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[7]~reg0 .is_wysiwyg = "true"; +defparam \Vout[7]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N30 +cycloneive_lcell_comb \Add5~44 ( +// Equation(s): +// \Add5~44_combout = (\Vout[13]~reg0_q & (!\Vout[7]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~42_combout ))) + + .dataa(gnd), + .datab(\Vout[7]~reg0_q ), + .datac(\Add5~42_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~44_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~44 .lut_mask = 16'h33F0; +defparam \Add5~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N10 +cycloneive_lcell_comb \Vout[8]~44 ( +// Equation(s): +// \Vout[8]~44_combout = (\Add7~15_combout & ((\Add5~47_combout & (\Vout[7]~43 & VCC)) # (!\Add5~47_combout & (!\Vout[7]~43 )))) # (!\Add7~15_combout & ((\Add5~47_combout & (!\Vout[7]~43 )) # (!\Add5~47_combout & ((\Vout[7]~43 ) # (GND))))) +// \Vout[8]~45 = CARRY((\Add7~15_combout & (!\Add5~47_combout & !\Vout[7]~43 )) # (!\Add7~15_combout & ((!\Vout[7]~43 ) # (!\Add5~47_combout )))) + + .dataa(\Add7~15_combout ), + .datab(\Add5~47_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[7]~43 ), + .combout(\Vout[8]~44_combout ), + .cout(\Vout[8]~45 )); +// synopsys translate_off +defparam \Vout[8]~44 .lut_mask = 16'h9617; +defparam \Vout[8]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N11 +dffeas \Vout[8]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[8]~44_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[8]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[8]~reg0 .is_wysiwyg = "true"; +defparam \Vout[8]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N26 +cycloneive_lcell_comb \Add5~47 ( +// Equation(s): +// \Add5~47_combout = (\Vout[13]~reg0_q & (!\Vout[8]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~45_combout ))) + + .dataa(\Vout[8]~reg0_q ), + .datab(\Vout[13]~reg0_q ), + .datac(gnd), + .datad(\Add5~45_combout ), + .cin(gnd), + .combout(\Add5~47_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~47 .lut_mask = 16'h7744; +defparam \Add5~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N12 +cycloneive_lcell_comb \Vout[9]~46 ( +// Equation(s): +// \Vout[9]~46_combout = ((\Add7~16_combout $ (\Add5~50_combout $ (!\Vout[8]~45 )))) # (GND) +// \Vout[9]~47 = CARRY((\Add7~16_combout & ((\Add5~50_combout ) # (!\Vout[8]~45 ))) # (!\Add7~16_combout & (\Add5~50_combout & !\Vout[8]~45 ))) + + .dataa(\Add7~16_combout ), + .datab(\Add5~50_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[8]~45 ), + .combout(\Vout[9]~46_combout ), + .cout(\Vout[9]~47 )); +// synopsys translate_off +defparam \Vout[9]~46 .lut_mask = 16'h698E; +defparam \Vout[9]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N13 +dffeas \Vout[9]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[9]~46_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[9]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[9]~reg0 .is_wysiwyg = "true"; +defparam \Vout[9]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N24 +cycloneive_lcell_comb \Add5~50 ( +// Equation(s): +// \Add5~50_combout = (\Vout[13]~reg0_q & ((!\Vout[9]~reg0_q ))) # (!\Vout[13]~reg0_q & (\Add5~48_combout )) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~48_combout ), + .datad(\Vout[9]~reg0_q ), + .cin(gnd), + .combout(\Add5~50_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~50 .lut_mask = 16'h30FC; +defparam \Add5~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N14 +cycloneive_lcell_comb \Vout[10]~48 ( +// Equation(s): +// \Vout[10]~48_combout = (\Add5~53_combout & ((\Add7~17_combout & (\Vout[9]~47 & VCC)) # (!\Add7~17_combout & (!\Vout[9]~47 )))) # (!\Add5~53_combout & ((\Add7~17_combout & (!\Vout[9]~47 )) # (!\Add7~17_combout & ((\Vout[9]~47 ) # (GND))))) +// \Vout[10]~49 = CARRY((\Add5~53_combout & (!\Add7~17_combout & !\Vout[9]~47 )) # (!\Add5~53_combout & ((!\Vout[9]~47 ) # (!\Add7~17_combout )))) + + .dataa(\Add5~53_combout ), + .datab(\Add7~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[9]~47 ), + .combout(\Vout[10]~48_combout ), + .cout(\Vout[10]~49 )); +// synopsys translate_off +defparam \Vout[10]~48 .lut_mask = 16'h9617; +defparam \Vout[10]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N15 +dffeas \Vout[10]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[10]~48_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[10]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[10]~reg0 .is_wysiwyg = "true"; +defparam \Vout[10]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N22 +cycloneive_lcell_comb \Add5~53 ( +// Equation(s): +// \Add5~53_combout = (\Vout[13]~reg0_q & (!\Vout[10]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~51_combout ))) + + .dataa(gnd), + .datab(\Vout[10]~reg0_q ), + .datac(\Add5~51_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~53_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~53 .lut_mask = 16'h33F0; +defparam \Add5~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N16 +cycloneive_lcell_comb \Vout[11]~50 ( +// Equation(s): +// \Vout[11]~50_combout = ((\Add7~18_combout $ (\Add5~56_combout $ (!\Vout[10]~49 )))) # (GND) +// \Vout[11]~51 = CARRY((\Add7~18_combout & ((\Add5~56_combout ) # (!\Vout[10]~49 ))) # (!\Add7~18_combout & (\Add5~56_combout & !\Vout[10]~49 ))) + + .dataa(\Add7~18_combout ), + .datab(\Add5~56_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[10]~49 ), + .combout(\Vout[11]~50_combout ), + .cout(\Vout[11]~51 )); +// synopsys translate_off +defparam \Vout[11]~50 .lut_mask = 16'h698E; +defparam \Vout[11]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N17 +dffeas \Vout[11]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[11]~50_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[11]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[11]~reg0 .is_wysiwyg = "true"; +defparam \Vout[11]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N28 +cycloneive_lcell_comb \Add5~56 ( +// Equation(s): +// \Add5~56_combout = (\Vout[13]~reg0_q & (!\Vout[11]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~54_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[11]~reg0_q ), + .datad(\Add5~54_combout ), + .cin(gnd), + .combout(\Add5~56_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~56 .lut_mask = 16'h3F0C; +defparam \Add5~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N18 +cycloneive_lcell_comb \Vout[12]~52 ( +// Equation(s): +// \Vout[12]~52_combout = (\Add7~19_combout & ((\Add5~59_combout & (\Vout[11]~51 & VCC)) # (!\Add5~59_combout & (!\Vout[11]~51 )))) # (!\Add7~19_combout & ((\Add5~59_combout & (!\Vout[11]~51 )) # (!\Add5~59_combout & ((\Vout[11]~51 ) # (GND))))) +// \Vout[12]~53 = CARRY((\Add7~19_combout & (!\Add5~59_combout & !\Vout[11]~51 )) # (!\Add7~19_combout & ((!\Vout[11]~51 ) # (!\Add5~59_combout )))) + + .dataa(\Add7~19_combout ), + .datab(\Add5~59_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[11]~51 ), + .combout(\Vout[12]~52_combout ), + .cout(\Vout[12]~53 )); +// synopsys translate_off +defparam \Vout[12]~52 .lut_mask = 16'h9617; +defparam \Vout[12]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N19 +dffeas \Vout[12]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[12]~52_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[12]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[12]~reg0 .is_wysiwyg = "true"; +defparam \Vout[12]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N22 +cycloneive_lcell_comb \Add5~59 ( +// Equation(s): +// \Add5~59_combout = (\Vout[13]~reg0_q & (!\Vout[12]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~57_combout ))) + + .dataa(gnd), + .datab(\Vout[12]~reg0_q ), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~57_combout ), + .cin(gnd), + .combout(\Add5~59_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~59 .lut_mask = 16'h3F30; +defparam \Add5~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N20 +cycloneive_lcell_comb \Vout[13]~54 ( +// Equation(s): +// \Vout[13]~54_combout = \Add7~20_combout $ (\Vout[12]~53 $ (!\Add5~62_combout )) + + .dataa(gnd), + .datab(\Add7~20_combout ), + .datac(gnd), + .datad(\Add5~62_combout ), + .cin(\Vout[12]~53 ), + .combout(\Vout[13]~54_combout ), + .cout()); +// synopsys translate_off +defparam \Vout[13]~54 .lut_mask = 16'h3CC3; +defparam \Vout[13]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N21 +dffeas \Vout[13]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[13]~54_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[13]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[13]~reg0 .is_wysiwyg = "true"; +defparam \Vout[13]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N20 +cycloneive_lcell_comb \Add7~0 ( +// Equation(s): +// \Add7~0_combout = (\Vout[13]~reg0_q ) # (Kd_Out[7]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[7]), + .cin(gnd), + .combout(\Add7~0_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~0 .lut_mask = 16'hFFF0; +defparam \Add7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y18_N27 +dffeas \Vout[0]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[0]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[0]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[0]~reg0 .is_wysiwyg = "true"; +defparam \Vout[0]~reg0 .power_up = "low"; +// synopsys translate_on + +assign Vout[0] = \Vout[0]~output_o ; + +assign Vout[1] = \Vout[1]~output_o ; + +assign Vout[2] = \Vout[2]~output_o ; + +assign Vout[3] = \Vout[3]~output_o ; + +assign Vout[4] = \Vout[4]~output_o ; + +assign Vout[5] = \Vout[5]~output_o ; + +assign Vout[6] = \Vout[6]~output_o ; + +assign Vout[7] = \Vout[7]~output_o ; + +assign Vout[8] = \Vout[8]~output_o ; + +assign Vout[9] = \Vout[9]~output_o ; + +assign Vout[10] = \Vout[10]~output_o ; + +assign Vout[11] = \Vout[11]~output_o ; + +assign Vout[12] = \Vout[12]~output_o ; + +assign Vout[13] = \Vout[13]~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_DATA0~~ibuf_o ; + + +endmodule diff --git a/pid/simulation/modelsim/pid_8_1200mv_0c_v_slow.sdo b/pid/simulation/modelsim/pid_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..42b347d --- /dev/null +++ b/pid/simulation/modelsim/pid_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,6913 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "pid") + (DATE "12/04/2018 14:36:39") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2312:2312:2312) (2157:2157:2157)) + (IOPATH i o (2793:2793:2793) (2757:2757:2757)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1545:1545:1545) (1386:1386:1386)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2227:2227:2227) (1949:1949:1949)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1446:1446:1446) (1272:1272:1272)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1528:1528:1528) (1346:1346:1346)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1795:1795:1795) (1550:1550:1550)) + (IOPATH i o (2773:2773:2773) (2737:2737:2737)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1249:1249:1249) (1176:1176:1176)) + (IOPATH i o (2790:2790:2790) (2752:2752:2752)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1782:1782:1782) (1538:1538:1538)) + (IOPATH i o (2793:2793:2793) (2757:2757:2757)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1797:1797:1797) (1751:1751:1751)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1804:1804:1804) (1582:1582:1582)) + (IOPATH i o (2697:2697:2697) (2676:2676:2676)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1797:1797:1797) (1530:1530:1530)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1928:1928:1928) (1732:1732:1732)) + (IOPATH i o (2790:2790:2790) (2752:2752:2752)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2260:2260:2260) (2125:2125:2125)) + (IOPATH i o (2763:2763:2763) (2727:2727:2727)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1591:1591:1591) (1421:1421:1421)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (194:194:194) (190:190:190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (393:393:393)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (416:416:416)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~1) + (DELAY + (ABSOLUTE + (PORT datac (982:982:982) (927:927:927)) + (PORT datad (3272:3272:3272) (3316:3316:3316)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (707:707:707) (731:731:731)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~0) + (DELAY + (ABSOLUTE + (PORT datac (982:982:982) (927:927:927)) + (PORT datad (3610:3610:3610) (3692:3692:3692)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~2) + (DELAY + (ABSOLUTE + (PORT datac (3381:3381:3381) (3438:3438:3438)) + (PORT datad (777:777:777) (705:705:705)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (3685:3685:3685) (3653:3653:3653)) + (PORT datac (987:987:987) (932:932:932)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (747:747:747) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~6) + (DELAY + (ABSOLUTE + (PORT datac (3177:3177:3177) (3277:3277:3277)) + (PORT datad (776:776:776) (705:705:705)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~8) + (DELAY + (ABSOLUTE + (PORT datac (986:986:986) (931:931:931)) + (PORT datad (3185:3185:3185) (3256:3256:3256)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (767:767:767) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~10) + (DELAY + (ABSOLUTE + (PORT datac (986:986:986) (932:932:932)) + (PORT datad (2900:2900:2900) (3030:3030:3030)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~12) + (DELAY + (ABSOLUTE + (PORT datac (982:982:982) (928:928:928)) + (PORT datad (3205:3205:3205) (3258:3258:3258)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (707:707:707) (731:731:731)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (708:708:708) (733:733:733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (3465:3465:3465) (3509:3509:3509)) + (PORT datad (656:656:656) (644:644:644)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~16) + (DELAY + (ABSOLUTE + (PORT datac (983:983:983) (929:929:929)) + (PORT datad (3558:3558:3558) (3605:3605:3605)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (3359:3359:3359) (3422:3422:3422)) + (PORT datad (660:660:660) (648:648:648)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (747:747:747) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~20) + (DELAY + (ABSOLUTE + (PORT datac (3217:3217:3217) (3317:3317:3317)) + (PORT datad (668:668:668) (657:657:657)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~22) + (DELAY + (ABSOLUTE + (PORT datac (3205:3205:3205) (3278:3278:3278)) + (PORT datad (663:663:663) (651:651:651)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (738:738:738) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~24) + (DELAY + (ABSOLUTE + (PORT datac (3408:3408:3408) (3492:3492:3492)) + (PORT datad (669:669:669) (658:658:658)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (758:758:758) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (758:758:758) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~26) + (DELAY + (ABSOLUTE + (PORT datac (1560:1560:1560) (1828:1828:1828)) + (PORT datad (664:664:664) (653:653:653)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (566:566:566) (560:560:560)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (430:430:430)) + (PORT datab (539:539:539) (448:448:448)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (458:458:458)) + (PORT datab (485:485:485) (426:426:426)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (758:758:758) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (194:194:194) (190:190:190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (548:548:548) (523:523:523)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~3) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (471:471:471)) + (PORT datab (570:570:570) (484:484:484)) + (PORT datac (714:714:714) (582:582:582)) + (PORT datad (260:260:260) (272:272:272)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1441:1441:1441) (1483:1483:1483)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1506:1506:1506) (1433:1433:1433)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1442:1442:1442) (1484:1484:1484)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1507:1507:1507) (1434:1434:1434)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1442:1442:1442) (1484:1484:1484)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1507:1507:1507) (1434:1434:1434)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (PORT datac (561:561:561) (533:533:533)) + (PORT datad (516:516:516) (500:500:500)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~2) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (465:465:465)) + (PORT datab (304:304:304) (317:317:317)) + (PORT datac (271:271:271) (295:295:295)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1442:1442:1442) (1484:1484:1484)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1507:1507:1507) (1434:1434:1434)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (389:389:389)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1442:1442:1442) (1484:1484:1484)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1507:1507:1507) (1434:1434:1434)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1442:1442:1442) (1484:1484:1484)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1507:1507:1507) (1434:1434:1434)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~0) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (329:329:329)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (482:482:482) (426:426:426)) + (PORT datad (270:270:270) (285:285:285)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1442:1442:1442) (1484:1484:1484)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1507:1507:1507) (1434:1434:1434)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (385:385:385)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1442:1442:1442) (1484:1484:1484)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1507:1507:1507) (1434:1434:1434)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (391:391:391)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1442:1442:1442) (1484:1484:1484)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1507:1507:1507) (1434:1434:1434)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~20) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (355:355:355)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1442:1442:1442) (1484:1484:1484)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1507:1507:1507) (1434:1434:1434)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (541:541:541)) + (PORT datab (327:327:327) (384:384:384)) + (PORT datac (285:285:285) (352:352:352)) + (PORT datad (284:284:284) (342:342:342)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~1) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (329:329:329)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (482:482:482) (426:426:426)) + (PORT datad (270:270:270) (286:286:286)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1442:1442:1442) (1484:1484:1484)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1507:1507:1507) (1434:1434:1434)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (397:397:397)) + (PORT datab (325:325:325) (382:382:382)) + (PORT datac (284:284:284) (350:350:350)) + (PORT datad (286:286:286) (345:345:345)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (470:470:470)) + (PORT datab (301:301:301) (312:312:312)) + (PORT datad (511:511:511) (444:444:444)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Clk_Ctrl) + (DELAY + (ABSOLUTE + (PORT clk (1441:1441:1441) (1483:1483:1483)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1506:1506:1506) (1433:1433:1433)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[1\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~25) + (DELAY + (ABSOLUTE + (PORT datab (3243:3243:3243) (3275:3275:3275)) + (PORT datac (748:748:748) (673:673:673)) + (PORT datad (665:665:665) (654:654:654)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (538:538:538) (447:447:447)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[2\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~23) + (DELAY + (ABSOLUTE + (PORT datab (3220:3220:3220) (3313:3313:3313)) + (PORT datad (301:301:301) (356:356:356)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (430:430:430)) + (PORT datab (482:482:482) (420:420:420)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[3\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (523:523:523)) + (PORT datac (3257:3257:3257) (3419:3419:3419)) + (PORT datad (653:653:653) (640:640:640)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (724:724:724)) + (PORT datab (479:479:479) (417:417:417)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[4\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (2913:2913:2913) (3048:3048:3048)) + (PORT datac (986:986:986) (932:932:932)) + (PORT datad (834:834:834) (777:777:777)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[5\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (757:757:757)) + (PORT datab (536:536:536) (444:444:444)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[5\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (551:551:551)) + (PORT datac (3147:3147:3147) (3238:3238:3238)) + (PORT datad (659:659:659) (647:647:647)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (425:425:425)) + (PORT datab (537:537:537) (444:444:444)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[6\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~15) + (DELAY + (ABSOLUTE + (PORT datab (703:703:703) (693:693:693)) + (PORT datac (3678:3678:3678) (3739:3739:3739)) + (PORT datad (821:821:821) (722:722:722)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[7\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (717:717:717)) + (PORT datab (536:536:536) (443:443:443)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[7\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~13) + (DELAY + (ABSOLUTE + (PORT datab (3684:3684:3684) (3760:3760:3760)) + (PORT datac (494:494:494) (481:481:481)) + (PORT datad (655:655:655) (643:643:643)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[8\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (459:459:459)) + (PORT datab (820:820:820) (709:709:709)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[8\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~11) + (DELAY + (ABSOLUTE + (PORT datab (697:697:697) (687:687:687)) + (PORT datac (3103:3103:3103) (3202:3202:3202)) + (PORT datad (487:487:487) (471:471:471)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[9\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (739:739:739)) + (PORT datab (539:539:539) (449:449:449)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[9\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~9) + (DELAY + (ABSOLUTE + (PORT datab (712:712:712) (703:703:703)) + (PORT datac (3254:3254:3254) (3261:3261:3261)) + (PORT datad (523:523:523) (496:496:496)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[10\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (813:813:813) (652:652:652)) + (PORT datab (754:754:754) (612:612:612)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~7) + (DELAY + (ABSOLUTE + (PORT datab (699:699:699) (689:689:689)) + (PORT datac (3497:3497:3497) (3559:3559:3559)) + (PORT datad (489:489:489) (473:473:473)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[11\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (748:748:748)) + (PORT datab (796:796:796) (630:630:630)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[11\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (3598:3598:3598) (3607:3607:3607)) + (PORT datac (571:571:571) (555:555:555)) + (PORT datad (907:907:907) (822:822:822)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[12\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (660:660:660)) + (PORT datab (543:543:543) (454:454:454)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[12\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~3) + (DELAY + (ABSOLUTE + (PORT datab (3278:3278:3278) (3317:3317:3317)) + (PORT datac (748:748:748) (678:678:678)) + (PORT datad (672:672:672) (661:661:661)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[13\]\~42) + (DELAY + (ABSOLUTE + (PORT datab (1229:1229:1229) (1035:1035:1035)) + (PORT datad (803:803:803) (682:682:682)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[13\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT asdata (871:871:871) (806:806:806)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (547:547:547)) + (PORT datac (3593:3593:3593) (3654:3654:3654)) + (PORT datad (670:670:670) (659:659:659)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[0\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1451:1451:1451) (1494:1494:1494)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1517:1517:1517) (1443:1443:1443)) + (PORT ena (2375:2375:2375) (2165:2165:2165)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (416:416:416)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1605:1605:1605) (1489:1489:1489)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (424:424:424)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1545:1545:1545) (1415:1415:1415)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (417:417:417)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (2197:2197:2197) (1966:1966:1966)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (425:425:425)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1892:1892:1892) (1687:1687:1687)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (425:425:425)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1569:1569:1569) (1421:1421:1421)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[6\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (363:363:363) (418:418:418)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1303:1303:1303) (1226:1226:1226)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[7\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (363:363:363) (418:418:418)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1346:1346:1346) (1256:1256:1256)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[8\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1986:1986:1986) (1783:1783:1783)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (363:363:363) (418:418:418)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (2211:2211:2211) (1933:1933:1933)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (425:425:425)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1971:1971:1971) (1724:1724:1724)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (363:363:363) (418:418:418)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1901:1901:1901) (1708:1708:1708)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[12\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1610:1610:1610) (1452:1452:1452)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[13\]\~40) + (DELAY + (ABSOLUTE + (PORT datad (307:307:307) (366:366:366)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1004:1004:1004) (987:987:987)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1299:1299:1299) (1229:1229:1229)) + (PORT clrn (1514:1514:1514) (1440:1440:1440)) + (PORT sload (1095:1095:1095) (1091:1091:1091)) + (PORT ena (1931:1931:1931) (1771:1771:1771)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1356:1356:1356) (1284:1284:1284)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1864:1864:1864) (1650:1650:1650)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1353:1353:1353) (1280:1280:1280)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1376:1376:1376) (1301:1301:1301)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1358:1358:1358) (1296:1296:1296)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[6\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1406:1406:1406) (1323:1323:1323)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[7\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1950:1950:1950) (1726:1726:1726)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[8\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1919:1919:1919) (1727:1727:1727)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1351:1351:1351) (1282:1282:1282)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1644:1644:1644) (1490:1490:1490)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1882:1882:1882) (1667:1667:1667)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[12\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (317:317:317) (371:371:371)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1591:1591:1591) (1447:1447:1447)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[13\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (416:416:416)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1380:1380:1380) (1296:1296:1296)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1439:1439:1439) (1480:1480:1480)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1618:1618:1618) (1465:1465:1465)) + (PORT clrn (1503:1503:1503) (1431:1431:1431)) + (PORT sload (1107:1107:1107) (1100:1100:1100)) + (PORT ena (1917:1917:1917) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (718:718:718) (743:743:743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (718:718:718) (743:743:743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult2\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT dataa[6] (543:543:543) (529:529:529)) + (PORT dataa[7] (505:505:505) (492:492:492)) + (PORT dataa[8] (535:535:535) (517:517:517)) + (PORT dataa[9] (511:511:511) (499:499:499)) + (PORT dataa[10] (788:788:788) (695:695:695)) + (PORT dataa[11] (504:504:504) (490:490:490)) + (PORT dataa[12] (507:507:507) (498:498:498)) + (PORT dataa[13] (780:780:780) (685:685:685)) + (PORT dataa[14] (788:788:788) (709:709:709)) + (PORT dataa[15] (508:508:508) (500:500:500)) + (PORT dataa[16] (782:782:782) (688:688:688)) + (PORT dataa[17] (532:532:532) (517:517:517)) + (PORT datab[10] (3257:3257:3257) (3399:3399:3399)) + (PORT datab[11] (3570:3570:3570) (3608:3608:3608)) + (PORT datab[12] (3325:3325:3325) (3410:3410:3410)) + (PORT datab[13] (3549:3549:3549) (3623:3623:3623)) + (PORT datab[14] (3594:3594:3594) (3604:3604:3604)) + (PORT datab[15] (3478:3478:3478) (3528:3528:3528)) + (PORT datab[16] (3478:3478:3478) (3548:3548:3548)) + (PORT datab[17] (3504:3504:3504) (3599:3599:3599)) + (IOPATH dataa dataout (3554:3554:3554) (3554:3554:3554)) + (IOPATH datab dataout (3476:3476:3476) (3476:3476:3476)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult2\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (124:124:124) (132:132:132)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1464:1464:1464) (1247:1247:1247)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1142:1142:1142) (1005:1005:1005)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1150:1150:1150) (1013:1013:1013)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1135:1135:1135) (1010:1010:1010)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1184:1184:1184) (1033:1033:1033)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1160:1160:1160) (1023:1023:1023)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1231:1231:1231) (1071:1071:1071)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (400:400:400)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1217:1217:1217) (1061:1061:1061)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (392:392:392)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1216:1216:1216) (1060:1060:1060)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (399:399:399)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1190:1190:1190) (1048:1048:1048)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (392:392:392)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1861:1861:1861)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1505:1505:1505) (1319:1319:1319)) + (PORT clrn (1499:1499:1499) (1429:1429:1429)) + (PORT sload (1433:1433:1433) (1578:1578:1578)) + (PORT ena (2021:2021:2021) (1828:1828:1828)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (955:955:955) (863:863:863)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (792:792:792) (669:669:669)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1168:1168:1168) (1018:1018:1018)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1861:1861:1861)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1255:1255:1255) (1115:1115:1115)) + (PORT clrn (1499:1499:1499) (1429:1429:1429)) + (PORT sload (1433:1433:1433) (1578:1578:1578)) + (PORT ena (2021:2021:2021) (1828:1828:1828)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1861:1861:1861)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1213:1213:1213) (1097:1097:1097)) + (PORT clrn (1499:1499:1499) (1429:1429:1429)) + (PORT sload (1433:1433:1433) (1578:1578:1578)) + (PORT ena (2021:2021:2021) (1828:1828:1828)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (869:869:869) (816:816:816)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (769:769:769) (658:658:658)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1437:1437:1437) (1226:1226:1226)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (855:855:855)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (802:802:802) (679:679:679)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (870:870:870) (789:789:789)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (401:401:401)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1868:1868:1868) (1861:1861:1861)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1162:1162:1162) (1057:1057:1057)) + (PORT clrn (1499:1499:1499) (1429:1429:1429)) + (PORT sload (1433:1433:1433) (1578:1578:1578)) + (PORT ena (2021:2021:2021) (1828:1828:1828)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (856:856:856)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[17\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (765:765:765) (658:658:658)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1523:1523:1523) (1285:1285:1285)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (918:918:918) (834:834:834)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[18\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (813:813:813) (691:691:691)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1179:1179:1179) (1033:1033:1033)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (918:918:918) (857:857:857)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[19\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (845:845:845) (708:708:708)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1850:1850:1850)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1473:1473:1473) (1245:1245:1245)) + (PORT clrn (1498:1498:1498) (1428:1428:1428)) + (PORT sload (1787:1787:1787) (1990:1990:1990)) + (PORT ena (1933:1933:1933) (1749:1749:1749)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (356:356:356)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1437:1437:1437) (1476:1476:1476)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1290:1290:1290) (1169:1169:1169)) + (PORT clrn (1499:1499:1499) (1429:1429:1429)) + (PORT sload (1433:1433:1433) (1578:1578:1578)) + (PORT ena (1962:1962:1962) (1774:1774:1774)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~20) + (DELAY + (ABSOLUTE + (PORT datac (509:509:509) (506:506:506)) + (PORT datad (1320:1320:1320) (1329:1329:1329)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (738:738:738) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult1\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT dataa[6] (539:539:539) (528:528:528)) + (PORT dataa[7] (561:561:561) (544:544:544)) + (PORT dataa[8] (790:790:790) (708:708:708)) + (PORT dataa[9] (567:567:567) (552:552:552)) + (PORT dataa[10] (831:831:831) (748:748:748)) + (PORT dataa[11] (558:558:558) (540:540:540)) + (PORT dataa[12] (534:534:534) (521:521:521)) + (PORT dataa[13] (803:803:803) (706:706:706)) + (PORT dataa[14] (542:542:542) (536:536:536)) + (PORT dataa[15] (534:534:534) (525:525:525)) + (PORT dataa[16] (805:805:805) (709:709:709)) + (PORT dataa[17] (556:556:556) (540:540:540)) + (PORT datab[10] (3304:3304:3304) (3335:3335:3335)) + (PORT datab[11] (3603:3603:3603) (3655:3655:3655)) + (PORT datab[12] (3694:3694:3694) (3809:3809:3809)) + (PORT datab[13] (3589:3589:3589) (3702:3702:3702)) + (PORT datab[14] (3627:3627:3627) (3635:3635:3635)) + (PORT datab[15] (3733:3733:3733) (3769:3769:3769)) + (PORT datab[16] (3314:3314:3314) (3369:3369:3369)) + (PORT datab[17] (3222:3222:3222) (3323:3323:3323)) + (IOPATH dataa dataout (3554:3554:3554) (3554:3554:3554)) + (IOPATH datab dataout (3476:3476:3476) (3476:3476:3476)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult1\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (124:124:124) (132:132:132)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1879:1879:1879) (1873:1873:1873)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1460:1460:1460) (1280:1280:1280)) + (PORT clrn (1513:1513:1513) (1440:1440:1440)) + (PORT sload (2122:2122:2122) (2359:2359:2359)) + (PORT ena (2259:2259:2259) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (395:395:395)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1879:1879:1879) (1873:1873:1873)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1558:1558:1558) (1357:1357:1357)) + (PORT clrn (1513:1513:1513) (1440:1440:1440)) + (PORT sload (2122:2122:2122) (2359:2359:2359)) + (PORT ena (2259:2259:2259) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (395:395:395)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1879:1879:1879) (1873:1873:1873)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1537:1537:1537) (1341:1341:1341)) + (PORT clrn (1513:1513:1513) (1440:1440:1440)) + (PORT sload (2122:2122:2122) (2359:2359:2359)) + (PORT ena (2259:2259:2259) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1879:1879:1879) (1873:1873:1873)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1550:1550:1550) (1348:1348:1348)) + (PORT clrn (1513:1513:1513) (1440:1440:1440)) + (PORT sload (2122:2122:2122) (2359:2359:2359)) + (PORT ena (2259:2259:2259) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1879:1879:1879) (1873:1873:1873)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1506:1506:1506) (1313:1313:1313)) + (PORT clrn (1513:1513:1513) (1440:1440:1440)) + (PORT sload (2122:2122:2122) (2359:2359:2359)) + (PORT ena (2259:2259:2259) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (401:401:401)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1879:1879:1879) (1873:1873:1873)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1487:1487:1487) (1305:1305:1305)) + (PORT clrn (1513:1513:1513) (1440:1440:1440)) + (PORT sload (2122:2122:2122) (2359:2359:2359)) + (PORT ena (2259:2259:2259) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1879:1879:1879) (1873:1873:1873)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1485:1485:1485) (1315:1315:1315)) + (PORT clrn (1513:1513:1513) (1440:1440:1440)) + (PORT sload (2122:2122:2122) (2359:2359:2359)) + (PORT ena (2259:2259:2259) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1879:1879:1879) (1873:1873:1873)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1508:1508:1508) (1308:1308:1308)) + (PORT clrn (1513:1513:1513) (1440:1440:1440)) + (PORT sload (2122:2122:2122) (2359:2359:2359)) + (PORT ena (2259:2259:2259) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1879:1879:1879) (1873:1873:1873)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1566:1566:1566) (1362:1362:1362)) + (PORT clrn (1513:1513:1513) (1440:1440:1440)) + (PORT sload (2122:2122:2122) (2359:2359:2359)) + (PORT ena (2259:2259:2259) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (400:400:400)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1879:1879:1879) (1873:1873:1873)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1593:1593:1593) (1382:1382:1382)) + (PORT clrn (1513:1513:1513) (1440:1440:1440)) + (PORT sload (2122:2122:2122) (2359:2359:2359)) + (PORT ena (2259:2259:2259) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1859:1859:1859)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1485:1485:1485) (1259:1259:1259)) + (PORT clrn (1511:1511:1511) (1435:1435:1435)) + (PORT sload (2138:2138:2138) (2385:2385:2385)) + (PORT ena (2292:2292:2292) (2068:2068:2068)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1859:1859:1859)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (870:870:870) (789:789:789)) + (PORT clrn (1511:1511:1511) (1435:1435:1435)) + (PORT sload (2138:2138:2138) (2385:2385:2385)) + (PORT ena (2292:2292:2292) (2068:2068:2068)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1859:1859:1859)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1127:1127:1127) (993:993:993)) + (PORT clrn (1511:1511:1511) (1435:1435:1435)) + (PORT sload (2138:2138:2138) (2385:2385:2385)) + (PORT ena (2292:2292:2292) (2068:2068:2068)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1859:1859:1859)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (869:869:869) (787:787:787)) + (PORT clrn (1511:1511:1511) (1435:1435:1435)) + (PORT sload (2138:2138:2138) (2385:2385:2385)) + (PORT ena (2292:2292:2292) (2068:2068:2068)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1859:1859:1859)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1134:1134:1134) (998:998:998)) + (PORT clrn (1511:1511:1511) (1435:1435:1435)) + (PORT sload (2138:2138:2138) (2385:2385:2385)) + (PORT ena (2292:2292:2292) (2068:2068:2068)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1859:1859:1859)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (869:869:869) (788:788:788)) + (PORT clrn (1511:1511:1511) (1435:1435:1435)) + (PORT sload (2138:2138:2138) (2385:2385:2385)) + (PORT ena (2292:2292:2292) (2068:2068:2068)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1859:1859:1859)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (871:871:871) (790:790:790)) + (PORT clrn (1511:1511:1511) (1435:1435:1435)) + (PORT sload (2138:2138:2138) (2385:2385:2385)) + (PORT ena (2292:2292:2292) (2068:2068:2068)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1859:1859:1859)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1129:1129:1129) (994:994:994)) + (PORT clrn (1511:1511:1511) (1435:1435:1435)) + (PORT sload (2138:2138:2138) (2385:2385:2385)) + (PORT ena (2292:2292:2292) (2068:2068:2068)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1859:1859:1859)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1176:1176:1176) (1029:1029:1029)) + (PORT clrn (1511:1511:1511) (1435:1435:1435)) + (PORT sload (2138:2138:2138) (2385:2385:2385)) + (PORT ena (2292:2292:2292) (2068:2068:2068)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1867:1867:1867) (1859:1859:1859)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (869:869:869) (787:787:787)) + (PORT clrn (1511:1511:1511) (1435:1435:1435)) + (PORT sload (2138:2138:2138) (2385:2385:2385)) + (PORT ena (2292:2292:2292) (2068:2068:2068)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (356:356:356)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1443:1443:1443) (1488:1488:1488)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (674:674:674) (688:688:688)) + (PORT clrn (1511:1511:1511) (1435:1435:1435)) + (PORT sload (2138:2138:2138) (2385:2385:2385)) + (PORT ena (2206:2206:2206) (1975:1975:1975)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (707:707:707) (731:731:731)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_data_reg") + (INSTANCE Mult0\|auto_generated\|mac_mult1.dataa_reg) + (DELAY + (ABSOLUTE + (PORT data[0] (229:229:229) (252:252:252)) + (PORT data[1] (229:229:229) (252:252:252)) + (PORT data[2] (229:229:229) (252:252:252)) + (PORT data[3] (229:229:229) (252:252:252)) + (PORT data[4] (664:664:664) (630:630:630)) + (PORT data[5] (929:929:929) (823:823:823)) + (PORT data[6] (667:667:667) (633:633:633)) + (PORT data[7] (990:990:990) (884:884:884)) + (PORT data[8] (658:658:658) (622:622:622)) + (PORT data[9] (700:700:700) (665:665:665)) + (PORT data[10] (931:931:931) (825:825:825)) + (PORT data[11] (656:656:656) (618:618:618)) + (PORT data[12] (696:696:696) (659:659:659)) + (PORT data[13] (657:657:657) (619:619:619)) + (PORT data[14] (657:657:657) (620:620:620)) + (PORT data[15] (697:697:697) (660:660:660)) + (PORT data[16] (936:936:936) (819:819:819)) + (PORT data[17] (661:661:661) (627:627:627)) + (PORT clk (1317:1317:1317) (1407:1407:1407)) + (PORT ena (2248:2248:2248) (2029:2029:2029)) + (PORT aclr (1472:1472:1472) (1503:1503:1503)) + (IOPATH (posedge aclr) dataout (246:246:246) (246:246:246)) + (IOPATH (posedge clk) dataout (318:318:318) (318:318:318)) + ) + ) + (TIMINGCHECK + (SETUP data (posedge clk) (211:211:211)) + (SETUP ena (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult0\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT datab[10] (3345:3345:3345) (3407:3407:3407)) + (PORT datab[11] (3734:3734:3734) (3836:3836:3836)) + (PORT datab[12] (3293:3293:3293) (3449:3449:3449)) + (PORT datab[13] (3296:3296:3296) (3375:3375:3375)) + (PORT datab[14] (3098:3098:3098) (3211:3211:3211)) + (PORT datab[15] (3319:3319:3319) (3449:3449:3449)) + (PORT datab[16] (3592:3592:3592) (3630:3630:3630)) + (PORT datab[17] (3230:3230:3230) (3371:3371:3371)) + (IOPATH dataa dataout (3302:3302:3302) (3302:3302:3302)) + (IOPATH datab dataout (3476:3476:3476) (3476:3476:3476)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult0\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (124:124:124) (132:132:132)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1434:1434:1434) (1473:1473:1473)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1560:1560:1560) (1353:1353:1353)) + (PORT clrn (1496:1496:1496) (1426:1426:1426)) + (PORT sload (1752:1752:1752) (1951:1951:1951)) + (PORT ena (2342:2342:2342) (2120:2120:2120)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (395:395:395)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1434:1434:1434) (1473:1473:1473)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1571:1571:1571) (1365:1365:1365)) + (PORT clrn (1496:1496:1496) (1426:1426:1426)) + (PORT sload (1752:1752:1752) (1951:1951:1951)) + (PORT ena (2342:2342:2342) (2120:2120:2120)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (395:395:395)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1434:1434:1434) (1473:1473:1473)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1552:1552:1552) (1354:1354:1354)) + (PORT clrn (1496:1496:1496) (1426:1426:1426)) + (PORT sload (1752:1752:1752) (1951:1951:1951)) + (PORT ena (2342:2342:2342) (2120:2120:2120)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1434:1434:1434) (1473:1473:1473)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1610:1610:1610) (1395:1395:1395)) + (PORT clrn (1496:1496:1496) (1426:1426:1426)) + (PORT sload (1752:1752:1752) (1951:1951:1951)) + (PORT ena (2342:2342:2342) (2120:2120:2120)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1434:1434:1434) (1473:1473:1473)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1565:1565:1565) (1360:1360:1360)) + (PORT clrn (1496:1496:1496) (1426:1426:1426)) + (PORT sload (1752:1752:1752) (1951:1951:1951)) + (PORT ena (2342:2342:2342) (2120:2120:2120)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (401:401:401)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1434:1434:1434) (1473:1473:1473)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1525:1525:1525) (1335:1335:1335)) + (PORT clrn (1496:1496:1496) (1426:1426:1426)) + (PORT sload (1752:1752:1752) (1951:1951:1951)) + (PORT ena (2342:2342:2342) (2120:2120:2120)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1434:1434:1434) (1473:1473:1473)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1512:1512:1512) (1322:1322:1322)) + (PORT clrn (1496:1496:1496) (1426:1426:1426)) + (PORT sload (1752:1752:1752) (1951:1951:1951)) + (PORT ena (2342:2342:2342) (2120:2120:2120)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1434:1434:1434) (1473:1473:1473)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1826:1826:1826) (1542:1542:1542)) + (PORT clrn (1496:1496:1496) (1426:1426:1426)) + (PORT sload (1752:1752:1752) (1951:1951:1951)) + (PORT ena (2342:2342:2342) (2120:2120:2120)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1434:1434:1434) (1473:1473:1473)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1582:1582:1582) (1375:1375:1375)) + (PORT clrn (1496:1496:1496) (1426:1426:1426)) + (PORT sload (1752:1752:1752) (1951:1951:1951)) + (PORT ena (2342:2342:2342) (2120:2120:2120)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (400:400:400)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1434:1434:1434) (1473:1473:1473)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1489:1489:1489) (1311:1311:1311)) + (PORT clrn (1496:1496:1496) (1426:1426:1426)) + (PORT sload (1752:1752:1752) (1951:1951:1951)) + (PORT ena (2342:2342:2342) (2120:2120:2120)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1436:1436:1436) (1474:1474:1474)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1502:1502:1502) (1322:1322:1322)) + (PORT clrn (1497:1497:1497) (1428:1428:1428)) + (PORT sload (1800:1800:1800) (2007:2007:2007)) + (PORT ena (2259:2259:2259) (2055:2055:2055)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1436:1436:1436) (1474:1474:1474)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1741:1741:1741) (1478:1478:1478)) + (PORT clrn (1497:1497:1497) (1428:1428:1428)) + (PORT sload (1800:1800:1800) (2007:2007:2007)) + (PORT ena (2259:2259:2259) (2055:2055:2055)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1436:1436:1436) (1474:1474:1474)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1164:1164:1164) (1061:1061:1061)) + (PORT clrn (1497:1497:1497) (1428:1428:1428)) + (PORT sload (1800:1800:1800) (2007:2007:2007)) + (PORT ena (2259:2259:2259) (2055:2055:2055)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1436:1436:1436) (1474:1474:1474)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1204:1204:1204) (1078:1078:1078)) + (PORT clrn (1497:1497:1497) (1428:1428:1428)) + (PORT sload (1800:1800:1800) (2007:2007:2007)) + (PORT ena (2259:2259:2259) (2055:2055:2055)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1436:1436:1436) (1474:1474:1474)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1474:1474:1474) (1299:1299:1299)) + (PORT clrn (1497:1497:1497) (1428:1428:1428)) + (PORT sload (1800:1800:1800) (2007:2007:2007)) + (PORT ena (2259:2259:2259) (2055:2055:2055)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1436:1436:1436) (1474:1474:1474)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1223:1223:1223) (1096:1096:1096)) + (PORT clrn (1497:1497:1497) (1428:1428:1428)) + (PORT sload (1800:1800:1800) (2007:2007:2007)) + (PORT ena (2259:2259:2259) (2055:2055:2055)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1436:1436:1436) (1474:1474:1474)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1527:1527:1527) (1328:1328:1328)) + (PORT clrn (1497:1497:1497) (1428:1428:1428)) + (PORT sload (1800:1800:1800) (2007:2007:2007)) + (PORT ena (2259:2259:2259) (2055:2055:2055)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1436:1436:1436) (1474:1474:1474)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1219:1219:1219) (1093:1093:1093)) + (PORT clrn (1497:1497:1497) (1428:1428:1428)) + (PORT sload (1800:1800:1800) (2007:2007:2007)) + (PORT ena (2259:2259:2259) (2055:2055:2055)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1436:1436:1436) (1474:1474:1474)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1840:1840:1840) (1607:1607:1607)) + (PORT clrn (1497:1497:1497) (1428:1428:1428)) + (PORT sload (1800:1800:1800) (2007:2007:2007)) + (PORT ena (2259:2259:2259) (2055:2055:2055)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1436:1436:1436) (1474:1474:1474)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1482:1482:1482) (1307:1307:1307)) + (PORT clrn (1497:1497:1497) (1428:1428:1428)) + (PORT sload (1800:1800:1800) (2007:2007:2007)) + (PORT ena (2259:2259:2259) (2055:2055:2055)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (356:356:356)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1436:1436:1436) (1474:1474:1474)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1544:1544:1544) (1348:1348:1348)) + (PORT clrn (1497:1497:1497) (1428:1428:1428)) + (PORT sload (1800:1800:1800) (2007:2007:2007)) + (PORT ena (2259:2259:2259) (2055:2055:2055)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (842:842:842)) + (PORT datab (863:863:863) (777:777:777)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (841:841:841)) + (PORT datab (944:944:944) (853:853:853)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~4) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (842:842:842)) + (PORT datab (549:549:549) (537:537:537)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1130:1130:1130)) + (PORT datab (607:607:607) (564:564:564)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~8) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (545:545:545)) + (PORT datab (952:952:952) (864:864:864)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~10) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (782:782:782)) + (PORT datab (952:952:952) (863:863:863)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~12) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (783:783:783)) + (PORT datab (1312:1312:1312) (1143:1143:1143)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout 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"cycloneive_lcell_comb") + (INSTANCE Add7\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1206:1206:1206)) + (PORT datad (885:885:885) (815:815:815)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~5) + (DELAY + (ABSOLUTE + (PORT datac (1245:1245:1245) (1125:1125:1125)) + (PORT datad (966:966:966) (912:912:912)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~21) + (DELAY + (ABSOLUTE + (PORT datac (1271:1271:1271) (1170:1170:1170)) + (PORT datad (508:508:508) (471:471:471)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~6) + (DELAY + (ABSOLUTE + (PORT datac (1149:1149:1149) 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(283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (281:281:281)) + (PORT datab (1273:1273:1273) (1188:1188:1188)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (527:527:527)) + (PORT datab (607:607:607) (548:548:548)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (411:411:411)) + (PORT datab (268:268:268) (275:275:275)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (534:534:534)) + (PORT datab (808:808:808) (677:677:677)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (558:558:558)) + (PORT datab (268:268:268) (275:275:275)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (411:411:411)) + (PORT datab (550:550:550) (519:519:519)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (789:789:789)) + (PORT datab (609:609:609) (550:550:550)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1269:1269:1269) (1119:1119:1119)) + (PORT datab (269:269:269) (276:276:276)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (445:445:445)) + (PORT datab (269:269:269) (277:277:277)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[1\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1468:1468:1468) (1508:1508:1508)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1531:1531:1531) (1460:1460:1460)) + (PORT ena (2295:2295:2295) (2084:2084:2084)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~26) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (397:397:397)) + (PORT datac (1271:1271:1271) (1170:1170:1170)) + (PORT datad (512:512:512) (481:481:481)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (1348:1348:1348) (1223:1223:1223)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[2\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1468:1468:1468) (1508:1508:1508)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1531:1531:1531) (1460:1460:1460)) + (PORT ena (2295:2295:2295) (2084:2084:2084)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~29) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (404:404:404)) + (PORT datab (1316:1316:1316) (1205:1205:1205)) + (PORT datac (556:556:556) (511:511:511)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (1266:1266:1266) (1098:1098:1098)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[3\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1937:1937:1937) (1935:1935:1935)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1528:1528:1528) (1457:1457:1457)) + (PORT ena (2267:2267:2267) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~32) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (461:461:461)) + (PORT datac (558:558:558) (517:517:517)) + (PORT datad (301:301:301) (357:357:357)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[4\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (556:556:556)) + (PORT datab (533:533:533) (439:439:439)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[4\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1465:1465:1465) (1505:1505:1505)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1528:1528:1528) (1457:1457:1457)) + (PORT ena (2691:2691:2691) (2437:2437:2437)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~35) + (DELAY + (ABSOLUTE + (PORT datab (737:737:737) (740:740:740)) + (PORT datac (839:839:839) (776:776:776)) + (PORT datad (230:230:230) (237:237:237)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[5\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (481:481:481) (411:411:411)) + (PORT datab (269:269:269) (276:276:276)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[5\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1465:1465:1465) (1505:1505:1505)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1528:1528:1528) (1457:1457:1457)) + (PORT ena (2691:2691:2691) (2437:2437:2437)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~38) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (461:461:461)) + (PORT datac (299:299:299) (363:363:363)) + (PORT datad (550:550:550) (510:510:510)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[6\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1219:1219:1219) (1173:1173:1173)) + (PORT datab (606:606:606) (539:539:539)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[6\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1937:1937:1937) (1935:1935:1935)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1528:1528:1528) (1457:1457:1457)) + (PORT ena (2267:2267:2267) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~41) + (DELAY + (ABSOLUTE + (PORT datab (737:737:737) (740:740:740)) + (PORT datac (562:562:562) (578:578:578)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[7\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (469:469:469) (400:400:400)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[7\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1937:1937:1937) (1935:1935:1935)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1528:1528:1528) (1457:1457:1457)) + (PORT ena (2267:2267:2267) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~44) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (398:398:398)) + (PORT datac (556:556:556) (514:514:514)) + (PORT datad (355:355:355) (424:424:424)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[8\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (443:443:443)) + (PORT datab (945:945:945) (805:805:805)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[8\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1937:1937:1937) (1935:1935:1935)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1528:1528:1528) (1457:1457:1457)) + (PORT ena (2267:2267:2267) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~47) + (DELAY + (ABSOLUTE + (PORT dataa (661:661:661) (652:652:652)) + (PORT datab (737:737:737) (740:740:740)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[9\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1162:1162:1162)) + (PORT datab (267:267:267) (274:274:274)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[9\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1937:1937:1937) (1935:1935:1935)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1528:1528:1528) (1457:1457:1457)) + (PORT ena (2267:2267:2267) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~50) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (462:462:462)) + (PORT datac (555:555:555) (512:512:512)) + (PORT datad (300:300:300) (355:355:355)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[10\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (281:281:281)) + (PORT datab (1213:1213:1213) (1162:1162:1162)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[10\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1937:1937:1937) (1935:1935:1935)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1528:1528:1528) (1457:1457:1457)) + (PORT ena (2267:2267:2267) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~53) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (PORT datac (554:554:554) (510:510:510)) + (PORT datad (355:355:355) (424:424:424)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[11\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (445:445:445)) + (PORT datab (547:547:547) (514:514:514)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[11\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1937:1937:1937) (1935:1935:1935)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1528:1528:1528) (1457:1457:1457)) + (PORT ena (2267:2267:2267) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~56) + (DELAY + (ABSOLUTE + (PORT datab (737:737:737) (740:740:740)) + (PORT datac (570:570:570) (586:586:586)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[12\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (437:437:437)) + (PORT datab (603:603:603) (538:538:538)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[12\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1937:1937:1937) (1935:1935:1935)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1528:1528:1528) (1457:1457:1457)) + (PORT ena (2267:2267:2267) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~59) + (DELAY + (ABSOLUTE + (PORT datab (597:597:597) (615:615:615)) + (PORT datac (893:893:893) (837:837:837)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[13\]\~54) + (DELAY + (ABSOLUTE + (PORT datab (1304:1304:1304) (1119:1119:1119)) + (PORT datad (463:463:463) (383:383:383)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[13\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1937:1937:1937) (1935:1935:1935)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1528:1528:1528) (1457:1457:1457)) + (PORT ena (2267:2267:2267) (2043:2043:2043)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~0) + (DELAY + (ABSOLUTE + (PORT datac (1228:1228:1228) (1219:1219:1219)) + (PORT datad (546:546:546) (522:522:522)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[0\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1941:1941:1941) (1937:1937:1937)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1531:1531:1531) (1460:1460:1460)) + (PORT ena (2707:2707:2707) (2434:2434:2434)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) +) diff --git a/pid/simulation/modelsim/pid_8_1200mv_85c_slow.vo b/pid/simulation/modelsim/pid_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..10102ca --- /dev/null +++ b/pid/simulation/modelsim/pid_8_1200mv_85c_slow.vo @@ -0,0 +1,8790 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" + +// DATE "12/04/2018 14:36:38" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module pid ( + clk, + rst_n, + Sample, + SetPoint, + Kp, + Ki, + Kd, + Vout); +input clk; +input rst_n; +input [13:0] Sample; +input [13:0] SetPoint; +input [7:0] Kp; +input [7:0] Ki; +input [7:0] Kd; +output [13:0] Vout; + +// Design Ports Information +// Vout[0] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// Vout[1] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[2] => Location: PIN_N8, I/O Standard: 2.5 V, Current Strength: Default +// Vout[3] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default +// Vout[4] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[5] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[6] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default +// Vout[7] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// Vout[8] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// Vout[9] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default +// Vout[10] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[11] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// Vout[12] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +// Vout[13] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[13] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default +// Sample[13] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default +// Sample[12] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[12] => Location: PIN_F10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[11] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[11] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default +// Sample[10] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[10] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[9] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[9] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default +// Sample[8] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[8] => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// Sample[7] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[7] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default +// Sample[6] => Location: PIN_F14, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[6] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default +// Sample[5] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[5] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[4] => Location: PIN_G11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[4] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[3] => Location: PIN_F11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[3] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default +// Sample[2] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[2] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default +// Sample[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[1] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default +// Sample[0] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[0] => Location: PIN_R12, I/O Standard: 2.5 V, Current Strength: Default +// Kd[0] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[1] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default +// Kd[2] => Location: PIN_J14, I/O Standard: 2.5 V, Current Strength: Default +// Kd[3] => Location: PIN_N9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[4] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default +// Kd[5] => Location: PIN_K9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[6] => Location: PIN_L9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[7] => Location: PIN_R9, I/O Standard: 2.5 V, Current Strength: Default +// Ki[0] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default +// Ki[1] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// Ki[2] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// Ki[3] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default +// Ki[4] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// Ki[5] => Location: PIN_J12, I/O Standard: 2.5 V, Current Strength: Default +// Ki[6] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default +// Ki[7] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[0] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// Kp[1] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default +// Kp[2] => Location: PIN_M9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[3] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default +// Kp[4] => Location: PIN_D9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[5] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// Kp[6] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// Kp[7] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("pid_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \Mult2|auto_generated|mac_out2~0 ; +wire \Mult2|auto_generated|mac_out2~1 ; +wire \Mult2|auto_generated|mac_out2~2 ; +wire \Mult2|auto_generated|mac_out2~3 ; +wire \Mult2|auto_generated|mac_out2~4 ; +wire \Mult2|auto_generated|mac_out2~5 ; +wire \Mult2|auto_generated|mac_out2~6 ; +wire \Mult2|auto_generated|mac_out2~7 ; +wire \Mult2|auto_generated|mac_out2~8 ; +wire \Mult2|auto_generated|mac_out2~9 ; +wire \Mult2|auto_generated|mac_out2~10 ; +wire \Mult2|auto_generated|mac_out2~11 ; +wire \Mult2|auto_generated|mac_out2~12 ; +wire \Mult2|auto_generated|mac_out2~13 ; +wire \Mult2|auto_generated|mac_out2~14 ; +wire \Mult2|auto_generated|mac_out2~15 ; +wire \Mult1|auto_generated|mac_out2~0 ; +wire \Mult1|auto_generated|mac_out2~1 ; +wire \Mult1|auto_generated|mac_out2~2 ; +wire \Mult1|auto_generated|mac_out2~3 ; +wire \Mult1|auto_generated|mac_out2~4 ; +wire \Mult1|auto_generated|mac_out2~5 ; +wire \Mult1|auto_generated|mac_out2~6 ; +wire \Mult1|auto_generated|mac_out2~7 ; +wire \Mult1|auto_generated|mac_out2~8 ; +wire \Mult1|auto_generated|mac_out2~9 ; +wire \Mult1|auto_generated|mac_out2~10 ; +wire \Mult1|auto_generated|mac_out2~11 ; +wire \Mult1|auto_generated|mac_out2~12 ; +wire \Mult1|auto_generated|mac_out2~13 ; +wire \Mult1|auto_generated|mac_out2~14 ; +wire \Mult1|auto_generated|mac_out2~15 ; +wire \Mult0|auto_generated|mac_out2~DATAOUT21 ; +wire \Mult0|auto_generated|mac_out2~0 ; +wire \Mult0|auto_generated|mac_out2~1 ; +wire \Mult0|auto_generated|mac_out2~2 ; +wire \Mult0|auto_generated|mac_out2~3 ; +wire \Mult0|auto_generated|mac_out2~4 ; +wire \Mult0|auto_generated|mac_out2~5 ; +wire \Mult0|auto_generated|mac_out2~6 ; +wire \Mult0|auto_generated|mac_out2~7 ; +wire \Mult0|auto_generated|mac_out2~8 ; +wire \Mult0|auto_generated|mac_out2~9 ; +wire \Mult0|auto_generated|mac_out2~10 ; +wire \Mult0|auto_generated|mac_out2~11 ; +wire \Mult0|auto_generated|mac_out2~12 ; +wire \Mult0|auto_generated|mac_out2~13 ; +wire \Vout[0]~output_o ; +wire \Vout[1]~output_o ; +wire \Vout[2]~output_o ; +wire \Vout[3]~output_o ; +wire \Vout[4]~output_o ; +wire \Vout[5]~output_o ; +wire \Vout[6]~output_o ; +wire \Vout[7]~output_o ; +wire \Vout[8]~output_o ; +wire \Vout[9]~output_o ; +wire \Vout[10]~output_o ; +wire \Vout[11]~output_o ; +wire \Vout[12]~output_o ; +wire \Vout[13]~output_o ; +wire \clk~input_o ; +wire \clk~inputclkctrl_outclk ; +wire \Kd_Out[0]~21_combout ; +wire \EE2[0]~14_combout ; +wire \EE1[0]~14_combout ; +wire \SetPoint[0]~input_o ; +wire \Sample[13]~input_o ; +wire \Add1~1_combout ; +wire \SetPoint[13]~input_o ; +wire \Add1~0_combout ; +wire \Sample[12]~input_o ; +wire \Add1~2_combout ; +wire \SetPoint[12]~input_o ; +wire \Sample[11]~input_o ; +wire \Add1~4_combout ; +wire \SetPoint[11]~input_o ; +wire \SetPoint[10]~input_o ; +wire \Sample[10]~input_o ; +wire \Add1~6_combout ; +wire \Sample[9]~input_o ; +wire \Add1~8_combout ; +wire \SetPoint[9]~input_o ; +wire \SetPoint[8]~input_o ; +wire \Sample[8]~input_o ; +wire \Add1~10_combout ; +wire \Sample[7]~input_o ; +wire \Add1~12_combout ; +wire \SetPoint[7]~input_o ; +wire \SetPoint[6]~input_o ; +wire \Sample[6]~input_o ; +wire \Add1~14_combout ; +wire \Sample[5]~input_o ; +wire \Add1~16_combout ; +wire \SetPoint[4]~input_o ; +wire \Sample[4]~input_o ; +wire \Add1~18_combout ; +wire \Sample[3]~input_o ; +wire \Add1~20_combout ; +wire \SetPoint[2]~input_o ; +wire \Sample[2]~input_o ; +wire \Add1~22_combout ; +wire \Sample[1]~input_o ; +wire \Add1~24_combout ; +wire \SetPoint[1]~input_o ; +wire \Sample[0]~input_o ; +wire \Add1~26_combout ; +wire \EE0[0]~15_cout ; +wire \EE0[0]~17 ; +wire \EE0[1]~18_combout ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \Add0~0_combout ; +wire \period~3_combout ; +wire \Add0~1 ; +wire \Add0~2_combout ; +wire \Add0~3 ; +wire \Add0~4_combout ; +wire \Equal0~2_combout ; +wire \Add0~5 ; +wire \Add0~6_combout ; +wire \period~2_combout ; +wire \Add0~7 ; +wire \Add0~8_combout ; +wire \Add0~9 ; +wire \Add0~10_combout ; +wire \Add0~11 ; +wire \Add0~13 ; +wire \Add0~14_combout ; +wire \period~0_combout ; +wire \Add0~15 ; +wire \Add0~16_combout ; +wire \Add0~17 ; +wire \Add0~18_combout ; +wire \Add0~19 ; +wire \Add0~20_combout ; +wire \Equal0~0_combout ; +wire \Add0~12_combout ; +wire \period~1_combout ; +wire \Equal0~1_combout ; +wire \Equal0~3_combout ; +wire \Clk_Ctrl~q ; +wire \EE0[1]~_Duplicate_1_q ; +wire \Add1~25_combout ; +wire \EE0[1]~19 ; +wire \EE0[2]~20_combout ; +wire \EE0[2]~_Duplicate_1_q ; +wire \Add1~23_combout ; +wire \EE0[2]~21 ; +wire \EE0[3]~22_combout ; +wire \EE0[3]~_Duplicate_1_q ; +wire \SetPoint[3]~input_o ; +wire \Add1~21_combout ; +wire \EE0[3]~23 ; +wire \EE0[4]~24_combout ; +wire \EE0[4]~_Duplicate_1_q ; +wire \Add1~19_combout ; +wire \EE0[4]~25 ; +wire \EE0[5]~26_combout ; +wire \EE0[5]~_Duplicate_1_q ; +wire \SetPoint[5]~input_o ; +wire \Add1~17_combout ; +wire \EE0[5]~27 ; +wire \EE0[6]~28_combout ; +wire \EE0[6]~_Duplicate_1_q ; +wire \Add1~15_combout ; +wire \EE0[6]~29 ; +wire \EE0[7]~30_combout ; +wire \EE0[7]~_Duplicate_1_q ; +wire \Add1~13_combout ; +wire \EE0[7]~31 ; +wire \EE0[8]~32_combout ; +wire \EE0[8]~_Duplicate_1_q ; +wire \Add1~11_combout ; +wire \EE0[8]~33 ; +wire \EE0[9]~34_combout ; +wire \EE0[9]~_Duplicate_1_q ; +wire \Add1~9_combout ; +wire \EE0[9]~35 ; +wire \EE0[10]~36_combout ; +wire \EE0[10]~_Duplicate_1_q ; +wire \Add1~7_combout ; +wire \EE0[10]~37 ; +wire \EE0[11]~38_combout ; +wire \EE0[11]~_Duplicate_1_q ; +wire \Add1~5_combout ; +wire \EE0[11]~39 ; +wire \EE0[12]~40_combout ; +wire \EE0[12]~_Duplicate_1_q ; +wire \Add1~3_combout ; +wire \EE0[12]~41 ; +wire \EE0[13]~42_combout ; +wire \EE0[13]~_Duplicate_1_q ; +wire \Add1~27_combout ; +wire \EE0[0]~16_combout ; +wire \EE0[0]~_Duplicate_1_q ; +wire \EE1[0]~15 ; +wire \EE1[1]~16_combout ; +wire \EE1[1]~17 ; +wire \EE1[2]~18_combout ; +wire \EE1[2]~19 ; +wire \EE1[3]~20_combout ; +wire \EE1[3]~21 ; +wire \EE1[4]~22_combout ; +wire \EE1[4]~23 ; +wire \EE1[5]~24_combout ; +wire \EE1[5]~25 ; +wire \EE1[6]~26_combout ; +wire \EE1[6]~27 ; +wire \EE1[7]~28_combout ; +wire \EE1[7]~29 ; +wire \EE1[8]~30_combout ; +wire \EE1[8]~31 ; +wire \EE1[9]~32_combout ; +wire \EE1[9]~33 ; +wire \EE1[10]~34_combout ; +wire \EE1[10]~35 ; +wire \EE1[11]~36_combout ; +wire \EE1[11]~37 ; +wire \EE1[12]~38_combout ; +wire \EE1[12]~39 ; +wire \EE1[13]~40_combout ; +wire \EE2[0]~15 ; +wire \EE2[1]~16_combout ; +wire \EE2[1]~17 ; +wire \EE2[2]~18_combout ; +wire \EE2[2]~19 ; +wire \EE2[3]~20_combout ; +wire \EE2[3]~21 ; +wire \EE2[4]~22_combout ; +wire \EE2[4]~23 ; +wire \EE2[5]~24_combout ; +wire \EE2[5]~25 ; +wire \EE2[6]~26_combout ; +wire \EE2[6]~27 ; +wire \EE2[7]~28_combout ; +wire \EE2[7]~29 ; +wire \EE2[8]~30_combout ; +wire \EE2[8]~31 ; +wire \EE2[9]~32_combout ; +wire \EE2[9]~33 ; +wire \EE2[10]~34_combout ; +wire \EE2[10]~35 ; +wire \EE2[11]~36_combout ; +wire \EE2[11]~37 ; +wire \EE2[12]~38_combout ; +wire \EE2[12]~39 ; +wire \EE2[13]~40_combout ; +wire \Kd[0]~input_o ; +wire \Kd[1]~input_o ; +wire \Kd[2]~input_o ; +wire \Kd[3]~input_o ; +wire \Kd[4]~input_o ; +wire \Kd[5]~input_o ; +wire \Kd[6]~input_o ; +wire \Kd[7]~input_o ; +wire \Mult2|auto_generated|mac_mult1~dataout ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult2|auto_generated|mac_mult1~0 ; +wire \Mult2|auto_generated|mac_mult1~1 ; +wire \Mult2|auto_generated|mac_mult1~2 ; +wire \Mult2|auto_generated|mac_mult1~3 ; +wire \Mult2|auto_generated|mac_mult1~4 ; +wire \Mult2|auto_generated|mac_mult1~5 ; +wire \Mult2|auto_generated|mac_mult1~6 ; +wire \Mult2|auto_generated|mac_mult1~7 ; +wire \Mult2|auto_generated|mac_mult1~8 ; +wire \Mult2|auto_generated|mac_mult1~9 ; +wire \Mult2|auto_generated|mac_mult1~10 ; +wire \Mult2|auto_generated|mac_mult1~11 ; +wire \Mult2|auto_generated|mac_mult1~12 ; +wire \Mult2|auto_generated|mac_mult1~13 ; +wire \Mult2|auto_generated|mac_mult1~14 ; +wire \Mult2|auto_generated|mac_mult1~15 ; +wire \Mult2|auto_generated|mac_out2~dataout ; +wire \Kd_Out[0]~22 ; +wire \Kd_Out[1]~23_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT1 ; +wire \Kd_Out[1]~24 ; +wire \Kd_Out[2]~25_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT2 ; +wire \Kd_Out[2]~26 ; +wire \Kd_Out[3]~27_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT3 ; +wire \Kd_Out[3]~28 ; +wire \Kd_Out[4]~29_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT4 ; +wire \Kd_Out[4]~30 ; +wire \Kd_Out[5]~31_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT5 ; +wire \Kd_Out[5]~32 ; +wire \Kd_Out[6]~33_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT6 ; +wire \Kd_Out[6]~34 ; +wire \Kd_Out[7]~35_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT7 ; +wire \Kd_Out[7]~36 ; +wire \Kd_Out[8]~37_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT8 ; +wire \Kd_Out[8]~38 ; +wire \Kd_Out[9]~39_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT9 ; +wire \Kd_Out[9]~40 ; +wire \Kd_Out[10]~41_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT10 ; +wire \Kd_Out[10]~42 ; +wire \Kd_Out[11]~43_combout ; +wire \Kd_Out[11]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT11 ; +wire \Kd_Out[11]~44 ; +wire \Kd_Out[12]~45_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT12 ; +wire \Kd_Out[12]~46 ; +wire \Kd_Out[13]~47_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT13 ; +wire \Kd_Out[13]~48 ; +wire \Kd_Out[14]~49_combout ; +wire \Kd_Out[14]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT14 ; +wire \Kd_Out[14]~50 ; +wire \Kd_Out[15]~51_combout ; +wire \Kd_Out[15]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT15 ; +wire \Kd_Out[15]~52 ; +wire \Kd_Out[16]~53_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT16 ; +wire \Kd_Out[16]~54 ; +wire \Kd_Out[17]~55_combout ; +wire \Kd_Out[17]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT17 ; +wire \Kd_Out[17]~56 ; +wire \Kd_Out[18]~57_combout ; +wire \Kd_Out[18]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT18 ; +wire \Kd_Out[18]~58 ; +wire \Kd_Out[19]~59_combout ; +wire \Kd_Out[19]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT19 ; +wire \Kd_Out[19]~60 ; +wire \Kd_Out[20]~61_combout ; +wire \~GND~combout ; +wire \Add7~20_combout ; +wire \Ki_Out[0]~21_combout ; +wire \Ki[0]~input_o ; +wire \Ki[1]~input_o ; +wire \Ki[2]~input_o ; +wire \Ki[3]~input_o ; +wire \Ki[4]~input_o ; +wire \Ki[5]~input_o ; +wire \Ki[6]~input_o ; +wire \Ki[7]~input_o ; +wire \Mult1|auto_generated|mac_mult1~dataout ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult1|auto_generated|mac_mult1~0 ; +wire \Mult1|auto_generated|mac_mult1~1 ; +wire \Mult1|auto_generated|mac_mult1~2 ; +wire \Mult1|auto_generated|mac_mult1~3 ; +wire \Mult1|auto_generated|mac_mult1~4 ; +wire \Mult1|auto_generated|mac_mult1~5 ; +wire \Mult1|auto_generated|mac_mult1~6 ; +wire \Mult1|auto_generated|mac_mult1~7 ; +wire \Mult1|auto_generated|mac_mult1~8 ; +wire \Mult1|auto_generated|mac_mult1~9 ; +wire \Mult1|auto_generated|mac_mult1~10 ; +wire \Mult1|auto_generated|mac_mult1~11 ; +wire \Mult1|auto_generated|mac_mult1~12 ; +wire \Mult1|auto_generated|mac_mult1~13 ; +wire \Mult1|auto_generated|mac_mult1~14 ; +wire \Mult1|auto_generated|mac_mult1~15 ; +wire \Mult1|auto_generated|mac_out2~dataout ; +wire \Ki_Out[0]~22 ; +wire \Ki_Out[1]~23_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT1 ; +wire \Ki_Out[1]~24 ; +wire \Ki_Out[2]~25_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT2 ; +wire \Ki_Out[2]~26 ; +wire \Ki_Out[3]~27_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT3 ; +wire \Ki_Out[3]~28 ; +wire \Ki_Out[4]~29_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT4 ; +wire \Ki_Out[4]~30 ; +wire \Ki_Out[5]~31_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT5 ; +wire \Ki_Out[5]~32 ; +wire \Ki_Out[6]~33_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT6 ; +wire \Ki_Out[6]~34 ; +wire \Ki_Out[7]~35_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT7 ; +wire \Ki_Out[7]~36 ; +wire \Ki_Out[8]~37_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT8 ; +wire \Ki_Out[8]~38 ; +wire \Ki_Out[9]~39_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT9 ; +wire \Ki_Out[9]~40 ; +wire \Ki_Out[10]~41_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT10 ; +wire \Ki_Out[10]~42 ; +wire \Ki_Out[11]~43_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT11 ; +wire \Ki_Out[11]~44 ; +wire \Ki_Out[12]~45_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT12 ; +wire \Ki_Out[12]~46 ; +wire \Ki_Out[13]~47_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT13 ; +wire \Ki_Out[13]~48 ; +wire \Ki_Out[14]~49_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT14 ; +wire \Ki_Out[14]~50 ; +wire \Ki_Out[15]~51_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT15 ; +wire \Ki_Out[15]~52 ; +wire \Ki_Out[16]~53_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT16 ; +wire \Ki_Out[16]~54 ; +wire \Ki_Out[17]~55_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT17 ; +wire \Ki_Out[17]~56 ; +wire \Ki_Out[18]~57_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT18 ; +wire \Ki_Out[18]~58 ; +wire \Ki_Out[19]~59_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT19 ; +wire \Ki_Out[19]~60 ; +wire \Ki_Out[20]~61_combout ; +wire \Kp_Out[0]~21_combout ; +wire \Kp[0]~input_o ; +wire \Kp[1]~input_o ; +wire \Kp[2]~input_o ; +wire \Kp[3]~input_o ; +wire \Kp[4]~input_o ; +wire \Kp[5]~input_o ; +wire \Kp[6]~input_o ; +wire \Kp[7]~input_o ; +wire \Mult0|auto_generated|mac_mult1~dataout ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT20 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT21 ; +wire \Mult0|auto_generated|mac_mult1~0 ; +wire \Mult0|auto_generated|mac_mult1~1 ; +wire \Mult0|auto_generated|mac_mult1~2 ; +wire \Mult0|auto_generated|mac_mult1~3 ; +wire \Mult0|auto_generated|mac_mult1~4 ; +wire \Mult0|auto_generated|mac_mult1~5 ; +wire \Mult0|auto_generated|mac_mult1~6 ; +wire \Mult0|auto_generated|mac_mult1~7 ; +wire \Mult0|auto_generated|mac_mult1~8 ; +wire \Mult0|auto_generated|mac_mult1~9 ; +wire \Mult0|auto_generated|mac_mult1~10 ; +wire \Mult0|auto_generated|mac_mult1~11 ; +wire \Mult0|auto_generated|mac_mult1~12 ; +wire \Mult0|auto_generated|mac_mult1~13 ; +wire \Mult0|auto_generated|mac_out2~dataout ; +wire \Kp_Out[0]~22 ; +wire \Kp_Out[1]~23_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT1 ; +wire \Kp_Out[1]~24 ; +wire \Kp_Out[2]~25_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT2 ; +wire \Kp_Out[2]~26 ; +wire \Kp_Out[3]~27_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT3 ; +wire \Kp_Out[3]~28 ; +wire \Kp_Out[4]~29_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT4 ; +wire \Kp_Out[4]~30 ; +wire \Kp_Out[5]~31_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT5 ; +wire \Kp_Out[5]~32 ; +wire \Kp_Out[6]~33_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT6 ; +wire \Kp_Out[6]~34 ; +wire \Kp_Out[7]~35_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT7 ; +wire \Kp_Out[7]~36 ; +wire \Kp_Out[8]~37_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT8 ; +wire \Kp_Out[8]~38 ; +wire \Kp_Out[9]~39_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT9 ; +wire \Kp_Out[9]~40 ; +wire \Kp_Out[10]~41_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT10 ; +wire \Kp_Out[10]~42 ; +wire \Kp_Out[11]~43_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT11 ; +wire \Kp_Out[11]~44 ; +wire \Kp_Out[12]~45_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT12 ; +wire \Kp_Out[12]~46 ; +wire \Kp_Out[13]~47_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT13 ; +wire \Kp_Out[13]~48 ; +wire \Kp_Out[14]~49_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT14 ; +wire \Kp_Out[14]~50 ; +wire \Kp_Out[15]~51_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT15 ; +wire \Kp_Out[15]~52 ; +wire \Kp_Out[16]~53_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT16 ; +wire \Kp_Out[16]~54 ; +wire \Kp_Out[17]~55_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT17 ; +wire \Kp_Out[17]~56 ; +wire \Kp_Out[18]~57_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT18 ; +wire \Kp_Out[18]~58 ; +wire \Kp_Out[19]~59_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT19 ; +wire \Kp_Out[19]~60 ; +wire \Kp_Out[20]~61_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT20 ; +wire \Add5~1 ; +wire \Add5~3 ; +wire \Add5~5 ; +wire \Add5~7 ; +wire \Add5~9 ; +wire \Add5~11 ; +wire \Add5~13 ; +wire \Add5~15 ; +wire \Add5~25 ; +wire \Add5~28 ; +wire \Add5~31 ; +wire \Add5~34 ; +wire \Add5~37 ; +wire \Add5~40 ; +wire \Add5~43 ; +wire \Add5~46 ; +wire \Add5~49 ; +wire \Add5~52 ; +wire \Add5~55 ; +wire \Add5~58 ; +wire \Add5~60_combout ; +wire \Add5~62_combout ; +wire \Add7~19_combout ; +wire \Add7~18_combout ; +wire \Add7~17_combout ; +wire \Add7~16_combout ; +wire \Add5~48_combout ; +wire \Add7~15_combout ; +wire \Add7~14_combout ; +wire \Add7~13_combout ; +wire \Add7~12_combout ; +wire \Add7~11_combout ; +wire \Add5~30_combout ; +wire \Add7~10_combout ; +wire \Add7~9_combout ; +wire \Add7~8_combout ; +wire \Add5~14_combout ; +wire \Add5~16_combout ; +wire \Add7~1_combout ; +wire \Add5~12_combout ; +wire \Add5~17_combout ; +wire \Add7~2_combout ; +wire \Add5~10_combout ; +wire \Add5~18_combout ; +wire \Add7~3_combout ; +wire \Add5~8_combout ; +wire \Add5~19_combout ; +wire \Add5~6_combout ; +wire \Add5~20_combout ; +wire \Add7~4_combout ; +wire \Add7~5_combout ; +wire \Add5~4_combout ; +wire \Add5~21_combout ; +wire \Add7~6_combout ; +wire \Add5~2_combout ; +wire \Add5~22_combout ; +wire \Add5~0_combout ; +wire \Add5~23_combout ; +wire \Add7~7_combout ; +wire \Vout[0]~15_cout ; +wire \Vout[0]~17_cout ; +wire \Vout[0]~19_cout ; +wire \Vout[0]~21_cout ; +wire \Vout[0]~23_cout ; +wire \Vout[0]~25_cout ; +wire \Vout[0]~27_cout ; +wire \Vout[0]~29 ; +wire \Vout[1]~30_combout ; +wire \Vout[1]~reg0_q ; +wire \Add5~24_combout ; +wire \Add5~26_combout ; +wire \Vout[1]~31 ; +wire \Vout[2]~32_combout ; +wire \Vout[2]~reg0_q ; +wire \Add5~27_combout ; +wire \Add5~29_combout ; +wire \Vout[2]~33 ; +wire \Vout[3]~34_combout ; +wire \Vout[3]~reg0_q ; +wire \Add5~32_combout ; +wire \Vout[3]~35 ; +wire \Vout[4]~36_combout ; +wire \Vout[4]~reg0_q ; +wire \Add5~33_combout ; +wire \Add5~35_combout ; +wire \Vout[4]~37 ; +wire \Vout[5]~38_combout ; +wire \Vout[5]~reg0_q ; +wire \Add5~36_combout ; +wire \Add5~38_combout ; +wire \Vout[5]~39 ; +wire \Vout[6]~40_combout ; +wire \Vout[6]~reg0_q ; +wire \Add5~39_combout ; +wire \Add5~41_combout ; +wire \Vout[6]~41 ; +wire \Vout[7]~42_combout ; +wire \Vout[7]~reg0_q ; +wire \Add5~42_combout ; +wire \Add5~44_combout ; +wire \Vout[7]~43 ; +wire \Vout[8]~44_combout ; +wire \Vout[8]~reg0_q ; +wire \Add5~45_combout ; +wire \Add5~47_combout ; +wire \Vout[8]~45 ; +wire \Vout[9]~46_combout ; +wire \Vout[9]~reg0_q ; +wire \Add5~50_combout ; +wire \Vout[9]~47 ; +wire \Vout[10]~48_combout ; +wire \Vout[10]~reg0_q ; +wire \Add5~51_combout ; +wire \Add5~53_combout ; +wire \Vout[10]~49 ; +wire \Vout[11]~50_combout ; +wire \Vout[11]~reg0_q ; +wire \Add5~54_combout ; +wire \Add5~56_combout ; +wire \Vout[11]~51 ; +wire \Vout[12]~52_combout ; +wire \Vout[12]~reg0_q ; +wire \Add5~57_combout ; +wire \Add5~59_combout ; +wire \Vout[12]~53 ; +wire \Vout[13]~54_combout ; +wire \Vout[13]~reg0_q ; +wire \Add7~0_combout ; +wire \Vout[0]~28_combout ; +wire \Vout[0]~reg0_q ; +wire [21:0] Kd_Out; +wire [21:0] Ki_Out; +wire [21:0] Kp_Out; +wire [13:0] EE2; +wire [13:0] EE1; +wire [10:0] period; + +wire [35:0] \Mult2|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult1|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult0|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult2|auto_generated|mac_mult1_DATAOUT_bus ; +wire [35:0] \Mult1|auto_generated|mac_mult1_DATAOUT_bus ; +wire [35:0] \Mult0|auto_generated|mac_mult1_DATAOUT_bus ; + +assign \Mult2|auto_generated|mac_out2~0 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult2|auto_generated|mac_out2~1 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult2|auto_generated|mac_out2~2 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult2|auto_generated|mac_out2~3 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult2|auto_generated|mac_out2~4 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult2|auto_generated|mac_out2~5 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult2|auto_generated|mac_out2~6 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult2|auto_generated|mac_out2~7 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult2|auto_generated|mac_out2~8 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult2|auto_generated|mac_out2~9 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult2|auto_generated|mac_out2~10 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult2|auto_generated|mac_out2~11 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult2|auto_generated|mac_out2~12 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult2|auto_generated|mac_out2~13 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult2|auto_generated|mac_out2~14 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult2|auto_generated|mac_out2~15 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult2|auto_generated|mac_out2~dataout = \Mult2|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult2|auto_generated|mac_out2~DATAOUT1 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult2|auto_generated|mac_out2~DATAOUT2 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult2|auto_generated|mac_out2~DATAOUT3 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult2|auto_generated|mac_out2~DATAOUT4 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult2|auto_generated|mac_out2~DATAOUT5 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult2|auto_generated|mac_out2~DATAOUT6 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult2|auto_generated|mac_out2~DATAOUT7 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult2|auto_generated|mac_out2~DATAOUT8 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult2|auto_generated|mac_out2~DATAOUT9 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult2|auto_generated|mac_out2~DATAOUT10 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult2|auto_generated|mac_out2~DATAOUT11 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult2|auto_generated|mac_out2~DATAOUT12 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult2|auto_generated|mac_out2~DATAOUT13 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult2|auto_generated|mac_out2~DATAOUT14 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult2|auto_generated|mac_out2~DATAOUT15 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult2|auto_generated|mac_out2~DATAOUT16 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult2|auto_generated|mac_out2~DATAOUT17 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult2|auto_generated|mac_out2~DATAOUT18 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult2|auto_generated|mac_out2~DATAOUT19 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult1|auto_generated|mac_out2~0 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult1|auto_generated|mac_out2~1 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult1|auto_generated|mac_out2~2 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult1|auto_generated|mac_out2~3 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult1|auto_generated|mac_out2~4 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult1|auto_generated|mac_out2~5 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult1|auto_generated|mac_out2~6 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult1|auto_generated|mac_out2~7 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult1|auto_generated|mac_out2~8 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult1|auto_generated|mac_out2~9 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult1|auto_generated|mac_out2~10 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult1|auto_generated|mac_out2~11 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult1|auto_generated|mac_out2~12 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult1|auto_generated|mac_out2~13 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult1|auto_generated|mac_out2~14 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult1|auto_generated|mac_out2~15 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult1|auto_generated|mac_out2~dataout = \Mult1|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult1|auto_generated|mac_out2~DATAOUT1 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult1|auto_generated|mac_out2~DATAOUT2 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult1|auto_generated|mac_out2~DATAOUT3 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult1|auto_generated|mac_out2~DATAOUT4 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult1|auto_generated|mac_out2~DATAOUT5 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult1|auto_generated|mac_out2~DATAOUT6 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult1|auto_generated|mac_out2~DATAOUT7 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult1|auto_generated|mac_out2~DATAOUT8 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult1|auto_generated|mac_out2~DATAOUT9 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult1|auto_generated|mac_out2~DATAOUT10 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult1|auto_generated|mac_out2~DATAOUT11 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult1|auto_generated|mac_out2~DATAOUT12 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult1|auto_generated|mac_out2~DATAOUT13 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult1|auto_generated|mac_out2~DATAOUT14 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult1|auto_generated|mac_out2~DATAOUT15 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult1|auto_generated|mac_out2~DATAOUT16 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult1|auto_generated|mac_out2~DATAOUT17 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult1|auto_generated|mac_out2~DATAOUT18 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult1|auto_generated|mac_out2~DATAOUT19 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult0|auto_generated|mac_out2~0 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult0|auto_generated|mac_out2~1 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult0|auto_generated|mac_out2~2 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult0|auto_generated|mac_out2~3 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult0|auto_generated|mac_out2~4 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult0|auto_generated|mac_out2~5 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult0|auto_generated|mac_out2~6 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult0|auto_generated|mac_out2~7 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult0|auto_generated|mac_out2~8 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult0|auto_generated|mac_out2~9 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult0|auto_generated|mac_out2~10 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult0|auto_generated|mac_out2~11 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult0|auto_generated|mac_out2~12 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult0|auto_generated|mac_out2~13 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult0|auto_generated|mac_out2~dataout = \Mult0|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult0|auto_generated|mac_out2~DATAOUT1 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult0|auto_generated|mac_out2~DATAOUT2 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult0|auto_generated|mac_out2~DATAOUT3 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult0|auto_generated|mac_out2~DATAOUT4 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult0|auto_generated|mac_out2~DATAOUT5 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult0|auto_generated|mac_out2~DATAOUT6 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult0|auto_generated|mac_out2~DATAOUT7 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult0|auto_generated|mac_out2~DATAOUT8 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult0|auto_generated|mac_out2~DATAOUT9 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult0|auto_generated|mac_out2~DATAOUT10 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult0|auto_generated|mac_out2~DATAOUT11 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult0|auto_generated|mac_out2~DATAOUT12 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult0|auto_generated|mac_out2~DATAOUT13 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult0|auto_generated|mac_out2~DATAOUT14 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult0|auto_generated|mac_out2~DATAOUT15 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult0|auto_generated|mac_out2~DATAOUT16 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult0|auto_generated|mac_out2~DATAOUT17 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult0|auto_generated|mac_out2~DATAOUT18 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult0|auto_generated|mac_out2~DATAOUT19 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult0|auto_generated|mac_out2~DATAOUT20 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult0|auto_generated|mac_out2~DATAOUT21 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult2|auto_generated|mac_mult1~0 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult2|auto_generated|mac_mult1~1 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult2|auto_generated|mac_mult1~2 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult2|auto_generated|mac_mult1~3 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult2|auto_generated|mac_mult1~4 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult2|auto_generated|mac_mult1~5 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult2|auto_generated|mac_mult1~6 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult2|auto_generated|mac_mult1~7 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult2|auto_generated|mac_mult1~8 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult2|auto_generated|mac_mult1~9 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult2|auto_generated|mac_mult1~10 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult2|auto_generated|mac_mult1~11 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult2|auto_generated|mac_mult1~12 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult2|auto_generated|mac_mult1~13 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult2|auto_generated|mac_mult1~14 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult2|auto_generated|mac_mult1~15 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult2|auto_generated|mac_mult1~dataout = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT1 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT2 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT3 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT4 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT5 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT6 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT7 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT8 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT9 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT10 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT11 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT12 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT13 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT14 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT15 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT16 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT17 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT18 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT19 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [35]; + +assign \Mult1|auto_generated|mac_mult1~0 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult1|auto_generated|mac_mult1~1 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult1|auto_generated|mac_mult1~2 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult1|auto_generated|mac_mult1~3 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult1|auto_generated|mac_mult1~4 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult1|auto_generated|mac_mult1~5 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult1|auto_generated|mac_mult1~6 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult1|auto_generated|mac_mult1~7 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult1|auto_generated|mac_mult1~8 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult1|auto_generated|mac_mult1~9 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult1|auto_generated|mac_mult1~10 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult1|auto_generated|mac_mult1~11 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult1|auto_generated|mac_mult1~12 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult1|auto_generated|mac_mult1~13 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult1|auto_generated|mac_mult1~14 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult1|auto_generated|mac_mult1~15 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult1|auto_generated|mac_mult1~dataout = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT1 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT2 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT3 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT4 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT5 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT6 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT7 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT8 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT9 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT10 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT11 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT12 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT13 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT14 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT15 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT16 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT17 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT18 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT19 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [35]; + +assign \Mult0|auto_generated|mac_mult1~0 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult0|auto_generated|mac_mult1~1 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult0|auto_generated|mac_mult1~2 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult0|auto_generated|mac_mult1~3 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult0|auto_generated|mac_mult1~4 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult0|auto_generated|mac_mult1~5 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult0|auto_generated|mac_mult1~6 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult0|auto_generated|mac_mult1~7 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult0|auto_generated|mac_mult1~8 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult0|auto_generated|mac_mult1~9 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult0|auto_generated|mac_mult1~10 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult0|auto_generated|mac_mult1~11 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult0|auto_generated|mac_mult1~12 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult0|auto_generated|mac_mult1~13 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult0|auto_generated|mac_mult1~dataout = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT1 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT2 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT3 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT4 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT5 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT6 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT7 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT8 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT9 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT10 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT11 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT12 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT13 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT14 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT15 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT16 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT17 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT18 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT19 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT20 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT21 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [35]; + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: IOOBUF_X7_Y24_N16 +cycloneive_io_obuf \Vout[0]~output ( + .i(\Vout[0]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[0]~output .bus_hold = "false"; +defparam \Vout[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N9 +cycloneive_io_obuf \Vout[1]~output ( + .i(\Vout[1]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[1]~output .bus_hold = "false"; +defparam \Vout[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N23 +cycloneive_io_obuf \Vout[2]~output ( + .i(\Vout[2]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[2]~output .bus_hold = "false"; +defparam \Vout[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N16 +cycloneive_io_obuf \Vout[3]~output ( + .i(\Vout[3]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[3]~output .bus_hold = "false"; +defparam \Vout[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N2 +cycloneive_io_obuf \Vout[4]~output ( + .i(\Vout[4]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[4]~output .bus_hold = "false"; +defparam \Vout[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y24_N2 +cycloneive_io_obuf \Vout[5]~output ( + .i(\Vout[5]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[5]~output .bus_hold = "false"; +defparam \Vout[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N16 +cycloneive_io_obuf \Vout[6]~output ( + .i(\Vout[6]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[6]~output .bus_hold = "false"; +defparam \Vout[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y24_N16 +cycloneive_io_obuf \Vout[7]~output ( + .i(\Vout[7]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[7]~output .bus_hold = "false"; +defparam \Vout[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N2 +cycloneive_io_obuf \Vout[8]~output ( + .i(\Vout[8]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[8]~output .bus_hold = "false"; +defparam \Vout[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N2 +cycloneive_io_obuf \Vout[9]~output ( + .i(\Vout[9]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[9]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[9]~output .bus_hold = "false"; +defparam \Vout[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N23 +cycloneive_io_obuf \Vout[10]~output ( + .i(\Vout[10]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[10]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[10]~output .bus_hold = "false"; +defparam \Vout[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y19_N16 +cycloneive_io_obuf \Vout[11]~output ( + .i(\Vout[11]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[11]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[11]~output .bus_hold = "false"; +defparam \Vout[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y24_N9 +cycloneive_io_obuf \Vout[12]~output ( + .i(\Vout[12]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[12]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[12]~output .bus_hold = "false"; +defparam \Vout[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N9 +cycloneive_io_obuf \Vout[13]~output ( + .i(\Vout[13]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[13]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[13]~output .bus_hold = "false"; +defparam \Vout[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk~inputclkctrl .clock_type = "global clock"; +defparam \clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N12 +cycloneive_lcell_comb \Kd_Out[0]~21 ( +// Equation(s): +// \Kd_Out[0]~21_combout = Kd_Out[0] $ (GND) +// \Kd_Out[0]~22 = CARRY(!Kd_Out[0]) + + .dataa(Kd_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Kd_Out[0]~21_combout ), + .cout(\Kd_Out[0]~22 )); +// synopsys translate_off +defparam \Kd_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Kd_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 +cycloneive_lcell_comb \EE2[0]~14 ( +// Equation(s): +// \EE2[0]~14_combout = EE2[0] $ (GND) +// \EE2[0]~15 = CARRY(!EE2[0]) + + .dataa(gnd), + .datab(EE2[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\EE2[0]~14_combout ), + .cout(\EE2[0]~15 )); +// synopsys translate_off +defparam \EE2[0]~14 .lut_mask = 16'hCC33; +defparam \EE2[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N2 +cycloneive_lcell_comb \EE1[0]~14 ( +// Equation(s): +// \EE1[0]~14_combout = EE1[0] $ (GND) +// \EE1[0]~15 = CARRY(!EE1[0]) + + .dataa(gnd), + .datab(EE1[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\EE1[0]~14_combout ), + .cout(\EE1[0]~15 )); +// synopsys translate_off +defparam \EE1[0]~14 .lut_mask = 16'hCC33; +defparam \EE1[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y0_N1 +cycloneive_io_ibuf \SetPoint[0]~input ( + .i(SetPoint[0]), + .ibar(gnd), + .o(\SetPoint[0]~input_o )); +// synopsys translate_off +defparam \SetPoint[0]~input .bus_hold = "false"; +defparam \SetPoint[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N8 +cycloneive_io_ibuf \Sample[13]~input ( + .i(Sample[13]), + .ibar(gnd), + .o(\Sample[13]~input_o )); +// synopsys translate_off +defparam \Sample[13]~input .bus_hold = "false"; +defparam \Sample[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N2 +cycloneive_lcell_comb \Add1~1 ( +// Equation(s): +// \Add1~1_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[13]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[13]~input_o ), + .cin(gnd), + .combout(\Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~1 .lut_mask = 16'hFFF0; +defparam \Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N22 +cycloneive_io_ibuf \SetPoint[13]~input ( + .i(SetPoint[13]), + .ibar(gnd), + .o(\SetPoint[13]~input_o )); +// synopsys translate_off +defparam \SetPoint[13]~input .bus_hold = "false"; +defparam \SetPoint[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N0 +cycloneive_lcell_comb \Add1~0 ( +// Equation(s): +// \Add1~0_combout = (!\EE0[13]~_Duplicate_1_q & \SetPoint[13]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\SetPoint[13]~input_o ), + .cin(gnd), + .combout(\Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~0 .lut_mask = 16'h0F00; +defparam \Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N1 +cycloneive_io_ibuf \Sample[12]~input ( + .i(Sample[12]), + .ibar(gnd), + .o(\Sample[12]~input_o )); +// synopsys translate_off +defparam \Sample[12]~input .bus_hold = "false"; +defparam \Sample[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N8 +cycloneive_lcell_comb \Add1~2 ( +// Equation(s): +// \Add1~2_combout = (\Sample[12]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[12]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~2_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~2 .lut_mask = 16'hFFF0; +defparam \Add1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N8 +cycloneive_io_ibuf \SetPoint[12]~input ( + .i(SetPoint[12]), + .ibar(gnd), + .o(\SetPoint[12]~input_o )); +// synopsys translate_off +defparam \SetPoint[12]~input .bus_hold = "false"; +defparam \SetPoint[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N22 +cycloneive_io_ibuf \Sample[11]~input ( + .i(Sample[11]), + .ibar(gnd), + .o(\Sample[11]~input_o )); +// synopsys translate_off +defparam \Sample[11]~input .bus_hold = "false"; +defparam \Sample[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N24 +cycloneive_lcell_comb \Add1~4 ( +// Equation(s): +// \Add1~4_combout = (\Sample[11]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(\Sample[11]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(gnd), + .cin(gnd), + .combout(\Add1~4_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~4 .lut_mask = 16'hFAFA; +defparam \Add1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N8 +cycloneive_io_ibuf \SetPoint[11]~input ( + .i(SetPoint[11]), + .ibar(gnd), + .o(\SetPoint[11]~input_o )); +// synopsys translate_off +defparam \SetPoint[11]~input .bus_hold = "false"; +defparam \SetPoint[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N1 +cycloneive_io_ibuf \SetPoint[10]~input ( + .i(SetPoint[10]), + .ibar(gnd), + .o(\SetPoint[10]~input_o )); +// synopsys translate_off +defparam \SetPoint[10]~input .bus_hold = "false"; +defparam \SetPoint[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N1 +cycloneive_io_ibuf \Sample[10]~input ( + .i(Sample[10]), + .ibar(gnd), + .o(\Sample[10]~input_o )); +// synopsys translate_off +defparam \Sample[10]~input .bus_hold = "false"; +defparam \Sample[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N10 +cycloneive_lcell_comb \Add1~6 ( +// Equation(s): +// \Add1~6_combout = (\Sample[10]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[10]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~6 .lut_mask = 16'hFFF0; +defparam \Add1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N8 +cycloneive_io_ibuf \Sample[9]~input ( + .i(Sample[9]), + .ibar(gnd), + .o(\Sample[9]~input_o )); +// synopsys translate_off +defparam \Sample[9]~input .bus_hold = "false"; +defparam \Sample[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N18 +cycloneive_lcell_comb \Add1~8 ( +// Equation(s): +// \Add1~8_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[9]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[9]~input_o ), + .cin(gnd), + .combout(\Add1~8_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~8 .lut_mask = 16'hFFF0; +defparam \Add1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N15 +cycloneive_io_ibuf \SetPoint[9]~input ( + .i(SetPoint[9]), + .ibar(gnd), + .o(\SetPoint[9]~input_o )); +// synopsys translate_off +defparam \SetPoint[9]~input .bus_hold = "false"; +defparam \SetPoint[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N22 +cycloneive_io_ibuf \SetPoint[8]~input ( + .i(SetPoint[8]), + .ibar(gnd), + .o(\SetPoint[8]~input_o )); +// synopsys translate_off +defparam \SetPoint[8]~input .bus_hold = "false"; +defparam \SetPoint[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N1 +cycloneive_io_ibuf \Sample[8]~input ( + .i(Sample[8]), + .ibar(gnd), + .o(\Sample[8]~input_o )); +// synopsys translate_off +defparam \Sample[8]~input .bus_hold = "false"; +defparam \Sample[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N20 +cycloneive_lcell_comb \Add1~10 ( +// Equation(s): +// \Add1~10_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[8]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[8]~input_o ), + .cin(gnd), + .combout(\Add1~10_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~10 .lut_mask = 16'hFFF0; +defparam \Add1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N15 +cycloneive_io_ibuf \Sample[7]~input ( + .i(Sample[7]), + .ibar(gnd), + .o(\Sample[7]~input_o )); +// synopsys translate_off +defparam \Sample[7]~input .bus_hold = "false"; +defparam \Sample[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N6 +cycloneive_lcell_comb \Add1~12 ( +// Equation(s): +// \Add1~12_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[7]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[7]~input_o ), + .cin(gnd), + .combout(\Add1~12_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~12 .lut_mask = 16'hFFF0; +defparam \Add1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N8 +cycloneive_io_ibuf \SetPoint[7]~input ( + .i(SetPoint[7]), + .ibar(gnd), + .o(\SetPoint[7]~input_o )); +// synopsys translate_off +defparam \SetPoint[7]~input .bus_hold = "false"; +defparam \SetPoint[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N15 +cycloneive_io_ibuf \SetPoint[6]~input ( + .i(SetPoint[6]), + .ibar(gnd), + .o(\SetPoint[6]~input_o )); +// synopsys translate_off +defparam \SetPoint[6]~input .bus_hold = "false"; +defparam \SetPoint[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N15 +cycloneive_io_ibuf \Sample[6]~input ( + .i(Sample[6]), + .ibar(gnd), + .o(\Sample[6]~input_o )); +// synopsys translate_off +defparam \Sample[6]~input .bus_hold = "false"; +defparam \Sample[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N22 +cycloneive_lcell_comb \Add1~14 ( +// Equation(s): +// \Add1~14_combout = (\Sample[6]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\Sample[6]~input_o ), + .datac(gnd), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~14_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~14 .lut_mask = 16'hFFCC; +defparam \Add1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N22 +cycloneive_io_ibuf \Sample[5]~input ( + .i(Sample[5]), + .ibar(gnd), + .o(\Sample[5]~input_o )); +// synopsys translate_off +defparam \Sample[5]~input .bus_hold = "false"; +defparam \Sample[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N12 +cycloneive_lcell_comb \Add1~16 ( +// Equation(s): +// \Add1~16_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[5]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[5]~input_o ), + .cin(gnd), + .combout(\Add1~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~16 .lut_mask = 16'hFFF0; +defparam \Add1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N15 +cycloneive_io_ibuf \SetPoint[4]~input ( + .i(SetPoint[4]), + .ibar(gnd), + .o(\SetPoint[4]~input_o )); +// synopsys translate_off +defparam \SetPoint[4]~input .bus_hold = "false"; +defparam \SetPoint[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N15 +cycloneive_io_ibuf \Sample[4]~input ( + .i(Sample[4]), + .ibar(gnd), + .o(\Sample[4]~input_o )); +// synopsys translate_off +defparam \Sample[4]~input .bus_hold = "false"; +defparam \Sample[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N16 +cycloneive_lcell_comb \Add1~18 ( +// Equation(s): +// \Add1~18_combout = (\Sample[4]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\Sample[4]~input_o ), + .datac(gnd), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~18 .lut_mask = 16'hFFCC; +defparam \Add1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N22 +cycloneive_io_ibuf \Sample[3]~input ( + .i(Sample[3]), + .ibar(gnd), + .o(\Sample[3]~input_o )); +// synopsys translate_off +defparam \Sample[3]~input .bus_hold = "false"; +defparam \Sample[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N6 +cycloneive_lcell_comb \Add1~20 ( +// Equation(s): +// \Add1~20_combout = (\Sample[3]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[3]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~20 .lut_mask = 16'hFFF0; +defparam \Add1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N1 +cycloneive_io_ibuf \SetPoint[2]~input ( + .i(SetPoint[2]), + .ibar(gnd), + .o(\SetPoint[2]~input_o )); +// synopsys translate_off +defparam \SetPoint[2]~input .bus_hold = "false"; +defparam \SetPoint[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N22 +cycloneive_io_ibuf \Sample[2]~input ( + .i(Sample[2]), + .ibar(gnd), + .o(\Sample[2]~input_o )); +// synopsys translate_off +defparam \Sample[2]~input .bus_hold = "false"; +defparam \Sample[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N14 +cycloneive_lcell_comb \Add1~22 ( +// Equation(s): +// \Add1~22_combout = (\Sample[2]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[2]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~22_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~22 .lut_mask = 16'hFFF0; +defparam \Add1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N8 +cycloneive_io_ibuf \Sample[1]~input ( + .i(Sample[1]), + .ibar(gnd), + .o(\Sample[1]~input_o )); +// synopsys translate_off +defparam \Sample[1]~input .bus_hold = "false"; +defparam \Sample[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N4 +cycloneive_lcell_comb \Add1~24 ( +// Equation(s): +// \Add1~24_combout = (\Sample[1]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[1]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~24_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~24 .lut_mask = 16'hFFF0; +defparam \Add1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N1 +cycloneive_io_ibuf \SetPoint[1]~input ( + .i(SetPoint[1]), + .ibar(gnd), + .o(\SetPoint[1]~input_o )); +// synopsys translate_off +defparam \SetPoint[1]~input .bus_hold = "false"; +defparam \SetPoint[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \Sample[0]~input ( + .i(Sample[0]), + .ibar(gnd), + .o(\Sample[0]~input_o )); +// synopsys translate_off +defparam \Sample[0]~input .bus_hold = "false"; +defparam \Sample[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N12 +cycloneive_lcell_comb \Add1~26 ( +// Equation(s): +// \Add1~26_combout = (\EE0[13]~_Duplicate_1_q ) # (!\Sample[0]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[0]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~26_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~26 .lut_mask = 16'hFF0F; +defparam \Add1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N0 +cycloneive_lcell_comb \EE0[0]~15 ( +// Equation(s): +// \EE0[0]~15_cout = CARRY(!\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\EE0[0]~15_cout )); +// synopsys translate_off +defparam \EE0[0]~15 .lut_mask = 16'h0033; +defparam \EE0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N2 +cycloneive_lcell_comb \EE0[0]~16 ( +// Equation(s): +// \EE0[0]~16_combout = (\Add1~27_combout & ((\Add1~26_combout & (\EE0[0]~15_cout & VCC)) # (!\Add1~26_combout & (!\EE0[0]~15_cout )))) # (!\Add1~27_combout & ((\Add1~26_combout & (!\EE0[0]~15_cout )) # (!\Add1~26_combout & ((\EE0[0]~15_cout ) # +// (GND))))) +// \EE0[0]~17 = CARRY((\Add1~27_combout & (!\Add1~26_combout & !\EE0[0]~15_cout )) # (!\Add1~27_combout & ((!\EE0[0]~15_cout ) # (!\Add1~26_combout )))) + + .dataa(\Add1~27_combout ), + .datab(\Add1~26_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[0]~15_cout ), + .combout(\EE0[0]~16_combout ), + .cout(\EE0[0]~17 )); +// synopsys translate_off +defparam \EE0[0]~16 .lut_mask = 16'h9617; +defparam \EE0[0]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N4 +cycloneive_lcell_comb \EE0[1]~18 ( +// Equation(s): +// \EE0[1]~18_combout = ((\Add1~24_combout $ (\Add1~25_combout $ (\EE0[0]~17 )))) # (GND) +// \EE0[1]~19 = CARRY((\Add1~24_combout & (\Add1~25_combout & !\EE0[0]~17 )) # (!\Add1~24_combout & ((\Add1~25_combout ) # (!\EE0[0]~17 )))) + + .dataa(\Add1~24_combout ), + .datab(\Add1~25_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[0]~17 ), + .combout(\EE0[1]~18_combout ), + .cout(\EE0[1]~19 )); +// synopsys translate_off +defparam \EE0[1]~18 .lut_mask = 16'h964D; +defparam \EE0[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \Add0~0 ( +// Equation(s): +// \Add0~0_combout = period[0] $ (VCC) +// \Add0~1 = CARRY(period[0]) + + .dataa(gnd), + .datab(period[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add0~0_combout ), + .cout(\Add0~1 )); +// synopsys translate_off +defparam \Add0~0 .lut_mask = 16'h33CC; +defparam \Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N6 +cycloneive_lcell_comb \period~3 ( +// Equation(s): +// \period~3_combout = (\Add0~0_combout & (((!\Equal0~2_combout ) # (!\Equal0~0_combout )) # (!\Equal0~1_combout ))) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~0_combout ), + .datac(\Add0~0_combout ), + .datad(\Equal0~2_combout ), + .cin(gnd), + .combout(\period~3_combout ), + .cout()); +// synopsys translate_off +defparam \period~3 .lut_mask = 16'h70F0; +defparam \period~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y13_N7 +dffeas \period[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~3_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[0]), + .prn(vcc)); +// synopsys translate_off +defparam \period[0] .is_wysiwyg = "true"; +defparam \period[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \Add0~2 ( +// Equation(s): +// \Add0~2_combout = (period[1] & (!\Add0~1 )) # (!period[1] & ((\Add0~1 ) # (GND))) +// \Add0~3 = CARRY((!\Add0~1 ) # (!period[1])) + + .dataa(period[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~1 ), + .combout(\Add0~2_combout ), + .cout(\Add0~3 )); +// synopsys translate_off +defparam \Add0~2 .lut_mask = 16'h5A5F; +defparam \Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N7 +dffeas \period[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~2_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[1]), + .prn(vcc)); +// synopsys translate_off +defparam \period[1] .is_wysiwyg = "true"; +defparam \period[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N8 +cycloneive_lcell_comb \Add0~4 ( +// Equation(s): +// \Add0~4_combout = (period[2] & (\Add0~3 $ (GND))) # (!period[2] & (!\Add0~3 & VCC)) +// \Add0~5 = CARRY((period[2] & !\Add0~3 )) + + .dataa(gnd), + .datab(period[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~3 ), + .combout(\Add0~4_combout ), + .cout(\Add0~5 )); +// synopsys translate_off +defparam \Add0~4 .lut_mask = 16'hC30C; +defparam \Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N9 +dffeas \period[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~4_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[2]), + .prn(vcc)); +// synopsys translate_off +defparam \period[2] .is_wysiwyg = "true"; +defparam \period[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N16 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!period[0] & (!period[2] & !period[1])) + + .dataa(period[0]), + .datab(gnd), + .datac(period[2]), + .datad(period[1]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0005; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \Add0~6 ( +// Equation(s): +// \Add0~6_combout = (period[3] & (!\Add0~5 )) # (!period[3] & ((\Add0~5 ) # (GND))) +// \Add0~7 = CARRY((!\Add0~5 ) # (!period[3])) + + .dataa(gnd), + .datab(period[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~5 ), + .combout(\Add0~6_combout ), + .cout(\Add0~7 )); +// synopsys translate_off +defparam \Add0~6 .lut_mask = 16'h3C3F; +defparam \Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N0 +cycloneive_lcell_comb \period~2 ( +// Equation(s): +// \period~2_combout = (\Add0~6_combout & (((!\Equal0~0_combout ) # (!\Equal0~1_combout )) # (!\Equal0~2_combout ))) + + .dataa(\Equal0~2_combout ), + .datab(\Equal0~1_combout ), + .datac(\Equal0~0_combout ), + .datad(\Add0~6_combout ), + .cin(gnd), + .combout(\period~2_combout ), + .cout()); +// synopsys translate_off +defparam \period~2 .lut_mask = 16'h7F00; +defparam \period~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N1 +dffeas \period[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~2_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[3]), + .prn(vcc)); +// synopsys translate_off +defparam \period[3] .is_wysiwyg = "true"; +defparam \period[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \Add0~8 ( +// Equation(s): +// \Add0~8_combout = (period[4] & (\Add0~7 $ (GND))) # (!period[4] & (!\Add0~7 & VCC)) +// \Add0~9 = CARRY((period[4] & !\Add0~7 )) + + .dataa(period[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~7 ), + .combout(\Add0~8_combout ), + .cout(\Add0~9 )); +// synopsys translate_off +defparam \Add0~8 .lut_mask = 16'hA50A; +defparam \Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N13 +dffeas \period[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~8_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[4]), + .prn(vcc)); +// synopsys translate_off +defparam \period[4] .is_wysiwyg = "true"; +defparam \period[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N14 +cycloneive_lcell_comb \Add0~10 ( +// Equation(s): +// \Add0~10_combout = (period[5] & (!\Add0~9 )) # (!period[5] & ((\Add0~9 ) # (GND))) +// \Add0~11 = CARRY((!\Add0~9 ) # (!period[5])) + + .dataa(gnd), + .datab(period[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~9 ), + .combout(\Add0~10_combout ), + .cout(\Add0~11 )); +// synopsys translate_off +defparam \Add0~10 .lut_mask = 16'h3C3F; +defparam \Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N15 +dffeas \period[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~10_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[5]), + .prn(vcc)); +// synopsys translate_off +defparam \period[5] .is_wysiwyg = "true"; +defparam \period[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \Add0~12 ( +// Equation(s): +// \Add0~12_combout = (period[6] & (\Add0~11 $ (GND))) # (!period[6] & (!\Add0~11 & VCC)) +// \Add0~13 = CARRY((period[6] & !\Add0~11 )) + + .dataa(period[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~11 ), + .combout(\Add0~12_combout ), + .cout(\Add0~13 )); +// synopsys translate_off +defparam \Add0~12 .lut_mask = 16'hA50A; +defparam \Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \Add0~14 ( +// Equation(s): +// \Add0~14_combout = (period[7] & (!\Add0~13 )) # (!period[7] & ((\Add0~13 ) # (GND))) +// \Add0~15 = CARRY((!\Add0~13 ) # (!period[7])) + + .dataa(gnd), + .datab(period[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~13 ), + .combout(\Add0~14_combout ), + .cout(\Add0~15 )); +// synopsys translate_off +defparam \Add0~14 .lut_mask = 16'h3C3F; +defparam \Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \period~0 ( +// Equation(s): +// \period~0_combout = (\Add0~14_combout & (((!\Equal0~1_combout ) # (!\Equal0~2_combout )) # (!\Equal0~0_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Add0~14_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\period~0_combout ), + .cout()); +// synopsys translate_off +defparam \period~0 .lut_mask = 16'h4CCC; +defparam \period~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N29 +dffeas \period[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~0_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[7]), + .prn(vcc)); +// synopsys translate_off +defparam \period[7] .is_wysiwyg = "true"; +defparam \period[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N20 +cycloneive_lcell_comb \Add0~16 ( +// Equation(s): +// \Add0~16_combout = (period[8] & (\Add0~15 $ (GND))) # (!period[8] & (!\Add0~15 & VCC)) +// \Add0~17 = CARRY((period[8] & !\Add0~15 )) + + .dataa(gnd), + .datab(period[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~15 ), + .combout(\Add0~16_combout ), + .cout(\Add0~17 )); +// synopsys translate_off +defparam \Add0~16 .lut_mask = 16'hC30C; +defparam \Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N21 +dffeas \period[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~16_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[8]), + .prn(vcc)); +// synopsys translate_off +defparam \period[8] .is_wysiwyg = "true"; +defparam \period[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \Add0~18 ( +// Equation(s): +// \Add0~18_combout = (period[9] & (!\Add0~17 )) # (!period[9] & ((\Add0~17 ) # (GND))) +// \Add0~19 = CARRY((!\Add0~17 ) # (!period[9])) + + .dataa(period[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~17 ), + .combout(\Add0~18_combout ), + .cout(\Add0~19 )); +// synopsys translate_off +defparam \Add0~18 .lut_mask = 16'h5A5F; +defparam \Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N23 +dffeas \period[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~18_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[9]), + .prn(vcc)); +// synopsys translate_off +defparam \period[9] .is_wysiwyg = "true"; +defparam \period[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \Add0~20 ( +// Equation(s): +// \Add0~20_combout = \Add0~19 $ (!period[10]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(period[10]), + .cin(\Add0~19 ), + .combout(\Add0~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add0~20 .lut_mask = 16'hF00F; +defparam \Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N25 +dffeas \period[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~20_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[10]), + .prn(vcc)); +// synopsys translate_off +defparam \period[10] .is_wysiwyg = "true"; +defparam \period[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!period[10] & (!period[8] & (!period[9] & period[7]))) + + .dataa(period[10]), + .datab(period[8]), + .datac(period[9]), + .datad(period[7]), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0100; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \period~1 ( +// Equation(s): +// \period~1_combout = (\Add0~12_combout & (((!\Equal0~1_combout ) # (!\Equal0~2_combout )) # (!\Equal0~0_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Add0~12_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\period~1_combout ), + .cout()); +// synopsys translate_off +defparam \period~1 .lut_mask = 16'h4CCC; +defparam \period~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N31 +dffeas \period[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~1_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[6]), + .prn(vcc)); +// synopsys translate_off +defparam \period[6] .is_wysiwyg = "true"; +defparam \period[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N2 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (period[6] & (period[3] & (!period[5] & !period[4]))) + + .dataa(period[6]), + .datab(period[3]), + .datac(period[5]), + .datad(period[4]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0008; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N0 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~0_combout )) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~2_combout ), + .datac(gnd), + .datad(\Equal0~0_combout ), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h8800; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y13_N1 +dffeas Clk_Ctrl( + .clk(\clk~inputclkctrl_outclk ), + .d(\Equal0~3_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\Clk_Ctrl~q ), + .prn(vcc)); +// synopsys translate_off +defparam Clk_Ctrl.is_wysiwyg = "true"; +defparam Clk_Ctrl.power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y18_N5 +dffeas \EE0[1]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[1]~18_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[1]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[1]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[1]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N10 +cycloneive_lcell_comb \Add1~25 ( +// Equation(s): +// \Add1~25_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[1]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[1]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[1]~input_o ), + .datac(\EE0[1]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~25_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~25 .lut_mask = 16'h0FCC; +defparam \Add1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N6 +cycloneive_lcell_comb \EE0[2]~20 ( +// Equation(s): +// \EE0[2]~20_combout = (\Add1~23_combout & ((\Add1~22_combout & (!\EE0[1]~19 )) # (!\Add1~22_combout & (\EE0[1]~19 & VCC)))) # (!\Add1~23_combout & ((\Add1~22_combout & ((\EE0[1]~19 ) # (GND))) # (!\Add1~22_combout & (!\EE0[1]~19 )))) +// \EE0[2]~21 = CARRY((\Add1~23_combout & (\Add1~22_combout & !\EE0[1]~19 )) # (!\Add1~23_combout & ((\Add1~22_combout ) # (!\EE0[1]~19 )))) + + .dataa(\Add1~23_combout ), + .datab(\Add1~22_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[1]~19 ), + .combout(\EE0[2]~20_combout ), + .cout(\EE0[2]~21 )); +// synopsys translate_off +defparam \EE0[2]~20 .lut_mask = 16'h694D; +defparam \EE0[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N7 +dffeas \EE0[2]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[2]~20_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[2]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[2]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[2]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N30 +cycloneive_lcell_comb \Add1~23 ( +// Equation(s): +// \Add1~23_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[2]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[2]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[2]~input_o ), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[2]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~23_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~23 .lut_mask = 16'h0CFC; +defparam \Add1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N8 +cycloneive_lcell_comb \EE0[3]~22 ( +// Equation(s): +// \EE0[3]~22_combout = ((\Add1~20_combout $ (\Add1~21_combout $ (\EE0[2]~21 )))) # (GND) +// \EE0[3]~23 = CARRY((\Add1~20_combout & (\Add1~21_combout & !\EE0[2]~21 )) # (!\Add1~20_combout & ((\Add1~21_combout ) # (!\EE0[2]~21 )))) + + .dataa(\Add1~20_combout ), + .datab(\Add1~21_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[2]~21 ), + .combout(\EE0[3]~22_combout ), + .cout(\EE0[3]~23 )); +// synopsys translate_off +defparam \EE0[3]~22 .lut_mask = 16'h964D; +defparam \EE0[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N9 +dffeas \EE0[3]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[3]~22_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[3]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[3]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[3]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N15 +cycloneive_io_ibuf \SetPoint[3]~input ( + .i(SetPoint[3]), + .ibar(gnd), + .o(\SetPoint[3]~input_o )); +// synopsys translate_off +defparam \SetPoint[3]~input .bus_hold = "false"; +defparam \SetPoint[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N28 +cycloneive_lcell_comb \Add1~21 ( +// Equation(s): +// \Add1~21_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[3]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[3]~input_o ))) + + .dataa(\EE0[3]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[3]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~21_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~21 .lut_mask = 16'h55F0; +defparam \Add1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N10 +cycloneive_lcell_comb \EE0[4]~24 ( +// Equation(s): +// \EE0[4]~24_combout = (\Add1~19_combout & ((\Add1~18_combout & (!\EE0[3]~23 )) # (!\Add1~18_combout & (\EE0[3]~23 & VCC)))) # (!\Add1~19_combout & ((\Add1~18_combout & ((\EE0[3]~23 ) # (GND))) # (!\Add1~18_combout & (!\EE0[3]~23 )))) +// \EE0[4]~25 = CARRY((\Add1~19_combout & (\Add1~18_combout & !\EE0[3]~23 )) # (!\Add1~19_combout & ((\Add1~18_combout ) # (!\EE0[3]~23 )))) + + .dataa(\Add1~19_combout ), + .datab(\Add1~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[3]~23 ), + .combout(\EE0[4]~24_combout ), + .cout(\EE0[4]~25 )); +// synopsys translate_off +defparam \EE0[4]~24 .lut_mask = 16'h694D; +defparam \EE0[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N11 +dffeas \EE0[4]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[4]~24_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[4]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[4]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[4]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N22 +cycloneive_lcell_comb \Add1~19 ( +// Equation(s): +// \Add1~19_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[4]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[4]~input_o )) + + .dataa(\SetPoint[4]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[4]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~19 .lut_mask = 16'h0AFA; +defparam \Add1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N12 +cycloneive_lcell_comb \EE0[5]~26 ( +// Equation(s): +// \EE0[5]~26_combout = ((\Add1~16_combout $ (\Add1~17_combout $ (\EE0[4]~25 )))) # (GND) +// \EE0[5]~27 = CARRY((\Add1~16_combout & (\Add1~17_combout & !\EE0[4]~25 )) # (!\Add1~16_combout & ((\Add1~17_combout ) # (!\EE0[4]~25 )))) + + .dataa(\Add1~16_combout ), + .datab(\Add1~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[4]~25 ), + .combout(\EE0[5]~26_combout ), + .cout(\EE0[5]~27 )); +// synopsys translate_off +defparam \EE0[5]~26 .lut_mask = 16'h964D; +defparam \EE0[5]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N13 +dffeas \EE0[5]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[5]~26_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[5]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[5]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[5]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N8 +cycloneive_io_ibuf \SetPoint[5]~input ( + .i(SetPoint[5]), + .ibar(gnd), + .o(\SetPoint[5]~input_o )); +// synopsys translate_off +defparam \SetPoint[5]~input .bus_hold = "false"; +defparam \SetPoint[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N18 +cycloneive_lcell_comb \Add1~17 ( +// Equation(s): +// \Add1~17_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[5]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[5]~input_o ))) + + .dataa(\EE0[5]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[5]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~17 .lut_mask = 16'h55F0; +defparam \Add1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N14 +cycloneive_lcell_comb \EE0[6]~28 ( +// Equation(s): +// \EE0[6]~28_combout = (\Add1~15_combout & ((\Add1~14_combout & (!\EE0[5]~27 )) # (!\Add1~14_combout & (\EE0[5]~27 & VCC)))) # (!\Add1~15_combout & ((\Add1~14_combout & ((\EE0[5]~27 ) # (GND))) # (!\Add1~14_combout & (!\EE0[5]~27 )))) +// \EE0[6]~29 = CARRY((\Add1~15_combout & (\Add1~14_combout & !\EE0[5]~27 )) # (!\Add1~15_combout & ((\Add1~14_combout ) # (!\EE0[5]~27 )))) + + .dataa(\Add1~15_combout ), + .datab(\Add1~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[5]~27 ), + .combout(\EE0[6]~28_combout ), + .cout(\EE0[6]~29 )); +// synopsys translate_off +defparam \EE0[6]~28 .lut_mask = 16'h694D; +defparam \EE0[6]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N15 +dffeas \EE0[6]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[6]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[6]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[6]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[6]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N20 +cycloneive_lcell_comb \Add1~15 ( +// Equation(s): +// \Add1~15_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[6]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[6]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[6]~input_o ), + .datad(\EE0[6]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~15_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~15 .lut_mask = 16'h30FC; +defparam \Add1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N16 +cycloneive_lcell_comb \EE0[7]~30 ( +// Equation(s): +// \EE0[7]~30_combout = ((\Add1~12_combout $ (\Add1~13_combout $ (\EE0[6]~29 )))) # (GND) +// \EE0[7]~31 = CARRY((\Add1~12_combout & (\Add1~13_combout & !\EE0[6]~29 )) # (!\Add1~12_combout & ((\Add1~13_combout ) # (!\EE0[6]~29 )))) + + .dataa(\Add1~12_combout ), + .datab(\Add1~13_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[6]~29 ), + .combout(\EE0[7]~30_combout ), + .cout(\EE0[7]~31 )); +// synopsys translate_off +defparam \EE0[7]~30 .lut_mask = 16'h964D; +defparam \EE0[7]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N17 +dffeas \EE0[7]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[7]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[7]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[7]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[7]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N24 +cycloneive_lcell_comb \Add1~13 ( +// Equation(s): +// \Add1~13_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[7]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[7]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[7]~input_o ), + .datac(\EE0[7]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~13_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~13 .lut_mask = 16'h0FCC; +defparam \Add1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N18 +cycloneive_lcell_comb \EE0[8]~32 ( +// Equation(s): +// \EE0[8]~32_combout = (\Add1~11_combout & ((\Add1~10_combout & (!\EE0[7]~31 )) # (!\Add1~10_combout & (\EE0[7]~31 & VCC)))) # (!\Add1~11_combout & ((\Add1~10_combout & ((\EE0[7]~31 ) # (GND))) # (!\Add1~10_combout & (!\EE0[7]~31 )))) +// \EE0[8]~33 = CARRY((\Add1~11_combout & (\Add1~10_combout & !\EE0[7]~31 )) # (!\Add1~11_combout & ((\Add1~10_combout ) # (!\EE0[7]~31 )))) + + .dataa(\Add1~11_combout ), + .datab(\Add1~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[7]~31 ), + .combout(\EE0[8]~32_combout ), + .cout(\EE0[8]~33 )); +// synopsys translate_off +defparam \EE0[8]~32 .lut_mask = 16'h694D; +defparam \EE0[8]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N19 +dffeas \EE0[8]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[8]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[8]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[8]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[8]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N30 +cycloneive_lcell_comb \Add1~11 ( +// Equation(s): +// \Add1~11_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[8]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[8]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[8]~input_o ), + .datad(\EE0[8]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~11_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~11 .lut_mask = 16'h30FC; +defparam \Add1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N20 +cycloneive_lcell_comb \EE0[9]~34 ( +// Equation(s): +// \EE0[9]~34_combout = ((\Add1~8_combout $ (\Add1~9_combout $ (\EE0[8]~33 )))) # (GND) +// \EE0[9]~35 = CARRY((\Add1~8_combout & (\Add1~9_combout & !\EE0[8]~33 )) # (!\Add1~8_combout & ((\Add1~9_combout ) # (!\EE0[8]~33 )))) + + .dataa(\Add1~8_combout ), + .datab(\Add1~9_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[8]~33 ), + .combout(\EE0[9]~34_combout ), + .cout(\EE0[9]~35 )); +// synopsys translate_off +defparam \EE0[9]~34 .lut_mask = 16'h964D; +defparam \EE0[9]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N21 +dffeas \EE0[9]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[9]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[9]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[9]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[9]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N8 +cycloneive_lcell_comb \Add1~9 ( +// Equation(s): +// \Add1~9_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[9]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[9]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[9]~input_o ), + .datad(\EE0[9]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~9_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~9 .lut_mask = 16'h30FC; +defparam \Add1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N22 +cycloneive_lcell_comb \EE0[10]~36 ( +// Equation(s): +// \EE0[10]~36_combout = (\Add1~7_combout & ((\Add1~6_combout & (!\EE0[9]~35 )) # (!\Add1~6_combout & (\EE0[9]~35 & VCC)))) # (!\Add1~7_combout & ((\Add1~6_combout & ((\EE0[9]~35 ) # (GND))) # (!\Add1~6_combout & (!\EE0[9]~35 )))) +// \EE0[10]~37 = CARRY((\Add1~7_combout & (\Add1~6_combout & !\EE0[9]~35 )) # (!\Add1~7_combout & ((\Add1~6_combout ) # (!\EE0[9]~35 )))) + + .dataa(\Add1~7_combout ), + .datab(\Add1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[9]~35 ), + .combout(\EE0[10]~36_combout ), + .cout(\EE0[10]~37 )); +// synopsys translate_off +defparam \EE0[10]~36 .lut_mask = 16'h694D; +defparam \EE0[10]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N23 +dffeas \EE0[10]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[10]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[10]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[10]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[10]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N26 +cycloneive_lcell_comb \Add1~7 ( +// Equation(s): +// \Add1~7_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[10]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[10]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[10]~input_o ), + .datad(\EE0[10]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~7_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~7 .lut_mask = 16'h30FC; +defparam \Add1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N24 +cycloneive_lcell_comb \EE0[11]~38 ( +// Equation(s): +// \EE0[11]~38_combout = ((\Add1~4_combout $ (\Add1~5_combout $ (\EE0[10]~37 )))) # (GND) +// \EE0[11]~39 = CARRY((\Add1~4_combout & (\Add1~5_combout & !\EE0[10]~37 )) # (!\Add1~4_combout & ((\Add1~5_combout ) # (!\EE0[10]~37 )))) + + .dataa(\Add1~4_combout ), + .datab(\Add1~5_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[10]~37 ), + .combout(\EE0[11]~38_combout ), + .cout(\EE0[11]~39 )); +// synopsys translate_off +defparam \EE0[11]~38 .lut_mask = 16'h964D; +defparam \EE0[11]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N25 +dffeas \EE0[11]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[11]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[11]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[11]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[11]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \Add1~5 ( +// Equation(s): +// \Add1~5_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[11]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[11]~input_o )) + + .dataa(\SetPoint[11]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[11]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~5_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~5 .lut_mask = 16'h0AFA; +defparam \Add1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N26 +cycloneive_lcell_comb \EE0[12]~40 ( +// Equation(s): +// \EE0[12]~40_combout = (\Add1~2_combout & ((\Add1~3_combout & (!\EE0[11]~39 )) # (!\Add1~3_combout & ((\EE0[11]~39 ) # (GND))))) # (!\Add1~2_combout & ((\Add1~3_combout & (\EE0[11]~39 & VCC)) # (!\Add1~3_combout & (!\EE0[11]~39 )))) +// \EE0[12]~41 = CARRY((\Add1~2_combout & ((!\EE0[11]~39 ) # (!\Add1~3_combout ))) # (!\Add1~2_combout & (!\Add1~3_combout & !\EE0[11]~39 ))) + + .dataa(\Add1~2_combout ), + .datab(\Add1~3_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[11]~39 ), + .combout(\EE0[12]~40_combout ), + .cout(\EE0[12]~41 )); +// synopsys translate_off +defparam \EE0[12]~40 .lut_mask = 16'h692B; +defparam \EE0[12]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N27 +dffeas \EE0[12]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[12]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[12]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[12]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[12]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N0 +cycloneive_lcell_comb \Add1~3 ( +// Equation(s): +// \Add1~3_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[12]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[12]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[12]~input_o ), + .datac(\EE0[12]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~3_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~3 .lut_mask = 16'h0FCC; +defparam \Add1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N28 +cycloneive_lcell_comb \EE0[13]~42 ( +// Equation(s): +// \EE0[13]~42_combout = \Add1~1_combout $ (\EE0[12]~41 $ (\Add1~0_combout )) + + .dataa(gnd), + .datab(\Add1~1_combout ), + .datac(gnd), + .datad(\Add1~0_combout ), + .cin(\EE0[12]~41 ), + .combout(\EE0[13]~42_combout ), + .cout()); +// synopsys translate_off +defparam \EE0[13]~42 .lut_mask = 16'hC33C; +defparam \EE0[13]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N31 +dffeas \EE0[13]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\EE0[13]~42_combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[13]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[13]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[13]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N2 +cycloneive_lcell_comb \Add1~27 ( +// Equation(s): +// \Add1~27_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[0]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[0]~input_o ))) + + .dataa(\EE0[0]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[0]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~27_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~27 .lut_mask = 16'h55F0; +defparam \Add1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y18_N3 +dffeas \EE0[0]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[0]~16_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[0]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[0]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[0]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N4 +cycloneive_lcell_comb \EE1[1]~16 ( +// Equation(s): +// \EE1[1]~16_combout = (EE1[1] & ((\EE1[0]~15 ) # (GND))) # (!EE1[1] & (!\EE1[0]~15 )) +// \EE1[1]~17 = CARRY((EE1[1]) # (!\EE1[0]~15 )) + + .dataa(gnd), + .datab(EE1[1]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[0]~15 ), + .combout(\EE1[1]~16_combout ), + .cout(\EE1[1]~17 )); +// synopsys translate_off +defparam \EE1[1]~16 .lut_mask = 16'hC3CF; +defparam \EE1[1]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N5 +dffeas \EE1[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[1]~16_combout ), + .asdata(\EE0[1]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[1]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[1] .is_wysiwyg = "true"; +defparam \EE1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N6 +cycloneive_lcell_comb \EE1[2]~18 ( +// Equation(s): +// \EE1[2]~18_combout = (EE1[2] & (!\EE1[1]~17 & VCC)) # (!EE1[2] & (\EE1[1]~17 $ (GND))) +// \EE1[2]~19 = CARRY((!EE1[2] & !\EE1[1]~17 )) + + .dataa(EE1[2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[1]~17 ), + .combout(\EE1[2]~18_combout ), + .cout(\EE1[2]~19 )); +// synopsys translate_off +defparam \EE1[2]~18 .lut_mask = 16'h5A05; +defparam \EE1[2]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N7 +dffeas \EE1[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[2]~18_combout ), + .asdata(\EE0[2]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[2]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[2] .is_wysiwyg = "true"; +defparam \EE1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N8 +cycloneive_lcell_comb \EE1[3]~20 ( +// Equation(s): +// \EE1[3]~20_combout = (EE1[3] & ((\EE1[2]~19 ) # (GND))) # (!EE1[3] & (!\EE1[2]~19 )) +// \EE1[3]~21 = CARRY((EE1[3]) # (!\EE1[2]~19 )) + + .dataa(gnd), + .datab(EE1[3]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[2]~19 ), + .combout(\EE1[3]~20_combout ), + .cout(\EE1[3]~21 )); +// synopsys translate_off +defparam \EE1[3]~20 .lut_mask = 16'hC3CF; +defparam \EE1[3]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N9 +dffeas \EE1[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[3]~20_combout ), + .asdata(\EE0[3]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[3]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[3] .is_wysiwyg = "true"; +defparam \EE1[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N10 +cycloneive_lcell_comb \EE1[4]~22 ( +// Equation(s): +// \EE1[4]~22_combout = (EE1[4] & (!\EE1[3]~21 & VCC)) # (!EE1[4] & (\EE1[3]~21 $ (GND))) +// \EE1[4]~23 = CARRY((!EE1[4] & !\EE1[3]~21 )) + + .dataa(EE1[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[3]~21 ), + .combout(\EE1[4]~22_combout ), + .cout(\EE1[4]~23 )); +// synopsys translate_off +defparam \EE1[4]~22 .lut_mask = 16'h5A05; +defparam \EE1[4]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N11 +dffeas \EE1[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[4]~22_combout ), + .asdata(\EE0[4]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[4]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[4] .is_wysiwyg = "true"; +defparam \EE1[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N12 +cycloneive_lcell_comb \EE1[5]~24 ( +// Equation(s): +// \EE1[5]~24_combout = (EE1[5] & ((\EE1[4]~23 ) # (GND))) # (!EE1[5] & (!\EE1[4]~23 )) +// \EE1[5]~25 = CARRY((EE1[5]) # (!\EE1[4]~23 )) + + .dataa(EE1[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[4]~23 ), + .combout(\EE1[5]~24_combout ), + .cout(\EE1[5]~25 )); +// synopsys translate_off +defparam \EE1[5]~24 .lut_mask = 16'hA5AF; +defparam \EE1[5]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N13 +dffeas \EE1[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[5]~24_combout ), + .asdata(\EE0[5]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[5]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[5] .is_wysiwyg = "true"; +defparam \EE1[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N14 +cycloneive_lcell_comb \EE1[6]~26 ( +// Equation(s): +// \EE1[6]~26_combout = (EE1[6] & (!\EE1[5]~25 & VCC)) # (!EE1[6] & (\EE1[5]~25 $ (GND))) +// \EE1[6]~27 = CARRY((!EE1[6] & !\EE1[5]~25 )) + + .dataa(gnd), + .datab(EE1[6]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[5]~25 ), + .combout(\EE1[6]~26_combout ), + .cout(\EE1[6]~27 )); +// synopsys translate_off +defparam \EE1[6]~26 .lut_mask = 16'h3C03; +defparam \EE1[6]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N15 +dffeas \EE1[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[6]~26_combout ), + .asdata(\EE0[6]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[6]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[6] .is_wysiwyg = "true"; +defparam \EE1[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N16 +cycloneive_lcell_comb \EE1[7]~28 ( +// Equation(s): +// \EE1[7]~28_combout = (EE1[7] & ((\EE1[6]~27 ) # (GND))) # (!EE1[7] & (!\EE1[6]~27 )) +// \EE1[7]~29 = CARRY((EE1[7]) # (!\EE1[6]~27 )) + + .dataa(gnd), + .datab(EE1[7]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[6]~27 ), + .combout(\EE1[7]~28_combout ), + .cout(\EE1[7]~29 )); +// synopsys translate_off +defparam \EE1[7]~28 .lut_mask = 16'hC3CF; +defparam \EE1[7]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N17 +dffeas \EE1[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[7]~28_combout ), + .asdata(\EE0[7]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[7]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[7] .is_wysiwyg = "true"; +defparam \EE1[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N18 +cycloneive_lcell_comb \EE1[8]~30 ( +// Equation(s): +// \EE1[8]~30_combout = (EE1[8] & (!\EE1[7]~29 & VCC)) # (!EE1[8] & (\EE1[7]~29 $ (GND))) +// \EE1[8]~31 = CARRY((!EE1[8] & !\EE1[7]~29 )) + + .dataa(gnd), + .datab(EE1[8]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[7]~29 ), + .combout(\EE1[8]~30_combout ), + .cout(\EE1[8]~31 )); +// synopsys translate_off +defparam \EE1[8]~30 .lut_mask = 16'h3C03; +defparam \EE1[8]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N19 +dffeas \EE1[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[8]~30_combout ), + .asdata(\EE0[8]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[8]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[8] .is_wysiwyg = "true"; +defparam \EE1[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N20 +cycloneive_lcell_comb \EE1[9]~32 ( +// Equation(s): +// \EE1[9]~32_combout = (EE1[9] & ((\EE1[8]~31 ) # (GND))) # (!EE1[9] & (!\EE1[8]~31 )) +// \EE1[9]~33 = CARRY((EE1[9]) # (!\EE1[8]~31 )) + + .dataa(gnd), + .datab(EE1[9]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[8]~31 ), + .combout(\EE1[9]~32_combout ), + .cout(\EE1[9]~33 )); +// synopsys translate_off +defparam \EE1[9]~32 .lut_mask = 16'hC3CF; +defparam \EE1[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N21 +dffeas \EE1[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[9]~32_combout ), + .asdata(\EE0[9]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[9]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[9] .is_wysiwyg = "true"; +defparam \EE1[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N22 +cycloneive_lcell_comb \EE1[10]~34 ( +// Equation(s): +// \EE1[10]~34_combout = (EE1[10] & (!\EE1[9]~33 & VCC)) # (!EE1[10] & (\EE1[9]~33 $ (GND))) +// \EE1[10]~35 = CARRY((!EE1[10] & !\EE1[9]~33 )) + + .dataa(EE1[10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[9]~33 ), + .combout(\EE1[10]~34_combout ), + .cout(\EE1[10]~35 )); +// synopsys translate_off +defparam \EE1[10]~34 .lut_mask = 16'h5A05; +defparam \EE1[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N23 +dffeas \EE1[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[10]~34_combout ), + .asdata(\EE0[10]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[10]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[10] .is_wysiwyg = "true"; +defparam \EE1[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N24 +cycloneive_lcell_comb \EE1[11]~36 ( +// Equation(s): +// \EE1[11]~36_combout = (EE1[11] & ((\EE1[10]~35 ) # (GND))) # (!EE1[11] & (!\EE1[10]~35 )) +// \EE1[11]~37 = CARRY((EE1[11]) # (!\EE1[10]~35 )) + + .dataa(gnd), + .datab(EE1[11]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[10]~35 ), + .combout(\EE1[11]~36_combout ), + .cout(\EE1[11]~37 )); +// synopsys translate_off +defparam \EE1[11]~36 .lut_mask = 16'hC3CF; +defparam \EE1[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N25 +dffeas \EE1[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[11]~36_combout ), + .asdata(\EE0[11]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[11]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[11] .is_wysiwyg = "true"; +defparam \EE1[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N26 +cycloneive_lcell_comb \EE1[12]~38 ( +// Equation(s): +// \EE1[12]~38_combout = (EE1[12] & (!\EE1[11]~37 & VCC)) # (!EE1[12] & (\EE1[11]~37 $ (GND))) +// \EE1[12]~39 = CARRY((!EE1[12] & !\EE1[11]~37 )) + + .dataa(EE1[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[11]~37 ), + .combout(\EE1[12]~38_combout ), + .cout(\EE1[12]~39 )); +// synopsys translate_off +defparam \EE1[12]~38 .lut_mask = 16'h5A05; +defparam \EE1[12]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N27 +dffeas \EE1[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[12]~38_combout ), + .asdata(\EE0[12]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[12]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[12] .is_wysiwyg = "true"; +defparam \EE1[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N28 +cycloneive_lcell_comb \EE1[13]~40 ( +// Equation(s): +// \EE1[13]~40_combout = \EE1[12]~39 $ (!EE1[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(EE1[13]), + .cin(\EE1[12]~39 ), + .combout(\EE1[13]~40_combout ), + .cout()); +// synopsys translate_off +defparam \EE1[13]~40 .lut_mask = 16'hF00F; +defparam \EE1[13]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N29 +dffeas \EE1[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[13]~40_combout ), + .asdata(\EE0[13]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[13]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[13] .is_wysiwyg = "true"; +defparam \EE1[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y17_N3 +dffeas \EE1[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[0]~14_combout ), + .asdata(\EE0[0]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[0]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[0] .is_wysiwyg = "true"; +defparam \EE1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N6 +cycloneive_lcell_comb \EE2[1]~16 ( +// Equation(s): +// \EE2[1]~16_combout = (EE2[1] & ((\EE2[0]~15 ) # (GND))) # (!EE2[1] & (!\EE2[0]~15 )) +// \EE2[1]~17 = CARRY((EE2[1]) # (!\EE2[0]~15 )) + + .dataa(EE2[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[0]~15 ), + .combout(\EE2[1]~16_combout ), + .cout(\EE2[1]~17 )); +// synopsys translate_off +defparam \EE2[1]~16 .lut_mask = 16'hA5AF; +defparam \EE2[1]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N7 +dffeas \EE2[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[1]~16_combout ), + .asdata(EE1[1]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[1]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[1] .is_wysiwyg = "true"; +defparam \EE2[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \EE2[2]~18 ( +// Equation(s): +// \EE2[2]~18_combout = (EE2[2] & (!\EE2[1]~17 & VCC)) # (!EE2[2] & (\EE2[1]~17 $ (GND))) +// \EE2[2]~19 = CARRY((!EE2[2] & !\EE2[1]~17 )) + + .dataa(gnd), + .datab(EE2[2]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[1]~17 ), + .combout(\EE2[2]~18_combout ), + .cout(\EE2[2]~19 )); +// synopsys translate_off +defparam \EE2[2]~18 .lut_mask = 16'h3C03; +defparam \EE2[2]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N9 +dffeas \EE2[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[2]~18_combout ), + .asdata(EE1[2]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[2]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[2] .is_wysiwyg = "true"; +defparam \EE2[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 +cycloneive_lcell_comb \EE2[3]~20 ( +// Equation(s): +// \EE2[3]~20_combout = (EE2[3] & ((\EE2[2]~19 ) # (GND))) # (!EE2[3] & (!\EE2[2]~19 )) +// \EE2[3]~21 = CARRY((EE2[3]) # (!\EE2[2]~19 )) + + .dataa(EE2[3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[2]~19 ), + .combout(\EE2[3]~20_combout ), + .cout(\EE2[3]~21 )); +// synopsys translate_off +defparam \EE2[3]~20 .lut_mask = 16'hA5AF; +defparam \EE2[3]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N11 +dffeas \EE2[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[3]~20_combout ), + .asdata(EE1[3]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[3]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[3] .is_wysiwyg = "true"; +defparam \EE2[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N12 +cycloneive_lcell_comb \EE2[4]~22 ( +// Equation(s): +// \EE2[4]~22_combout = (EE2[4] & (!\EE2[3]~21 & VCC)) # (!EE2[4] & (\EE2[3]~21 $ (GND))) +// \EE2[4]~23 = CARRY((!EE2[4] & !\EE2[3]~21 )) + + .dataa(EE2[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[3]~21 ), + .combout(\EE2[4]~22_combout ), + .cout(\EE2[4]~23 )); +// synopsys translate_off +defparam \EE2[4]~22 .lut_mask = 16'h5A05; +defparam \EE2[4]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N13 +dffeas \EE2[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[4]~22_combout ), + .asdata(EE1[4]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[4]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[4] .is_wysiwyg = "true"; +defparam \EE2[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \EE2[5]~24 ( +// Equation(s): +// \EE2[5]~24_combout = (EE2[5] & ((\EE2[4]~23 ) # (GND))) # (!EE2[5] & (!\EE2[4]~23 )) +// \EE2[5]~25 = CARRY((EE2[5]) # (!\EE2[4]~23 )) + + .dataa(gnd), + .datab(EE2[5]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[4]~23 ), + .combout(\EE2[5]~24_combout ), + .cout(\EE2[5]~25 )); +// synopsys translate_off +defparam \EE2[5]~24 .lut_mask = 16'hC3CF; +defparam \EE2[5]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N15 +dffeas \EE2[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[5]~24_combout ), + .asdata(EE1[5]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[5]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[5] .is_wysiwyg = "true"; +defparam \EE2[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \EE2[6]~26 ( +// Equation(s): +// \EE2[6]~26_combout = (EE2[6] & (!\EE2[5]~25 & VCC)) # (!EE2[6] & (\EE2[5]~25 $ (GND))) +// \EE2[6]~27 = CARRY((!EE2[6] & !\EE2[5]~25 )) + + .dataa(gnd), + .datab(EE2[6]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[5]~25 ), + .combout(\EE2[6]~26_combout ), + .cout(\EE2[6]~27 )); +// synopsys translate_off +defparam \EE2[6]~26 .lut_mask = 16'h3C03; +defparam \EE2[6]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N17 +dffeas \EE2[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[6]~26_combout ), + .asdata(EE1[6]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[6]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[6] .is_wysiwyg = "true"; +defparam \EE2[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \EE2[7]~28 ( +// Equation(s): +// \EE2[7]~28_combout = (EE2[7] & ((\EE2[6]~27 ) # (GND))) # (!EE2[7] & (!\EE2[6]~27 )) +// \EE2[7]~29 = CARRY((EE2[7]) # (!\EE2[6]~27 )) + + .dataa(gnd), + .datab(EE2[7]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[6]~27 ), + .combout(\EE2[7]~28_combout ), + .cout(\EE2[7]~29 )); +// synopsys translate_off +defparam \EE2[7]~28 .lut_mask = 16'hC3CF; +defparam \EE2[7]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N19 +dffeas \EE2[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[7]~28_combout ), + .asdata(EE1[7]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[7]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[7] .is_wysiwyg = "true"; +defparam \EE2[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \EE2[8]~30 ( +// Equation(s): +// \EE2[8]~30_combout = (EE2[8] & (!\EE2[7]~29 & VCC)) # (!EE2[8] & (\EE2[7]~29 $ (GND))) +// \EE2[8]~31 = CARRY((!EE2[8] & !\EE2[7]~29 )) + + .dataa(gnd), + .datab(EE2[8]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[7]~29 ), + .combout(\EE2[8]~30_combout ), + .cout(\EE2[8]~31 )); +// synopsys translate_off +defparam \EE2[8]~30 .lut_mask = 16'h3C03; +defparam \EE2[8]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N21 +dffeas \EE2[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[8]~30_combout ), + .asdata(EE1[8]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[8]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[8] .is_wysiwyg = "true"; +defparam \EE2[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N22 +cycloneive_lcell_comb \EE2[9]~32 ( +// Equation(s): +// \EE2[9]~32_combout = (EE2[9] & ((\EE2[8]~31 ) # (GND))) # (!EE2[9] & (!\EE2[8]~31 )) +// \EE2[9]~33 = CARRY((EE2[9]) # (!\EE2[8]~31 )) + + .dataa(EE2[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[8]~31 ), + .combout(\EE2[9]~32_combout ), + .cout(\EE2[9]~33 )); +// synopsys translate_off +defparam \EE2[9]~32 .lut_mask = 16'hA5AF; +defparam \EE2[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N23 +dffeas \EE2[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[9]~32_combout ), + .asdata(EE1[9]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[9]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[9] .is_wysiwyg = "true"; +defparam \EE2[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \EE2[10]~34 ( +// Equation(s): +// \EE2[10]~34_combout = (EE2[10] & (!\EE2[9]~33 & VCC)) # (!EE2[10] & (\EE2[9]~33 $ (GND))) +// \EE2[10]~35 = CARRY((!EE2[10] & !\EE2[9]~33 )) + + .dataa(gnd), + .datab(EE2[10]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[9]~33 ), + .combout(\EE2[10]~34_combout ), + .cout(\EE2[10]~35 )); +// synopsys translate_off +defparam \EE2[10]~34 .lut_mask = 16'h3C03; +defparam \EE2[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N25 +dffeas \EE2[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[10]~34_combout ), + .asdata(EE1[10]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[10]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[10] .is_wysiwyg = "true"; +defparam \EE2[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \EE2[11]~36 ( +// Equation(s): +// \EE2[11]~36_combout = (EE2[11] & ((\EE2[10]~35 ) # (GND))) # (!EE2[11] & (!\EE2[10]~35 )) +// \EE2[11]~37 = CARRY((EE2[11]) # (!\EE2[10]~35 )) + + .dataa(EE2[11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[10]~35 ), + .combout(\EE2[11]~36_combout ), + .cout(\EE2[11]~37 )); +// synopsys translate_off +defparam \EE2[11]~36 .lut_mask = 16'hA5AF; +defparam \EE2[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N27 +dffeas \EE2[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[11]~36_combout ), + .asdata(EE1[11]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[11]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[11] .is_wysiwyg = "true"; +defparam \EE2[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \EE2[12]~38 ( +// Equation(s): +// \EE2[12]~38_combout = (EE2[12] & (!\EE2[11]~37 & VCC)) # (!EE2[12] & (\EE2[11]~37 $ (GND))) +// \EE2[12]~39 = CARRY((!EE2[12] & !\EE2[11]~37 )) + + .dataa(gnd), + .datab(EE2[12]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[11]~37 ), + .combout(\EE2[12]~38_combout ), + .cout(\EE2[12]~39 )); +// synopsys translate_off +defparam \EE2[12]~38 .lut_mask = 16'h3C03; +defparam \EE2[12]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N29 +dffeas \EE2[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[12]~38_combout ), + .asdata(EE1[12]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[12]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[12] .is_wysiwyg = "true"; +defparam \EE2[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 +cycloneive_lcell_comb \EE2[13]~40 ( +// Equation(s): +// \EE2[13]~40_combout = EE2[13] $ (!\EE2[12]~39 ) + + .dataa(EE2[13]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\EE2[12]~39 ), + .combout(\EE2[13]~40_combout ), + .cout()); +// synopsys translate_off +defparam \EE2[13]~40 .lut_mask = 16'hA5A5; +defparam \EE2[13]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N31 +dffeas \EE2[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[13]~40_combout ), + .asdata(EE1[13]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[13]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[13] .is_wysiwyg = "true"; +defparam \EE2[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y14_N5 +dffeas \EE2[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[0]~14_combout ), + .asdata(EE1[0]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[0]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[0] .is_wysiwyg = "true"; +defparam \EE2[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N15 +cycloneive_io_ibuf \Kd[0]~input ( + .i(Kd[0]), + .ibar(gnd), + .o(\Kd[0]~input_o )); +// synopsys translate_off +defparam \Kd[0]~input .bus_hold = "false"; +defparam \Kd[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N8 +cycloneive_io_ibuf \Kd[1]~input ( + .i(Kd[1]), + .ibar(gnd), + .o(\Kd[1]~input_o )); +// synopsys translate_off +defparam \Kd[1]~input .bus_hold = "false"; +defparam \Kd[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N1 +cycloneive_io_ibuf \Kd[2]~input ( + .i(Kd[2]), + .ibar(gnd), + .o(\Kd[2]~input_o )); +// synopsys translate_off +defparam \Kd[2]~input .bus_hold = "false"; +defparam \Kd[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N15 +cycloneive_io_ibuf \Kd[3]~input ( + .i(Kd[3]), + .ibar(gnd), + .o(\Kd[3]~input_o )); +// synopsys translate_off +defparam \Kd[3]~input .bus_hold = "false"; +defparam \Kd[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N8 +cycloneive_io_ibuf \Kd[4]~input ( + .i(Kd[4]), + .ibar(gnd), + .o(\Kd[4]~input_o )); +// synopsys translate_off +defparam \Kd[4]~input .bus_hold = "false"; +defparam \Kd[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N8 +cycloneive_io_ibuf \Kd[5]~input ( + .i(Kd[5]), + .ibar(gnd), + .o(\Kd[5]~input_o )); +// synopsys translate_off +defparam \Kd[5]~input .bus_hold = "false"; +defparam \Kd[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N1 +cycloneive_io_ibuf \Kd[6]~input ( + .i(Kd[6]), + .ibar(gnd), + .o(\Kd[6]~input_o )); +// synopsys translate_off +defparam \Kd[6]~input .bus_hold = "false"; +defparam \Kd[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N22 +cycloneive_io_ibuf \Kd[7]~input ( + .i(Kd[7]), + .ibar(gnd), + .o(\Kd[7]~input_o )); +// synopsys translate_off +defparam \Kd[7]~input .bus_hold = "false"; +defparam \Kd[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y14_N0 +cycloneive_mac_mult \Mult2|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({EE2[11],EE2[10],EE2[9],EE2[8],EE2[7],EE2[6],EE2[5],EE2[4],EE2[3],EE2[2],EE2[1],EE2[0],gnd,gnd,gnd,gnd,gnd,gnd}), + .datab({\Kd[7]~input_o ,\Kd[6]~input_o ,\Kd[5]~input_o ,\Kd[4]~input_o ,\Kd[3]~input_o ,\Kd[2]~input_o ,\Kd[1]~input_o ,\Kd[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult2|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult2|auto_generated|mac_mult1 .dataa_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult2|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult2|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y14_N2 +cycloneive_mac_out \Mult2|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult2|auto_generated|mac_mult1~DATAOUT19 ,\Mult2|auto_generated|mac_mult1~DATAOUT18 ,\Mult2|auto_generated|mac_mult1~DATAOUT17 ,\Mult2|auto_generated|mac_mult1~DATAOUT16 ,\Mult2|auto_generated|mac_mult1~DATAOUT15 ,\Mult2|auto_generated|mac_mult1~DATAOUT14 , +\Mult2|auto_generated|mac_mult1~DATAOUT13 ,\Mult2|auto_generated|mac_mult1~DATAOUT12 ,\Mult2|auto_generated|mac_mult1~DATAOUT11 ,\Mult2|auto_generated|mac_mult1~DATAOUT10 ,\Mult2|auto_generated|mac_mult1~DATAOUT9 ,\Mult2|auto_generated|mac_mult1~DATAOUT8 , +\Mult2|auto_generated|mac_mult1~DATAOUT7 ,\Mult2|auto_generated|mac_mult1~DATAOUT6 ,\Mult2|auto_generated|mac_mult1~DATAOUT5 ,\Mult2|auto_generated|mac_mult1~DATAOUT4 ,\Mult2|auto_generated|mac_mult1~DATAOUT3 ,\Mult2|auto_generated|mac_mult1~DATAOUT2 , +\Mult2|auto_generated|mac_mult1~DATAOUT1 ,\Mult2|auto_generated|mac_mult1~dataout ,\Mult2|auto_generated|mac_mult1~15 ,\Mult2|auto_generated|mac_mult1~14 ,\Mult2|auto_generated|mac_mult1~13 ,\Mult2|auto_generated|mac_mult1~12 ,\Mult2|auto_generated|mac_mult1~11 , +\Mult2|auto_generated|mac_mult1~10 ,\Mult2|auto_generated|mac_mult1~9 ,\Mult2|auto_generated|mac_mult1~8 ,\Mult2|auto_generated|mac_mult1~7 ,\Mult2|auto_generated|mac_mult1~6 ,\Mult2|auto_generated|mac_mult1~5 ,\Mult2|auto_generated|mac_mult1~4 , +\Mult2|auto_generated|mac_mult1~3 ,\Mult2|auto_generated|mac_mult1~2 ,\Mult2|auto_generated|mac_mult1~1 ,\Mult2|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult2|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult2|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult2|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y14_N13 +dffeas \Kd_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[0]~21_combout ), + .asdata(\Mult2|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[0] .is_wysiwyg = "true"; +defparam \Kd_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N14 +cycloneive_lcell_comb \Kd_Out[1]~23 ( +// Equation(s): +// \Kd_Out[1]~23_combout = (Kd_Out[1] & ((\Kd_Out[0]~22 ) # (GND))) # (!Kd_Out[1] & (!\Kd_Out[0]~22 )) +// \Kd_Out[1]~24 = CARRY((Kd_Out[1]) # (!\Kd_Out[0]~22 )) + + .dataa(gnd), + .datab(Kd_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[0]~22 ), + .combout(\Kd_Out[1]~23_combout ), + .cout(\Kd_Out[1]~24 )); +// synopsys translate_off +defparam \Kd_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Kd_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N15 +dffeas \Kd_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[1]~23_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[1] .is_wysiwyg = "true"; +defparam \Kd_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N16 +cycloneive_lcell_comb \Kd_Out[2]~25 ( +// Equation(s): +// \Kd_Out[2]~25_combout = (Kd_Out[2] & (!\Kd_Out[1]~24 & VCC)) # (!Kd_Out[2] & (\Kd_Out[1]~24 $ (GND))) +// \Kd_Out[2]~26 = CARRY((!Kd_Out[2] & !\Kd_Out[1]~24 )) + + .dataa(gnd), + .datab(Kd_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[1]~24 ), + .combout(\Kd_Out[2]~25_combout ), + .cout(\Kd_Out[2]~26 )); +// synopsys translate_off +defparam \Kd_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Kd_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N17 +dffeas \Kd_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[2]~25_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[2] .is_wysiwyg = "true"; +defparam \Kd_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N18 +cycloneive_lcell_comb \Kd_Out[3]~27 ( +// Equation(s): +// \Kd_Out[3]~27_combout = (Kd_Out[3] & ((\Kd_Out[2]~26 ) # (GND))) # (!Kd_Out[3] & (!\Kd_Out[2]~26 )) +// \Kd_Out[3]~28 = CARRY((Kd_Out[3]) # (!\Kd_Out[2]~26 )) + + .dataa(gnd), + .datab(Kd_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[2]~26 ), + .combout(\Kd_Out[3]~27_combout ), + .cout(\Kd_Out[3]~28 )); +// synopsys translate_off +defparam \Kd_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Kd_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N19 +dffeas \Kd_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[3]~27_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[3] .is_wysiwyg = "true"; +defparam \Kd_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N20 +cycloneive_lcell_comb \Kd_Out[4]~29 ( +// Equation(s): +// \Kd_Out[4]~29_combout = (Kd_Out[4] & (!\Kd_Out[3]~28 & VCC)) # (!Kd_Out[4] & (\Kd_Out[3]~28 $ (GND))) +// \Kd_Out[4]~30 = CARRY((!Kd_Out[4] & !\Kd_Out[3]~28 )) + + .dataa(gnd), + .datab(Kd_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[3]~28 ), + .combout(\Kd_Out[4]~29_combout ), + .cout(\Kd_Out[4]~30 )); +// synopsys translate_off +defparam \Kd_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Kd_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N21 +dffeas \Kd_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[4]~29_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[4] .is_wysiwyg = "true"; +defparam \Kd_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N22 +cycloneive_lcell_comb \Kd_Out[5]~31 ( +// Equation(s): +// \Kd_Out[5]~31_combout = (Kd_Out[5] & ((\Kd_Out[4]~30 ) # (GND))) # (!Kd_Out[5] & (!\Kd_Out[4]~30 )) +// \Kd_Out[5]~32 = CARRY((Kd_Out[5]) # (!\Kd_Out[4]~30 )) + + .dataa(Kd_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[4]~30 ), + .combout(\Kd_Out[5]~31_combout ), + .cout(\Kd_Out[5]~32 )); +// synopsys translate_off +defparam \Kd_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Kd_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N23 +dffeas \Kd_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[5]~31_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[5] .is_wysiwyg = "true"; +defparam \Kd_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N24 +cycloneive_lcell_comb \Kd_Out[6]~33 ( +// Equation(s): +// \Kd_Out[6]~33_combout = (Kd_Out[6] & (!\Kd_Out[5]~32 & VCC)) # (!Kd_Out[6] & (\Kd_Out[5]~32 $ (GND))) +// \Kd_Out[6]~34 = CARRY((!Kd_Out[6] & !\Kd_Out[5]~32 )) + + .dataa(gnd), + .datab(Kd_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[5]~32 ), + .combout(\Kd_Out[6]~33_combout ), + .cout(\Kd_Out[6]~34 )); +// synopsys translate_off +defparam \Kd_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Kd_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N25 +dffeas \Kd_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[6]~33_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[6] .is_wysiwyg = "true"; +defparam \Kd_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N26 +cycloneive_lcell_comb \Kd_Out[7]~35 ( +// Equation(s): +// \Kd_Out[7]~35_combout = (Kd_Out[7] & ((\Kd_Out[6]~34 ) # (GND))) # (!Kd_Out[7] & (!\Kd_Out[6]~34 )) +// \Kd_Out[7]~36 = CARRY((Kd_Out[7]) # (!\Kd_Out[6]~34 )) + + .dataa(Kd_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[6]~34 ), + .combout(\Kd_Out[7]~35_combout ), + .cout(\Kd_Out[7]~36 )); +// synopsys translate_off +defparam \Kd_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Kd_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N27 +dffeas \Kd_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[7]~35_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[7] .is_wysiwyg = "true"; +defparam \Kd_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N28 +cycloneive_lcell_comb \Kd_Out[8]~37 ( +// Equation(s): +// \Kd_Out[8]~37_combout = (Kd_Out[8] & (!\Kd_Out[7]~36 & VCC)) # (!Kd_Out[8] & (\Kd_Out[7]~36 $ (GND))) +// \Kd_Out[8]~38 = CARRY((!Kd_Out[8] & !\Kd_Out[7]~36 )) + + .dataa(gnd), + .datab(Kd_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[7]~36 ), + .combout(\Kd_Out[8]~37_combout ), + .cout(\Kd_Out[8]~38 )); +// synopsys translate_off +defparam \Kd_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Kd_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N29 +dffeas \Kd_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[8]~37_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[8] .is_wysiwyg = "true"; +defparam \Kd_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N30 +cycloneive_lcell_comb \Kd_Out[9]~39 ( +// Equation(s): +// \Kd_Out[9]~39_combout = (Kd_Out[9] & ((\Kd_Out[8]~38 ) # (GND))) # (!Kd_Out[9] & (!\Kd_Out[8]~38 )) +// \Kd_Out[9]~40 = CARRY((Kd_Out[9]) # (!\Kd_Out[8]~38 )) + + .dataa(Kd_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[8]~38 ), + .combout(\Kd_Out[9]~39_combout ), + .cout(\Kd_Out[9]~40 )); +// synopsys translate_off +defparam \Kd_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Kd_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N31 +dffeas \Kd_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[9]~39_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[9] .is_wysiwyg = "true"; +defparam \Kd_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N0 +cycloneive_lcell_comb \Kd_Out[10]~41 ( +// Equation(s): +// \Kd_Out[10]~41_combout = (Kd_Out[10] & (!\Kd_Out[9]~40 & VCC)) # (!Kd_Out[10] & (\Kd_Out[9]~40 $ (GND))) +// \Kd_Out[10]~42 = CARRY((!Kd_Out[10] & !\Kd_Out[9]~40 )) + + .dataa(gnd), + .datab(Kd_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[9]~40 ), + .combout(\Kd_Out[10]~41_combout ), + .cout(\Kd_Out[10]~42 )); +// synopsys translate_off +defparam \Kd_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Kd_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N1 +dffeas \Kd_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[10]~41_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[10] .is_wysiwyg = "true"; +defparam \Kd_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N2 +cycloneive_lcell_comb \Kd_Out[11]~43 ( +// Equation(s): +// \Kd_Out[11]~43_combout = (Kd_Out[11] & ((\Kd_Out[10]~42 ) # (GND))) # (!Kd_Out[11] & (!\Kd_Out[10]~42 )) +// \Kd_Out[11]~44 = CARRY((Kd_Out[11]) # (!\Kd_Out[10]~42 )) + + .dataa(gnd), + .datab(Kd_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[10]~42 ), + .combout(\Kd_Out[11]~43_combout ), + .cout(\Kd_Out[11]~44 )); +// synopsys translate_off +defparam \Kd_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Kd_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N0 +cycloneive_lcell_comb \Kd_Out[11]~feeder ( +// Equation(s): +// \Kd_Out[11]~feeder_combout = \Kd_Out[11]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[11]~43_combout ), + .cin(gnd), + .combout(\Kd_Out[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[11]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N1 +dffeas \Kd_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[11]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[11] .is_wysiwyg = "true"; +defparam \Kd_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N4 +cycloneive_lcell_comb \Kd_Out[12]~45 ( +// Equation(s): +// \Kd_Out[12]~45_combout = (Kd_Out[12] & (!\Kd_Out[11]~44 & VCC)) # (!Kd_Out[12] & (\Kd_Out[11]~44 $ (GND))) +// \Kd_Out[12]~46 = CARRY((!Kd_Out[12] & !\Kd_Out[11]~44 )) + + .dataa(gnd), + .datab(Kd_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[11]~44 ), + .combout(\Kd_Out[12]~45_combout ), + .cout(\Kd_Out[12]~46 )); +// synopsys translate_off +defparam \Kd_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Kd_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N5 +dffeas \Kd_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[12]~45_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[12] .is_wysiwyg = "true"; +defparam \Kd_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N6 +cycloneive_lcell_comb \Kd_Out[13]~47 ( +// Equation(s): +// \Kd_Out[13]~47_combout = (Kd_Out[13] & ((\Kd_Out[12]~46 ) # (GND))) # (!Kd_Out[13] & (!\Kd_Out[12]~46 )) +// \Kd_Out[13]~48 = CARRY((Kd_Out[13]) # (!\Kd_Out[12]~46 )) + + .dataa(Kd_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[12]~46 ), + .combout(\Kd_Out[13]~47_combout ), + .cout(\Kd_Out[13]~48 )); +// synopsys translate_off +defparam \Kd_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Kd_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N7 +dffeas \Kd_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[13]~47_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[13] .is_wysiwyg = "true"; +defparam \Kd_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N8 +cycloneive_lcell_comb \Kd_Out[14]~49 ( +// Equation(s): +// \Kd_Out[14]~49_combout = (Kd_Out[14] & (!\Kd_Out[13]~48 & VCC)) # (!Kd_Out[14] & (\Kd_Out[13]~48 $ (GND))) +// \Kd_Out[14]~50 = CARRY((!Kd_Out[14] & !\Kd_Out[13]~48 )) + + .dataa(gnd), + .datab(Kd_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[13]~48 ), + .combout(\Kd_Out[14]~49_combout ), + .cout(\Kd_Out[14]~50 )); +// synopsys translate_off +defparam \Kd_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Kd_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N6 +cycloneive_lcell_comb \Kd_Out[14]~feeder ( +// Equation(s): +// \Kd_Out[14]~feeder_combout = \Kd_Out[14]~49_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[14]~49_combout ), + .cin(gnd), + .combout(\Kd_Out[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[14]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N7 +dffeas \Kd_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[14]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[14] .is_wysiwyg = "true"; +defparam \Kd_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N10 +cycloneive_lcell_comb \Kd_Out[15]~51 ( +// Equation(s): +// \Kd_Out[15]~51_combout = (Kd_Out[15] & ((\Kd_Out[14]~50 ) # (GND))) # (!Kd_Out[15] & (!\Kd_Out[14]~50 )) +// \Kd_Out[15]~52 = CARRY((Kd_Out[15]) # (!\Kd_Out[14]~50 )) + + .dataa(Kd_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[14]~50 ), + .combout(\Kd_Out[15]~51_combout ), + .cout(\Kd_Out[15]~52 )); +// synopsys translate_off +defparam \Kd_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Kd_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N4 +cycloneive_lcell_comb \Kd_Out[15]~feeder ( +// Equation(s): +// \Kd_Out[15]~feeder_combout = \Kd_Out[15]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[15]~51_combout ), + .cin(gnd), + .combout(\Kd_Out[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[15]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N5 +dffeas \Kd_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[15]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[15] .is_wysiwyg = "true"; +defparam \Kd_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N12 +cycloneive_lcell_comb \Kd_Out[16]~53 ( +// Equation(s): +// \Kd_Out[16]~53_combout = (Kd_Out[16] & (!\Kd_Out[15]~52 & VCC)) # (!Kd_Out[16] & (\Kd_Out[15]~52 $ (GND))) +// \Kd_Out[16]~54 = CARRY((!Kd_Out[16] & !\Kd_Out[15]~52 )) + + .dataa(Kd_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[15]~52 ), + .combout(\Kd_Out[16]~53_combout ), + .cout(\Kd_Out[16]~54 )); +// synopsys translate_off +defparam \Kd_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Kd_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N13 +dffeas \Kd_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[16]~53_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[16] .is_wysiwyg = "true"; +defparam \Kd_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N14 +cycloneive_lcell_comb \Kd_Out[17]~55 ( +// Equation(s): +// \Kd_Out[17]~55_combout = (Kd_Out[17] & ((\Kd_Out[16]~54 ) # (GND))) # (!Kd_Out[17] & (!\Kd_Out[16]~54 )) +// \Kd_Out[17]~56 = CARRY((Kd_Out[17]) # (!\Kd_Out[16]~54 )) + + .dataa(Kd_Out[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[16]~54 ), + .combout(\Kd_Out[17]~55_combout ), + .cout(\Kd_Out[17]~56 )); +// synopsys translate_off +defparam \Kd_Out[17]~55 .lut_mask = 16'hA5AF; +defparam \Kd_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N10 +cycloneive_lcell_comb \Kd_Out[17]~feeder ( +// Equation(s): +// \Kd_Out[17]~feeder_combout = \Kd_Out[17]~55_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[17]~55_combout ), + .cin(gnd), + .combout(\Kd_Out[17]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[17]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[17]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N11 +dffeas \Kd_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[17]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[17] .is_wysiwyg = "true"; +defparam \Kd_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N16 +cycloneive_lcell_comb \Kd_Out[18]~57 ( +// Equation(s): +// \Kd_Out[18]~57_combout = (Kd_Out[18] & (!\Kd_Out[17]~56 & VCC)) # (!Kd_Out[18] & (\Kd_Out[17]~56 $ (GND))) +// \Kd_Out[18]~58 = CARRY((!Kd_Out[18] & !\Kd_Out[17]~56 )) + + .dataa(gnd), + .datab(Kd_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[17]~56 ), + .combout(\Kd_Out[18]~57_combout ), + .cout(\Kd_Out[18]~58 )); +// synopsys translate_off +defparam \Kd_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Kd_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N8 +cycloneive_lcell_comb \Kd_Out[18]~feeder ( +// Equation(s): +// \Kd_Out[18]~feeder_combout = \Kd_Out[18]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[18]~57_combout ), + .cin(gnd), + .combout(\Kd_Out[18]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[18]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[18]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N9 +dffeas \Kd_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[18]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[18] .is_wysiwyg = "true"; +defparam \Kd_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N18 +cycloneive_lcell_comb \Kd_Out[19]~59 ( +// Equation(s): +// \Kd_Out[19]~59_combout = (Kd_Out[19] & ((\Kd_Out[18]~58 ) # (GND))) # (!Kd_Out[19] & (!\Kd_Out[18]~58 )) +// \Kd_Out[19]~60 = CARRY((Kd_Out[19]) # (!\Kd_Out[18]~58 )) + + .dataa(gnd), + .datab(Kd_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[18]~58 ), + .combout(\Kd_Out[19]~59_combout ), + .cout(\Kd_Out[19]~60 )); +// synopsys translate_off +defparam \Kd_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Kd_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N2 +cycloneive_lcell_comb \Kd_Out[19]~feeder ( +// Equation(s): +// \Kd_Out[19]~feeder_combout = \Kd_Out[19]~59_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[19]~59_combout ), + .cin(gnd), + .combout(\Kd_Out[19]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[19]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[19]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N3 +dffeas \Kd_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[19]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[19] .is_wysiwyg = "true"; +defparam \Kd_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N20 +cycloneive_lcell_comb \Kd_Out[20]~61 ( +// Equation(s): +// \Kd_Out[20]~61_combout = \Kd_Out[19]~60 $ (Kd_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[20]), + .cin(\Kd_Out[19]~60 ), + .combout(\Kd_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Kd_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N26 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y13_N21 +dffeas \Kd_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[20]~61_combout ), + .asdata(\~GND~combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[20] .is_wysiwyg = "true"; +defparam \Kd_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N30 +cycloneive_lcell_comb \Add7~20 ( +// Equation(s): +// \Add7~20_combout = (Kd_Out[20] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[20]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~20 .lut_mask = 16'h00F0; +defparam \Add7~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N12 +cycloneive_lcell_comb \Ki_Out[0]~21 ( +// Equation(s): +// \Ki_Out[0]~21_combout = Ki_Out[0] $ (GND) +// \Ki_Out[0]~22 = CARRY(!Ki_Out[0]) + + .dataa(Ki_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Ki_Out[0]~21_combout ), + .cout(\Ki_Out[0]~22 )); +// synopsys translate_off +defparam \Ki_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Ki_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y17_N22 +cycloneive_io_ibuf \Ki[0]~input ( + .i(Ki[0]), + .ibar(gnd), + .o(\Ki[0]~input_o )); +// synopsys translate_off +defparam \Ki[0]~input .bus_hold = "false"; +defparam \Ki[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N1 +cycloneive_io_ibuf \Ki[1]~input ( + .i(Ki[1]), + .ibar(gnd), + .o(\Ki[1]~input_o )); +// synopsys translate_off +defparam \Ki[1]~input .bus_hold = "false"; +defparam \Ki[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N22 +cycloneive_io_ibuf \Ki[2]~input ( + .i(Ki[2]), + .ibar(gnd), + .o(\Ki[2]~input_o )); +// synopsys translate_off +defparam \Ki[2]~input .bus_hold = "false"; +defparam \Ki[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N15 +cycloneive_io_ibuf \Ki[3]~input ( + .i(Ki[3]), + .ibar(gnd), + .o(\Ki[3]~input_o )); +// synopsys translate_off +defparam \Ki[3]~input .bus_hold = "false"; +defparam \Ki[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N15 +cycloneive_io_ibuf \Ki[4]~input ( + .i(Ki[4]), + .ibar(gnd), + .o(\Ki[4]~input_o )); +// synopsys translate_off +defparam \Ki[4]~input .bus_hold = "false"; +defparam \Ki[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N8 +cycloneive_io_ibuf \Ki[5]~input ( + .i(Ki[5]), + .ibar(gnd), + .o(\Ki[5]~input_o )); +// synopsys translate_off +defparam \Ki[5]~input .bus_hold = "false"; +defparam \Ki[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N1 +cycloneive_io_ibuf \Ki[6]~input ( + .i(Ki[6]), + .ibar(gnd), + .o(\Ki[6]~input_o )); +// synopsys translate_off +defparam \Ki[6]~input .bus_hold = "false"; +defparam \Ki[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N8 +cycloneive_io_ibuf \Ki[7]~input ( + .i(Ki[7]), + .ibar(gnd), + .o(\Ki[7]~input_o )); +// synopsys translate_off +defparam \Ki[7]~input .bus_hold = "false"; +defparam \Ki[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y17_N0 +cycloneive_mac_mult \Mult1|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({EE1[11],EE1[10],EE1[9],EE1[8],EE1[7],EE1[6],EE1[5],EE1[4],EE1[3],EE1[2],EE1[1],EE1[0],gnd,gnd,gnd,gnd,gnd,gnd}), + .datab({\Ki[7]~input_o ,\Ki[6]~input_o ,\Ki[5]~input_o ,\Ki[4]~input_o ,\Ki[3]~input_o ,\Ki[2]~input_o ,\Ki[1]~input_o ,\Ki[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult1|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult1|auto_generated|mac_mult1 .dataa_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult1|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult1|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y17_N2 +cycloneive_mac_out \Mult1|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult1|auto_generated|mac_mult1~DATAOUT19 ,\Mult1|auto_generated|mac_mult1~DATAOUT18 ,\Mult1|auto_generated|mac_mult1~DATAOUT17 ,\Mult1|auto_generated|mac_mult1~DATAOUT16 ,\Mult1|auto_generated|mac_mult1~DATAOUT15 ,\Mult1|auto_generated|mac_mult1~DATAOUT14 , +\Mult1|auto_generated|mac_mult1~DATAOUT13 ,\Mult1|auto_generated|mac_mult1~DATAOUT12 ,\Mult1|auto_generated|mac_mult1~DATAOUT11 ,\Mult1|auto_generated|mac_mult1~DATAOUT10 ,\Mult1|auto_generated|mac_mult1~DATAOUT9 ,\Mult1|auto_generated|mac_mult1~DATAOUT8 , +\Mult1|auto_generated|mac_mult1~DATAOUT7 ,\Mult1|auto_generated|mac_mult1~DATAOUT6 ,\Mult1|auto_generated|mac_mult1~DATAOUT5 ,\Mult1|auto_generated|mac_mult1~DATAOUT4 ,\Mult1|auto_generated|mac_mult1~DATAOUT3 ,\Mult1|auto_generated|mac_mult1~DATAOUT2 , +\Mult1|auto_generated|mac_mult1~DATAOUT1 ,\Mult1|auto_generated|mac_mult1~dataout ,\Mult1|auto_generated|mac_mult1~15 ,\Mult1|auto_generated|mac_mult1~14 ,\Mult1|auto_generated|mac_mult1~13 ,\Mult1|auto_generated|mac_mult1~12 ,\Mult1|auto_generated|mac_mult1~11 , +\Mult1|auto_generated|mac_mult1~10 ,\Mult1|auto_generated|mac_mult1~9 ,\Mult1|auto_generated|mac_mult1~8 ,\Mult1|auto_generated|mac_mult1~7 ,\Mult1|auto_generated|mac_mult1~6 ,\Mult1|auto_generated|mac_mult1~5 ,\Mult1|auto_generated|mac_mult1~4 , +\Mult1|auto_generated|mac_mult1~3 ,\Mult1|auto_generated|mac_mult1~2 ,\Mult1|auto_generated|mac_mult1~1 ,\Mult1|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult1|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult1|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult1|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y18_N13 +dffeas \Ki_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[0]~21_combout ), + .asdata(\Mult1|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[0] .is_wysiwyg = "true"; +defparam \Ki_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N14 +cycloneive_lcell_comb \Ki_Out[1]~23 ( +// Equation(s): +// \Ki_Out[1]~23_combout = (Ki_Out[1] & ((\Ki_Out[0]~22 ) # (GND))) # (!Ki_Out[1] & (!\Ki_Out[0]~22 )) +// \Ki_Out[1]~24 = CARRY((Ki_Out[1]) # (!\Ki_Out[0]~22 )) + + .dataa(gnd), + .datab(Ki_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[0]~22 ), + .combout(\Ki_Out[1]~23_combout ), + .cout(\Ki_Out[1]~24 )); +// synopsys translate_off +defparam \Ki_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Ki_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N15 +dffeas \Ki_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[1]~23_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[1] .is_wysiwyg = "true"; +defparam \Ki_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N16 +cycloneive_lcell_comb \Ki_Out[2]~25 ( +// Equation(s): +// \Ki_Out[2]~25_combout = (Ki_Out[2] & (!\Ki_Out[1]~24 & VCC)) # (!Ki_Out[2] & (\Ki_Out[1]~24 $ (GND))) +// \Ki_Out[2]~26 = CARRY((!Ki_Out[2] & !\Ki_Out[1]~24 )) + + .dataa(gnd), + .datab(Ki_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[1]~24 ), + .combout(\Ki_Out[2]~25_combout ), + .cout(\Ki_Out[2]~26 )); +// synopsys translate_off +defparam \Ki_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Ki_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N17 +dffeas \Ki_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[2]~25_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[2] .is_wysiwyg = "true"; +defparam \Ki_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N18 +cycloneive_lcell_comb \Ki_Out[3]~27 ( +// Equation(s): +// \Ki_Out[3]~27_combout = (Ki_Out[3] & ((\Ki_Out[2]~26 ) # (GND))) # (!Ki_Out[3] & (!\Ki_Out[2]~26 )) +// \Ki_Out[3]~28 = CARRY((Ki_Out[3]) # (!\Ki_Out[2]~26 )) + + .dataa(gnd), + .datab(Ki_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[2]~26 ), + .combout(\Ki_Out[3]~27_combout ), + .cout(\Ki_Out[3]~28 )); +// synopsys translate_off +defparam \Ki_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Ki_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N19 +dffeas \Ki_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[3]~27_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[3] .is_wysiwyg = "true"; +defparam \Ki_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N20 +cycloneive_lcell_comb \Ki_Out[4]~29 ( +// Equation(s): +// \Ki_Out[4]~29_combout = (Ki_Out[4] & (!\Ki_Out[3]~28 & VCC)) # (!Ki_Out[4] & (\Ki_Out[3]~28 $ (GND))) +// \Ki_Out[4]~30 = CARRY((!Ki_Out[4] & !\Ki_Out[3]~28 )) + + .dataa(gnd), + .datab(Ki_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[3]~28 ), + .combout(\Ki_Out[4]~29_combout ), + .cout(\Ki_Out[4]~30 )); +// synopsys translate_off +defparam \Ki_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Ki_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N21 +dffeas \Ki_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[4]~29_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[4] .is_wysiwyg = "true"; +defparam \Ki_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N22 +cycloneive_lcell_comb \Ki_Out[5]~31 ( +// Equation(s): +// \Ki_Out[5]~31_combout = (Ki_Out[5] & ((\Ki_Out[4]~30 ) # (GND))) # (!Ki_Out[5] & (!\Ki_Out[4]~30 )) +// \Ki_Out[5]~32 = CARRY((Ki_Out[5]) # (!\Ki_Out[4]~30 )) + + .dataa(Ki_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[4]~30 ), + .combout(\Ki_Out[5]~31_combout ), + .cout(\Ki_Out[5]~32 )); +// synopsys translate_off +defparam \Ki_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Ki_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N23 +dffeas \Ki_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[5]~31_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[5] .is_wysiwyg = "true"; +defparam \Ki_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N24 +cycloneive_lcell_comb \Ki_Out[6]~33 ( +// Equation(s): +// \Ki_Out[6]~33_combout = (Ki_Out[6] & (!\Ki_Out[5]~32 & VCC)) # (!Ki_Out[6] & (\Ki_Out[5]~32 $ (GND))) +// \Ki_Out[6]~34 = CARRY((!Ki_Out[6] & !\Ki_Out[5]~32 )) + + .dataa(gnd), + .datab(Ki_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[5]~32 ), + .combout(\Ki_Out[6]~33_combout ), + .cout(\Ki_Out[6]~34 )); +// synopsys translate_off +defparam \Ki_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Ki_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N25 +dffeas \Ki_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[6]~33_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[6] .is_wysiwyg = "true"; +defparam \Ki_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N26 +cycloneive_lcell_comb \Ki_Out[7]~35 ( +// Equation(s): +// \Ki_Out[7]~35_combout = (Ki_Out[7] & ((\Ki_Out[6]~34 ) # (GND))) # (!Ki_Out[7] & (!\Ki_Out[6]~34 )) +// \Ki_Out[7]~36 = CARRY((Ki_Out[7]) # (!\Ki_Out[6]~34 )) + + .dataa(Ki_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[6]~34 ), + .combout(\Ki_Out[7]~35_combout ), + .cout(\Ki_Out[7]~36 )); +// synopsys translate_off +defparam \Ki_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Ki_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N27 +dffeas \Ki_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[7]~35_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[7] .is_wysiwyg = "true"; +defparam \Ki_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N28 +cycloneive_lcell_comb \Ki_Out[8]~37 ( +// Equation(s): +// \Ki_Out[8]~37_combout = (Ki_Out[8] & (!\Ki_Out[7]~36 & VCC)) # (!Ki_Out[8] & (\Ki_Out[7]~36 $ (GND))) +// \Ki_Out[8]~38 = CARRY((!Ki_Out[8] & !\Ki_Out[7]~36 )) + + .dataa(gnd), + .datab(Ki_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[7]~36 ), + .combout(\Ki_Out[8]~37_combout ), + .cout(\Ki_Out[8]~38 )); +// synopsys translate_off +defparam \Ki_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Ki_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N29 +dffeas \Ki_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[8]~37_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[8] .is_wysiwyg = "true"; +defparam \Ki_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N30 +cycloneive_lcell_comb \Ki_Out[9]~39 ( +// Equation(s): +// \Ki_Out[9]~39_combout = (Ki_Out[9] & ((\Ki_Out[8]~38 ) # (GND))) # (!Ki_Out[9] & (!\Ki_Out[8]~38 )) +// \Ki_Out[9]~40 = CARRY((Ki_Out[9]) # (!\Ki_Out[8]~38 )) + + .dataa(Ki_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[8]~38 ), + .combout(\Ki_Out[9]~39_combout ), + .cout(\Ki_Out[9]~40 )); +// synopsys translate_off +defparam \Ki_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Ki_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N31 +dffeas \Ki_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[9]~39_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[9] .is_wysiwyg = "true"; +defparam \Ki_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N0 +cycloneive_lcell_comb \Ki_Out[10]~41 ( +// Equation(s): +// \Ki_Out[10]~41_combout = (Ki_Out[10] & (!\Ki_Out[9]~40 & VCC)) # (!Ki_Out[10] & (\Ki_Out[9]~40 $ (GND))) +// \Ki_Out[10]~42 = CARRY((!Ki_Out[10] & !\Ki_Out[9]~40 )) + + .dataa(gnd), + .datab(Ki_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[9]~40 ), + .combout(\Ki_Out[10]~41_combout ), + .cout(\Ki_Out[10]~42 )); +// synopsys translate_off +defparam \Ki_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Ki_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N1 +dffeas \Ki_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[10]~41_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[10] .is_wysiwyg = "true"; +defparam \Ki_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N2 +cycloneive_lcell_comb \Ki_Out[11]~43 ( +// Equation(s): +// \Ki_Out[11]~43_combout = (Ki_Out[11] & ((\Ki_Out[10]~42 ) # (GND))) # (!Ki_Out[11] & (!\Ki_Out[10]~42 )) +// \Ki_Out[11]~44 = CARRY((Ki_Out[11]) # (!\Ki_Out[10]~42 )) + + .dataa(gnd), + .datab(Ki_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[10]~42 ), + .combout(\Ki_Out[11]~43_combout ), + .cout(\Ki_Out[11]~44 )); +// synopsys translate_off +defparam \Ki_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Ki_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N3 +dffeas \Ki_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[11]~43_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[11] .is_wysiwyg = "true"; +defparam \Ki_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N4 +cycloneive_lcell_comb \Ki_Out[12]~45 ( +// Equation(s): +// \Ki_Out[12]~45_combout = (Ki_Out[12] & (!\Ki_Out[11]~44 & VCC)) # (!Ki_Out[12] & (\Ki_Out[11]~44 $ (GND))) +// \Ki_Out[12]~46 = CARRY((!Ki_Out[12] & !\Ki_Out[11]~44 )) + + .dataa(gnd), + .datab(Ki_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[11]~44 ), + .combout(\Ki_Out[12]~45_combout ), + .cout(\Ki_Out[12]~46 )); +// synopsys translate_off +defparam \Ki_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Ki_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N5 +dffeas \Ki_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[12]~45_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[12] .is_wysiwyg = "true"; +defparam \Ki_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N6 +cycloneive_lcell_comb \Ki_Out[13]~47 ( +// Equation(s): +// \Ki_Out[13]~47_combout = (Ki_Out[13] & ((\Ki_Out[12]~46 ) # (GND))) # (!Ki_Out[13] & (!\Ki_Out[12]~46 )) +// \Ki_Out[13]~48 = CARRY((Ki_Out[13]) # (!\Ki_Out[12]~46 )) + + .dataa(Ki_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[12]~46 ), + .combout(\Ki_Out[13]~47_combout ), + .cout(\Ki_Out[13]~48 )); +// synopsys translate_off +defparam \Ki_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Ki_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N7 +dffeas \Ki_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[13]~47_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[13] .is_wysiwyg = "true"; +defparam \Ki_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N8 +cycloneive_lcell_comb \Ki_Out[14]~49 ( +// Equation(s): +// \Ki_Out[14]~49_combout = (Ki_Out[14] & (!\Ki_Out[13]~48 & VCC)) # (!Ki_Out[14] & (\Ki_Out[13]~48 $ (GND))) +// \Ki_Out[14]~50 = CARRY((!Ki_Out[14] & !\Ki_Out[13]~48 )) + + .dataa(gnd), + .datab(Ki_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[13]~48 ), + .combout(\Ki_Out[14]~49_combout ), + .cout(\Ki_Out[14]~50 )); +// synopsys translate_off +defparam \Ki_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Ki_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N9 +dffeas \Ki_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[14]~49_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[14] .is_wysiwyg = "true"; +defparam \Ki_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N10 +cycloneive_lcell_comb \Ki_Out[15]~51 ( +// Equation(s): +// \Ki_Out[15]~51_combout = (Ki_Out[15] & ((\Ki_Out[14]~50 ) # (GND))) # (!Ki_Out[15] & (!\Ki_Out[14]~50 )) +// \Ki_Out[15]~52 = CARRY((Ki_Out[15]) # (!\Ki_Out[14]~50 )) + + .dataa(Ki_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[14]~50 ), + .combout(\Ki_Out[15]~51_combout ), + .cout(\Ki_Out[15]~52 )); +// synopsys translate_off +defparam \Ki_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Ki_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N11 +dffeas \Ki_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[15]~51_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[15] .is_wysiwyg = "true"; +defparam \Ki_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N12 +cycloneive_lcell_comb \Ki_Out[16]~53 ( +// Equation(s): +// \Ki_Out[16]~53_combout = (Ki_Out[16] & (!\Ki_Out[15]~52 & VCC)) # (!Ki_Out[16] & (\Ki_Out[15]~52 $ (GND))) +// \Ki_Out[16]~54 = CARRY((!Ki_Out[16] & !\Ki_Out[15]~52 )) + + .dataa(Ki_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[15]~52 ), + .combout(\Ki_Out[16]~53_combout ), + .cout(\Ki_Out[16]~54 )); +// synopsys translate_off +defparam \Ki_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Ki_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N13 +dffeas \Ki_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[16]~53_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[16] .is_wysiwyg = "true"; +defparam \Ki_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N14 +cycloneive_lcell_comb \Ki_Out[17]~55 ( +// Equation(s): +// \Ki_Out[17]~55_combout = (Ki_Out[17] & ((\Ki_Out[16]~54 ) # (GND))) # (!Ki_Out[17] & (!\Ki_Out[16]~54 )) +// \Ki_Out[17]~56 = CARRY((Ki_Out[17]) # (!\Ki_Out[16]~54 )) + + .dataa(gnd), + .datab(Ki_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[16]~54 ), + .combout(\Ki_Out[17]~55_combout ), + .cout(\Ki_Out[17]~56 )); +// synopsys translate_off +defparam \Ki_Out[17]~55 .lut_mask = 16'hC3CF; +defparam \Ki_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N15 +dffeas \Ki_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[17]~55_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[17] .is_wysiwyg = "true"; +defparam \Ki_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N16 +cycloneive_lcell_comb \Ki_Out[18]~57 ( +// Equation(s): +// \Ki_Out[18]~57_combout = (Ki_Out[18] & (!\Ki_Out[17]~56 & VCC)) # (!Ki_Out[18] & (\Ki_Out[17]~56 $ (GND))) +// \Ki_Out[18]~58 = CARRY((!Ki_Out[18] & !\Ki_Out[17]~56 )) + + .dataa(gnd), + .datab(Ki_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[17]~56 ), + .combout(\Ki_Out[18]~57_combout ), + .cout(\Ki_Out[18]~58 )); +// synopsys translate_off +defparam \Ki_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Ki_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N17 +dffeas \Ki_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[18]~57_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[18] .is_wysiwyg = "true"; +defparam \Ki_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N18 +cycloneive_lcell_comb \Ki_Out[19]~59 ( +// Equation(s): +// \Ki_Out[19]~59_combout = (Ki_Out[19] & ((\Ki_Out[18]~58 ) # (GND))) # (!Ki_Out[19] & (!\Ki_Out[18]~58 )) +// \Ki_Out[19]~60 = CARRY((Ki_Out[19]) # (!\Ki_Out[18]~58 )) + + .dataa(gnd), + .datab(Ki_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[18]~58 ), + .combout(\Ki_Out[19]~59_combout ), + .cout(\Ki_Out[19]~60 )); +// synopsys translate_off +defparam \Ki_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Ki_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N19 +dffeas \Ki_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[19]~59_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[19] .is_wysiwyg = "true"; +defparam \Ki_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N20 +cycloneive_lcell_comb \Ki_Out[20]~61 ( +// Equation(s): +// \Ki_Out[20]~61_combout = \Ki_Out[19]~60 $ (Ki_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Ki_Out[20]), + .cin(\Ki_Out[19]~60 ), + .combout(\Ki_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Ki_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Ki_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N21 +dffeas \Ki_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[20]~61_combout ), + .asdata(\~GND~combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[20] .is_wysiwyg = "true"; +defparam \Ki_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N12 +cycloneive_lcell_comb \Kp_Out[0]~21 ( +// Equation(s): +// \Kp_Out[0]~21_combout = Kp_Out[0] $ (GND) +// \Kp_Out[0]~22 = CARRY(!Kp_Out[0]) + + .dataa(Kp_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Kp_Out[0]~21_combout ), + .cout(\Kp_Out[0]~22 )); +// synopsys translate_off +defparam \Kp_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Kp_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \Kp[0]~input ( + .i(Kp[0]), + .ibar(gnd), + .o(\Kp[0]~input_o )); +// synopsys translate_off +defparam \Kp[0]~input .bus_hold = "false"; +defparam \Kp[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N22 +cycloneive_io_ibuf \Kp[1]~input ( + .i(Kp[1]), + .ibar(gnd), + .o(\Kp[1]~input_o )); +// synopsys translate_off +defparam \Kp[1]~input .bus_hold = "false"; +defparam \Kp[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N22 +cycloneive_io_ibuf \Kp[2]~input ( + .i(Kp[2]), + .ibar(gnd), + .o(\Kp[2]~input_o )); +// synopsys translate_off +defparam \Kp[2]~input .bus_hold = "false"; +defparam \Kp[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N22 +cycloneive_io_ibuf \Kp[3]~input ( + .i(Kp[3]), + .ibar(gnd), + .o(\Kp[3]~input_o )); +// synopsys translate_off +defparam \Kp[3]~input .bus_hold = "false"; +defparam \Kp[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N15 +cycloneive_io_ibuf \Kp[4]~input ( + .i(Kp[4]), + .ibar(gnd), + .o(\Kp[4]~input_o )); +// synopsys translate_off +defparam \Kp[4]~input .bus_hold = "false"; +defparam \Kp[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N15 +cycloneive_io_ibuf \Kp[5]~input ( + .i(Kp[5]), + .ibar(gnd), + .o(\Kp[5]~input_o )); +// synopsys translate_off +defparam \Kp[5]~input .bus_hold = "false"; +defparam \Kp[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N1 +cycloneive_io_ibuf \Kp[6]~input ( + .i(Kp[6]), + .ibar(gnd), + .o(\Kp[6]~input_o )); +// synopsys translate_off +defparam \Kp[6]~input .bus_hold = "false"; +defparam \Kp[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N22 +cycloneive_io_ibuf \Kp[7]~input ( + .i(Kp[7]), + .ibar(gnd), + .o(\Kp[7]~input_o )); +// synopsys translate_off +defparam \Kp[7]~input .bus_hold = "false"; +defparam \Kp[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y18_N0 +cycloneive_mac_mult \Mult0|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(\clk~inputclkctrl_outclk ), + .aclr(!\rst_n~inputclkctrl_outclk ), + .ena(\Clk_Ctrl~q ), + .dataa({\EE0[13]~42_combout ,\EE0[12]~40_combout ,\EE0[11]~38_combout ,\EE0[10]~36_combout ,\EE0[9]~34_combout ,\EE0[8]~32_combout ,\EE0[7]~30_combout ,\EE0[6]~28_combout ,\EE0[5]~26_combout ,\EE0[4]~24_combout ,\EE0[3]~22_combout ,\EE0[2]~20_combout ,\EE0[1]~18_combout , +\EE0[0]~16_combout ,gnd,gnd,gnd,gnd}), + .datab({\Kp[7]~input_o ,\Kp[6]~input_o ,\Kp[5]~input_o ,\Kp[4]~input_o ,\Kp[3]~input_o ,\Kp[2]~input_o ,\Kp[1]~input_o ,\Kp[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult0|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult0|auto_generated|mac_mult1 .dataa_clock = "0"; +defparam \Mult0|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult0|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult0|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult0|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult0|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y18_N2 +cycloneive_mac_out \Mult0|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult0|auto_generated|mac_mult1~DATAOUT21 ,\Mult0|auto_generated|mac_mult1~DATAOUT20 ,\Mult0|auto_generated|mac_mult1~DATAOUT19 ,\Mult0|auto_generated|mac_mult1~DATAOUT18 ,\Mult0|auto_generated|mac_mult1~DATAOUT17 ,\Mult0|auto_generated|mac_mult1~DATAOUT16 , +\Mult0|auto_generated|mac_mult1~DATAOUT15 ,\Mult0|auto_generated|mac_mult1~DATAOUT14 ,\Mult0|auto_generated|mac_mult1~DATAOUT13 ,\Mult0|auto_generated|mac_mult1~DATAOUT12 ,\Mult0|auto_generated|mac_mult1~DATAOUT11 ,\Mult0|auto_generated|mac_mult1~DATAOUT10 , +\Mult0|auto_generated|mac_mult1~DATAOUT9 ,\Mult0|auto_generated|mac_mult1~DATAOUT8 ,\Mult0|auto_generated|mac_mult1~DATAOUT7 ,\Mult0|auto_generated|mac_mult1~DATAOUT6 ,\Mult0|auto_generated|mac_mult1~DATAOUT5 ,\Mult0|auto_generated|mac_mult1~DATAOUT4 , +\Mult0|auto_generated|mac_mult1~DATAOUT3 ,\Mult0|auto_generated|mac_mult1~DATAOUT2 ,\Mult0|auto_generated|mac_mult1~DATAOUT1 ,\Mult0|auto_generated|mac_mult1~dataout ,\Mult0|auto_generated|mac_mult1~13 ,\Mult0|auto_generated|mac_mult1~12 , +\Mult0|auto_generated|mac_mult1~11 ,\Mult0|auto_generated|mac_mult1~10 ,\Mult0|auto_generated|mac_mult1~9 ,\Mult0|auto_generated|mac_mult1~8 ,\Mult0|auto_generated|mac_mult1~7 ,\Mult0|auto_generated|mac_mult1~6 ,\Mult0|auto_generated|mac_mult1~5 , +\Mult0|auto_generated|mac_mult1~4 ,\Mult0|auto_generated|mac_mult1~3 ,\Mult0|auto_generated|mac_mult1~2 ,\Mult0|auto_generated|mac_mult1~1 ,\Mult0|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult0|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult0|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult0|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y16_N13 +dffeas \Kp_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[0]~21_combout ), + .asdata(\Mult0|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[0] .is_wysiwyg = "true"; +defparam \Kp_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N14 +cycloneive_lcell_comb \Kp_Out[1]~23 ( +// Equation(s): +// \Kp_Out[1]~23_combout = (Kp_Out[1] & ((\Kp_Out[0]~22 ) # (GND))) # (!Kp_Out[1] & (!\Kp_Out[0]~22 )) +// \Kp_Out[1]~24 = CARRY((Kp_Out[1]) # (!\Kp_Out[0]~22 )) + + .dataa(gnd), + .datab(Kp_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[0]~22 ), + .combout(\Kp_Out[1]~23_combout ), + .cout(\Kp_Out[1]~24 )); +// synopsys translate_off +defparam \Kp_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Kp_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N15 +dffeas \Kp_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[1]~23_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[1] .is_wysiwyg = "true"; +defparam \Kp_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N16 +cycloneive_lcell_comb \Kp_Out[2]~25 ( +// Equation(s): +// \Kp_Out[2]~25_combout = (Kp_Out[2] & (!\Kp_Out[1]~24 & VCC)) # (!Kp_Out[2] & (\Kp_Out[1]~24 $ (GND))) +// \Kp_Out[2]~26 = CARRY((!Kp_Out[2] & !\Kp_Out[1]~24 )) + + .dataa(gnd), + .datab(Kp_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[1]~24 ), + .combout(\Kp_Out[2]~25_combout ), + .cout(\Kp_Out[2]~26 )); +// synopsys translate_off +defparam \Kp_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Kp_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N17 +dffeas \Kp_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[2]~25_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[2] .is_wysiwyg = "true"; +defparam \Kp_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N18 +cycloneive_lcell_comb \Kp_Out[3]~27 ( +// Equation(s): +// \Kp_Out[3]~27_combout = (Kp_Out[3] & ((\Kp_Out[2]~26 ) # (GND))) # (!Kp_Out[3] & (!\Kp_Out[2]~26 )) +// \Kp_Out[3]~28 = CARRY((Kp_Out[3]) # (!\Kp_Out[2]~26 )) + + .dataa(gnd), + .datab(Kp_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[2]~26 ), + .combout(\Kp_Out[3]~27_combout ), + .cout(\Kp_Out[3]~28 )); +// synopsys translate_off +defparam \Kp_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Kp_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N19 +dffeas \Kp_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[3]~27_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[3] .is_wysiwyg = "true"; +defparam \Kp_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N20 +cycloneive_lcell_comb \Kp_Out[4]~29 ( +// Equation(s): +// \Kp_Out[4]~29_combout = (Kp_Out[4] & (!\Kp_Out[3]~28 & VCC)) # (!Kp_Out[4] & (\Kp_Out[3]~28 $ (GND))) +// \Kp_Out[4]~30 = CARRY((!Kp_Out[4] & !\Kp_Out[3]~28 )) + + .dataa(gnd), + .datab(Kp_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[3]~28 ), + .combout(\Kp_Out[4]~29_combout ), + .cout(\Kp_Out[4]~30 )); +// synopsys translate_off +defparam \Kp_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Kp_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N21 +dffeas \Kp_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[4]~29_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[4] .is_wysiwyg = "true"; +defparam \Kp_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N22 +cycloneive_lcell_comb \Kp_Out[5]~31 ( +// Equation(s): +// \Kp_Out[5]~31_combout = (Kp_Out[5] & ((\Kp_Out[4]~30 ) # (GND))) # (!Kp_Out[5] & (!\Kp_Out[4]~30 )) +// \Kp_Out[5]~32 = CARRY((Kp_Out[5]) # (!\Kp_Out[4]~30 )) + + .dataa(Kp_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[4]~30 ), + .combout(\Kp_Out[5]~31_combout ), + .cout(\Kp_Out[5]~32 )); +// synopsys translate_off +defparam \Kp_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Kp_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N23 +dffeas \Kp_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[5]~31_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[5] .is_wysiwyg = "true"; +defparam \Kp_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N24 +cycloneive_lcell_comb \Kp_Out[6]~33 ( +// Equation(s): +// \Kp_Out[6]~33_combout = (Kp_Out[6] & (!\Kp_Out[5]~32 & VCC)) # (!Kp_Out[6] & (\Kp_Out[5]~32 $ (GND))) +// \Kp_Out[6]~34 = CARRY((!Kp_Out[6] & !\Kp_Out[5]~32 )) + + .dataa(gnd), + .datab(Kp_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[5]~32 ), + .combout(\Kp_Out[6]~33_combout ), + .cout(\Kp_Out[6]~34 )); +// synopsys translate_off +defparam \Kp_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Kp_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N25 +dffeas \Kp_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[6]~33_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[6] .is_wysiwyg = "true"; +defparam \Kp_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N26 +cycloneive_lcell_comb \Kp_Out[7]~35 ( +// Equation(s): +// \Kp_Out[7]~35_combout = (Kp_Out[7] & ((\Kp_Out[6]~34 ) # (GND))) # (!Kp_Out[7] & (!\Kp_Out[6]~34 )) +// \Kp_Out[7]~36 = CARRY((Kp_Out[7]) # (!\Kp_Out[6]~34 )) + + .dataa(Kp_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[6]~34 ), + .combout(\Kp_Out[7]~35_combout ), + .cout(\Kp_Out[7]~36 )); +// synopsys translate_off +defparam \Kp_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Kp_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N27 +dffeas \Kp_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[7]~35_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[7] .is_wysiwyg = "true"; +defparam \Kp_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N28 +cycloneive_lcell_comb \Kp_Out[8]~37 ( +// Equation(s): +// \Kp_Out[8]~37_combout = (Kp_Out[8] & (!\Kp_Out[7]~36 & VCC)) # (!Kp_Out[8] & (\Kp_Out[7]~36 $ (GND))) +// \Kp_Out[8]~38 = CARRY((!Kp_Out[8] & !\Kp_Out[7]~36 )) + + .dataa(gnd), + .datab(Kp_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[7]~36 ), + .combout(\Kp_Out[8]~37_combout ), + .cout(\Kp_Out[8]~38 )); +// synopsys translate_off +defparam \Kp_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Kp_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N29 +dffeas \Kp_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[8]~37_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[8] .is_wysiwyg = "true"; +defparam \Kp_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N30 +cycloneive_lcell_comb \Kp_Out[9]~39 ( +// Equation(s): +// \Kp_Out[9]~39_combout = (Kp_Out[9] & ((\Kp_Out[8]~38 ) # (GND))) # (!Kp_Out[9] & (!\Kp_Out[8]~38 )) +// \Kp_Out[9]~40 = CARRY((Kp_Out[9]) # (!\Kp_Out[8]~38 )) + + .dataa(Kp_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[8]~38 ), + .combout(\Kp_Out[9]~39_combout ), + .cout(\Kp_Out[9]~40 )); +// synopsys translate_off +defparam \Kp_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Kp_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N31 +dffeas \Kp_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[9]~39_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[9] .is_wysiwyg = "true"; +defparam \Kp_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \Kp_Out[10]~41 ( +// Equation(s): +// \Kp_Out[10]~41_combout = (Kp_Out[10] & (!\Kp_Out[9]~40 & VCC)) # (!Kp_Out[10] & (\Kp_Out[9]~40 $ (GND))) +// \Kp_Out[10]~42 = CARRY((!Kp_Out[10] & !\Kp_Out[9]~40 )) + + .dataa(gnd), + .datab(Kp_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[9]~40 ), + .combout(\Kp_Out[10]~41_combout ), + .cout(\Kp_Out[10]~42 )); +// synopsys translate_off +defparam \Kp_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Kp_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N1 +dffeas \Kp_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[10]~41_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[10] .is_wysiwyg = "true"; +defparam \Kp_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \Kp_Out[11]~43 ( +// Equation(s): +// \Kp_Out[11]~43_combout = (Kp_Out[11] & ((\Kp_Out[10]~42 ) # (GND))) # (!Kp_Out[11] & (!\Kp_Out[10]~42 )) +// \Kp_Out[11]~44 = CARRY((Kp_Out[11]) # (!\Kp_Out[10]~42 )) + + .dataa(gnd), + .datab(Kp_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[10]~42 ), + .combout(\Kp_Out[11]~43_combout ), + .cout(\Kp_Out[11]~44 )); +// synopsys translate_off +defparam \Kp_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Kp_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N3 +dffeas \Kp_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[11]~43_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[11] .is_wysiwyg = "true"; +defparam \Kp_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \Kp_Out[12]~45 ( +// Equation(s): +// \Kp_Out[12]~45_combout = (Kp_Out[12] & (!\Kp_Out[11]~44 & VCC)) # (!Kp_Out[12] & (\Kp_Out[11]~44 $ (GND))) +// \Kp_Out[12]~46 = CARRY((!Kp_Out[12] & !\Kp_Out[11]~44 )) + + .dataa(gnd), + .datab(Kp_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[11]~44 ), + .combout(\Kp_Out[12]~45_combout ), + .cout(\Kp_Out[12]~46 )); +// synopsys translate_off +defparam \Kp_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Kp_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N5 +dffeas \Kp_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[12]~45_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[12] .is_wysiwyg = "true"; +defparam \Kp_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \Kp_Out[13]~47 ( +// Equation(s): +// \Kp_Out[13]~47_combout = (Kp_Out[13] & ((\Kp_Out[12]~46 ) # (GND))) # (!Kp_Out[13] & (!\Kp_Out[12]~46 )) +// \Kp_Out[13]~48 = CARRY((Kp_Out[13]) # (!\Kp_Out[12]~46 )) + + .dataa(Kp_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[12]~46 ), + .combout(\Kp_Out[13]~47_combout ), + .cout(\Kp_Out[13]~48 )); +// synopsys translate_off +defparam \Kp_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Kp_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N7 +dffeas \Kp_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[13]~47_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[13] .is_wysiwyg = "true"; +defparam \Kp_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \Kp_Out[14]~49 ( +// Equation(s): +// \Kp_Out[14]~49_combout = (Kp_Out[14] & (!\Kp_Out[13]~48 & VCC)) # (!Kp_Out[14] & (\Kp_Out[13]~48 $ (GND))) +// \Kp_Out[14]~50 = CARRY((!Kp_Out[14] & !\Kp_Out[13]~48 )) + + .dataa(gnd), + .datab(Kp_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[13]~48 ), + .combout(\Kp_Out[14]~49_combout ), + .cout(\Kp_Out[14]~50 )); +// synopsys translate_off +defparam \Kp_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Kp_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N9 +dffeas \Kp_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[14]~49_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[14] .is_wysiwyg = "true"; +defparam \Kp_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \Kp_Out[15]~51 ( +// Equation(s): +// \Kp_Out[15]~51_combout = (Kp_Out[15] & ((\Kp_Out[14]~50 ) # (GND))) # (!Kp_Out[15] & (!\Kp_Out[14]~50 )) +// \Kp_Out[15]~52 = CARRY((Kp_Out[15]) # (!\Kp_Out[14]~50 )) + + .dataa(Kp_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[14]~50 ), + .combout(\Kp_Out[15]~51_combout ), + .cout(\Kp_Out[15]~52 )); +// synopsys translate_off +defparam \Kp_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Kp_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N11 +dffeas \Kp_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[15]~51_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[15] .is_wysiwyg = "true"; +defparam \Kp_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \Kp_Out[16]~53 ( +// Equation(s): +// \Kp_Out[16]~53_combout = (Kp_Out[16] & (!\Kp_Out[15]~52 & VCC)) # (!Kp_Out[16] & (\Kp_Out[15]~52 $ (GND))) +// \Kp_Out[16]~54 = CARRY((!Kp_Out[16] & !\Kp_Out[15]~52 )) + + .dataa(Kp_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[15]~52 ), + .combout(\Kp_Out[16]~53_combout ), + .cout(\Kp_Out[16]~54 )); +// synopsys translate_off +defparam \Kp_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Kp_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N13 +dffeas \Kp_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[16]~53_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[16] .is_wysiwyg = "true"; +defparam \Kp_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \Kp_Out[17]~55 ( +// Equation(s): +// \Kp_Out[17]~55_combout = (Kp_Out[17] & ((\Kp_Out[16]~54 ) # (GND))) # (!Kp_Out[17] & (!\Kp_Out[16]~54 )) +// \Kp_Out[17]~56 = CARRY((Kp_Out[17]) # (!\Kp_Out[16]~54 )) + + .dataa(gnd), + .datab(Kp_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[16]~54 ), + .combout(\Kp_Out[17]~55_combout ), + .cout(\Kp_Out[17]~56 )); +// synopsys translate_off +defparam \Kp_Out[17]~55 .lut_mask = 16'hC3CF; +defparam \Kp_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N15 +dffeas \Kp_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[17]~55_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[17] .is_wysiwyg = "true"; +defparam \Kp_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \Kp_Out[18]~57 ( +// Equation(s): +// \Kp_Out[18]~57_combout = (Kp_Out[18] & (!\Kp_Out[17]~56 & VCC)) # (!Kp_Out[18] & (\Kp_Out[17]~56 $ (GND))) +// \Kp_Out[18]~58 = CARRY((!Kp_Out[18] & !\Kp_Out[17]~56 )) + + .dataa(gnd), + .datab(Kp_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[17]~56 ), + .combout(\Kp_Out[18]~57_combout ), + .cout(\Kp_Out[18]~58 )); +// synopsys translate_off +defparam \Kp_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Kp_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N17 +dffeas \Kp_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[18]~57_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[18] .is_wysiwyg = "true"; +defparam \Kp_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \Kp_Out[19]~59 ( +// Equation(s): +// \Kp_Out[19]~59_combout = (Kp_Out[19] & ((\Kp_Out[18]~58 ) # (GND))) # (!Kp_Out[19] & (!\Kp_Out[18]~58 )) +// \Kp_Out[19]~60 = CARRY((Kp_Out[19]) # (!\Kp_Out[18]~58 )) + + .dataa(gnd), + .datab(Kp_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[18]~58 ), + .combout(\Kp_Out[19]~59_combout ), + .cout(\Kp_Out[19]~60 )); +// synopsys translate_off +defparam \Kp_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Kp_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N19 +dffeas \Kp_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[19]~59_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[19] .is_wysiwyg = "true"; +defparam \Kp_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \Kp_Out[20]~61 ( +// Equation(s): +// \Kp_Out[20]~61_combout = \Kp_Out[19]~60 $ (Kp_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Kp_Out[20]), + .cin(\Kp_Out[19]~60 ), + .combout(\Kp_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Kp_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Kp_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \Kp_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[20]~61_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT20 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[20] .is_wysiwyg = "true"; +defparam \Kp_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N12 +cycloneive_lcell_comb \Add5~0 ( +// Equation(s): +// \Add5~0_combout = (Kp_Out[0] & ((GND) # (!Ki_Out[0]))) # (!Kp_Out[0] & (Ki_Out[0] $ (GND))) +// \Add5~1 = CARRY((Kp_Out[0]) # (!Ki_Out[0])) + + .dataa(Kp_Out[0]), + .datab(Ki_Out[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add5~0_combout ), + .cout(\Add5~1 )); +// synopsys translate_off +defparam \Add5~0 .lut_mask = 16'h66BB; +defparam \Add5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N14 +cycloneive_lcell_comb \Add5~2 ( +// Equation(s): +// \Add5~2_combout = (Ki_Out[1] & ((Kp_Out[1] & (!\Add5~1 )) # (!Kp_Out[1] & ((\Add5~1 ) # (GND))))) # (!Ki_Out[1] & ((Kp_Out[1] & (\Add5~1 & VCC)) # (!Kp_Out[1] & (!\Add5~1 )))) +// \Add5~3 = CARRY((Ki_Out[1] & ((!\Add5~1 ) # (!Kp_Out[1]))) # (!Ki_Out[1] & (!Kp_Out[1] & !\Add5~1 ))) + + .dataa(Ki_Out[1]), + .datab(Kp_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~1 ), + .combout(\Add5~2_combout ), + .cout(\Add5~3 )); +// synopsys translate_off +defparam \Add5~2 .lut_mask = 16'h692B; +defparam \Add5~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N16 +cycloneive_lcell_comb \Add5~4 ( +// Equation(s): +// \Add5~4_combout = ((Kp_Out[2] $ (Ki_Out[2] $ (\Add5~3 )))) # (GND) +// \Add5~5 = CARRY((Kp_Out[2] & ((!\Add5~3 ) # (!Ki_Out[2]))) # (!Kp_Out[2] & (!Ki_Out[2] & !\Add5~3 ))) + + .dataa(Kp_Out[2]), + .datab(Ki_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~3 ), + .combout(\Add5~4_combout ), + .cout(\Add5~5 )); +// synopsys translate_off +defparam \Add5~4 .lut_mask = 16'h962B; +defparam \Add5~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N18 +cycloneive_lcell_comb \Add5~6 ( +// Equation(s): +// \Add5~6_combout = (Kp_Out[3] & ((Ki_Out[3] & (!\Add5~5 )) # (!Ki_Out[3] & (\Add5~5 & VCC)))) # (!Kp_Out[3] & ((Ki_Out[3] & ((\Add5~5 ) # (GND))) # (!Ki_Out[3] & (!\Add5~5 )))) +// \Add5~7 = CARRY((Kp_Out[3] & (Ki_Out[3] & !\Add5~5 )) # (!Kp_Out[3] & ((Ki_Out[3]) # (!\Add5~5 )))) + + .dataa(Kp_Out[3]), + .datab(Ki_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~5 ), + .combout(\Add5~6_combout ), + .cout(\Add5~7 )); +// synopsys translate_off +defparam \Add5~6 .lut_mask = 16'h694D; +defparam \Add5~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N20 +cycloneive_lcell_comb \Add5~8 ( +// Equation(s): +// \Add5~8_combout = ((Ki_Out[4] $ (Kp_Out[4] $ (\Add5~7 )))) # (GND) +// \Add5~9 = CARRY((Ki_Out[4] & (Kp_Out[4] & !\Add5~7 )) # (!Ki_Out[4] & ((Kp_Out[4]) # (!\Add5~7 )))) + + .dataa(Ki_Out[4]), + .datab(Kp_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~7 ), + .combout(\Add5~8_combout ), + .cout(\Add5~9 )); +// synopsys translate_off +defparam \Add5~8 .lut_mask = 16'h964D; +defparam \Add5~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N22 +cycloneive_lcell_comb \Add5~10 ( +// Equation(s): +// \Add5~10_combout = (Ki_Out[5] & ((Kp_Out[5] & (!\Add5~9 )) # (!Kp_Out[5] & ((\Add5~9 ) # (GND))))) # (!Ki_Out[5] & ((Kp_Out[5] & (\Add5~9 & VCC)) # (!Kp_Out[5] & (!\Add5~9 )))) +// \Add5~11 = CARRY((Ki_Out[5] & ((!\Add5~9 ) # (!Kp_Out[5]))) # (!Ki_Out[5] & (!Kp_Out[5] & !\Add5~9 ))) + + .dataa(Ki_Out[5]), + .datab(Kp_Out[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~9 ), + .combout(\Add5~10_combout ), + .cout(\Add5~11 )); +// synopsys translate_off +defparam \Add5~10 .lut_mask = 16'h692B; +defparam \Add5~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N24 +cycloneive_lcell_comb \Add5~12 ( +// Equation(s): +// \Add5~12_combout = ((Ki_Out[6] $ (Kp_Out[6] $ (\Add5~11 )))) # (GND) +// \Add5~13 = CARRY((Ki_Out[6] & (Kp_Out[6] & !\Add5~11 )) # (!Ki_Out[6] & ((Kp_Out[6]) # (!\Add5~11 )))) + + .dataa(Ki_Out[6]), + .datab(Kp_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~11 ), + .combout(\Add5~12_combout ), + .cout(\Add5~13 )); +// synopsys translate_off +defparam \Add5~12 .lut_mask = 16'h964D; +defparam \Add5~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N26 +cycloneive_lcell_comb \Add5~14 ( +// Equation(s): +// \Add5~14_combout = (Kp_Out[7] & ((Ki_Out[7] & (!\Add5~13 )) # (!Ki_Out[7] & (\Add5~13 & VCC)))) # (!Kp_Out[7] & ((Ki_Out[7] & ((\Add5~13 ) # (GND))) # (!Ki_Out[7] & (!\Add5~13 )))) +// \Add5~15 = CARRY((Kp_Out[7] & (Ki_Out[7] & !\Add5~13 )) # (!Kp_Out[7] & ((Ki_Out[7]) # (!\Add5~13 )))) + + .dataa(Kp_Out[7]), + .datab(Ki_Out[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~13 ), + .combout(\Add5~14_combout ), + .cout(\Add5~15 )); +// synopsys translate_off +defparam \Add5~14 .lut_mask = 16'h694D; +defparam \Add5~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N28 +cycloneive_lcell_comb \Add5~24 ( +// Equation(s): +// \Add5~24_combout = ((Kp_Out[8] $ (Ki_Out[8] $ (\Add5~15 )))) # (GND) +// \Add5~25 = CARRY((Kp_Out[8] & ((!\Add5~15 ) # (!Ki_Out[8]))) # (!Kp_Out[8] & (!Ki_Out[8] & !\Add5~15 ))) + + .dataa(Kp_Out[8]), + .datab(Ki_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~15 ), + .combout(\Add5~24_combout ), + .cout(\Add5~25 )); +// synopsys translate_off +defparam \Add5~24 .lut_mask = 16'h962B; +defparam \Add5~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N30 +cycloneive_lcell_comb \Add5~27 ( +// Equation(s): +// \Add5~27_combout = (Ki_Out[9] & ((Kp_Out[9] & (!\Add5~25 )) # (!Kp_Out[9] & ((\Add5~25 ) # (GND))))) # (!Ki_Out[9] & ((Kp_Out[9] & (\Add5~25 & VCC)) # (!Kp_Out[9] & (!\Add5~25 )))) +// \Add5~28 = CARRY((Ki_Out[9] & ((!\Add5~25 ) # (!Kp_Out[9]))) # (!Ki_Out[9] & (!Kp_Out[9] & !\Add5~25 ))) + + .dataa(Ki_Out[9]), + .datab(Kp_Out[9]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~25 ), + .combout(\Add5~27_combout ), + .cout(\Add5~28 )); +// synopsys translate_off +defparam \Add5~27 .lut_mask = 16'h692B; +defparam \Add5~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N0 +cycloneive_lcell_comb \Add5~30 ( +// Equation(s): +// \Add5~30_combout = ((Kp_Out[10] $ (Ki_Out[10] $ (\Add5~28 )))) # (GND) +// \Add5~31 = CARRY((Kp_Out[10] & ((!\Add5~28 ) # (!Ki_Out[10]))) # (!Kp_Out[10] & (!Ki_Out[10] & !\Add5~28 ))) + + .dataa(Kp_Out[10]), + .datab(Ki_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~28 ), + .combout(\Add5~30_combout ), + .cout(\Add5~31 )); +// synopsys translate_off +defparam \Add5~30 .lut_mask = 16'h962B; +defparam \Add5~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N2 +cycloneive_lcell_comb \Add5~33 ( +// Equation(s): +// \Add5~33_combout = (Ki_Out[11] & ((Kp_Out[11] & (!\Add5~31 )) # (!Kp_Out[11] & ((\Add5~31 ) # (GND))))) # (!Ki_Out[11] & ((Kp_Out[11] & (\Add5~31 & VCC)) # (!Kp_Out[11] & (!\Add5~31 )))) +// \Add5~34 = CARRY((Ki_Out[11] & ((!\Add5~31 ) # (!Kp_Out[11]))) # (!Ki_Out[11] & (!Kp_Out[11] & !\Add5~31 ))) + + .dataa(Ki_Out[11]), + .datab(Kp_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~31 ), + .combout(\Add5~33_combout ), + .cout(\Add5~34 )); +// synopsys translate_off +defparam \Add5~33 .lut_mask = 16'h692B; +defparam \Add5~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N4 +cycloneive_lcell_comb \Add5~36 ( +// Equation(s): +// \Add5~36_combout = ((Ki_Out[12] $ (Kp_Out[12] $ (\Add5~34 )))) # (GND) +// \Add5~37 = CARRY((Ki_Out[12] & (Kp_Out[12] & !\Add5~34 )) # (!Ki_Out[12] & ((Kp_Out[12]) # (!\Add5~34 )))) + + .dataa(Ki_Out[12]), + .datab(Kp_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~34 ), + .combout(\Add5~36_combout ), + .cout(\Add5~37 )); +// synopsys translate_off +defparam \Add5~36 .lut_mask = 16'h964D; +defparam \Add5~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N6 +cycloneive_lcell_comb \Add5~39 ( +// Equation(s): +// \Add5~39_combout = (Ki_Out[13] & ((Kp_Out[13] & (!\Add5~37 )) # (!Kp_Out[13] & ((\Add5~37 ) # (GND))))) # (!Ki_Out[13] & ((Kp_Out[13] & (\Add5~37 & VCC)) # (!Kp_Out[13] & (!\Add5~37 )))) +// \Add5~40 = CARRY((Ki_Out[13] & ((!\Add5~37 ) # (!Kp_Out[13]))) # (!Ki_Out[13] & (!Kp_Out[13] & !\Add5~37 ))) + + .dataa(Ki_Out[13]), + .datab(Kp_Out[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~37 ), + .combout(\Add5~39_combout ), + .cout(\Add5~40 )); +// synopsys translate_off +defparam \Add5~39 .lut_mask = 16'h692B; +defparam \Add5~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N8 +cycloneive_lcell_comb \Add5~42 ( +// Equation(s): +// \Add5~42_combout = ((Kp_Out[14] $ (Ki_Out[14] $ (\Add5~40 )))) # (GND) +// \Add5~43 = CARRY((Kp_Out[14] & ((!\Add5~40 ) # (!Ki_Out[14]))) # (!Kp_Out[14] & (!Ki_Out[14] & !\Add5~40 ))) + + .dataa(Kp_Out[14]), + .datab(Ki_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~40 ), + .combout(\Add5~42_combout ), + .cout(\Add5~43 )); +// synopsys translate_off +defparam \Add5~42 .lut_mask = 16'h962B; +defparam \Add5~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N10 +cycloneive_lcell_comb \Add5~45 ( +// Equation(s): +// \Add5~45_combout = (Ki_Out[15] & ((Kp_Out[15] & (!\Add5~43 )) # (!Kp_Out[15] & ((\Add5~43 ) # (GND))))) # (!Ki_Out[15] & ((Kp_Out[15] & (\Add5~43 & VCC)) # (!Kp_Out[15] & (!\Add5~43 )))) +// \Add5~46 = CARRY((Ki_Out[15] & ((!\Add5~43 ) # (!Kp_Out[15]))) # (!Ki_Out[15] & (!Kp_Out[15] & !\Add5~43 ))) + + .dataa(Ki_Out[15]), + .datab(Kp_Out[15]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~43 ), + .combout(\Add5~45_combout ), + .cout(\Add5~46 )); +// synopsys translate_off +defparam \Add5~45 .lut_mask = 16'h692B; +defparam \Add5~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N12 +cycloneive_lcell_comb \Add5~48 ( +// Equation(s): +// \Add5~48_combout = ((Ki_Out[16] $ (Kp_Out[16] $ (\Add5~46 )))) # (GND) +// \Add5~49 = CARRY((Ki_Out[16] & (Kp_Out[16] & !\Add5~46 )) # (!Ki_Out[16] & ((Kp_Out[16]) # (!\Add5~46 )))) + + .dataa(Ki_Out[16]), + .datab(Kp_Out[16]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~46 ), + .combout(\Add5~48_combout ), + .cout(\Add5~49 )); +// synopsys translate_off +defparam \Add5~48 .lut_mask = 16'h964D; +defparam \Add5~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N14 +cycloneive_lcell_comb \Add5~51 ( +// Equation(s): +// \Add5~51_combout = (Kp_Out[17] & ((Ki_Out[17] & (!\Add5~49 )) # (!Ki_Out[17] & (\Add5~49 & VCC)))) # (!Kp_Out[17] & ((Ki_Out[17] & ((\Add5~49 ) # (GND))) # (!Ki_Out[17] & (!\Add5~49 )))) +// \Add5~52 = CARRY((Kp_Out[17] & (Ki_Out[17] & !\Add5~49 )) # (!Kp_Out[17] & ((Ki_Out[17]) # (!\Add5~49 )))) + + .dataa(Kp_Out[17]), + .datab(Ki_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~49 ), + .combout(\Add5~51_combout ), + .cout(\Add5~52 )); +// synopsys translate_off +defparam \Add5~51 .lut_mask = 16'h694D; +defparam \Add5~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N16 +cycloneive_lcell_comb \Add5~54 ( +// Equation(s): +// \Add5~54_combout = ((Kp_Out[18] $ (Ki_Out[18] $ (\Add5~52 )))) # (GND) +// \Add5~55 = CARRY((Kp_Out[18] & ((!\Add5~52 ) # (!Ki_Out[18]))) # (!Kp_Out[18] & (!Ki_Out[18] & !\Add5~52 ))) + + .dataa(Kp_Out[18]), + .datab(Ki_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~52 ), + .combout(\Add5~54_combout ), + .cout(\Add5~55 )); +// synopsys translate_off +defparam \Add5~54 .lut_mask = 16'h962B; +defparam \Add5~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N18 +cycloneive_lcell_comb \Add5~57 ( +// Equation(s): +// \Add5~57_combout = (Kp_Out[19] & ((Ki_Out[19] & (!\Add5~55 )) # (!Ki_Out[19] & (\Add5~55 & VCC)))) # (!Kp_Out[19] & ((Ki_Out[19] & ((\Add5~55 ) # (GND))) # (!Ki_Out[19] & (!\Add5~55 )))) +// \Add5~58 = CARRY((Kp_Out[19] & (Ki_Out[19] & !\Add5~55 )) # (!Kp_Out[19] & ((Ki_Out[19]) # (!\Add5~55 )))) + + .dataa(Kp_Out[19]), + .datab(Ki_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~55 ), + .combout(\Add5~57_combout ), + .cout(\Add5~58 )); +// synopsys translate_off +defparam \Add5~57 .lut_mask = 16'h694D; +defparam \Add5~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N20 +cycloneive_lcell_comb \Add5~60 ( +// Equation(s): +// \Add5~60_combout = Ki_Out[20] $ (\Add5~58 $ (Kp_Out[20])) + + .dataa(Ki_Out[20]), + .datab(gnd), + .datac(gnd), + .datad(Kp_Out[20]), + .cin(\Add5~58 ), + .combout(\Add5~60_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~60 .lut_mask = 16'hA55A; +defparam \Add5~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N12 +cycloneive_lcell_comb \Add5~62 ( +// Equation(s): +// \Add5~62_combout = (!\Vout[13]~reg0_q & \Add5~60_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~60_combout ), + .cin(gnd), + .combout(\Add5~62_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~62 .lut_mask = 16'h0F00; +defparam \Add5~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N10 +cycloneive_lcell_comb \Add7~19 ( +// Equation(s): +// \Add7~19_combout = (!\Vout[13]~reg0_q & Kd_Out[19]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[19]), + .cin(gnd), + .combout(\Add7~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~19 .lut_mask = 16'h0F00; +defparam \Add7~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N16 +cycloneive_lcell_comb \Add7~18 ( +// Equation(s): +// \Add7~18_combout = (!\Vout[13]~reg0_q & Kd_Out[18]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[18]), + .cin(gnd), + .combout(\Add7~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~18 .lut_mask = 16'h0F00; +defparam \Add7~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N10 +cycloneive_lcell_comb \Add7~17 ( +// Equation(s): +// \Add7~17_combout = (Kd_Out[17] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[17]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~17 .lut_mask = 16'h00F0; +defparam \Add7~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N20 +cycloneive_lcell_comb \Add7~16 ( +// Equation(s): +// \Add7~16_combout = (Kd_Out[16] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[16]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~16 .lut_mask = 16'h00F0; +defparam \Add7~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N26 +cycloneive_lcell_comb \Add7~15 ( +// Equation(s): +// \Add7~15_combout = (!\Vout[13]~reg0_q & Kd_Out[15]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[15]), + .cin(gnd), + .combout(\Add7~15_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~15 .lut_mask = 16'h0F00; +defparam \Add7~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N4 +cycloneive_lcell_comb \Add7~14 ( +// Equation(s): +// \Add7~14_combout = (!\Vout[13]~reg0_q & Kd_Out[14]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[14]), + .cin(gnd), + .combout(\Add7~14_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~14 .lut_mask = 16'h0F00; +defparam \Add7~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N2 +cycloneive_lcell_comb \Add7~13 ( +// Equation(s): +// \Add7~13_combout = (Kd_Out[13] & !\Vout[13]~reg0_q ) + + .dataa(Kd_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~13_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~13 .lut_mask = 16'h00AA; +defparam \Add7~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N14 +cycloneive_lcell_comb \Add7~12 ( +// Equation(s): +// \Add7~12_combout = (Kd_Out[12] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(Kd_Out[12]), + .datac(\Vout[13]~reg0_q ), + .datad(gnd), + .cin(gnd), + .combout(\Add7~12_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~12 .lut_mask = 16'h0C0C; +defparam \Add7~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N20 +cycloneive_lcell_comb \Add7~11 ( +// Equation(s): +// \Add7~11_combout = (!\Vout[13]~reg0_q & Kd_Out[11]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[11]), + .cin(gnd), + .combout(\Add7~11_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~11 .lut_mask = 16'h0F00; +defparam \Add7~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N16 +cycloneive_lcell_comb \Add7~10 ( +// Equation(s): +// \Add7~10_combout = (Kd_Out[10] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[10]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~10_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~10 .lut_mask = 16'h00F0; +defparam \Add7~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N12 +cycloneive_lcell_comb \Add7~9 ( +// Equation(s): +// \Add7~9_combout = (Kd_Out[9] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[9]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~9_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~9 .lut_mask = 16'h00F0; +defparam \Add7~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N16 +cycloneive_lcell_comb \Add7~8 ( +// Equation(s): +// \Add7~8_combout = (!\Vout[13]~reg0_q & Kd_Out[8]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[8]), + .cin(gnd), + .combout(\Add7~8_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~8 .lut_mask = 16'h5500; +defparam \Add7~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N8 +cycloneive_lcell_comb \Add5~16 ( +// Equation(s): +// \Add5~16_combout = (\Vout[13]~reg0_q & (!\Vout[0]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~14_combout ))) + + .dataa(\Vout[0]~reg0_q ), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~14_combout ), + .cin(gnd), + .combout(\Add5~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~16 .lut_mask = 16'h5F50; +defparam \Add5~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y14_N0 +cycloneive_lcell_comb \Add7~1 ( +// Equation(s): +// \Add7~1_combout = (!\Vout[13]~reg0_q & Kd_Out[6]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[6]), + .cin(gnd), + .combout(\Add7~1_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~1 .lut_mask = 16'h0F00; +defparam \Add7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N0 +cycloneive_lcell_comb \Add5~17 ( +// Equation(s): +// \Add5~17_combout = (!\Vout[13]~reg0_q & \Add5~12_combout ) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\Add5~12_combout ), + .cin(gnd), + .combout(\Add5~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~17 .lut_mask = 16'h5500; +defparam \Add5~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N8 +cycloneive_lcell_comb \Add7~2 ( +// Equation(s): +// \Add7~2_combout = (!\Vout[13]~reg0_q & Kd_Out[5]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[5]), + .cin(gnd), + .combout(\Add7~2_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~2 .lut_mask = 16'h5500; +defparam \Add7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N10 +cycloneive_lcell_comb \Add5~18 ( +// Equation(s): +// \Add5~18_combout = (\Add5~10_combout & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Add5~10_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~18 .lut_mask = 16'h00F0; +defparam \Add5~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N4 +cycloneive_lcell_comb \Add7~3 ( +// Equation(s): +// \Add7~3_combout = (Kd_Out[4] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(Kd_Out[4]), + .datac(gnd), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~3_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~3 .lut_mask = 16'h00CC; +defparam \Add7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N2 +cycloneive_lcell_comb \Add5~19 ( +// Equation(s): +// \Add5~19_combout = (!\Vout[13]~reg0_q & \Add5~8_combout ) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~19 .lut_mask = 16'h3030; +defparam \Add5~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N2 +cycloneive_lcell_comb \Add5~20 ( +// Equation(s): +// \Add5~20_combout = (!\Vout[13]~reg0_q & \Add5~6_combout ) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\Add5~6_combout ), + .cin(gnd), + .combout(\Add5~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~20 .lut_mask = 16'h5500; +defparam \Add5~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N8 +cycloneive_lcell_comb \Add7~4 ( +// Equation(s): +// \Add7~4_combout = (!\Vout[13]~reg0_q & Kd_Out[3]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[3]), + .cin(gnd), + .combout(\Add7~4_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~4 .lut_mask = 16'h5500; +defparam \Add7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N14 +cycloneive_lcell_comb \Add7~5 ( +// Equation(s): +// \Add7~5_combout = (Kd_Out[2] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[2]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~5_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~5 .lut_mask = 16'h00F0; +defparam \Add7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N0 +cycloneive_lcell_comb \Add5~21 ( +// Equation(s): +// \Add5~21_combout = (!\Vout[13]~reg0_q & \Add5~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~4_combout ), + .cin(gnd), + .combout(\Add5~21_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~21 .lut_mask = 16'h0F00; +defparam \Add5~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N6 +cycloneive_lcell_comb \Add7~6 ( +// Equation(s): +// \Add7~6_combout = (Kd_Out[1] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[1]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~6_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~6 .lut_mask = 16'h00F0; +defparam \Add7~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N8 +cycloneive_lcell_comb \Add5~22 ( +// Equation(s): +// \Add5~22_combout = (\Add5~2_combout & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Add5~2_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~22_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~22 .lut_mask = 16'h00F0; +defparam \Add5~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N10 +cycloneive_lcell_comb \Add5~23 ( +// Equation(s): +// \Add5~23_combout = (!\Vout[13]~reg0_q & \Add5~0_combout ) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~23_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~23 .lut_mask = 16'h3030; +defparam \Add5~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N22 +cycloneive_lcell_comb \Add7~7 ( +// Equation(s): +// \Add7~7_combout = (Kd_Out[0] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[0]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~7_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~7 .lut_mask = 16'h00F0; +defparam \Add7~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N12 +cycloneive_lcell_comb \Vout[0]~15 ( +// Equation(s): +// \Vout[0]~15_cout = CARRY((\Add5~23_combout & \Add7~7_combout )) + + .dataa(\Add5~23_combout ), + .datab(\Add7~7_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\Vout[0]~15_cout )); +// synopsys translate_off +defparam \Vout[0]~15 .lut_mask = 16'h0088; +defparam \Vout[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N14 +cycloneive_lcell_comb \Vout[0]~17 ( +// Equation(s): +// \Vout[0]~17_cout = CARRY((\Add7~6_combout & (!\Add5~22_combout & !\Vout[0]~15_cout )) # (!\Add7~6_combout & ((!\Vout[0]~15_cout ) # (!\Add5~22_combout )))) + + .dataa(\Add7~6_combout ), + .datab(\Add5~22_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~15_cout ), + .combout(), + .cout(\Vout[0]~17_cout )); +// synopsys translate_off +defparam \Vout[0]~17 .lut_mask = 16'h0017; +defparam \Vout[0]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N16 +cycloneive_lcell_comb \Vout[0]~19 ( +// Equation(s): +// \Vout[0]~19_cout = CARRY((\Add7~5_combout & ((\Add5~21_combout ) # (!\Vout[0]~17_cout ))) # (!\Add7~5_combout & (\Add5~21_combout & !\Vout[0]~17_cout ))) + + .dataa(\Add7~5_combout ), + .datab(\Add5~21_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~17_cout ), + .combout(), + .cout(\Vout[0]~19_cout )); +// synopsys translate_off +defparam \Vout[0]~19 .lut_mask = 16'h008E; +defparam \Vout[0]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N18 +cycloneive_lcell_comb \Vout[0]~21 ( +// Equation(s): +// \Vout[0]~21_cout = CARRY((\Add5~20_combout & (!\Add7~4_combout & !\Vout[0]~19_cout )) # (!\Add5~20_combout & ((!\Vout[0]~19_cout ) # (!\Add7~4_combout )))) + + .dataa(\Add5~20_combout ), + .datab(\Add7~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~19_cout ), + .combout(), + .cout(\Vout[0]~21_cout )); +// synopsys translate_off +defparam \Vout[0]~21 .lut_mask = 16'h0017; +defparam \Vout[0]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N20 +cycloneive_lcell_comb \Vout[0]~23 ( +// Equation(s): +// \Vout[0]~23_cout = CARRY((\Add7~3_combout & ((\Add5~19_combout ) # (!\Vout[0]~21_cout ))) # (!\Add7~3_combout & (\Add5~19_combout & !\Vout[0]~21_cout ))) + + .dataa(\Add7~3_combout ), + .datab(\Add5~19_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~21_cout ), + .combout(), + .cout(\Vout[0]~23_cout )); +// synopsys translate_off +defparam \Vout[0]~23 .lut_mask = 16'h008E; +defparam \Vout[0]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N22 +cycloneive_lcell_comb \Vout[0]~25 ( +// Equation(s): +// \Vout[0]~25_cout = CARRY((\Add7~2_combout & (!\Add5~18_combout & !\Vout[0]~23_cout )) # (!\Add7~2_combout & ((!\Vout[0]~23_cout ) # (!\Add5~18_combout )))) + + .dataa(\Add7~2_combout ), + .datab(\Add5~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~23_cout ), + .combout(), + .cout(\Vout[0]~25_cout )); +// synopsys translate_off +defparam \Vout[0]~25 .lut_mask = 16'h0017; +defparam \Vout[0]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N24 +cycloneive_lcell_comb \Vout[0]~27 ( +// Equation(s): +// \Vout[0]~27_cout = CARRY((\Add7~1_combout & ((\Add5~17_combout ) # (!\Vout[0]~25_cout ))) # (!\Add7~1_combout & (\Add5~17_combout & !\Vout[0]~25_cout ))) + + .dataa(\Add7~1_combout ), + .datab(\Add5~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~25_cout ), + .combout(), + .cout(\Vout[0]~27_cout )); +// synopsys translate_off +defparam \Vout[0]~27 .lut_mask = 16'h008E; +defparam \Vout[0]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N26 +cycloneive_lcell_comb \Vout[0]~28 ( +// Equation(s): +// \Vout[0]~28_combout = (\Add7~0_combout & ((\Add5~16_combout & (\Vout[0]~27_cout & VCC)) # (!\Add5~16_combout & (!\Vout[0]~27_cout )))) # (!\Add7~0_combout & ((\Add5~16_combout & (!\Vout[0]~27_cout )) # (!\Add5~16_combout & ((\Vout[0]~27_cout ) # +// (GND))))) +// \Vout[0]~29 = CARRY((\Add7~0_combout & (!\Add5~16_combout & !\Vout[0]~27_cout )) # (!\Add7~0_combout & ((!\Vout[0]~27_cout ) # (!\Add5~16_combout )))) + + .dataa(\Add7~0_combout ), + .datab(\Add5~16_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~27_cout ), + .combout(\Vout[0]~28_combout ), + .cout(\Vout[0]~29 )); +// synopsys translate_off +defparam \Vout[0]~28 .lut_mask = 16'h9617; +defparam \Vout[0]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N28 +cycloneive_lcell_comb \Vout[1]~30 ( +// Equation(s): +// \Vout[1]~30_combout = ((\Add7~8_combout $ (\Add5~26_combout $ (!\Vout[0]~29 )))) # (GND) +// \Vout[1]~31 = CARRY((\Add7~8_combout & ((\Add5~26_combout ) # (!\Vout[0]~29 ))) # (!\Add7~8_combout & (\Add5~26_combout & !\Vout[0]~29 ))) + + .dataa(\Add7~8_combout ), + .datab(\Add5~26_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~29 ), + .combout(\Vout[1]~30_combout ), + .cout(\Vout[1]~31 )); +// synopsys translate_off +defparam \Vout[1]~30 .lut_mask = 16'h698E; +defparam \Vout[1]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y18_N29 +dffeas \Vout[1]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[1]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[1]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[1]~reg0 .is_wysiwyg = "true"; +defparam \Vout[1]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N4 +cycloneive_lcell_comb \Add5~26 ( +// Equation(s): +// \Add5~26_combout = (\Vout[13]~reg0_q & (!\Vout[1]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~24_combout ))) + + .dataa(gnd), + .datab(\Vout[1]~reg0_q ), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~24_combout ), + .cin(gnd), + .combout(\Add5~26_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~26 .lut_mask = 16'h3F30; +defparam \Add5~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N30 +cycloneive_lcell_comb \Vout[2]~32 ( +// Equation(s): +// \Vout[2]~32_combout = (\Add5~29_combout & ((\Add7~9_combout & (\Vout[1]~31 & VCC)) # (!\Add7~9_combout & (!\Vout[1]~31 )))) # (!\Add5~29_combout & ((\Add7~9_combout & (!\Vout[1]~31 )) # (!\Add7~9_combout & ((\Vout[1]~31 ) # (GND))))) +// \Vout[2]~33 = CARRY((\Add5~29_combout & (!\Add7~9_combout & !\Vout[1]~31 )) # (!\Add5~29_combout & ((!\Vout[1]~31 ) # (!\Add7~9_combout )))) + + .dataa(\Add5~29_combout ), + .datab(\Add7~9_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[1]~31 ), + .combout(\Vout[2]~32_combout ), + .cout(\Vout[2]~33 )); +// synopsys translate_off +defparam \Vout[2]~32 .lut_mask = 16'h9617; +defparam \Vout[2]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y18_N31 +dffeas \Vout[2]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[2]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[2]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[2]~reg0 .is_wysiwyg = "true"; +defparam \Vout[2]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N6 +cycloneive_lcell_comb \Add5~29 ( +// Equation(s): +// \Add5~29_combout = (\Vout[13]~reg0_q & (!\Vout[2]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~27_combout ))) + + .dataa(\Vout[2]~reg0_q ), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~27_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~29_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~29 .lut_mask = 16'h7474; +defparam \Add5~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N0 +cycloneive_lcell_comb \Vout[3]~34 ( +// Equation(s): +// \Vout[3]~34_combout = ((\Add5~32_combout $ (\Add7~10_combout $ (!\Vout[2]~33 )))) # (GND) +// \Vout[3]~35 = CARRY((\Add5~32_combout & ((\Add7~10_combout ) # (!\Vout[2]~33 ))) # (!\Add5~32_combout & (\Add7~10_combout & !\Vout[2]~33 ))) + + .dataa(\Add5~32_combout ), + .datab(\Add7~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[2]~33 ), + .combout(\Vout[3]~34_combout ), + .cout(\Vout[3]~35 )); +// synopsys translate_off +defparam \Vout[3]~34 .lut_mask = 16'h698E; +defparam \Vout[3]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N1 +dffeas \Vout[3]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[3]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[3]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[3]~reg0 .is_wysiwyg = "true"; +defparam \Vout[3]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N26 +cycloneive_lcell_comb \Add5~32 ( +// Equation(s): +// \Add5~32_combout = (\Vout[13]~reg0_q & ((!\Vout[3]~reg0_q ))) # (!\Vout[13]~reg0_q & (\Add5~30_combout )) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~30_combout ), + .datad(\Vout[3]~reg0_q ), + .cin(gnd), + .combout(\Add5~32_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~32 .lut_mask = 16'h30FC; +defparam \Add5~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N2 +cycloneive_lcell_comb \Vout[4]~36 ( +// Equation(s): +// \Vout[4]~36_combout = (\Add5~35_combout & ((\Add7~11_combout & (\Vout[3]~35 & VCC)) # (!\Add7~11_combout & (!\Vout[3]~35 )))) # (!\Add5~35_combout & ((\Add7~11_combout & (!\Vout[3]~35 )) # (!\Add7~11_combout & ((\Vout[3]~35 ) # (GND))))) +// \Vout[4]~37 = CARRY((\Add5~35_combout & (!\Add7~11_combout & !\Vout[3]~35 )) # (!\Add5~35_combout & ((!\Vout[3]~35 ) # (!\Add7~11_combout )))) + + .dataa(\Add5~35_combout ), + .datab(\Add7~11_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[3]~35 ), + .combout(\Vout[4]~36_combout ), + .cout(\Vout[4]~37 )); +// synopsys translate_off +defparam \Vout[4]~36 .lut_mask = 16'h9617; +defparam \Vout[4]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N3 +dffeas \Vout[4]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[4]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[4]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[4]~reg0 .is_wysiwyg = "true"; +defparam \Vout[4]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N30 +cycloneive_lcell_comb \Add5~35 ( +// Equation(s): +// \Add5~35_combout = (\Vout[13]~reg0_q & (!\Vout[4]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~33_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[4]~reg0_q ), + .datad(\Add5~33_combout ), + .cin(gnd), + .combout(\Add5~35_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~35 .lut_mask = 16'h3F0C; +defparam \Add5~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N4 +cycloneive_lcell_comb \Vout[5]~38 ( +// Equation(s): +// \Vout[5]~38_combout = ((\Add7~12_combout $ (\Add5~38_combout $ (!\Vout[4]~37 )))) # (GND) +// \Vout[5]~39 = CARRY((\Add7~12_combout & ((\Add5~38_combout ) # (!\Vout[4]~37 ))) # (!\Add7~12_combout & (\Add5~38_combout & !\Vout[4]~37 ))) + + .dataa(\Add7~12_combout ), + .datab(\Add5~38_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[4]~37 ), + .combout(\Vout[5]~38_combout ), + .cout(\Vout[5]~39 )); +// synopsys translate_off +defparam \Vout[5]~38 .lut_mask = 16'h698E; +defparam \Vout[5]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N5 +dffeas \Vout[5]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[5]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[5]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[5]~reg0 .is_wysiwyg = "true"; +defparam \Vout[5]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N28 +cycloneive_lcell_comb \Add5~38 ( +// Equation(s): +// \Add5~38_combout = (\Vout[13]~reg0_q & (!\Vout[5]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~36_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[5]~reg0_q ), + .datad(\Add5~36_combout ), + .cin(gnd), + .combout(\Add5~38_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~38 .lut_mask = 16'h3F0C; +defparam \Add5~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N6 +cycloneive_lcell_comb \Vout[6]~40 ( +// Equation(s): +// \Vout[6]~40_combout = (\Add7~13_combout & ((\Add5~41_combout & (\Vout[5]~39 & VCC)) # (!\Add5~41_combout & (!\Vout[5]~39 )))) # (!\Add7~13_combout & ((\Add5~41_combout & (!\Vout[5]~39 )) # (!\Add5~41_combout & ((\Vout[5]~39 ) # (GND))))) +// \Vout[6]~41 = CARRY((\Add7~13_combout & (!\Add5~41_combout & !\Vout[5]~39 )) # (!\Add7~13_combout & ((!\Vout[5]~39 ) # (!\Add5~41_combout )))) + + .dataa(\Add7~13_combout ), + .datab(\Add5~41_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[5]~39 ), + .combout(\Vout[6]~40_combout ), + .cout(\Vout[6]~41 )); +// synopsys translate_off +defparam \Vout[6]~40 .lut_mask = 16'h9617; +defparam \Vout[6]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N7 +dffeas \Vout[6]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[6]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[6]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[6]~reg0 .is_wysiwyg = "true"; +defparam \Vout[6]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N24 +cycloneive_lcell_comb \Add5~41 ( +// Equation(s): +// \Add5~41_combout = (\Vout[13]~reg0_q & (!\Vout[6]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~39_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[6]~reg0_q ), + .datad(\Add5~39_combout ), + .cin(gnd), + .combout(\Add5~41_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~41 .lut_mask = 16'h3F0C; +defparam \Add5~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N8 +cycloneive_lcell_comb \Vout[7]~42 ( +// Equation(s): +// \Vout[7]~42_combout = ((\Add5~44_combout $ (\Add7~14_combout $ (!\Vout[6]~41 )))) # (GND) +// \Vout[7]~43 = CARRY((\Add5~44_combout & ((\Add7~14_combout ) # (!\Vout[6]~41 ))) # (!\Add5~44_combout & (\Add7~14_combout & !\Vout[6]~41 ))) + + .dataa(\Add5~44_combout ), + .datab(\Add7~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[6]~41 ), + .combout(\Vout[7]~42_combout ), + .cout(\Vout[7]~43 )); +// synopsys translate_off +defparam \Vout[7]~42 .lut_mask = 16'h698E; +defparam \Vout[7]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N9 +dffeas \Vout[7]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[7]~42_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[7]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[7]~reg0 .is_wysiwyg = "true"; +defparam \Vout[7]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N30 +cycloneive_lcell_comb \Add5~44 ( +// Equation(s): +// \Add5~44_combout = (\Vout[13]~reg0_q & (!\Vout[7]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~42_combout ))) + + .dataa(gnd), + .datab(\Vout[7]~reg0_q ), + .datac(\Add5~42_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~44_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~44 .lut_mask = 16'h33F0; +defparam \Add5~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N10 +cycloneive_lcell_comb \Vout[8]~44 ( +// Equation(s): +// \Vout[8]~44_combout = (\Add7~15_combout & ((\Add5~47_combout & (\Vout[7]~43 & VCC)) # (!\Add5~47_combout & (!\Vout[7]~43 )))) # (!\Add7~15_combout & ((\Add5~47_combout & (!\Vout[7]~43 )) # (!\Add5~47_combout & ((\Vout[7]~43 ) # (GND))))) +// \Vout[8]~45 = CARRY((\Add7~15_combout & (!\Add5~47_combout & !\Vout[7]~43 )) # (!\Add7~15_combout & ((!\Vout[7]~43 ) # (!\Add5~47_combout )))) + + .dataa(\Add7~15_combout ), + .datab(\Add5~47_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[7]~43 ), + .combout(\Vout[8]~44_combout ), + .cout(\Vout[8]~45 )); +// synopsys translate_off +defparam \Vout[8]~44 .lut_mask = 16'h9617; +defparam \Vout[8]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N11 +dffeas \Vout[8]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[8]~44_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[8]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[8]~reg0 .is_wysiwyg = "true"; +defparam \Vout[8]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N26 +cycloneive_lcell_comb \Add5~47 ( +// Equation(s): +// \Add5~47_combout = (\Vout[13]~reg0_q & (!\Vout[8]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~45_combout ))) + + .dataa(\Vout[8]~reg0_q ), + .datab(\Vout[13]~reg0_q ), + .datac(gnd), + .datad(\Add5~45_combout ), + .cin(gnd), + .combout(\Add5~47_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~47 .lut_mask = 16'h7744; +defparam \Add5~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N12 +cycloneive_lcell_comb \Vout[9]~46 ( +// Equation(s): +// \Vout[9]~46_combout = ((\Add7~16_combout $ (\Add5~50_combout $ (!\Vout[8]~45 )))) # (GND) +// \Vout[9]~47 = CARRY((\Add7~16_combout & ((\Add5~50_combout ) # (!\Vout[8]~45 ))) # (!\Add7~16_combout & (\Add5~50_combout & !\Vout[8]~45 ))) + + .dataa(\Add7~16_combout ), + .datab(\Add5~50_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[8]~45 ), + .combout(\Vout[9]~46_combout ), + .cout(\Vout[9]~47 )); +// synopsys translate_off +defparam \Vout[9]~46 .lut_mask = 16'h698E; +defparam \Vout[9]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N13 +dffeas \Vout[9]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[9]~46_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[9]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[9]~reg0 .is_wysiwyg = "true"; +defparam \Vout[9]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N24 +cycloneive_lcell_comb \Add5~50 ( +// Equation(s): +// \Add5~50_combout = (\Vout[13]~reg0_q & ((!\Vout[9]~reg0_q ))) # (!\Vout[13]~reg0_q & (\Add5~48_combout )) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~48_combout ), + .datad(\Vout[9]~reg0_q ), + .cin(gnd), + .combout(\Add5~50_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~50 .lut_mask = 16'h30FC; +defparam \Add5~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N14 +cycloneive_lcell_comb \Vout[10]~48 ( +// Equation(s): +// \Vout[10]~48_combout = (\Add5~53_combout & ((\Add7~17_combout & (\Vout[9]~47 & VCC)) # (!\Add7~17_combout & (!\Vout[9]~47 )))) # (!\Add5~53_combout & ((\Add7~17_combout & (!\Vout[9]~47 )) # (!\Add7~17_combout & ((\Vout[9]~47 ) # (GND))))) +// \Vout[10]~49 = CARRY((\Add5~53_combout & (!\Add7~17_combout & !\Vout[9]~47 )) # (!\Add5~53_combout & ((!\Vout[9]~47 ) # (!\Add7~17_combout )))) + + .dataa(\Add5~53_combout ), + .datab(\Add7~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[9]~47 ), + .combout(\Vout[10]~48_combout ), + .cout(\Vout[10]~49 )); +// synopsys translate_off +defparam \Vout[10]~48 .lut_mask = 16'h9617; +defparam \Vout[10]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N15 +dffeas \Vout[10]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[10]~48_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[10]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[10]~reg0 .is_wysiwyg = "true"; +defparam \Vout[10]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N22 +cycloneive_lcell_comb \Add5~53 ( +// Equation(s): +// \Add5~53_combout = (\Vout[13]~reg0_q & (!\Vout[10]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~51_combout ))) + + .dataa(gnd), + .datab(\Vout[10]~reg0_q ), + .datac(\Add5~51_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~53_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~53 .lut_mask = 16'h33F0; +defparam \Add5~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N16 +cycloneive_lcell_comb \Vout[11]~50 ( +// Equation(s): +// \Vout[11]~50_combout = ((\Add7~18_combout $ (\Add5~56_combout $ (!\Vout[10]~49 )))) # (GND) +// \Vout[11]~51 = CARRY((\Add7~18_combout & ((\Add5~56_combout ) # (!\Vout[10]~49 ))) # (!\Add7~18_combout & (\Add5~56_combout & !\Vout[10]~49 ))) + + .dataa(\Add7~18_combout ), + .datab(\Add5~56_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[10]~49 ), + .combout(\Vout[11]~50_combout ), + .cout(\Vout[11]~51 )); +// synopsys translate_off +defparam \Vout[11]~50 .lut_mask = 16'h698E; +defparam \Vout[11]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N17 +dffeas \Vout[11]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[11]~50_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[11]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[11]~reg0 .is_wysiwyg = "true"; +defparam \Vout[11]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N28 +cycloneive_lcell_comb \Add5~56 ( +// Equation(s): +// \Add5~56_combout = (\Vout[13]~reg0_q & (!\Vout[11]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~54_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[11]~reg0_q ), + .datad(\Add5~54_combout ), + .cin(gnd), + .combout(\Add5~56_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~56 .lut_mask = 16'h3F0C; +defparam \Add5~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N18 +cycloneive_lcell_comb \Vout[12]~52 ( +// Equation(s): +// \Vout[12]~52_combout = (\Add7~19_combout & ((\Add5~59_combout & (\Vout[11]~51 & VCC)) # (!\Add5~59_combout & (!\Vout[11]~51 )))) # (!\Add7~19_combout & ((\Add5~59_combout & (!\Vout[11]~51 )) # (!\Add5~59_combout & ((\Vout[11]~51 ) # (GND))))) +// \Vout[12]~53 = CARRY((\Add7~19_combout & (!\Add5~59_combout & !\Vout[11]~51 )) # (!\Add7~19_combout & ((!\Vout[11]~51 ) # (!\Add5~59_combout )))) + + .dataa(\Add7~19_combout ), + .datab(\Add5~59_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[11]~51 ), + .combout(\Vout[12]~52_combout ), + .cout(\Vout[12]~53 )); +// synopsys translate_off +defparam \Vout[12]~52 .lut_mask = 16'h9617; +defparam \Vout[12]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N19 +dffeas \Vout[12]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[12]~52_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[12]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[12]~reg0 .is_wysiwyg = "true"; +defparam \Vout[12]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N22 +cycloneive_lcell_comb \Add5~59 ( +// Equation(s): +// \Add5~59_combout = (\Vout[13]~reg0_q & (!\Vout[12]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~57_combout ))) + + .dataa(gnd), + .datab(\Vout[12]~reg0_q ), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~57_combout ), + .cin(gnd), + .combout(\Add5~59_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~59 .lut_mask = 16'h3F30; +defparam \Add5~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N20 +cycloneive_lcell_comb \Vout[13]~54 ( +// Equation(s): +// \Vout[13]~54_combout = \Add7~20_combout $ (\Vout[12]~53 $ (!\Add5~62_combout )) + + .dataa(gnd), + .datab(\Add7~20_combout ), + .datac(gnd), + .datad(\Add5~62_combout ), + .cin(\Vout[12]~53 ), + .combout(\Vout[13]~54_combout ), + .cout()); +// synopsys translate_off +defparam \Vout[13]~54 .lut_mask = 16'h3CC3; +defparam \Vout[13]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N21 +dffeas \Vout[13]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[13]~54_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[13]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[13]~reg0 .is_wysiwyg = "true"; +defparam \Vout[13]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N20 +cycloneive_lcell_comb \Add7~0 ( +// Equation(s): +// \Add7~0_combout = (\Vout[13]~reg0_q ) # (Kd_Out[7]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[7]), + .cin(gnd), + .combout(\Add7~0_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~0 .lut_mask = 16'hFFF0; +defparam \Add7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y18_N27 +dffeas \Vout[0]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[0]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[0]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[0]~reg0 .is_wysiwyg = "true"; +defparam \Vout[0]~reg0 .power_up = "low"; +// synopsys translate_on + +assign Vout[0] = \Vout[0]~output_o ; + +assign Vout[1] = \Vout[1]~output_o ; + +assign Vout[2] = \Vout[2]~output_o ; + +assign Vout[3] = \Vout[3]~output_o ; + +assign Vout[4] = \Vout[4]~output_o ; + +assign Vout[5] = \Vout[5]~output_o ; + +assign Vout[6] = \Vout[6]~output_o ; + +assign Vout[7] = \Vout[7]~output_o ; + +assign Vout[8] = \Vout[8]~output_o ; + +assign Vout[9] = \Vout[9]~output_o ; + +assign Vout[10] = \Vout[10]~output_o ; + +assign Vout[11] = \Vout[11]~output_o ; + +assign Vout[12] = \Vout[12]~output_o ; + +assign Vout[13] = \Vout[13]~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_DATA0~~ibuf_o ; + + +endmodule diff --git a/pid/simulation/modelsim/pid_8_1200mv_85c_v_slow.sdo b/pid/simulation/modelsim/pid_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..e8d3b00 --- /dev/null +++ b/pid/simulation/modelsim/pid_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,6913 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "pid") + (DATE "12/04/2018 14:36:39") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2429:2429:2429) (2385:2385:2385)) + (IOPATH i o (3147:3147:3147) (3095:3095:3095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1594:1594:1594) (1550:1550:1550)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2312:2312:2312) (2168:2168:2168)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1498:1498:1498) (1416:1416:1416)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1578:1578:1578) (1500:1500:1500)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1855:1855:1855) (1729:1729:1729)) + (IOPATH i o (3127:3127:3127) (3075:3075:3075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1304:1304:1304) (1310:1310:1310)) + (IOPATH i o (3128:3128:3128) (3105:3105:3105)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1839:1839:1839) (1715:1715:1715)) + (IOPATH i o (3147:3147:3147) (3095:3095:3095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1914:1914:1914) (1922:1922:1922)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1887:1887:1887) (1761:1761:1761)) + (IOPATH i o (3048:3048:3048) (3009:3009:3009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1851:1851:1851) (1712:1712:1712)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1994:1994:1994) (1932:1932:1932)) + (IOPATH i o (3128:3128:3128) (3105:3105:3105)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2370:2370:2370) (2343:2343:2343)) + (IOPATH i o (3117:3117:3117) (3065:3065:3065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1659:1659:1659) (1580:1580:1580)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (383:383:383) (459:459:459)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~1) + (DELAY + (ABSOLUTE + (PORT datac (1013:1013:1013) (1037:1037:1037)) + (PORT datad (3685:3685:3685) (3854:3854:3854)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~0) + (DELAY + (ABSOLUTE + (PORT datac (1013:1013:1013) (1037:1037:1037)) + (PORT datad (4040:4040:4040) (4269:4269:4269)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~2) + (DELAY + (ABSOLUTE + (PORT datac (3798:3798:3798) (3991:3991:3991)) + (PORT datad (809:809:809) (791:791:791)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (4099:4099:4099) (4236:4236:4236)) + (PORT datac (1017:1017:1017) (1042:1042:1042)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~6) + (DELAY + (ABSOLUTE + (PORT datac (3584:3584:3584) (3811:3811:3811)) + (PORT datad (808:808:808) (791:791:791)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~8) + (DELAY + (ABSOLUTE + (PORT datac (1016:1016:1016) (1041:1041:1041)) + (PORT datad (3611:3611:3611) (3785:3785:3785)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (784:784:784) (831:831:831)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~10) + (DELAY + (ABSOLUTE + (PORT datac (1017:1017:1017) (1041:1041:1041)) + (PORT datad (3306:3306:3306) (3534:3534:3534)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~12) + (DELAY + (ABSOLUTE + (PORT datac (1013:1013:1013) (1037:1037:1037)) + (PORT datad (3610:3610:3610) (3791:3791:3791)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (726:726:726) (772:772:772)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (3886:3886:3886) (4074:4074:4074)) + (PORT datad (692:692:692) (733:733:733)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~16) + (DELAY + (ABSOLUTE + (PORT datac (1014:1014:1014) (1039:1039:1039)) + (PORT datad (4006:4006:4006) (4168:4168:4168)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (3773:3773:3773) (3971:3971:3971)) + (PORT datad (695:695:695) (736:736:736)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~20) + (DELAY + (ABSOLUTE + (PORT datac (3630:3630:3630) (3856:3856:3856)) + (PORT datad (703:703:703) (745:745:745)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~22) + (DELAY + (ABSOLUTE + (PORT datac (3602:3602:3602) (3817:3817:3817)) + (PORT datad (698:698:698) (740:740:740)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~24) + (DELAY + (ABSOLUTE + (PORT datac (3836:3836:3836) (4046:4046:4046)) + (PORT datad (704:704:704) (746:746:746)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~26) + (DELAY + (ABSOLUTE + (PORT datac (1743:1743:1743) (1897:1897:1897)) + (PORT datad (699:699:699) (741:741:741)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (583:583:583) (627:627:627)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (483:483:483)) + (PORT datab (543:543:543) (506:506:506)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (517:517:517)) + (PORT datab (491:491:491) (478:478:478)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (566:566:566) (585:585:585)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~3) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (526:526:526)) + (PORT datab (581:581:581) (543:543:543)) + (PORT datac (722:722:722) (660:660:660)) + (PORT datad (275:275:275) (300:300:300)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1640:1640:1640)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1670:1670:1670) (1620:1620:1620)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datac (579:579:579) (594:594:594)) + (PORT datad (536:536:536) (556:556:556)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~2) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (525:525:525)) + (PORT datab (320:320:320) (350:350:350)) + (PORT datac (284:284:284) (323:323:323)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~0) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (365:365:365)) + (PORT datab (277:277:277) (303:303:303)) + (PORT datac (496:496:496) (477:477:477)) + (PORT datad (286:286:286) (314:314:314)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~20) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (392:392:392)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (606:606:606)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (301:301:301) (377:377:377)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~1) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (365:365:365)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (496:496:496) (477:477:477)) + (PORT datad (287:287:287) (315:315:315)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (439:439:439)) + (PORT datab (341:341:341) (423:423:423)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (303:303:303) (379:379:379)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (526:526:526)) + (PORT datab (316:316:316) (344:344:344)) + (PORT datad (522:522:522) (495:495:495)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Clk_Ctrl) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1640:1640:1640)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1670:1670:1670) (1620:1620:1620)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[1\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~25) + (DELAY + (ABSOLUTE + (PORT datab (3634:3634:3634) (3811:3811:3811)) + (PORT datac (773:773:773) (753:753:753)) + (PORT datad (700:700:700) (743:743:743)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (542:542:542) (504:504:504)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[2\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~23) + (DELAY + (ABSOLUTE + (PORT datab (3623:3623:3623) (3850:3850:3850)) + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (483:483:483)) + (PORT datab (488:488:488) (469:469:469)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[3\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (590:590:590)) + (PORT datac (3687:3687:3687) (3961:3961:3961)) + (PORT datad (688:688:688) (729:729:729)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (810:810:810)) + (PORT datab (484:484:484) (464:464:464)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[4\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (3320:3320:3320) (3553:3553:3553)) + (PORT datac (1017:1017:1017) (1042:1042:1042)) + (PORT datad (864:864:864) (869:869:869)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[5\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (845:845:845)) + (PORT datab (540:540:540) (499:499:499)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[5\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (623:623:623)) + (PORT datac (3559:3559:3559) (3769:3769:3769)) + (PORT datad (694:694:694) (735:735:735)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (475:475:475)) + (PORT datab (541:541:541) (499:499:499)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[6\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~15) + (DELAY + (ABSOLUTE + (PORT datab (740:740:740) (788:788:788)) + (PORT datac (4095:4095:4095) (4327:4327:4327)) + (PORT datad (845:845:845) (809:809:809)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[7\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (805:805:805)) + (PORT datab (540:540:540) (499:499:499)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[7\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~13) + (DELAY + (ABSOLUTE + (PORT datab (4110:4110:4110) (4357:4357:4357)) + (PORT datac (514:514:514) (538:538:538)) + (PORT datad (691:691:691) (731:731:731)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[8\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (515:515:515)) + (PORT datab (835:835:835) (792:792:792)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[8\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~11) + (DELAY + (ABSOLUTE + (PORT datab (734:734:734) (782:782:782)) + (PORT datac (3518:3518:3518) (3726:3726:3726)) + (PORT datad (501:501:501) (529:529:529)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[9\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (829:829:829)) + (PORT datab (544:544:544) (506:506:506)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[9\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~9) + (DELAY + (ABSOLUTE + (PORT datab (749:749:749) (798:798:798)) + (PORT datac (3646:3646:3646) (3792:3792:3792)) + (PORT datad (537:537:537) (559:559:559)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[10\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (742:742:742)) + (PORT datab (761:761:761) (691:691:691)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~7) + (DELAY + (ABSOLUTE + (PORT datab (737:737:737) (784:784:784)) + (PORT datac (3916:3916:3916) (4131:4131:4131)) + (PORT datad (505:505:505) (532:532:532)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[11\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (839:839:839)) + (PORT datab (799:799:799) (719:719:719)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[11\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (4004:4004:4004) (4179:4179:4179)) + (PORT datac (589:589:589) (624:624:624)) + (PORT datad (935:935:935) (922:922:922)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[12\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (747:747:747)) + (PORT datab (548:548:548) (512:512:512)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[12\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~3) + (DELAY + (ABSOLUTE + (PORT datab (3681:3681:3681) (3863:3863:3863)) + (PORT datac (771:771:771) (757:757:757)) + (PORT datad (707:707:707) (749:749:749)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[13\]\~42) + (DELAY + (ABSOLUTE + (PORT datab (1260:1260:1260) (1157:1157:1157)) + (PORT datad (824:824:824) (764:764:764)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[13\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT asdata (920:920:920) (886:886:886)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (619:619:619)) + (PORT datac (4018:4018:4018) (4233:4233:4233)) + (PORT datad (705:705:705) (748:748:748)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[0\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (383:383:383) (460:460:460)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1688:1688:1688) (1645:1645:1645)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (470:470:470)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1625:1625:1625) (1574:1574:1574)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (384:384:384) (461:461:461)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2292:2292:2292) (2182:2182:2182)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1971:1971:1971) (1878:1878:1878)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1636:1636:1636) (1578:1578:1578)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[6\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (462:462:462)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1369:1369:1369) (1357:1357:1357)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[7\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (462:462:462)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1414:1414:1414) (1393:1393:1393)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[8\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2077:2077:2077) (1980:1980:1980)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (462:462:462)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2305:2305:2305) (2153:2153:2153)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (472:472:472)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2048:2048:2048) (1923:1923:1923)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (462:462:462)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1987:1987:1987) (1904:1904:1904)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[12\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1682:1682:1682) (1615:1615:1615)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[13\]\~40) + (DELAY + (ABSOLUTE + (PORT datad (331:331:331) (404:404:404)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1064:1064:1064) (1090:1090:1090)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1369:1369:1369) (1362:1362:1362)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1431:1431:1431) (1419:1419:1419)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1949:1949:1949) (1826:1826:1826)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1428:1428:1428) (1412:1412:1412)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1449:1449:1449) (1428:1428:1428)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1435:1435:1435) (1431:1431:1431)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[6\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1480:1480:1480) (1463:1463:1463)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[7\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2042:2042:2042) (1915:1915:1915)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[8\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2020:2020:2020) (1915:1915:1915)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1427:1427:1427) (1414:1414:1414)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1725:1725:1725) (1648:1648:1648)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1967:1967:1967) (1852:1852:1852)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[12\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (333:333:333) (409:409:409)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1663:1663:1663) (1610:1610:1610)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[13\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (462:462:462)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1454:1454:1454) (1437:1437:1437)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1697:1697:1697) (1621:1621:1621)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult2\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT dataa[6] (570:570:570) (587:587:587)) + (PORT dataa[7] (532:532:532) (545:545:545)) + (PORT dataa[8] (561:561:561) (573:573:573)) + (PORT dataa[9] (538:538:538) (553:553:553)) + (PORT dataa[10] (814:814:814) (775:775:775)) + (PORT dataa[11] (531:531:531) (543:543:543)) + (PORT dataa[12] (531:531:531) (551:551:551)) + (PORT dataa[13] (806:806:806) (764:764:764)) + (PORT dataa[14] (817:817:817) (791:791:791)) + (PORT dataa[15] (533:533:533) (553:553:553)) + (PORT dataa[16] (811:811:811) (767:767:767)) + (PORT dataa[17] (556:556:556) (573:573:573)) + (PORT datab[10] (3685:3685:3685) (3935:3935:3935)) + (PORT datab[11] (3989:3989:3989) (4180:4180:4180)) + (PORT datab[12] (3751:3751:3751) (3950:3950:3950)) + (PORT datab[13] (3987:3987:3987) (4184:4184:4184)) + (PORT datab[14] (4019:4019:4019) (4168:4168:4168)) + (PORT datab[15] (3903:3903:3903) (4090:4090:4090)) + (PORT datab[16] (3905:3905:3905) (4113:4113:4113)) + (PORT datab[17] (3935:3935:3935) (4168:4168:4168)) + (IOPATH dataa dataout (3928:3928:3928) (3928:3928:3928)) + (IOPATH datab dataout (3863:3863:3863) (3863:3863:3863)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult2\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (139:139:139) (148:148:148)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1518:1518:1518) (1396:1396:1396)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1190:1190:1190) (1114:1114:1114)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1198:1198:1198) (1122:1122:1122)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1182:1182:1182) (1124:1124:1124)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1228:1228:1228) (1144:1144:1144)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1209:1209:1209) (1133:1133:1133)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1275:1275:1275) (1193:1193:1193)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1264:1264:1264) (1181:1181:1181)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1263:1263:1263) (1182:1182:1182)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (443:443:443)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1238:1238:1238) (1166:1166:1166)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (433:433:433)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2071:2071:2071)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1570:1570:1570) (1467:1467:1467)) + (PORT clrn (1665:1665:1665) (1616:1616:1616)) + (PORT sload (1586:1586:1586) (1673:1673:1673)) + (PORT ena (2107:2107:2107) (2026:2026:2026)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (985:985:985) (967:967:967)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (813:813:813) (753:753:753)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1214:1214:1214) (1132:1132:1132)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2071:2071:2071)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1310:1310:1310) (1240:1240:1240)) + (PORT clrn (1665:1665:1665) (1616:1616:1616)) + (PORT sload (1586:1586:1586) (1673:1673:1673)) + (PORT ena (2107:2107:2107) (2026:2026:2026)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2071:2071:2071)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1272:1272:1272) (1216:1216:1216)) + (PORT clrn (1665:1665:1665) (1616:1616:1616)) + (PORT sload (1586:1586:1586) (1673:1673:1673)) + (PORT ena (2107:2107:2107) (2026:2026:2026)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (899:899:899) (913:913:913)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (786:786:786) (739:739:739)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1495:1495:1495) (1364:1364:1364)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (961:961:961)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (819:819:819) (766:766:766)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (914:914:914) (873:873:873)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2071:2071:2071)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1222:1222:1222) (1170:1170:1170)) + (PORT clrn (1665:1665:1665) (1616:1616:1616)) + (PORT sload (1586:1586:1586) (1673:1673:1673)) + (PORT ena (2107:2107:2107) (2026:2026:2026)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (954:954:954)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[17\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (789:789:789) (738:738:738)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1574:1574:1574) (1442:1442:1442)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (948:948:948) (938:938:938)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[18\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (832:832:832) (779:779:779)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1223:1223:1223) (1151:1151:1151)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (950:950:950) (954:954:954)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[19\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (862:862:862) (801:801:801)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1523:1523:1523) (1389:1389:1389)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1635:1635:1635)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1352:1352:1352) (1291:1291:1291)) + (PORT clrn (1665:1665:1665) (1616:1616:1616)) + (PORT sload (1586:1586:1586) (1673:1673:1673)) + (PORT ena (2047:2047:2047) (1958:1958:1958)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~20) + (DELAY + (ABSOLUTE + (PORT datac (528:528:528) (560:560:560)) + (PORT datad (1405:1405:1405) (1462:1462:1462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult1\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT dataa[6] (568:568:568) (585:585:585)) + (PORT dataa[7] (589:589:589) (601:601:601)) + (PORT dataa[8] (818:818:818) (790:790:790)) + (PORT dataa[9] (594:594:594) (609:609:609)) + (PORT dataa[10] (859:859:859) (834:834:834)) + (PORT dataa[11] (586:586:586) (596:596:596)) + (PORT dataa[12] (561:561:561) (575:575:575)) + (PORT dataa[13] (832:832:832) (788:788:788)) + (PORT dataa[14] (571:571:571) (595:595:595)) + (PORT dataa[15] (561:561:561) (580:580:580)) + (PORT dataa[16] (835:835:835) (789:789:789)) + (PORT dataa[17] (582:582:582) (597:597:597)) + (PORT datab[10] (3710:3710:3710) (3872:3872:3872)) + (PORT datab[11] (4046:4046:4046) (4225:4225:4225)) + (PORT datab[12] (4136:4136:4136) (4399:4399:4399)) + (PORT datab[13] (4026:4026:4026) (4280:4280:4280)) + (PORT datab[14] (4065:4065:4065) (4204:4204:4204)) + (PORT datab[15] (4164:4164:4164) (4354:4354:4354)) + (PORT datab[16] (3738:3738:3738) (3906:3906:3906)) + (PORT datab[17] (3648:3648:3648) (3856:3856:3856)) + (IOPATH dataa dataout (3928:3928:3928) (3928:3928:3928)) + (IOPATH datab dataout (3863:3863:3863) (3863:3863:3863)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult1\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (139:139:139) (148:148:148)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1526:1526:1526) (1428:1428:1428)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1624:1624:1624) (1512:1512:1512)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1598:1598:1598) (1487:1487:1487)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1615:1615:1615) (1501:1501:1501)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1565:1565:1565) (1466:1466:1466)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1554:1554:1554) (1451:1451:1451)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1550:1550:1550) (1461:1461:1461)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1565:1565:1565) (1454:1454:1454)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1628:1628:1628) (1519:1519:1519)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1658:1658:1658) (1540:1540:1540)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1539:1539:1539) (1407:1407:1407)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (913:913:913) (872:872:872)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1177:1177:1177) (1105:1105:1105)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (911:911:911) (870:870:870)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1185:1185:1185) (1112:1112:1112)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (912:912:912) (871:871:871)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (914:914:914) (873:873:873)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1180:1180:1180) (1107:1107:1107)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1219:1219:1219) (1148:1148:1148)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (911:911:911) (870:870:870)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1649:1649:1649)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (731:731:731) (748:748:748)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2301:2301:2301) (2183:2183:2183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_data_reg") + (INSTANCE Mult0\|auto_generated\|mac_mult1.dataa_reg) + (DELAY + (ABSOLUTE + (PORT data[0] (257:257:257) (271:271:271)) + (PORT data[1] (257:257:257) (271:271:271)) + (PORT data[2] (257:257:257) (271:271:271)) + (PORT data[3] (257:257:257) (271:271:271)) + (PORT data[4] (705:705:705) (692:692:692)) + (PORT data[5] (971:971:971) (913:913:913)) + (PORT data[6] (708:708:708) (697:697:697)) + (PORT data[7] (1039:1039:1039) (980:980:980)) + (PORT data[8] (699:699:699) (683:683:683)) + (PORT data[9] (741:741:741) (732:732:732)) + (PORT data[10] (974:974:974) (915:915:915)) + (PORT data[11] (697:697:697) (677:677:677)) + (PORT data[12] (738:738:738) (724:724:724)) + (PORT data[13] (698:698:698) (679:679:679)) + (PORT data[14] (698:698:698) (679:679:679)) + (PORT data[15] (738:738:738) (725:725:725)) + (PORT data[16] (976:976:976) (907:907:907)) + (PORT data[17] (704:704:704) (687:687:687)) + (PORT clk (1486:1486:1486) (1570:1570:1570)) + (PORT ena (2359:2359:2359) (2248:2248:2248)) + (PORT aclr (1662:1662:1662) (1680:1680:1680)) + (IOPATH (posedge aclr) dataout (275:275:275) (275:275:275)) + (IOPATH (posedge clk) dataout (355:355:355) (355:355:355)) + ) + ) + (TIMINGCHECK + (SETUP data (posedge clk) (228:228:228)) + (SETUP ena (posedge clk) (228:228:228)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult0\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT datab[10] (3773:3773:3773) (3943:3943:3943)) + (PORT datab[11] (4190:4190:4190) (4424:4424:4424)) + (PORT datab[12] (3728:3728:3728) (3987:3987:3987)) + (PORT datab[13] (3722:3722:3722) (3910:3910:3910)) + (PORT datab[14] (3519:3519:3519) (3730:3730:3730)) + (PORT datab[15] (3754:3754:3754) (3989:3989:3989)) + (PORT datab[16] (4007:4007:4007) (4201:4201:4201)) + (PORT datab[17] (3662:3662:3662) (3903:3903:3903)) + (IOPATH dataa dataout (3655:3655:3655) (3655:3655:3655)) + (IOPATH datab dataout (3863:3863:3863) (3863:3863:3863)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult0\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (139:139:139) (148:148:148)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1617:1617:1617) (1508:1508:1508)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1633:1633:1633) (1513:1513:1513)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1617:1617:1617) (1512:1512:1512)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1671:1671:1671) (1554:1554:1554)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1626:1626:1626) (1507:1507:1507)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1585:1585:1585) (1487:1487:1487)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1572:1572:1572) (1473:1473:1473)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1889:1889:1889) (1715:1715:1715)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1645:1645:1645) (1523:1523:1523)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1555:1555:1555) (1454:1454:1454)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1569:1569:1569) (1468:1468:1468)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1807:1807:1807) (1649:1649:1649)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1223:1223:1223) (1172:1172:1172)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1260:1260:1260) (1195:1195:1195)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1540:1540:1540) (1447:1447:1447)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1278:1278:1278) (1215:1215:1215)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1596:1596:1596) (1474:1474:1474)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1274:1274:1274) (1211:1211:1211)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1916:1916:1916) (1796:1796:1796)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1550:1550:1550) (1456:1456:1456)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1610:1610:1610) (1493:1493:1493)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (940:940:940)) + (PORT datab (887:887:887) (874:874:874)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (947:947:947)) + (PORT datab (975:975:975) (955:955:955)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~4) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (940:940:940)) + (PORT datab (566:566:566) (596:596:596)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1328:1328:1328) (1270:1270:1270)) + (PORT datab (623:623:623) (631:631:631)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~8) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (607:607:607)) + (PORT datab (980:980:980) (966:966:966)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~10) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (881:881:881)) + (PORT datab (980:980:980) (966:966:966)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~12) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (882:882:882)) + (PORT datab (1350:1350:1350) (1283:1283:1283)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1241:1241:1241) (1208:1208:1208)) + (PORT datab (906:906:906) (889:889:889)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1244:1244:1244)) + (PORT datab (568:568:568) (598:598:598)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~27) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (647:647:647)) + (PORT datab (1299:1299:1299) (1222:1222:1222)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1529:1529:1529) (1452:1452:1452)) + (PORT datab (627:627:627) (631:631:631)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~33) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (612:612:612)) + (PORT datab (935:935:935) (939:939:939)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~36) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (642:642:642)) + (PORT datab (980:980:980) (962:962:962)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~39) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (614:614:614)) + (PORT datab (986:986:986) (969:969:969)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1612:1612:1612) (1593:1593:1593)) + (PORT datab (626:626:626) (630:630:630)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~45) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (957:957:957)) + (PORT datab (1246:1246:1246) (1209:1209:1209)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~48) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (951:951:951)) + (PORT datab (1346:1346:1346) (1309:1309:1309)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1251:1251:1251)) + (PORT datab (626:626:626) (629:629:629)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1347:1347:1347) (1297:1297:1297)) + (PORT datab (571:571:571) (602:602:602)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1306:1306:1306)) + (PORT datab (970:970:970) (932:932:932)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~60) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (609:609:609)) + (PORT datad (1225:1225:1225) (1155:1155:1155)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~62) + (DELAY + (ABSOLUTE + (PORT datac (635:635:635) (702:702:702)) + (PORT datad (879:879:879) (838:838:838)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~19) + (DELAY + (ABSOLUTE + (PORT datac (634:634:634) (701:701:701)) + (PORT datad (1370:1370:1370) (1346:1346:1346)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~18) + (DELAY + (ABSOLUTE + (PORT datac (633:633:633) (700:700:700)) + (PORT datad (1259:1259:1259) (1236:1236:1236)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~17) + (DELAY + (ABSOLUTE + (PORT datac (513:513:513) (549:549:549)) + (PORT datad (1395:1395:1395) (1451:1451:1451)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~16) + (DELAY + (ABSOLUTE + (PORT datac (578:578:578) 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dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (594:594:594)) + (PORT datab (819:819:819) (759:759:759)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (624:624:624)) + (PORT datab (277:277:277) (302:302:302)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (466:466:466)) + (PORT datab (567:567:567) (577:577:577)) + (IOPATH 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) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[2\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1672:1672:1672)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1702:1702:1702) (1649:1649:1649)) + (PORT ena (2393:2393:2393) (2302:2302:2302)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~29) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datab (1371:1371:1371) (1357:1357:1357)) + (PORT datac (572:572:572) (570:570:570)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) 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(PORT datab (419:419:419) (517:517:517)) + (PORT datac (575:575:575) (576:576:576)) + (PORT datad (323:323:323) (393:393:393)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[4\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (621:621:621)) + (PORT datab (535:535:535) (500:500:500)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[4\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1669:1669:1669)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2812:2812:2812) (2691:2691:2691)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~35) + (DELAY + (ABSOLUTE + (PORT datab (769:769:769) (828:828:828)) + (PORT datac (870:870:870) (862:862:862)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[5\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (465:465:465)) + (PORT datab (278:278:278) (303:303:303)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[5\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1669:1669:1669)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2812:2812:2812) (2691:2691:2691)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~38) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (517:517:517)) + (PORT datac (322:322:322) (400:400:400)) + (PORT datad (568:568:568) (567:567:567)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[6\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1289:1289:1289)) + (PORT datab (619:619:619) (605:605:605)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[6\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~41) + (DELAY + (ABSOLUTE + (PORT datab (769:769:769) (828:828:828)) + (PORT datac (591:591:591) (642:642:642)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[7\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (472:472:472) (452:452:452)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[7\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~44) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (439:439:439)) + (PORT datac (573:573:573) (573:573:573)) + (PORT datad (379:379:379) (474:474:474)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[8\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (504:504:504)) + (PORT datab (964:964:964) (908:908:908)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[8\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~47) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (729:729:729)) + (PORT datab (769:769:769) (828:828:828)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[9\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1272:1272:1272) (1278:1278:1278)) + (PORT datab (276:276:276) (301:301:301)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[9\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~50) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (517:517:517)) + (PORT datac (571:571:571) (572:572:572)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[10\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (1275:1275:1275) (1276:1276:1276)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[10\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~53) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (PORT datac (570:570:570) (569:569:569)) + (PORT datad (379:379:379) (474:474:474)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[11\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (507:507:507)) + (PORT datab (565:565:565) (572:572:572)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[11\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~56) + (DELAY + (ABSOLUTE + (PORT datab (769:769:769) (828:828:828)) + (PORT datac (602:602:602) (652:652:652)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[12\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (498:498:498)) + (PORT datab (619:619:619) (603:603:603)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[12\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~59) + (DELAY + (ABSOLUTE + (PORT datab (622:622:622) (683:683:683)) + (PORT datac (933:933:933) (929:929:929)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[13\]\~54) + (DELAY + (ABSOLUTE + (PORT datab (1338:1338:1338) (1249:1249:1249)) + (PORT datad (468:468:468) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[13\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~0) + (DELAY + (ABSOLUTE + (PORT datac (1304:1304:1304) (1339:1339:1339)) + (PORT datad (564:564:564) (582:582:582)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[0\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2134:2134:2134) (2162:2162:2162)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1702:1702:1702) (1649:1649:1649)) + (PORT ena (2828:2828:2828) (2685:2685:2685)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) +) diff --git a/pid/simulation/modelsim/pid_min_1200mv_0c_fast.vo b/pid/simulation/modelsim/pid_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..2c160c5 --- /dev/null +++ b/pid/simulation/modelsim/pid_min_1200mv_0c_fast.vo @@ -0,0 +1,8790 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" + +// DATE "12/04/2018 14:36:39" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module pid ( + clk, + rst_n, + Sample, + SetPoint, + Kp, + Ki, + Kd, + Vout); +input clk; +input rst_n; +input [13:0] Sample; +input [13:0] SetPoint; +input [7:0] Kp; +input [7:0] Ki; +input [7:0] Kd; +output [13:0] Vout; + +// Design Ports Information +// Vout[0] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// Vout[1] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[2] => Location: PIN_N8, I/O Standard: 2.5 V, Current Strength: Default +// Vout[3] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default +// Vout[4] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[5] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[6] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default +// Vout[7] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// Vout[8] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// Vout[9] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default +// Vout[10] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// Vout[11] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// Vout[12] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +// Vout[13] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[13] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default +// Sample[13] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default +// Sample[12] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[12] => Location: PIN_F10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[11] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[11] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default +// Sample[10] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[10] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[9] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[9] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default +// Sample[8] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[8] => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// Sample[7] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[7] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default +// Sample[6] => Location: PIN_F14, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[6] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default +// Sample[5] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[5] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[4] => Location: PIN_G11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[4] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default +// Sample[3] => Location: PIN_F11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[3] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default +// Sample[2] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[2] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default +// Sample[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[1] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default +// Sample[0] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// SetPoint[0] => Location: PIN_R12, I/O Standard: 2.5 V, Current Strength: Default +// Kd[0] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[1] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default +// Kd[2] => Location: PIN_J14, I/O Standard: 2.5 V, Current Strength: Default +// Kd[3] => Location: PIN_N9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[4] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default +// Kd[5] => Location: PIN_K9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[6] => Location: PIN_L9, I/O Standard: 2.5 V, Current Strength: Default +// Kd[7] => Location: PIN_R9, I/O Standard: 2.5 V, Current Strength: Default +// Ki[0] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default +// Ki[1] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// Ki[2] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// Ki[3] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default +// Ki[4] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// Ki[5] => Location: PIN_J12, I/O Standard: 2.5 V, Current Strength: Default +// Ki[6] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default +// Ki[7] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[0] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// Kp[1] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default +// Kp[2] => Location: PIN_M9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[3] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default +// Kp[4] => Location: PIN_D9, I/O Standard: 2.5 V, Current Strength: Default +// Kp[5] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// Kp[6] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// Kp[7] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("pid_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \Mult2|auto_generated|mac_out2~0 ; +wire \Mult2|auto_generated|mac_out2~1 ; +wire \Mult2|auto_generated|mac_out2~2 ; +wire \Mult2|auto_generated|mac_out2~3 ; +wire \Mult2|auto_generated|mac_out2~4 ; +wire \Mult2|auto_generated|mac_out2~5 ; +wire \Mult2|auto_generated|mac_out2~6 ; +wire \Mult2|auto_generated|mac_out2~7 ; +wire \Mult2|auto_generated|mac_out2~8 ; +wire \Mult2|auto_generated|mac_out2~9 ; +wire \Mult2|auto_generated|mac_out2~10 ; +wire \Mult2|auto_generated|mac_out2~11 ; +wire \Mult2|auto_generated|mac_out2~12 ; +wire \Mult2|auto_generated|mac_out2~13 ; +wire \Mult2|auto_generated|mac_out2~14 ; +wire \Mult2|auto_generated|mac_out2~15 ; +wire \Mult1|auto_generated|mac_out2~0 ; +wire \Mult1|auto_generated|mac_out2~1 ; +wire \Mult1|auto_generated|mac_out2~2 ; +wire \Mult1|auto_generated|mac_out2~3 ; +wire \Mult1|auto_generated|mac_out2~4 ; +wire \Mult1|auto_generated|mac_out2~5 ; +wire \Mult1|auto_generated|mac_out2~6 ; +wire \Mult1|auto_generated|mac_out2~7 ; +wire \Mult1|auto_generated|mac_out2~8 ; +wire \Mult1|auto_generated|mac_out2~9 ; +wire \Mult1|auto_generated|mac_out2~10 ; +wire \Mult1|auto_generated|mac_out2~11 ; +wire \Mult1|auto_generated|mac_out2~12 ; +wire \Mult1|auto_generated|mac_out2~13 ; +wire \Mult1|auto_generated|mac_out2~14 ; +wire \Mult1|auto_generated|mac_out2~15 ; +wire \Mult0|auto_generated|mac_out2~DATAOUT21 ; +wire \Mult0|auto_generated|mac_out2~0 ; +wire \Mult0|auto_generated|mac_out2~1 ; +wire \Mult0|auto_generated|mac_out2~2 ; +wire \Mult0|auto_generated|mac_out2~3 ; +wire \Mult0|auto_generated|mac_out2~4 ; +wire \Mult0|auto_generated|mac_out2~5 ; +wire \Mult0|auto_generated|mac_out2~6 ; +wire \Mult0|auto_generated|mac_out2~7 ; +wire \Mult0|auto_generated|mac_out2~8 ; +wire \Mult0|auto_generated|mac_out2~9 ; +wire \Mult0|auto_generated|mac_out2~10 ; +wire \Mult0|auto_generated|mac_out2~11 ; +wire \Mult0|auto_generated|mac_out2~12 ; +wire \Mult0|auto_generated|mac_out2~13 ; +wire \Vout[0]~output_o ; +wire \Vout[1]~output_o ; +wire \Vout[2]~output_o ; +wire \Vout[3]~output_o ; +wire \Vout[4]~output_o ; +wire \Vout[5]~output_o ; +wire \Vout[6]~output_o ; +wire \Vout[7]~output_o ; +wire \Vout[8]~output_o ; +wire \Vout[9]~output_o ; +wire \Vout[10]~output_o ; +wire \Vout[11]~output_o ; +wire \Vout[12]~output_o ; +wire \Vout[13]~output_o ; +wire \clk~input_o ; +wire \clk~inputclkctrl_outclk ; +wire \Kd_Out[0]~21_combout ; +wire \EE2[0]~14_combout ; +wire \EE1[0]~14_combout ; +wire \SetPoint[0]~input_o ; +wire \Sample[13]~input_o ; +wire \Add1~1_combout ; +wire \SetPoint[13]~input_o ; +wire \Add1~0_combout ; +wire \Sample[12]~input_o ; +wire \Add1~2_combout ; +wire \SetPoint[12]~input_o ; +wire \Sample[11]~input_o ; +wire \Add1~4_combout ; +wire \SetPoint[11]~input_o ; +wire \SetPoint[10]~input_o ; +wire \Sample[10]~input_o ; +wire \Add1~6_combout ; +wire \Sample[9]~input_o ; +wire \Add1~8_combout ; +wire \SetPoint[9]~input_o ; +wire \SetPoint[8]~input_o ; +wire \Sample[8]~input_o ; +wire \Add1~10_combout ; +wire \Sample[7]~input_o ; +wire \Add1~12_combout ; +wire \SetPoint[7]~input_o ; +wire \SetPoint[6]~input_o ; +wire \Sample[6]~input_o ; +wire \Add1~14_combout ; +wire \Sample[5]~input_o ; +wire \Add1~16_combout ; +wire \SetPoint[4]~input_o ; +wire \Sample[4]~input_o ; +wire \Add1~18_combout ; +wire \Sample[3]~input_o ; +wire \Add1~20_combout ; +wire \SetPoint[2]~input_o ; +wire \Sample[2]~input_o ; +wire \Add1~22_combout ; +wire \Sample[1]~input_o ; +wire \Add1~24_combout ; +wire \SetPoint[1]~input_o ; +wire \Sample[0]~input_o ; +wire \Add1~26_combout ; +wire \EE0[0]~15_cout ; +wire \EE0[0]~17 ; +wire \EE0[1]~18_combout ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \Add0~0_combout ; +wire \period~3_combout ; +wire \Add0~1 ; +wire \Add0~2_combout ; +wire \Add0~3 ; +wire \Add0~4_combout ; +wire \Equal0~2_combout ; +wire \Add0~5 ; +wire \Add0~6_combout ; +wire \period~2_combout ; +wire \Add0~7 ; +wire \Add0~8_combout ; +wire \Add0~9 ; +wire \Add0~10_combout ; +wire \Add0~11 ; +wire \Add0~13 ; +wire \Add0~14_combout ; +wire \period~0_combout ; +wire \Add0~15 ; +wire \Add0~16_combout ; +wire \Add0~17 ; +wire \Add0~18_combout ; +wire \Add0~19 ; +wire \Add0~20_combout ; +wire \Equal0~0_combout ; +wire \Add0~12_combout ; +wire \period~1_combout ; +wire \Equal0~1_combout ; +wire \Equal0~3_combout ; +wire \Clk_Ctrl~q ; +wire \EE0[1]~_Duplicate_1_q ; +wire \Add1~25_combout ; +wire \EE0[1]~19 ; +wire \EE0[2]~20_combout ; +wire \EE0[2]~_Duplicate_1_q ; +wire \Add1~23_combout ; +wire \EE0[2]~21 ; +wire \EE0[3]~22_combout ; +wire \EE0[3]~_Duplicate_1_q ; +wire \SetPoint[3]~input_o ; +wire \Add1~21_combout ; +wire \EE0[3]~23 ; +wire \EE0[4]~24_combout ; +wire \EE0[4]~_Duplicate_1_q ; +wire \Add1~19_combout ; +wire \EE0[4]~25 ; +wire \EE0[5]~26_combout ; +wire \EE0[5]~_Duplicate_1_q ; +wire \SetPoint[5]~input_o ; +wire \Add1~17_combout ; +wire \EE0[5]~27 ; +wire \EE0[6]~28_combout ; +wire \EE0[6]~_Duplicate_1_q ; +wire \Add1~15_combout ; +wire \EE0[6]~29 ; +wire \EE0[7]~30_combout ; +wire \EE0[7]~_Duplicate_1_q ; +wire \Add1~13_combout ; +wire \EE0[7]~31 ; +wire \EE0[8]~32_combout ; +wire \EE0[8]~_Duplicate_1_q ; +wire \Add1~11_combout ; +wire \EE0[8]~33 ; +wire \EE0[9]~34_combout ; +wire \EE0[9]~_Duplicate_1_q ; +wire \Add1~9_combout ; +wire \EE0[9]~35 ; +wire \EE0[10]~36_combout ; +wire \EE0[10]~_Duplicate_1_q ; +wire \Add1~7_combout ; +wire \EE0[10]~37 ; +wire \EE0[11]~38_combout ; +wire \EE0[11]~_Duplicate_1_q ; +wire \Add1~5_combout ; +wire \EE0[11]~39 ; +wire \EE0[12]~40_combout ; +wire \EE0[12]~_Duplicate_1_q ; +wire \Add1~3_combout ; +wire \EE0[12]~41 ; +wire \EE0[13]~42_combout ; +wire \EE0[13]~_Duplicate_1_q ; +wire \Add1~27_combout ; +wire \EE0[0]~16_combout ; +wire \EE0[0]~_Duplicate_1_q ; +wire \EE1[0]~15 ; +wire \EE1[1]~16_combout ; +wire \EE1[1]~17 ; +wire \EE1[2]~18_combout ; +wire \EE1[2]~19 ; +wire \EE1[3]~20_combout ; +wire \EE1[3]~21 ; +wire \EE1[4]~22_combout ; +wire \EE1[4]~23 ; +wire \EE1[5]~24_combout ; +wire \EE1[5]~25 ; +wire \EE1[6]~26_combout ; +wire \EE1[6]~27 ; +wire \EE1[7]~28_combout ; +wire \EE1[7]~29 ; +wire \EE1[8]~30_combout ; +wire \EE1[8]~31 ; +wire \EE1[9]~32_combout ; +wire \EE1[9]~33 ; +wire \EE1[10]~34_combout ; +wire \EE1[10]~35 ; +wire \EE1[11]~36_combout ; +wire \EE1[11]~37 ; +wire \EE1[12]~38_combout ; +wire \EE1[12]~39 ; +wire \EE1[13]~40_combout ; +wire \EE2[0]~15 ; +wire \EE2[1]~16_combout ; +wire \EE2[1]~17 ; +wire \EE2[2]~18_combout ; +wire \EE2[2]~19 ; +wire \EE2[3]~20_combout ; +wire \EE2[3]~21 ; +wire \EE2[4]~22_combout ; +wire \EE2[4]~23 ; +wire \EE2[5]~24_combout ; +wire \EE2[5]~25 ; +wire \EE2[6]~26_combout ; +wire \EE2[6]~27 ; +wire \EE2[7]~28_combout ; +wire \EE2[7]~29 ; +wire \EE2[8]~30_combout ; +wire \EE2[8]~31 ; +wire \EE2[9]~32_combout ; +wire \EE2[9]~33 ; +wire \EE2[10]~34_combout ; +wire \EE2[10]~35 ; +wire \EE2[11]~36_combout ; +wire \EE2[11]~37 ; +wire \EE2[12]~38_combout ; +wire \EE2[12]~39 ; +wire \EE2[13]~40_combout ; +wire \Kd[0]~input_o ; +wire \Kd[1]~input_o ; +wire \Kd[2]~input_o ; +wire \Kd[3]~input_o ; +wire \Kd[4]~input_o ; +wire \Kd[5]~input_o ; +wire \Kd[6]~input_o ; +wire \Kd[7]~input_o ; +wire \Mult2|auto_generated|mac_mult1~dataout ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult2|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult2|auto_generated|mac_mult1~0 ; +wire \Mult2|auto_generated|mac_mult1~1 ; +wire \Mult2|auto_generated|mac_mult1~2 ; +wire \Mult2|auto_generated|mac_mult1~3 ; +wire \Mult2|auto_generated|mac_mult1~4 ; +wire \Mult2|auto_generated|mac_mult1~5 ; +wire \Mult2|auto_generated|mac_mult1~6 ; +wire \Mult2|auto_generated|mac_mult1~7 ; +wire \Mult2|auto_generated|mac_mult1~8 ; +wire \Mult2|auto_generated|mac_mult1~9 ; +wire \Mult2|auto_generated|mac_mult1~10 ; +wire \Mult2|auto_generated|mac_mult1~11 ; +wire \Mult2|auto_generated|mac_mult1~12 ; +wire \Mult2|auto_generated|mac_mult1~13 ; +wire \Mult2|auto_generated|mac_mult1~14 ; +wire \Mult2|auto_generated|mac_mult1~15 ; +wire \Mult2|auto_generated|mac_out2~dataout ; +wire \Kd_Out[0]~22 ; +wire \Kd_Out[1]~23_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT1 ; +wire \Kd_Out[1]~24 ; +wire \Kd_Out[2]~25_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT2 ; +wire \Kd_Out[2]~26 ; +wire \Kd_Out[3]~27_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT3 ; +wire \Kd_Out[3]~28 ; +wire \Kd_Out[4]~29_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT4 ; +wire \Kd_Out[4]~30 ; +wire \Kd_Out[5]~31_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT5 ; +wire \Kd_Out[5]~32 ; +wire \Kd_Out[6]~33_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT6 ; +wire \Kd_Out[6]~34 ; +wire \Kd_Out[7]~35_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT7 ; +wire \Kd_Out[7]~36 ; +wire \Kd_Out[8]~37_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT8 ; +wire \Kd_Out[8]~38 ; +wire \Kd_Out[9]~39_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT9 ; +wire \Kd_Out[9]~40 ; +wire \Kd_Out[10]~41_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT10 ; +wire \Kd_Out[10]~42 ; +wire \Kd_Out[11]~43_combout ; +wire \Kd_Out[11]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT11 ; +wire \Kd_Out[11]~44 ; +wire \Kd_Out[12]~45_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT12 ; +wire \Kd_Out[12]~46 ; +wire \Kd_Out[13]~47_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT13 ; +wire \Kd_Out[13]~48 ; +wire \Kd_Out[14]~49_combout ; +wire \Kd_Out[14]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT14 ; +wire \Kd_Out[14]~50 ; +wire \Kd_Out[15]~51_combout ; +wire \Kd_Out[15]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT15 ; +wire \Kd_Out[15]~52 ; +wire \Kd_Out[16]~53_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT16 ; +wire \Kd_Out[16]~54 ; +wire \Kd_Out[17]~55_combout ; +wire \Kd_Out[17]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT17 ; +wire \Kd_Out[17]~56 ; +wire \Kd_Out[18]~57_combout ; +wire \Kd_Out[18]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT18 ; +wire \Kd_Out[18]~58 ; +wire \Kd_Out[19]~59_combout ; +wire \Kd_Out[19]~feeder_combout ; +wire \Mult2|auto_generated|mac_out2~DATAOUT19 ; +wire \Kd_Out[19]~60 ; +wire \Kd_Out[20]~61_combout ; +wire \~GND~combout ; +wire \Add7~20_combout ; +wire \Ki_Out[0]~21_combout ; +wire \Ki[0]~input_o ; +wire \Ki[1]~input_o ; +wire \Ki[2]~input_o ; +wire \Ki[3]~input_o ; +wire \Ki[4]~input_o ; +wire \Ki[5]~input_o ; +wire \Ki[6]~input_o ; +wire \Ki[7]~input_o ; +wire \Mult1|auto_generated|mac_mult1~dataout ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult1|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult1|auto_generated|mac_mult1~0 ; +wire \Mult1|auto_generated|mac_mult1~1 ; +wire \Mult1|auto_generated|mac_mult1~2 ; +wire \Mult1|auto_generated|mac_mult1~3 ; +wire \Mult1|auto_generated|mac_mult1~4 ; +wire \Mult1|auto_generated|mac_mult1~5 ; +wire \Mult1|auto_generated|mac_mult1~6 ; +wire \Mult1|auto_generated|mac_mult1~7 ; +wire \Mult1|auto_generated|mac_mult1~8 ; +wire \Mult1|auto_generated|mac_mult1~9 ; +wire \Mult1|auto_generated|mac_mult1~10 ; +wire \Mult1|auto_generated|mac_mult1~11 ; +wire \Mult1|auto_generated|mac_mult1~12 ; +wire \Mult1|auto_generated|mac_mult1~13 ; +wire \Mult1|auto_generated|mac_mult1~14 ; +wire \Mult1|auto_generated|mac_mult1~15 ; +wire \Mult1|auto_generated|mac_out2~dataout ; +wire \Ki_Out[0]~22 ; +wire \Ki_Out[1]~23_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT1 ; +wire \Ki_Out[1]~24 ; +wire \Ki_Out[2]~25_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT2 ; +wire \Ki_Out[2]~26 ; +wire \Ki_Out[3]~27_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT3 ; +wire \Ki_Out[3]~28 ; +wire \Ki_Out[4]~29_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT4 ; +wire \Ki_Out[4]~30 ; +wire \Ki_Out[5]~31_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT5 ; +wire \Ki_Out[5]~32 ; +wire \Ki_Out[6]~33_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT6 ; +wire \Ki_Out[6]~34 ; +wire \Ki_Out[7]~35_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT7 ; +wire \Ki_Out[7]~36 ; +wire \Ki_Out[8]~37_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT8 ; +wire \Ki_Out[8]~38 ; +wire \Ki_Out[9]~39_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT9 ; +wire \Ki_Out[9]~40 ; +wire \Ki_Out[10]~41_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT10 ; +wire \Ki_Out[10]~42 ; +wire \Ki_Out[11]~43_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT11 ; +wire \Ki_Out[11]~44 ; +wire \Ki_Out[12]~45_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT12 ; +wire \Ki_Out[12]~46 ; +wire \Ki_Out[13]~47_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT13 ; +wire \Ki_Out[13]~48 ; +wire \Ki_Out[14]~49_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT14 ; +wire \Ki_Out[14]~50 ; +wire \Ki_Out[15]~51_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT15 ; +wire \Ki_Out[15]~52 ; +wire \Ki_Out[16]~53_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT16 ; +wire \Ki_Out[16]~54 ; +wire \Ki_Out[17]~55_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT17 ; +wire \Ki_Out[17]~56 ; +wire \Ki_Out[18]~57_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT18 ; +wire \Ki_Out[18]~58 ; +wire \Ki_Out[19]~59_combout ; +wire \Mult1|auto_generated|mac_out2~DATAOUT19 ; +wire \Ki_Out[19]~60 ; +wire \Ki_Out[20]~61_combout ; +wire \Kp_Out[0]~21_combout ; +wire \Kp[0]~input_o ; +wire \Kp[1]~input_o ; +wire \Kp[2]~input_o ; +wire \Kp[3]~input_o ; +wire \Kp[4]~input_o ; +wire \Kp[5]~input_o ; +wire \Kp[6]~input_o ; +wire \Kp[7]~input_o ; +wire \Mult0|auto_generated|mac_mult1~dataout ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT1 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT2 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT3 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT4 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT5 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT6 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT7 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT8 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT9 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT10 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT11 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT12 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT13 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT14 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT15 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT16 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT17 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT18 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT19 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT20 ; +wire \Mult0|auto_generated|mac_mult1~DATAOUT21 ; +wire \Mult0|auto_generated|mac_mult1~0 ; +wire \Mult0|auto_generated|mac_mult1~1 ; +wire \Mult0|auto_generated|mac_mult1~2 ; +wire \Mult0|auto_generated|mac_mult1~3 ; +wire \Mult0|auto_generated|mac_mult1~4 ; +wire \Mult0|auto_generated|mac_mult1~5 ; +wire \Mult0|auto_generated|mac_mult1~6 ; +wire \Mult0|auto_generated|mac_mult1~7 ; +wire \Mult0|auto_generated|mac_mult1~8 ; +wire \Mult0|auto_generated|mac_mult1~9 ; +wire \Mult0|auto_generated|mac_mult1~10 ; +wire \Mult0|auto_generated|mac_mult1~11 ; +wire \Mult0|auto_generated|mac_mult1~12 ; +wire \Mult0|auto_generated|mac_mult1~13 ; +wire \Mult0|auto_generated|mac_out2~dataout ; +wire \Kp_Out[0]~22 ; +wire \Kp_Out[1]~23_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT1 ; +wire \Kp_Out[1]~24 ; +wire \Kp_Out[2]~25_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT2 ; +wire \Kp_Out[2]~26 ; +wire \Kp_Out[3]~27_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT3 ; +wire \Kp_Out[3]~28 ; +wire \Kp_Out[4]~29_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT4 ; +wire \Kp_Out[4]~30 ; +wire \Kp_Out[5]~31_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT5 ; +wire \Kp_Out[5]~32 ; +wire \Kp_Out[6]~33_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT6 ; +wire \Kp_Out[6]~34 ; +wire \Kp_Out[7]~35_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT7 ; +wire \Kp_Out[7]~36 ; +wire \Kp_Out[8]~37_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT8 ; +wire \Kp_Out[8]~38 ; +wire \Kp_Out[9]~39_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT9 ; +wire \Kp_Out[9]~40 ; +wire \Kp_Out[10]~41_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT10 ; +wire \Kp_Out[10]~42 ; +wire \Kp_Out[11]~43_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT11 ; +wire \Kp_Out[11]~44 ; +wire \Kp_Out[12]~45_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT12 ; +wire \Kp_Out[12]~46 ; +wire \Kp_Out[13]~47_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT13 ; +wire \Kp_Out[13]~48 ; +wire \Kp_Out[14]~49_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT14 ; +wire \Kp_Out[14]~50 ; +wire \Kp_Out[15]~51_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT15 ; +wire \Kp_Out[15]~52 ; +wire \Kp_Out[16]~53_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT16 ; +wire \Kp_Out[16]~54 ; +wire \Kp_Out[17]~55_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT17 ; +wire \Kp_Out[17]~56 ; +wire \Kp_Out[18]~57_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT18 ; +wire \Kp_Out[18]~58 ; +wire \Kp_Out[19]~59_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT19 ; +wire \Kp_Out[19]~60 ; +wire \Kp_Out[20]~61_combout ; +wire \Mult0|auto_generated|mac_out2~DATAOUT20 ; +wire \Add5~1 ; +wire \Add5~3 ; +wire \Add5~5 ; +wire \Add5~7 ; +wire \Add5~9 ; +wire \Add5~11 ; +wire \Add5~13 ; +wire \Add5~15 ; +wire \Add5~25 ; +wire \Add5~28 ; +wire \Add5~31 ; +wire \Add5~34 ; +wire \Add5~37 ; +wire \Add5~40 ; +wire \Add5~43 ; +wire \Add5~46 ; +wire \Add5~49 ; +wire \Add5~52 ; +wire \Add5~55 ; +wire \Add5~58 ; +wire \Add5~60_combout ; +wire \Add5~62_combout ; +wire \Add7~19_combout ; +wire \Add7~18_combout ; +wire \Add7~17_combout ; +wire \Add7~16_combout ; +wire \Add5~48_combout ; +wire \Add7~15_combout ; +wire \Add7~14_combout ; +wire \Add7~13_combout ; +wire \Add7~12_combout ; +wire \Add7~11_combout ; +wire \Add5~30_combout ; +wire \Add7~10_combout ; +wire \Add7~9_combout ; +wire \Add7~8_combout ; +wire \Add5~14_combout ; +wire \Add5~16_combout ; +wire \Add7~1_combout ; +wire \Add5~12_combout ; +wire \Add5~17_combout ; +wire \Add7~2_combout ; +wire \Add5~10_combout ; +wire \Add5~18_combout ; +wire \Add7~3_combout ; +wire \Add5~8_combout ; +wire \Add5~19_combout ; +wire \Add5~6_combout ; +wire \Add5~20_combout ; +wire \Add7~4_combout ; +wire \Add7~5_combout ; +wire \Add5~4_combout ; +wire \Add5~21_combout ; +wire \Add7~6_combout ; +wire \Add5~2_combout ; +wire \Add5~22_combout ; +wire \Add5~0_combout ; +wire \Add5~23_combout ; +wire \Add7~7_combout ; +wire \Vout[0]~15_cout ; +wire \Vout[0]~17_cout ; +wire \Vout[0]~19_cout ; +wire \Vout[0]~21_cout ; +wire \Vout[0]~23_cout ; +wire \Vout[0]~25_cout ; +wire \Vout[0]~27_cout ; +wire \Vout[0]~29 ; +wire \Vout[1]~30_combout ; +wire \Vout[1]~reg0_q ; +wire \Add5~24_combout ; +wire \Add5~26_combout ; +wire \Vout[1]~31 ; +wire \Vout[2]~32_combout ; +wire \Vout[2]~reg0_q ; +wire \Add5~27_combout ; +wire \Add5~29_combout ; +wire \Vout[2]~33 ; +wire \Vout[3]~34_combout ; +wire \Vout[3]~reg0_q ; +wire \Add5~32_combout ; +wire \Vout[3]~35 ; +wire \Vout[4]~36_combout ; +wire \Vout[4]~reg0_q ; +wire \Add5~33_combout ; +wire \Add5~35_combout ; +wire \Vout[4]~37 ; +wire \Vout[5]~38_combout ; +wire \Vout[5]~reg0_q ; +wire \Add5~36_combout ; +wire \Add5~38_combout ; +wire \Vout[5]~39 ; +wire \Vout[6]~40_combout ; +wire \Vout[6]~reg0_q ; +wire \Add5~39_combout ; +wire \Add5~41_combout ; +wire \Vout[6]~41 ; +wire \Vout[7]~42_combout ; +wire \Vout[7]~reg0_q ; +wire \Add5~42_combout ; +wire \Add5~44_combout ; +wire \Vout[7]~43 ; +wire \Vout[8]~44_combout ; +wire \Vout[8]~reg0_q ; +wire \Add5~45_combout ; +wire \Add5~47_combout ; +wire \Vout[8]~45 ; +wire \Vout[9]~46_combout ; +wire \Vout[9]~reg0_q ; +wire \Add5~50_combout ; +wire \Vout[9]~47 ; +wire \Vout[10]~48_combout ; +wire \Vout[10]~reg0_q ; +wire \Add5~51_combout ; +wire \Add5~53_combout ; +wire \Vout[10]~49 ; +wire \Vout[11]~50_combout ; +wire \Vout[11]~reg0_q ; +wire \Add5~54_combout ; +wire \Add5~56_combout ; +wire \Vout[11]~51 ; +wire \Vout[12]~52_combout ; +wire \Vout[12]~reg0_q ; +wire \Add5~57_combout ; +wire \Add5~59_combout ; +wire \Vout[12]~53 ; +wire \Vout[13]~54_combout ; +wire \Vout[13]~reg0_q ; +wire \Add7~0_combout ; +wire \Vout[0]~28_combout ; +wire \Vout[0]~reg0_q ; +wire [21:0] Kd_Out; +wire [21:0] Ki_Out; +wire [21:0] Kp_Out; +wire [13:0] EE2; +wire [13:0] EE1; +wire [10:0] period; + +wire [35:0] \Mult2|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult1|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult0|auto_generated|mac_out2_DATAOUT_bus ; +wire [35:0] \Mult2|auto_generated|mac_mult1_DATAOUT_bus ; +wire [35:0] \Mult1|auto_generated|mac_mult1_DATAOUT_bus ; +wire [35:0] \Mult0|auto_generated|mac_mult1_DATAOUT_bus ; + +assign \Mult2|auto_generated|mac_out2~0 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult2|auto_generated|mac_out2~1 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult2|auto_generated|mac_out2~2 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult2|auto_generated|mac_out2~3 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult2|auto_generated|mac_out2~4 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult2|auto_generated|mac_out2~5 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult2|auto_generated|mac_out2~6 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult2|auto_generated|mac_out2~7 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult2|auto_generated|mac_out2~8 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult2|auto_generated|mac_out2~9 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult2|auto_generated|mac_out2~10 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult2|auto_generated|mac_out2~11 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult2|auto_generated|mac_out2~12 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult2|auto_generated|mac_out2~13 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult2|auto_generated|mac_out2~14 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult2|auto_generated|mac_out2~15 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult2|auto_generated|mac_out2~dataout = \Mult2|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult2|auto_generated|mac_out2~DATAOUT1 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult2|auto_generated|mac_out2~DATAOUT2 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult2|auto_generated|mac_out2~DATAOUT3 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult2|auto_generated|mac_out2~DATAOUT4 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult2|auto_generated|mac_out2~DATAOUT5 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult2|auto_generated|mac_out2~DATAOUT6 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult2|auto_generated|mac_out2~DATAOUT7 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult2|auto_generated|mac_out2~DATAOUT8 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult2|auto_generated|mac_out2~DATAOUT9 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult2|auto_generated|mac_out2~DATAOUT10 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult2|auto_generated|mac_out2~DATAOUT11 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult2|auto_generated|mac_out2~DATAOUT12 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult2|auto_generated|mac_out2~DATAOUT13 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult2|auto_generated|mac_out2~DATAOUT14 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult2|auto_generated|mac_out2~DATAOUT15 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult2|auto_generated|mac_out2~DATAOUT16 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult2|auto_generated|mac_out2~DATAOUT17 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult2|auto_generated|mac_out2~DATAOUT18 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult2|auto_generated|mac_out2~DATAOUT19 = \Mult2|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult1|auto_generated|mac_out2~0 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult1|auto_generated|mac_out2~1 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult1|auto_generated|mac_out2~2 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult1|auto_generated|mac_out2~3 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult1|auto_generated|mac_out2~4 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult1|auto_generated|mac_out2~5 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult1|auto_generated|mac_out2~6 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult1|auto_generated|mac_out2~7 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult1|auto_generated|mac_out2~8 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult1|auto_generated|mac_out2~9 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult1|auto_generated|mac_out2~10 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult1|auto_generated|mac_out2~11 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult1|auto_generated|mac_out2~12 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult1|auto_generated|mac_out2~13 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult1|auto_generated|mac_out2~14 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult1|auto_generated|mac_out2~15 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult1|auto_generated|mac_out2~dataout = \Mult1|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult1|auto_generated|mac_out2~DATAOUT1 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult1|auto_generated|mac_out2~DATAOUT2 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult1|auto_generated|mac_out2~DATAOUT3 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult1|auto_generated|mac_out2~DATAOUT4 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult1|auto_generated|mac_out2~DATAOUT5 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult1|auto_generated|mac_out2~DATAOUT6 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult1|auto_generated|mac_out2~DATAOUT7 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult1|auto_generated|mac_out2~DATAOUT8 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult1|auto_generated|mac_out2~DATAOUT9 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult1|auto_generated|mac_out2~DATAOUT10 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult1|auto_generated|mac_out2~DATAOUT11 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult1|auto_generated|mac_out2~DATAOUT12 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult1|auto_generated|mac_out2~DATAOUT13 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult1|auto_generated|mac_out2~DATAOUT14 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult1|auto_generated|mac_out2~DATAOUT15 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult1|auto_generated|mac_out2~DATAOUT16 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult1|auto_generated|mac_out2~DATAOUT17 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult1|auto_generated|mac_out2~DATAOUT18 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult1|auto_generated|mac_out2~DATAOUT19 = \Mult1|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult0|auto_generated|mac_out2~0 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [0]; +assign \Mult0|auto_generated|mac_out2~1 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [1]; +assign \Mult0|auto_generated|mac_out2~2 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [2]; +assign \Mult0|auto_generated|mac_out2~3 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [3]; +assign \Mult0|auto_generated|mac_out2~4 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [4]; +assign \Mult0|auto_generated|mac_out2~5 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [5]; +assign \Mult0|auto_generated|mac_out2~6 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [6]; +assign \Mult0|auto_generated|mac_out2~7 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [7]; +assign \Mult0|auto_generated|mac_out2~8 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [8]; +assign \Mult0|auto_generated|mac_out2~9 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [9]; +assign \Mult0|auto_generated|mac_out2~10 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [10]; +assign \Mult0|auto_generated|mac_out2~11 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [11]; +assign \Mult0|auto_generated|mac_out2~12 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [12]; +assign \Mult0|auto_generated|mac_out2~13 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [13]; +assign \Mult0|auto_generated|mac_out2~dataout = \Mult0|auto_generated|mac_out2_DATAOUT_bus [14]; +assign \Mult0|auto_generated|mac_out2~DATAOUT1 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [15]; +assign \Mult0|auto_generated|mac_out2~DATAOUT2 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [16]; +assign \Mult0|auto_generated|mac_out2~DATAOUT3 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [17]; +assign \Mult0|auto_generated|mac_out2~DATAOUT4 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [18]; +assign \Mult0|auto_generated|mac_out2~DATAOUT5 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [19]; +assign \Mult0|auto_generated|mac_out2~DATAOUT6 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [20]; +assign \Mult0|auto_generated|mac_out2~DATAOUT7 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [21]; +assign \Mult0|auto_generated|mac_out2~DATAOUT8 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [22]; +assign \Mult0|auto_generated|mac_out2~DATAOUT9 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [23]; +assign \Mult0|auto_generated|mac_out2~DATAOUT10 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [24]; +assign \Mult0|auto_generated|mac_out2~DATAOUT11 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [25]; +assign \Mult0|auto_generated|mac_out2~DATAOUT12 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [26]; +assign \Mult0|auto_generated|mac_out2~DATAOUT13 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [27]; +assign \Mult0|auto_generated|mac_out2~DATAOUT14 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [28]; +assign \Mult0|auto_generated|mac_out2~DATAOUT15 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [29]; +assign \Mult0|auto_generated|mac_out2~DATAOUT16 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [30]; +assign \Mult0|auto_generated|mac_out2~DATAOUT17 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [31]; +assign \Mult0|auto_generated|mac_out2~DATAOUT18 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [32]; +assign \Mult0|auto_generated|mac_out2~DATAOUT19 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [33]; +assign \Mult0|auto_generated|mac_out2~DATAOUT20 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [34]; +assign \Mult0|auto_generated|mac_out2~DATAOUT21 = \Mult0|auto_generated|mac_out2_DATAOUT_bus [35]; + +assign \Mult2|auto_generated|mac_mult1~0 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult2|auto_generated|mac_mult1~1 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult2|auto_generated|mac_mult1~2 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult2|auto_generated|mac_mult1~3 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult2|auto_generated|mac_mult1~4 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult2|auto_generated|mac_mult1~5 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult2|auto_generated|mac_mult1~6 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult2|auto_generated|mac_mult1~7 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult2|auto_generated|mac_mult1~8 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult2|auto_generated|mac_mult1~9 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult2|auto_generated|mac_mult1~10 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult2|auto_generated|mac_mult1~11 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult2|auto_generated|mac_mult1~12 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult2|auto_generated|mac_mult1~13 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult2|auto_generated|mac_mult1~14 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult2|auto_generated|mac_mult1~15 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult2|auto_generated|mac_mult1~dataout = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT1 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT2 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT3 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT4 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT5 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT6 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT7 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT8 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT9 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT10 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT11 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT12 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT13 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT14 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT15 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT16 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT17 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT18 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult2|auto_generated|mac_mult1~DATAOUT19 = \Mult2|auto_generated|mac_mult1_DATAOUT_bus [35]; + +assign \Mult1|auto_generated|mac_mult1~0 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult1|auto_generated|mac_mult1~1 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult1|auto_generated|mac_mult1~2 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult1|auto_generated|mac_mult1~3 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult1|auto_generated|mac_mult1~4 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult1|auto_generated|mac_mult1~5 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult1|auto_generated|mac_mult1~6 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult1|auto_generated|mac_mult1~7 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult1|auto_generated|mac_mult1~8 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult1|auto_generated|mac_mult1~9 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult1|auto_generated|mac_mult1~10 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult1|auto_generated|mac_mult1~11 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult1|auto_generated|mac_mult1~12 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult1|auto_generated|mac_mult1~13 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult1|auto_generated|mac_mult1~14 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult1|auto_generated|mac_mult1~15 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult1|auto_generated|mac_mult1~dataout = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT1 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT2 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT3 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT4 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT5 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT6 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT7 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT8 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT9 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT10 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT11 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT12 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT13 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT14 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT15 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT16 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT17 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT18 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult1|auto_generated|mac_mult1~DATAOUT19 = \Mult1|auto_generated|mac_mult1_DATAOUT_bus [35]; + +assign \Mult0|auto_generated|mac_mult1~0 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [0]; +assign \Mult0|auto_generated|mac_mult1~1 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [1]; +assign \Mult0|auto_generated|mac_mult1~2 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [2]; +assign \Mult0|auto_generated|mac_mult1~3 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [3]; +assign \Mult0|auto_generated|mac_mult1~4 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [4]; +assign \Mult0|auto_generated|mac_mult1~5 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [5]; +assign \Mult0|auto_generated|mac_mult1~6 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [6]; +assign \Mult0|auto_generated|mac_mult1~7 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [7]; +assign \Mult0|auto_generated|mac_mult1~8 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [8]; +assign \Mult0|auto_generated|mac_mult1~9 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [9]; +assign \Mult0|auto_generated|mac_mult1~10 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [10]; +assign \Mult0|auto_generated|mac_mult1~11 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [11]; +assign \Mult0|auto_generated|mac_mult1~12 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [12]; +assign \Mult0|auto_generated|mac_mult1~13 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [13]; +assign \Mult0|auto_generated|mac_mult1~dataout = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [14]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT1 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [15]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT2 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [16]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT3 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [17]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT4 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [18]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT5 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [19]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT6 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [20]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT7 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [21]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT8 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [22]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT9 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [23]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT10 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [24]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT11 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [25]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT12 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [26]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT13 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [27]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT14 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [28]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT15 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [29]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT16 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [30]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT17 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [31]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT18 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [32]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT19 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [33]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT20 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [34]; +assign \Mult0|auto_generated|mac_mult1~DATAOUT21 = \Mult0|auto_generated|mac_mult1_DATAOUT_bus [35]; + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: IOOBUF_X7_Y24_N16 +cycloneive_io_obuf \Vout[0]~output ( + .i(\Vout[0]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[0]~output .bus_hold = "false"; +defparam \Vout[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N9 +cycloneive_io_obuf \Vout[1]~output ( + .i(\Vout[1]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[1]~output .bus_hold = "false"; +defparam \Vout[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N23 +cycloneive_io_obuf \Vout[2]~output ( + .i(\Vout[2]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[2]~output .bus_hold = "false"; +defparam \Vout[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N16 +cycloneive_io_obuf \Vout[3]~output ( + .i(\Vout[3]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[3]~output .bus_hold = "false"; +defparam \Vout[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N2 +cycloneive_io_obuf \Vout[4]~output ( + .i(\Vout[4]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[4]~output .bus_hold = "false"; +defparam \Vout[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y24_N2 +cycloneive_io_obuf \Vout[5]~output ( + .i(\Vout[5]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[5]~output .bus_hold = "false"; +defparam \Vout[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N16 +cycloneive_io_obuf \Vout[6]~output ( + .i(\Vout[6]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[6]~output .bus_hold = "false"; +defparam \Vout[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y24_N16 +cycloneive_io_obuf \Vout[7]~output ( + .i(\Vout[7]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[7]~output .bus_hold = "false"; +defparam \Vout[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N2 +cycloneive_io_obuf \Vout[8]~output ( + .i(\Vout[8]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[8]~output .bus_hold = "false"; +defparam \Vout[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y17_N2 +cycloneive_io_obuf \Vout[9]~output ( + .i(\Vout[9]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[9]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[9]~output .bus_hold = "false"; +defparam \Vout[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N23 +cycloneive_io_obuf \Vout[10]~output ( + .i(\Vout[10]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[10]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[10]~output .bus_hold = "false"; +defparam \Vout[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y19_N16 +cycloneive_io_obuf \Vout[11]~output ( + .i(\Vout[11]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[11]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[11]~output .bus_hold = "false"; +defparam \Vout[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y24_N9 +cycloneive_io_obuf \Vout[12]~output ( + .i(\Vout[12]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[12]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[12]~output .bus_hold = "false"; +defparam \Vout[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N9 +cycloneive_io_obuf \Vout[13]~output ( + .i(\Vout[13]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Vout[13]~output_o ), + .obar()); +// synopsys translate_off +defparam \Vout[13]~output .bus_hold = "false"; +defparam \Vout[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk~inputclkctrl .clock_type = "global clock"; +defparam \clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N12 +cycloneive_lcell_comb \Kd_Out[0]~21 ( +// Equation(s): +// \Kd_Out[0]~21_combout = Kd_Out[0] $ (GND) +// \Kd_Out[0]~22 = CARRY(!Kd_Out[0]) + + .dataa(Kd_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Kd_Out[0]~21_combout ), + .cout(\Kd_Out[0]~22 )); +// synopsys translate_off +defparam \Kd_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Kd_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N4 +cycloneive_lcell_comb \EE2[0]~14 ( +// Equation(s): +// \EE2[0]~14_combout = EE2[0] $ (GND) +// \EE2[0]~15 = CARRY(!EE2[0]) + + .dataa(gnd), + .datab(EE2[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\EE2[0]~14_combout ), + .cout(\EE2[0]~15 )); +// synopsys translate_off +defparam \EE2[0]~14 .lut_mask = 16'hCC33; +defparam \EE2[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N2 +cycloneive_lcell_comb \EE1[0]~14 ( +// Equation(s): +// \EE1[0]~14_combout = EE1[0] $ (GND) +// \EE1[0]~15 = CARRY(!EE1[0]) + + .dataa(gnd), + .datab(EE1[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\EE1[0]~14_combout ), + .cout(\EE1[0]~15 )); +// synopsys translate_off +defparam \EE1[0]~14 .lut_mask = 16'hCC33; +defparam \EE1[0]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y0_N1 +cycloneive_io_ibuf \SetPoint[0]~input ( + .i(SetPoint[0]), + .ibar(gnd), + .o(\SetPoint[0]~input_o )); +// synopsys translate_off +defparam \SetPoint[0]~input .bus_hold = "false"; +defparam \SetPoint[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N8 +cycloneive_io_ibuf \Sample[13]~input ( + .i(Sample[13]), + .ibar(gnd), + .o(\Sample[13]~input_o )); +// synopsys translate_off +defparam \Sample[13]~input .bus_hold = "false"; +defparam \Sample[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N2 +cycloneive_lcell_comb \Add1~1 ( +// Equation(s): +// \Add1~1_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[13]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[13]~input_o ), + .cin(gnd), + .combout(\Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~1 .lut_mask = 16'hFFF0; +defparam \Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N22 +cycloneive_io_ibuf \SetPoint[13]~input ( + .i(SetPoint[13]), + .ibar(gnd), + .o(\SetPoint[13]~input_o )); +// synopsys translate_off +defparam \SetPoint[13]~input .bus_hold = "false"; +defparam \SetPoint[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N0 +cycloneive_lcell_comb \Add1~0 ( +// Equation(s): +// \Add1~0_combout = (!\EE0[13]~_Duplicate_1_q & \SetPoint[13]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\SetPoint[13]~input_o ), + .cin(gnd), + .combout(\Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~0 .lut_mask = 16'h0F00; +defparam \Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N1 +cycloneive_io_ibuf \Sample[12]~input ( + .i(Sample[12]), + .ibar(gnd), + .o(\Sample[12]~input_o )); +// synopsys translate_off +defparam \Sample[12]~input .bus_hold = "false"; +defparam \Sample[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N8 +cycloneive_lcell_comb \Add1~2 ( +// Equation(s): +// \Add1~2_combout = (\Sample[12]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[12]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~2_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~2 .lut_mask = 16'hFFF0; +defparam \Add1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N8 +cycloneive_io_ibuf \SetPoint[12]~input ( + .i(SetPoint[12]), + .ibar(gnd), + .o(\SetPoint[12]~input_o )); +// synopsys translate_off +defparam \SetPoint[12]~input .bus_hold = "false"; +defparam \SetPoint[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N22 +cycloneive_io_ibuf \Sample[11]~input ( + .i(Sample[11]), + .ibar(gnd), + .o(\Sample[11]~input_o )); +// synopsys translate_off +defparam \Sample[11]~input .bus_hold = "false"; +defparam \Sample[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N24 +cycloneive_lcell_comb \Add1~4 ( +// Equation(s): +// \Add1~4_combout = (\Sample[11]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(\Sample[11]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(gnd), + .cin(gnd), + .combout(\Add1~4_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~4 .lut_mask = 16'hFAFA; +defparam \Add1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N8 +cycloneive_io_ibuf \SetPoint[11]~input ( + .i(SetPoint[11]), + .ibar(gnd), + .o(\SetPoint[11]~input_o )); +// synopsys translate_off +defparam \SetPoint[11]~input .bus_hold = "false"; +defparam \SetPoint[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N1 +cycloneive_io_ibuf \SetPoint[10]~input ( + .i(SetPoint[10]), + .ibar(gnd), + .o(\SetPoint[10]~input_o )); +// synopsys translate_off +defparam \SetPoint[10]~input .bus_hold = "false"; +defparam \SetPoint[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N1 +cycloneive_io_ibuf \Sample[10]~input ( + .i(Sample[10]), + .ibar(gnd), + .o(\Sample[10]~input_o )); +// synopsys translate_off +defparam \Sample[10]~input .bus_hold = "false"; +defparam \Sample[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y18_N10 +cycloneive_lcell_comb \Add1~6 ( +// Equation(s): +// \Add1~6_combout = (\Sample[10]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[10]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~6 .lut_mask = 16'hFFF0; +defparam \Add1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N8 +cycloneive_io_ibuf \Sample[9]~input ( + .i(Sample[9]), + .ibar(gnd), + .o(\Sample[9]~input_o )); +// synopsys translate_off +defparam \Sample[9]~input .bus_hold = "false"; +defparam \Sample[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N18 +cycloneive_lcell_comb \Add1~8 ( +// Equation(s): +// \Add1~8_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[9]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[9]~input_o ), + .cin(gnd), + .combout(\Add1~8_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~8 .lut_mask = 16'hFFF0; +defparam \Add1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N15 +cycloneive_io_ibuf \SetPoint[9]~input ( + .i(SetPoint[9]), + .ibar(gnd), + .o(\SetPoint[9]~input_o )); +// synopsys translate_off +defparam \SetPoint[9]~input .bus_hold = "false"; +defparam \SetPoint[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N22 +cycloneive_io_ibuf \SetPoint[8]~input ( + .i(SetPoint[8]), + .ibar(gnd), + .o(\SetPoint[8]~input_o )); +// synopsys translate_off +defparam \SetPoint[8]~input .bus_hold = "false"; +defparam \SetPoint[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N1 +cycloneive_io_ibuf \Sample[8]~input ( + .i(Sample[8]), + .ibar(gnd), + .o(\Sample[8]~input_o )); +// synopsys translate_off +defparam \Sample[8]~input .bus_hold = "false"; +defparam \Sample[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N20 +cycloneive_lcell_comb \Add1~10 ( +// Equation(s): +// \Add1~10_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[8]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[8]~input_o ), + .cin(gnd), + .combout(\Add1~10_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~10 .lut_mask = 16'hFFF0; +defparam \Add1~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N15 +cycloneive_io_ibuf \Sample[7]~input ( + .i(Sample[7]), + .ibar(gnd), + .o(\Sample[7]~input_o )); +// synopsys translate_off +defparam \Sample[7]~input .bus_hold = "false"; +defparam \Sample[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N6 +cycloneive_lcell_comb \Add1~12 ( +// Equation(s): +// \Add1~12_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[7]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[7]~input_o ), + .cin(gnd), + .combout(\Add1~12_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~12 .lut_mask = 16'hFFF0; +defparam \Add1~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N8 +cycloneive_io_ibuf \SetPoint[7]~input ( + .i(SetPoint[7]), + .ibar(gnd), + .o(\SetPoint[7]~input_o )); +// synopsys translate_off +defparam \SetPoint[7]~input .bus_hold = "false"; +defparam \SetPoint[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N15 +cycloneive_io_ibuf \SetPoint[6]~input ( + .i(SetPoint[6]), + .ibar(gnd), + .o(\SetPoint[6]~input_o )); +// synopsys translate_off +defparam \SetPoint[6]~input .bus_hold = "false"; +defparam \SetPoint[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N15 +cycloneive_io_ibuf \Sample[6]~input ( + .i(Sample[6]), + .ibar(gnd), + .o(\Sample[6]~input_o )); +// synopsys translate_off +defparam \Sample[6]~input .bus_hold = "false"; +defparam \Sample[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N22 +cycloneive_lcell_comb \Add1~14 ( +// Equation(s): +// \Add1~14_combout = (\Sample[6]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\Sample[6]~input_o ), + .datac(gnd), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~14_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~14 .lut_mask = 16'hFFCC; +defparam \Add1~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N22 +cycloneive_io_ibuf \Sample[5]~input ( + .i(Sample[5]), + .ibar(gnd), + .o(\Sample[5]~input_o )); +// synopsys translate_off +defparam \Sample[5]~input .bus_hold = "false"; +defparam \Sample[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N12 +cycloneive_lcell_comb \Add1~16 ( +// Equation(s): +// \Add1~16_combout = (\EE0[13]~_Duplicate_1_q ) # (\Sample[5]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\Sample[5]~input_o ), + .cin(gnd), + .combout(\Add1~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~16 .lut_mask = 16'hFFF0; +defparam \Add1~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N15 +cycloneive_io_ibuf \SetPoint[4]~input ( + .i(SetPoint[4]), + .ibar(gnd), + .o(\SetPoint[4]~input_o )); +// synopsys translate_off +defparam \SetPoint[4]~input .bus_hold = "false"; +defparam \SetPoint[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N15 +cycloneive_io_ibuf \Sample[4]~input ( + .i(Sample[4]), + .ibar(gnd), + .o(\Sample[4]~input_o )); +// synopsys translate_off +defparam \Sample[4]~input .bus_hold = "false"; +defparam \Sample[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N16 +cycloneive_lcell_comb \Add1~18 ( +// Equation(s): +// \Add1~18_combout = (\Sample[4]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\Sample[4]~input_o ), + .datac(gnd), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~18 .lut_mask = 16'hFFCC; +defparam \Add1~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N22 +cycloneive_io_ibuf \Sample[3]~input ( + .i(Sample[3]), + .ibar(gnd), + .o(\Sample[3]~input_o )); +// synopsys translate_off +defparam \Sample[3]~input .bus_hold = "false"; +defparam \Sample[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N6 +cycloneive_lcell_comb \Add1~20 ( +// Equation(s): +// \Add1~20_combout = (\Sample[3]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[3]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~20 .lut_mask = 16'hFFF0; +defparam \Add1~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N1 +cycloneive_io_ibuf \SetPoint[2]~input ( + .i(SetPoint[2]), + .ibar(gnd), + .o(\SetPoint[2]~input_o )); +// synopsys translate_off +defparam \SetPoint[2]~input .bus_hold = "false"; +defparam \SetPoint[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N22 +cycloneive_io_ibuf \Sample[2]~input ( + .i(Sample[2]), + .ibar(gnd), + .o(\Sample[2]~input_o )); +// synopsys translate_off +defparam \Sample[2]~input .bus_hold = "false"; +defparam \Sample[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N14 +cycloneive_lcell_comb \Add1~22 ( +// Equation(s): +// \Add1~22_combout = (\Sample[2]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[2]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~22_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~22 .lut_mask = 16'hFFF0; +defparam \Add1~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N8 +cycloneive_io_ibuf \Sample[1]~input ( + .i(Sample[1]), + .ibar(gnd), + .o(\Sample[1]~input_o )); +// synopsys translate_off +defparam \Sample[1]~input .bus_hold = "false"; +defparam \Sample[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N4 +cycloneive_lcell_comb \Add1~24 ( +// Equation(s): +// \Add1~24_combout = (\Sample[1]~input_o ) # (\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[1]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~24_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~24 .lut_mask = 16'hFFF0; +defparam \Add1~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N1 +cycloneive_io_ibuf \SetPoint[1]~input ( + .i(SetPoint[1]), + .ibar(gnd), + .o(\SetPoint[1]~input_o )); +// synopsys translate_off +defparam \SetPoint[1]~input .bus_hold = "false"; +defparam \SetPoint[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \Sample[0]~input ( + .i(Sample[0]), + .ibar(gnd), + .o(\Sample[0]~input_o )); +// synopsys translate_off +defparam \Sample[0]~input .bus_hold = "false"; +defparam \Sample[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N12 +cycloneive_lcell_comb \Add1~26 ( +// Equation(s): +// \Add1~26_combout = (\EE0[13]~_Duplicate_1_q ) # (!\Sample[0]~input_o ) + + .dataa(gnd), + .datab(gnd), + .datac(\Sample[0]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~26_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~26 .lut_mask = 16'hFF0F; +defparam \Add1~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N0 +cycloneive_lcell_comb \EE0[0]~15 ( +// Equation(s): +// \EE0[0]~15_cout = CARRY(!\EE0[13]~_Duplicate_1_q ) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\EE0[0]~15_cout )); +// synopsys translate_off +defparam \EE0[0]~15 .lut_mask = 16'h0033; +defparam \EE0[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N2 +cycloneive_lcell_comb \EE0[0]~16 ( +// Equation(s): +// \EE0[0]~16_combout = (\Add1~27_combout & ((\Add1~26_combout & (\EE0[0]~15_cout & VCC)) # (!\Add1~26_combout & (!\EE0[0]~15_cout )))) # (!\Add1~27_combout & ((\Add1~26_combout & (!\EE0[0]~15_cout )) # (!\Add1~26_combout & ((\EE0[0]~15_cout ) # +// (GND))))) +// \EE0[0]~17 = CARRY((\Add1~27_combout & (!\Add1~26_combout & !\EE0[0]~15_cout )) # (!\Add1~27_combout & ((!\EE0[0]~15_cout ) # (!\Add1~26_combout )))) + + .dataa(\Add1~27_combout ), + .datab(\Add1~26_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[0]~15_cout ), + .combout(\EE0[0]~16_combout ), + .cout(\EE0[0]~17 )); +// synopsys translate_off +defparam \EE0[0]~16 .lut_mask = 16'h9617; +defparam \EE0[0]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N4 +cycloneive_lcell_comb \EE0[1]~18 ( +// Equation(s): +// \EE0[1]~18_combout = ((\Add1~24_combout $ (\Add1~25_combout $ (\EE0[0]~17 )))) # (GND) +// \EE0[1]~19 = CARRY((\Add1~24_combout & (\Add1~25_combout & !\EE0[0]~17 )) # (!\Add1~24_combout & ((\Add1~25_combout ) # (!\EE0[0]~17 )))) + + .dataa(\Add1~24_combout ), + .datab(\Add1~25_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[0]~17 ), + .combout(\EE0[1]~18_combout ), + .cout(\EE0[1]~19 )); +// synopsys translate_off +defparam \EE0[1]~18 .lut_mask = 16'h964D; +defparam \EE0[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N4 +cycloneive_lcell_comb \Add0~0 ( +// Equation(s): +// \Add0~0_combout = period[0] $ (VCC) +// \Add0~1 = CARRY(period[0]) + + .dataa(gnd), + .datab(period[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add0~0_combout ), + .cout(\Add0~1 )); +// synopsys translate_off +defparam \Add0~0 .lut_mask = 16'h33CC; +defparam \Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N6 +cycloneive_lcell_comb \period~3 ( +// Equation(s): +// \period~3_combout = (\Add0~0_combout & (((!\Equal0~2_combout ) # (!\Equal0~0_combout )) # (!\Equal0~1_combout ))) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~0_combout ), + .datac(\Add0~0_combout ), + .datad(\Equal0~2_combout ), + .cin(gnd), + .combout(\period~3_combout ), + .cout()); +// synopsys translate_off +defparam \period~3 .lut_mask = 16'h70F0; +defparam \period~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y13_N7 +dffeas \period[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~3_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[0]), + .prn(vcc)); +// synopsys translate_off +defparam \period[0] .is_wysiwyg = "true"; +defparam \period[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N6 +cycloneive_lcell_comb \Add0~2 ( +// Equation(s): +// \Add0~2_combout = (period[1] & (!\Add0~1 )) # (!period[1] & ((\Add0~1 ) # (GND))) +// \Add0~3 = CARRY((!\Add0~1 ) # (!period[1])) + + .dataa(period[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~1 ), + .combout(\Add0~2_combout ), + .cout(\Add0~3 )); +// synopsys translate_off +defparam \Add0~2 .lut_mask = 16'h5A5F; +defparam \Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N7 +dffeas \period[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~2_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[1]), + .prn(vcc)); +// synopsys translate_off +defparam \period[1] .is_wysiwyg = "true"; +defparam \period[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N8 +cycloneive_lcell_comb \Add0~4 ( +// Equation(s): +// \Add0~4_combout = (period[2] & (\Add0~3 $ (GND))) # (!period[2] & (!\Add0~3 & VCC)) +// \Add0~5 = CARRY((period[2] & !\Add0~3 )) + + .dataa(gnd), + .datab(period[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~3 ), + .combout(\Add0~4_combout ), + .cout(\Add0~5 )); +// synopsys translate_off +defparam \Add0~4 .lut_mask = 16'hC30C; +defparam \Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N9 +dffeas \period[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~4_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[2]), + .prn(vcc)); +// synopsys translate_off +defparam \period[2] .is_wysiwyg = "true"; +defparam \period[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N16 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (!period[0] & (!period[2] & !period[1])) + + .dataa(period[0]), + .datab(gnd), + .datac(period[2]), + .datad(period[1]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0005; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N10 +cycloneive_lcell_comb \Add0~6 ( +// Equation(s): +// \Add0~6_combout = (period[3] & (!\Add0~5 )) # (!period[3] & ((\Add0~5 ) # (GND))) +// \Add0~7 = CARRY((!\Add0~5 ) # (!period[3])) + + .dataa(gnd), + .datab(period[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~5 ), + .combout(\Add0~6_combout ), + .cout(\Add0~7 )); +// synopsys translate_off +defparam \Add0~6 .lut_mask = 16'h3C3F; +defparam \Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N0 +cycloneive_lcell_comb \period~2 ( +// Equation(s): +// \period~2_combout = (\Add0~6_combout & (((!\Equal0~0_combout ) # (!\Equal0~1_combout )) # (!\Equal0~2_combout ))) + + .dataa(\Equal0~2_combout ), + .datab(\Equal0~1_combout ), + .datac(\Equal0~0_combout ), + .datad(\Add0~6_combout ), + .cin(gnd), + .combout(\period~2_combout ), + .cout()); +// synopsys translate_off +defparam \period~2 .lut_mask = 16'h7F00; +defparam \period~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N1 +dffeas \period[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~2_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[3]), + .prn(vcc)); +// synopsys translate_off +defparam \period[3] .is_wysiwyg = "true"; +defparam \period[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N12 +cycloneive_lcell_comb \Add0~8 ( +// Equation(s): +// \Add0~8_combout = (period[4] & (\Add0~7 $ (GND))) # (!period[4] & (!\Add0~7 & VCC)) +// \Add0~9 = CARRY((period[4] & !\Add0~7 )) + + .dataa(period[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~7 ), + .combout(\Add0~8_combout ), + .cout(\Add0~9 )); +// synopsys translate_off +defparam \Add0~8 .lut_mask = 16'hA50A; +defparam \Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N13 +dffeas \period[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~8_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[4]), + .prn(vcc)); +// synopsys translate_off +defparam \period[4] .is_wysiwyg = "true"; +defparam \period[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N14 +cycloneive_lcell_comb \Add0~10 ( +// Equation(s): +// \Add0~10_combout = (period[5] & (!\Add0~9 )) # (!period[5] & ((\Add0~9 ) # (GND))) +// \Add0~11 = CARRY((!\Add0~9 ) # (!period[5])) + + .dataa(gnd), + .datab(period[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~9 ), + .combout(\Add0~10_combout ), + .cout(\Add0~11 )); +// synopsys translate_off +defparam \Add0~10 .lut_mask = 16'h3C3F; +defparam \Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N15 +dffeas \period[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~10_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[5]), + .prn(vcc)); +// synopsys translate_off +defparam \period[5] .is_wysiwyg = "true"; +defparam \period[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N16 +cycloneive_lcell_comb \Add0~12 ( +// Equation(s): +// \Add0~12_combout = (period[6] & (\Add0~11 $ (GND))) # (!period[6] & (!\Add0~11 & VCC)) +// \Add0~13 = CARRY((period[6] & !\Add0~11 )) + + .dataa(period[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~11 ), + .combout(\Add0~12_combout ), + .cout(\Add0~13 )); +// synopsys translate_off +defparam \Add0~12 .lut_mask = 16'hA50A; +defparam \Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N18 +cycloneive_lcell_comb \Add0~14 ( +// Equation(s): +// \Add0~14_combout = (period[7] & (!\Add0~13 )) # (!period[7] & ((\Add0~13 ) # (GND))) +// \Add0~15 = CARRY((!\Add0~13 ) # (!period[7])) + + .dataa(gnd), + .datab(period[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~13 ), + .combout(\Add0~14_combout ), + .cout(\Add0~15 )); +// synopsys translate_off +defparam \Add0~14 .lut_mask = 16'h3C3F; +defparam \Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N28 +cycloneive_lcell_comb \period~0 ( +// Equation(s): +// \period~0_combout = (\Add0~14_combout & (((!\Equal0~1_combout ) # (!\Equal0~2_combout )) # (!\Equal0~0_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Add0~14_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\period~0_combout ), + .cout()); +// synopsys translate_off +defparam \period~0 .lut_mask = 16'h4CCC; +defparam \period~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N29 +dffeas \period[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~0_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[7]), + .prn(vcc)); +// synopsys translate_off +defparam \period[7] .is_wysiwyg = "true"; +defparam \period[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N20 +cycloneive_lcell_comb \Add0~16 ( +// Equation(s): +// \Add0~16_combout = (period[8] & (\Add0~15 $ (GND))) # (!period[8] & (!\Add0~15 & VCC)) +// \Add0~17 = CARRY((period[8] & !\Add0~15 )) + + .dataa(gnd), + .datab(period[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add0~15 ), + .combout(\Add0~16_combout ), + .cout(\Add0~17 )); +// synopsys translate_off +defparam \Add0~16 .lut_mask = 16'hC30C; +defparam \Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N21 +dffeas \period[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~16_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[8]), + .prn(vcc)); +// synopsys translate_off +defparam \period[8] .is_wysiwyg = "true"; +defparam \period[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N22 +cycloneive_lcell_comb \Add0~18 ( +// Equation(s): +// \Add0~18_combout = (period[9] & (!\Add0~17 )) # (!period[9] & ((\Add0~17 ) # (GND))) +// \Add0~19 = CARRY((!\Add0~17 ) # (!period[9])) + + .dataa(period[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add0~17 ), + .combout(\Add0~18_combout ), + .cout(\Add0~19 )); +// synopsys translate_off +defparam \Add0~18 .lut_mask = 16'h5A5F; +defparam \Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N23 +dffeas \period[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~18_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[9]), + .prn(vcc)); +// synopsys translate_off +defparam \period[9] .is_wysiwyg = "true"; +defparam \period[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N24 +cycloneive_lcell_comb \Add0~20 ( +// Equation(s): +// \Add0~20_combout = \Add0~19 $ (!period[10]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(period[10]), + .cin(\Add0~19 ), + .combout(\Add0~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add0~20 .lut_mask = 16'hF00F; +defparam \Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y13_N25 +dffeas \period[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Add0~20_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[10]), + .prn(vcc)); +// synopsys translate_off +defparam \period[10] .is_wysiwyg = "true"; +defparam \period[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N26 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!period[10] & (!period[8] & (!period[9] & period[7]))) + + .dataa(period[10]), + .datab(period[8]), + .datac(period[9]), + .datad(period[7]), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0100; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N30 +cycloneive_lcell_comb \period~1 ( +// Equation(s): +// \period~1_combout = (\Add0~12_combout & (((!\Equal0~1_combout ) # (!\Equal0~2_combout )) # (!\Equal0~0_combout ))) + + .dataa(\Equal0~0_combout ), + .datab(\Add0~12_combout ), + .datac(\Equal0~2_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\period~1_combout ), + .cout()); +// synopsys translate_off +defparam \period~1 .lut_mask = 16'h4CCC; +defparam \period~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y13_N31 +dffeas \period[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\period~1_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(period[6]), + .prn(vcc)); +// synopsys translate_off +defparam \period[6] .is_wysiwyg = "true"; +defparam \period[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y13_N2 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (period[6] & (period[3] & (!period[5] & !period[4]))) + + .dataa(period[6]), + .datab(period[3]), + .datac(period[5]), + .datad(period[4]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0008; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y13_N0 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (\Equal0~1_combout & (\Equal0~2_combout & \Equal0~0_combout )) + + .dataa(\Equal0~1_combout ), + .datab(\Equal0~2_combout ), + .datac(gnd), + .datad(\Equal0~0_combout ), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h8800; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y13_N1 +dffeas Clk_Ctrl( + .clk(\clk~inputclkctrl_outclk ), + .d(\Equal0~3_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\Clk_Ctrl~q ), + .prn(vcc)); +// synopsys translate_off +defparam Clk_Ctrl.is_wysiwyg = "true"; +defparam Clk_Ctrl.power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y18_N5 +dffeas \EE0[1]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[1]~18_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[1]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[1]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[1]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N10 +cycloneive_lcell_comb \Add1~25 ( +// Equation(s): +// \Add1~25_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[1]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[1]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[1]~input_o ), + .datac(\EE0[1]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~25_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~25 .lut_mask = 16'h0FCC; +defparam \Add1~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N6 +cycloneive_lcell_comb \EE0[2]~20 ( +// Equation(s): +// \EE0[2]~20_combout = (\Add1~23_combout & ((\Add1~22_combout & (!\EE0[1]~19 )) # (!\Add1~22_combout & (\EE0[1]~19 & VCC)))) # (!\Add1~23_combout & ((\Add1~22_combout & ((\EE0[1]~19 ) # (GND))) # (!\Add1~22_combout & (!\EE0[1]~19 )))) +// \EE0[2]~21 = CARRY((\Add1~23_combout & (\Add1~22_combout & !\EE0[1]~19 )) # (!\Add1~23_combout & ((\Add1~22_combout ) # (!\EE0[1]~19 )))) + + .dataa(\Add1~23_combout ), + .datab(\Add1~22_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[1]~19 ), + .combout(\EE0[2]~20_combout ), + .cout(\EE0[2]~21 )); +// synopsys translate_off +defparam \EE0[2]~20 .lut_mask = 16'h694D; +defparam \EE0[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N7 +dffeas \EE0[2]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[2]~20_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[2]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[2]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[2]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N30 +cycloneive_lcell_comb \Add1~23 ( +// Equation(s): +// \Add1~23_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[2]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[2]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[2]~input_o ), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[2]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~23_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~23 .lut_mask = 16'h0CFC; +defparam \Add1~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N8 +cycloneive_lcell_comb \EE0[3]~22 ( +// Equation(s): +// \EE0[3]~22_combout = ((\Add1~20_combout $ (\Add1~21_combout $ (\EE0[2]~21 )))) # (GND) +// \EE0[3]~23 = CARRY((\Add1~20_combout & (\Add1~21_combout & !\EE0[2]~21 )) # (!\Add1~20_combout & ((\Add1~21_combout ) # (!\EE0[2]~21 )))) + + .dataa(\Add1~20_combout ), + .datab(\Add1~21_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[2]~21 ), + .combout(\EE0[3]~22_combout ), + .cout(\EE0[3]~23 )); +// synopsys translate_off +defparam \EE0[3]~22 .lut_mask = 16'h964D; +defparam \EE0[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N9 +dffeas \EE0[3]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[3]~22_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[3]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[3]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[3]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N15 +cycloneive_io_ibuf \SetPoint[3]~input ( + .i(SetPoint[3]), + .ibar(gnd), + .o(\SetPoint[3]~input_o )); +// synopsys translate_off +defparam \SetPoint[3]~input .bus_hold = "false"; +defparam \SetPoint[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N28 +cycloneive_lcell_comb \Add1~21 ( +// Equation(s): +// \Add1~21_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[3]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[3]~input_o ))) + + .dataa(\EE0[3]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[3]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~21_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~21 .lut_mask = 16'h55F0; +defparam \Add1~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N10 +cycloneive_lcell_comb \EE0[4]~24 ( +// Equation(s): +// \EE0[4]~24_combout = (\Add1~19_combout & ((\Add1~18_combout & (!\EE0[3]~23 )) # (!\Add1~18_combout & (\EE0[3]~23 & VCC)))) # (!\Add1~19_combout & ((\Add1~18_combout & ((\EE0[3]~23 ) # (GND))) # (!\Add1~18_combout & (!\EE0[3]~23 )))) +// \EE0[4]~25 = CARRY((\Add1~19_combout & (\Add1~18_combout & !\EE0[3]~23 )) # (!\Add1~19_combout & ((\Add1~18_combout ) # (!\EE0[3]~23 )))) + + .dataa(\Add1~19_combout ), + .datab(\Add1~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[3]~23 ), + .combout(\EE0[4]~24_combout ), + .cout(\EE0[4]~25 )); +// synopsys translate_off +defparam \EE0[4]~24 .lut_mask = 16'h694D; +defparam \EE0[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N11 +dffeas \EE0[4]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[4]~24_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[4]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[4]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[4]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y20_N22 +cycloneive_lcell_comb \Add1~19 ( +// Equation(s): +// \Add1~19_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[4]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[4]~input_o )) + + .dataa(\SetPoint[4]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[4]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~19 .lut_mask = 16'h0AFA; +defparam \Add1~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N12 +cycloneive_lcell_comb \EE0[5]~26 ( +// Equation(s): +// \EE0[5]~26_combout = ((\Add1~16_combout $ (\Add1~17_combout $ (\EE0[4]~25 )))) # (GND) +// \EE0[5]~27 = CARRY((\Add1~16_combout & (\Add1~17_combout & !\EE0[4]~25 )) # (!\Add1~16_combout & ((\Add1~17_combout ) # (!\EE0[4]~25 )))) + + .dataa(\Add1~16_combout ), + .datab(\Add1~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[4]~25 ), + .combout(\EE0[5]~26_combout ), + .cout(\EE0[5]~27 )); +// synopsys translate_off +defparam \EE0[5]~26 .lut_mask = 16'h964D; +defparam \EE0[5]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N13 +dffeas \EE0[5]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[5]~26_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[5]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[5]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[5]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N8 +cycloneive_io_ibuf \SetPoint[5]~input ( + .i(SetPoint[5]), + .ibar(gnd), + .o(\SetPoint[5]~input_o )); +// synopsys translate_off +defparam \SetPoint[5]~input .bus_hold = "false"; +defparam \SetPoint[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N18 +cycloneive_lcell_comb \Add1~17 ( +// Equation(s): +// \Add1~17_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[5]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[5]~input_o ))) + + .dataa(\EE0[5]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[5]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~17 .lut_mask = 16'h55F0; +defparam \Add1~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N14 +cycloneive_lcell_comb \EE0[6]~28 ( +// Equation(s): +// \EE0[6]~28_combout = (\Add1~15_combout & ((\Add1~14_combout & (!\EE0[5]~27 )) # (!\Add1~14_combout & (\EE0[5]~27 & VCC)))) # (!\Add1~15_combout & ((\Add1~14_combout & ((\EE0[5]~27 ) # (GND))) # (!\Add1~14_combout & (!\EE0[5]~27 )))) +// \EE0[6]~29 = CARRY((\Add1~15_combout & (\Add1~14_combout & !\EE0[5]~27 )) # (!\Add1~15_combout & ((\Add1~14_combout ) # (!\EE0[5]~27 )))) + + .dataa(\Add1~15_combout ), + .datab(\Add1~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[5]~27 ), + .combout(\EE0[6]~28_combout ), + .cout(\EE0[6]~29 )); +// synopsys translate_off +defparam \EE0[6]~28 .lut_mask = 16'h694D; +defparam \EE0[6]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N15 +dffeas \EE0[6]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[6]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[6]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[6]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[6]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N20 +cycloneive_lcell_comb \Add1~15 ( +// Equation(s): +// \Add1~15_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[6]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[6]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[6]~input_o ), + .datad(\EE0[6]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~15_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~15 .lut_mask = 16'h30FC; +defparam \Add1~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N16 +cycloneive_lcell_comb \EE0[7]~30 ( +// Equation(s): +// \EE0[7]~30_combout = ((\Add1~12_combout $ (\Add1~13_combout $ (\EE0[6]~29 )))) # (GND) +// \EE0[7]~31 = CARRY((\Add1~12_combout & (\Add1~13_combout & !\EE0[6]~29 )) # (!\Add1~12_combout & ((\Add1~13_combout ) # (!\EE0[6]~29 )))) + + .dataa(\Add1~12_combout ), + .datab(\Add1~13_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[6]~29 ), + .combout(\EE0[7]~30_combout ), + .cout(\EE0[7]~31 )); +// synopsys translate_off +defparam \EE0[7]~30 .lut_mask = 16'h964D; +defparam \EE0[7]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N17 +dffeas \EE0[7]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[7]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[7]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[7]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[7]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N24 +cycloneive_lcell_comb \Add1~13 ( +// Equation(s): +// \Add1~13_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[7]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[7]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[7]~input_o ), + .datac(\EE0[7]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~13_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~13 .lut_mask = 16'h0FCC; +defparam \Add1~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N18 +cycloneive_lcell_comb \EE0[8]~32 ( +// Equation(s): +// \EE0[8]~32_combout = (\Add1~11_combout & ((\Add1~10_combout & (!\EE0[7]~31 )) # (!\Add1~10_combout & (\EE0[7]~31 & VCC)))) # (!\Add1~11_combout & ((\Add1~10_combout & ((\EE0[7]~31 ) # (GND))) # (!\Add1~10_combout & (!\EE0[7]~31 )))) +// \EE0[8]~33 = CARRY((\Add1~11_combout & (\Add1~10_combout & !\EE0[7]~31 )) # (!\Add1~11_combout & ((\Add1~10_combout ) # (!\EE0[7]~31 )))) + + .dataa(\Add1~11_combout ), + .datab(\Add1~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[7]~31 ), + .combout(\EE0[8]~32_combout ), + .cout(\EE0[8]~33 )); +// synopsys translate_off +defparam \EE0[8]~32 .lut_mask = 16'h694D; +defparam \EE0[8]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N19 +dffeas \EE0[8]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[8]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[8]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[8]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[8]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N30 +cycloneive_lcell_comb \Add1~11 ( +// Equation(s): +// \Add1~11_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[8]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[8]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[8]~input_o ), + .datad(\EE0[8]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~11_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~11 .lut_mask = 16'h30FC; +defparam \Add1~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N20 +cycloneive_lcell_comb \EE0[9]~34 ( +// Equation(s): +// \EE0[9]~34_combout = ((\Add1~8_combout $ (\Add1~9_combout $ (\EE0[8]~33 )))) # (GND) +// \EE0[9]~35 = CARRY((\Add1~8_combout & (\Add1~9_combout & !\EE0[8]~33 )) # (!\Add1~8_combout & ((\Add1~9_combout ) # (!\EE0[8]~33 )))) + + .dataa(\Add1~8_combout ), + .datab(\Add1~9_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[8]~33 ), + .combout(\EE0[9]~34_combout ), + .cout(\EE0[9]~35 )); +// synopsys translate_off +defparam \EE0[9]~34 .lut_mask = 16'h964D; +defparam \EE0[9]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N21 +dffeas \EE0[9]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[9]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[9]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[9]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[9]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N8 +cycloneive_lcell_comb \Add1~9 ( +// Equation(s): +// \Add1~9_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[9]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[9]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[9]~input_o ), + .datad(\EE0[9]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~9_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~9 .lut_mask = 16'h30FC; +defparam \Add1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N22 +cycloneive_lcell_comb \EE0[10]~36 ( +// Equation(s): +// \EE0[10]~36_combout = (\Add1~7_combout & ((\Add1~6_combout & (!\EE0[9]~35 )) # (!\Add1~6_combout & (\EE0[9]~35 & VCC)))) # (!\Add1~7_combout & ((\Add1~6_combout & ((\EE0[9]~35 ) # (GND))) # (!\Add1~6_combout & (!\EE0[9]~35 )))) +// \EE0[10]~37 = CARRY((\Add1~7_combout & (\Add1~6_combout & !\EE0[9]~35 )) # (!\Add1~7_combout & ((\Add1~6_combout ) # (!\EE0[9]~35 )))) + + .dataa(\Add1~7_combout ), + .datab(\Add1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[9]~35 ), + .combout(\EE0[10]~36_combout ), + .cout(\EE0[10]~37 )); +// synopsys translate_off +defparam \EE0[10]~36 .lut_mask = 16'h694D; +defparam \EE0[10]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N23 +dffeas \EE0[10]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[10]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[10]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[10]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[10]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N26 +cycloneive_lcell_comb \Add1~7 ( +// Equation(s): +// \Add1~7_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[10]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[10]~input_o )) + + .dataa(gnd), + .datab(\EE0[13]~_Duplicate_1_q ), + .datac(\SetPoint[10]~input_o ), + .datad(\EE0[10]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~7_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~7 .lut_mask = 16'h30FC; +defparam \Add1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N24 +cycloneive_lcell_comb \EE0[11]~38 ( +// Equation(s): +// \EE0[11]~38_combout = ((\Add1~4_combout $ (\Add1~5_combout $ (\EE0[10]~37 )))) # (GND) +// \EE0[11]~39 = CARRY((\Add1~4_combout & (\Add1~5_combout & !\EE0[10]~37 )) # (!\Add1~4_combout & ((\Add1~5_combout ) # (!\EE0[10]~37 )))) + + .dataa(\Add1~4_combout ), + .datab(\Add1~5_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[10]~37 ), + .combout(\EE0[11]~38_combout ), + .cout(\EE0[11]~39 )); +// synopsys translate_off +defparam \EE0[11]~38 .lut_mask = 16'h964D; +defparam \EE0[11]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N25 +dffeas \EE0[11]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[11]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[11]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[11]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[11]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N0 +cycloneive_lcell_comb \Add1~5 ( +// Equation(s): +// \Add1~5_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[11]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[11]~input_o )) + + .dataa(\SetPoint[11]~input_o ), + .datab(gnd), + .datac(\EE0[13]~_Duplicate_1_q ), + .datad(\EE0[11]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~5_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~5 .lut_mask = 16'h0AFA; +defparam \Add1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N26 +cycloneive_lcell_comb \EE0[12]~40 ( +// Equation(s): +// \EE0[12]~40_combout = (\Add1~2_combout & ((\Add1~3_combout & (!\EE0[11]~39 )) # (!\Add1~3_combout & ((\EE0[11]~39 ) # (GND))))) # (!\Add1~2_combout & ((\Add1~3_combout & (\EE0[11]~39 & VCC)) # (!\Add1~3_combout & (!\EE0[11]~39 )))) +// \EE0[12]~41 = CARRY((\Add1~2_combout & ((!\EE0[11]~39 ) # (!\Add1~3_combout ))) # (!\Add1~2_combout & (!\Add1~3_combout & !\EE0[11]~39 ))) + + .dataa(\Add1~2_combout ), + .datab(\Add1~3_combout ), + .datac(gnd), + .datad(vcc), + .cin(\EE0[11]~39 ), + .combout(\EE0[12]~40_combout ), + .cout(\EE0[12]~41 )); +// synopsys translate_off +defparam \EE0[12]~40 .lut_mask = 16'h692B; +defparam \EE0[12]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N27 +dffeas \EE0[12]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[12]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[12]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[12]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[12]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N0 +cycloneive_lcell_comb \Add1~3 ( +// Equation(s): +// \Add1~3_combout = (\EE0[13]~_Duplicate_1_q & ((!\EE0[12]~_Duplicate_1_q ))) # (!\EE0[13]~_Duplicate_1_q & (\SetPoint[12]~input_o )) + + .dataa(gnd), + .datab(\SetPoint[12]~input_o ), + .datac(\EE0[12]~_Duplicate_1_q ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~3_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~3 .lut_mask = 16'h0FCC; +defparam \Add1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y18_N28 +cycloneive_lcell_comb \EE0[13]~42 ( +// Equation(s): +// \EE0[13]~42_combout = \Add1~1_combout $ (\EE0[12]~41 $ (\Add1~0_combout )) + + .dataa(gnd), + .datab(\Add1~1_combout ), + .datac(gnd), + .datad(\Add1~0_combout ), + .cin(\EE0[12]~41 ), + .combout(\EE0[13]~42_combout ), + .cout()); +// synopsys translate_off +defparam \EE0[13]~42 .lut_mask = 16'hC33C; +defparam \EE0[13]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y18_N31 +dffeas \EE0[13]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\EE0[13]~42_combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[13]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[13]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[13]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y18_N2 +cycloneive_lcell_comb \Add1~27 ( +// Equation(s): +// \Add1~27_combout = (\EE0[13]~_Duplicate_1_q & (!\EE0[0]~_Duplicate_1_q )) # (!\EE0[13]~_Duplicate_1_q & ((\SetPoint[0]~input_o ))) + + .dataa(\EE0[0]~_Duplicate_1_q ), + .datab(gnd), + .datac(\SetPoint[0]~input_o ), + .datad(\EE0[13]~_Duplicate_1_q ), + .cin(gnd), + .combout(\Add1~27_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~27 .lut_mask = 16'h55F0; +defparam \Add1~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y18_N3 +dffeas \EE0[0]~_Duplicate_1 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE0[0]~16_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\EE0[0]~_Duplicate_1_q ), + .prn(vcc)); +// synopsys translate_off +defparam \EE0[0]~_Duplicate_1 .is_wysiwyg = "true"; +defparam \EE0[0]~_Duplicate_1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N4 +cycloneive_lcell_comb \EE1[1]~16 ( +// Equation(s): +// \EE1[1]~16_combout = (EE1[1] & ((\EE1[0]~15 ) # (GND))) # (!EE1[1] & (!\EE1[0]~15 )) +// \EE1[1]~17 = CARRY((EE1[1]) # (!\EE1[0]~15 )) + + .dataa(gnd), + .datab(EE1[1]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[0]~15 ), + .combout(\EE1[1]~16_combout ), + .cout(\EE1[1]~17 )); +// synopsys translate_off +defparam \EE1[1]~16 .lut_mask = 16'hC3CF; +defparam \EE1[1]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N5 +dffeas \EE1[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[1]~16_combout ), + .asdata(\EE0[1]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[1]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[1] .is_wysiwyg = "true"; +defparam \EE1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N6 +cycloneive_lcell_comb \EE1[2]~18 ( +// Equation(s): +// \EE1[2]~18_combout = (EE1[2] & (!\EE1[1]~17 & VCC)) # (!EE1[2] & (\EE1[1]~17 $ (GND))) +// \EE1[2]~19 = CARRY((!EE1[2] & !\EE1[1]~17 )) + + .dataa(EE1[2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[1]~17 ), + .combout(\EE1[2]~18_combout ), + .cout(\EE1[2]~19 )); +// synopsys translate_off +defparam \EE1[2]~18 .lut_mask = 16'h5A05; +defparam \EE1[2]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N7 +dffeas \EE1[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[2]~18_combout ), + .asdata(\EE0[2]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[2]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[2] .is_wysiwyg = "true"; +defparam \EE1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N8 +cycloneive_lcell_comb \EE1[3]~20 ( +// Equation(s): +// \EE1[3]~20_combout = (EE1[3] & ((\EE1[2]~19 ) # (GND))) # (!EE1[3] & (!\EE1[2]~19 )) +// \EE1[3]~21 = CARRY((EE1[3]) # (!\EE1[2]~19 )) + + .dataa(gnd), + .datab(EE1[3]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[2]~19 ), + .combout(\EE1[3]~20_combout ), + .cout(\EE1[3]~21 )); +// synopsys translate_off +defparam \EE1[3]~20 .lut_mask = 16'hC3CF; +defparam \EE1[3]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N9 +dffeas \EE1[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[3]~20_combout ), + .asdata(\EE0[3]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[3]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[3] .is_wysiwyg = "true"; +defparam \EE1[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N10 +cycloneive_lcell_comb \EE1[4]~22 ( +// Equation(s): +// \EE1[4]~22_combout = (EE1[4] & (!\EE1[3]~21 & VCC)) # (!EE1[4] & (\EE1[3]~21 $ (GND))) +// \EE1[4]~23 = CARRY((!EE1[4] & !\EE1[3]~21 )) + + .dataa(EE1[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[3]~21 ), + .combout(\EE1[4]~22_combout ), + .cout(\EE1[4]~23 )); +// synopsys translate_off +defparam \EE1[4]~22 .lut_mask = 16'h5A05; +defparam \EE1[4]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N11 +dffeas \EE1[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[4]~22_combout ), + .asdata(\EE0[4]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[4]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[4] .is_wysiwyg = "true"; +defparam \EE1[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N12 +cycloneive_lcell_comb \EE1[5]~24 ( +// Equation(s): +// \EE1[5]~24_combout = (EE1[5] & ((\EE1[4]~23 ) # (GND))) # (!EE1[5] & (!\EE1[4]~23 )) +// \EE1[5]~25 = CARRY((EE1[5]) # (!\EE1[4]~23 )) + + .dataa(EE1[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[4]~23 ), + .combout(\EE1[5]~24_combout ), + .cout(\EE1[5]~25 )); +// synopsys translate_off +defparam \EE1[5]~24 .lut_mask = 16'hA5AF; +defparam \EE1[5]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N13 +dffeas \EE1[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[5]~24_combout ), + .asdata(\EE0[5]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[5]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[5] .is_wysiwyg = "true"; +defparam \EE1[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N14 +cycloneive_lcell_comb \EE1[6]~26 ( +// Equation(s): +// \EE1[6]~26_combout = (EE1[6] & (!\EE1[5]~25 & VCC)) # (!EE1[6] & (\EE1[5]~25 $ (GND))) +// \EE1[6]~27 = CARRY((!EE1[6] & !\EE1[5]~25 )) + + .dataa(gnd), + .datab(EE1[6]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[5]~25 ), + .combout(\EE1[6]~26_combout ), + .cout(\EE1[6]~27 )); +// synopsys translate_off +defparam \EE1[6]~26 .lut_mask = 16'h3C03; +defparam \EE1[6]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N15 +dffeas \EE1[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[6]~26_combout ), + .asdata(\EE0[6]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[6]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[6] .is_wysiwyg = "true"; +defparam \EE1[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N16 +cycloneive_lcell_comb \EE1[7]~28 ( +// Equation(s): +// \EE1[7]~28_combout = (EE1[7] & ((\EE1[6]~27 ) # (GND))) # (!EE1[7] & (!\EE1[6]~27 )) +// \EE1[7]~29 = CARRY((EE1[7]) # (!\EE1[6]~27 )) + + .dataa(gnd), + .datab(EE1[7]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[6]~27 ), + .combout(\EE1[7]~28_combout ), + .cout(\EE1[7]~29 )); +// synopsys translate_off +defparam \EE1[7]~28 .lut_mask = 16'hC3CF; +defparam \EE1[7]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N17 +dffeas \EE1[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[7]~28_combout ), + .asdata(\EE0[7]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[7]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[7] .is_wysiwyg = "true"; +defparam \EE1[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N18 +cycloneive_lcell_comb \EE1[8]~30 ( +// Equation(s): +// \EE1[8]~30_combout = (EE1[8] & (!\EE1[7]~29 & VCC)) # (!EE1[8] & (\EE1[7]~29 $ (GND))) +// \EE1[8]~31 = CARRY((!EE1[8] & !\EE1[7]~29 )) + + .dataa(gnd), + .datab(EE1[8]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[7]~29 ), + .combout(\EE1[8]~30_combout ), + .cout(\EE1[8]~31 )); +// synopsys translate_off +defparam \EE1[8]~30 .lut_mask = 16'h3C03; +defparam \EE1[8]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N19 +dffeas \EE1[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[8]~30_combout ), + .asdata(\EE0[8]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[8]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[8] .is_wysiwyg = "true"; +defparam \EE1[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N20 +cycloneive_lcell_comb \EE1[9]~32 ( +// Equation(s): +// \EE1[9]~32_combout = (EE1[9] & ((\EE1[8]~31 ) # (GND))) # (!EE1[9] & (!\EE1[8]~31 )) +// \EE1[9]~33 = CARRY((EE1[9]) # (!\EE1[8]~31 )) + + .dataa(gnd), + .datab(EE1[9]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[8]~31 ), + .combout(\EE1[9]~32_combout ), + .cout(\EE1[9]~33 )); +// synopsys translate_off +defparam \EE1[9]~32 .lut_mask = 16'hC3CF; +defparam \EE1[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N21 +dffeas \EE1[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[9]~32_combout ), + .asdata(\EE0[9]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[9]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[9] .is_wysiwyg = "true"; +defparam \EE1[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N22 +cycloneive_lcell_comb \EE1[10]~34 ( +// Equation(s): +// \EE1[10]~34_combout = (EE1[10] & (!\EE1[9]~33 & VCC)) # (!EE1[10] & (\EE1[9]~33 $ (GND))) +// \EE1[10]~35 = CARRY((!EE1[10] & !\EE1[9]~33 )) + + .dataa(EE1[10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[9]~33 ), + .combout(\EE1[10]~34_combout ), + .cout(\EE1[10]~35 )); +// synopsys translate_off +defparam \EE1[10]~34 .lut_mask = 16'h5A05; +defparam \EE1[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N23 +dffeas \EE1[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[10]~34_combout ), + .asdata(\EE0[10]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[10]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[10] .is_wysiwyg = "true"; +defparam \EE1[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N24 +cycloneive_lcell_comb \EE1[11]~36 ( +// Equation(s): +// \EE1[11]~36_combout = (EE1[11] & ((\EE1[10]~35 ) # (GND))) # (!EE1[11] & (!\EE1[10]~35 )) +// \EE1[11]~37 = CARRY((EE1[11]) # (!\EE1[10]~35 )) + + .dataa(gnd), + .datab(EE1[11]), + .datac(gnd), + .datad(vcc), + .cin(\EE1[10]~35 ), + .combout(\EE1[11]~36_combout ), + .cout(\EE1[11]~37 )); +// synopsys translate_off +defparam \EE1[11]~36 .lut_mask = 16'hC3CF; +defparam \EE1[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N25 +dffeas \EE1[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[11]~36_combout ), + .asdata(\EE0[11]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[11]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[11] .is_wysiwyg = "true"; +defparam \EE1[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N26 +cycloneive_lcell_comb \EE1[12]~38 ( +// Equation(s): +// \EE1[12]~38_combout = (EE1[12] & (!\EE1[11]~37 & VCC)) # (!EE1[12] & (\EE1[11]~37 $ (GND))) +// \EE1[12]~39 = CARRY((!EE1[12] & !\EE1[11]~37 )) + + .dataa(EE1[12]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE1[11]~37 ), + .combout(\EE1[12]~38_combout ), + .cout(\EE1[12]~39 )); +// synopsys translate_off +defparam \EE1[12]~38 .lut_mask = 16'h5A05; +defparam \EE1[12]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N27 +dffeas \EE1[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[12]~38_combout ), + .asdata(\EE0[12]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[12]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[12] .is_wysiwyg = "true"; +defparam \EE1[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y17_N28 +cycloneive_lcell_comb \EE1[13]~40 ( +// Equation(s): +// \EE1[13]~40_combout = \EE1[12]~39 $ (!EE1[13]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(EE1[13]), + .cin(\EE1[12]~39 ), + .combout(\EE1[13]~40_combout ), + .cout()); +// synopsys translate_off +defparam \EE1[13]~40 .lut_mask = 16'hF00F; +defparam \EE1[13]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y17_N29 +dffeas \EE1[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[13]~40_combout ), + .asdata(\EE0[13]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[13]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[13] .is_wysiwyg = "true"; +defparam \EE1[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y17_N3 +dffeas \EE1[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE1[0]~14_combout ), + .asdata(\EE0[0]~_Duplicate_1_q ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE1[0]), + .prn(vcc)); +// synopsys translate_off +defparam \EE1[0] .is_wysiwyg = "true"; +defparam \EE1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N6 +cycloneive_lcell_comb \EE2[1]~16 ( +// Equation(s): +// \EE2[1]~16_combout = (EE2[1] & ((\EE2[0]~15 ) # (GND))) # (!EE2[1] & (!\EE2[0]~15 )) +// \EE2[1]~17 = CARRY((EE2[1]) # (!\EE2[0]~15 )) + + .dataa(EE2[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[0]~15 ), + .combout(\EE2[1]~16_combout ), + .cout(\EE2[1]~17 )); +// synopsys translate_off +defparam \EE2[1]~16 .lut_mask = 16'hA5AF; +defparam \EE2[1]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N7 +dffeas \EE2[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[1]~16_combout ), + .asdata(EE1[1]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[1]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[1] .is_wysiwyg = "true"; +defparam \EE2[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N8 +cycloneive_lcell_comb \EE2[2]~18 ( +// Equation(s): +// \EE2[2]~18_combout = (EE2[2] & (!\EE2[1]~17 & VCC)) # (!EE2[2] & (\EE2[1]~17 $ (GND))) +// \EE2[2]~19 = CARRY((!EE2[2] & !\EE2[1]~17 )) + + .dataa(gnd), + .datab(EE2[2]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[1]~17 ), + .combout(\EE2[2]~18_combout ), + .cout(\EE2[2]~19 )); +// synopsys translate_off +defparam \EE2[2]~18 .lut_mask = 16'h3C03; +defparam \EE2[2]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N9 +dffeas \EE2[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[2]~18_combout ), + .asdata(EE1[2]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[2]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[2] .is_wysiwyg = "true"; +defparam \EE2[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N10 +cycloneive_lcell_comb \EE2[3]~20 ( +// Equation(s): +// \EE2[3]~20_combout = (EE2[3] & ((\EE2[2]~19 ) # (GND))) # (!EE2[3] & (!\EE2[2]~19 )) +// \EE2[3]~21 = CARRY((EE2[3]) # (!\EE2[2]~19 )) + + .dataa(EE2[3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[2]~19 ), + .combout(\EE2[3]~20_combout ), + .cout(\EE2[3]~21 )); +// synopsys translate_off +defparam \EE2[3]~20 .lut_mask = 16'hA5AF; +defparam \EE2[3]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N11 +dffeas \EE2[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[3]~20_combout ), + .asdata(EE1[3]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[3]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[3] .is_wysiwyg = "true"; +defparam \EE2[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N12 +cycloneive_lcell_comb \EE2[4]~22 ( +// Equation(s): +// \EE2[4]~22_combout = (EE2[4] & (!\EE2[3]~21 & VCC)) # (!EE2[4] & (\EE2[3]~21 $ (GND))) +// \EE2[4]~23 = CARRY((!EE2[4] & !\EE2[3]~21 )) + + .dataa(EE2[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[3]~21 ), + .combout(\EE2[4]~22_combout ), + .cout(\EE2[4]~23 )); +// synopsys translate_off +defparam \EE2[4]~22 .lut_mask = 16'h5A05; +defparam \EE2[4]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N13 +dffeas \EE2[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[4]~22_combout ), + .asdata(EE1[4]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[4]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[4] .is_wysiwyg = "true"; +defparam \EE2[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N14 +cycloneive_lcell_comb \EE2[5]~24 ( +// Equation(s): +// \EE2[5]~24_combout = (EE2[5] & ((\EE2[4]~23 ) # (GND))) # (!EE2[5] & (!\EE2[4]~23 )) +// \EE2[5]~25 = CARRY((EE2[5]) # (!\EE2[4]~23 )) + + .dataa(gnd), + .datab(EE2[5]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[4]~23 ), + .combout(\EE2[5]~24_combout ), + .cout(\EE2[5]~25 )); +// synopsys translate_off +defparam \EE2[5]~24 .lut_mask = 16'hC3CF; +defparam \EE2[5]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N15 +dffeas \EE2[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[5]~24_combout ), + .asdata(EE1[5]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[5]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[5] .is_wysiwyg = "true"; +defparam \EE2[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N16 +cycloneive_lcell_comb \EE2[6]~26 ( +// Equation(s): +// \EE2[6]~26_combout = (EE2[6] & (!\EE2[5]~25 & VCC)) # (!EE2[6] & (\EE2[5]~25 $ (GND))) +// \EE2[6]~27 = CARRY((!EE2[6] & !\EE2[5]~25 )) + + .dataa(gnd), + .datab(EE2[6]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[5]~25 ), + .combout(\EE2[6]~26_combout ), + .cout(\EE2[6]~27 )); +// synopsys translate_off +defparam \EE2[6]~26 .lut_mask = 16'h3C03; +defparam \EE2[6]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N17 +dffeas \EE2[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[6]~26_combout ), + .asdata(EE1[6]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[6]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[6] .is_wysiwyg = "true"; +defparam \EE2[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N18 +cycloneive_lcell_comb \EE2[7]~28 ( +// Equation(s): +// \EE2[7]~28_combout = (EE2[7] & ((\EE2[6]~27 ) # (GND))) # (!EE2[7] & (!\EE2[6]~27 )) +// \EE2[7]~29 = CARRY((EE2[7]) # (!\EE2[6]~27 )) + + .dataa(gnd), + .datab(EE2[7]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[6]~27 ), + .combout(\EE2[7]~28_combout ), + .cout(\EE2[7]~29 )); +// synopsys translate_off +defparam \EE2[7]~28 .lut_mask = 16'hC3CF; +defparam \EE2[7]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N19 +dffeas \EE2[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[7]~28_combout ), + .asdata(EE1[7]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[7]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[7] .is_wysiwyg = "true"; +defparam \EE2[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N20 +cycloneive_lcell_comb \EE2[8]~30 ( +// Equation(s): +// \EE2[8]~30_combout = (EE2[8] & (!\EE2[7]~29 & VCC)) # (!EE2[8] & (\EE2[7]~29 $ (GND))) +// \EE2[8]~31 = CARRY((!EE2[8] & !\EE2[7]~29 )) + + .dataa(gnd), + .datab(EE2[8]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[7]~29 ), + .combout(\EE2[8]~30_combout ), + .cout(\EE2[8]~31 )); +// synopsys translate_off +defparam \EE2[8]~30 .lut_mask = 16'h3C03; +defparam \EE2[8]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N21 +dffeas \EE2[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[8]~30_combout ), + .asdata(EE1[8]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[8]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[8] .is_wysiwyg = "true"; +defparam \EE2[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N22 +cycloneive_lcell_comb \EE2[9]~32 ( +// Equation(s): +// \EE2[9]~32_combout = (EE2[9] & ((\EE2[8]~31 ) # (GND))) # (!EE2[9] & (!\EE2[8]~31 )) +// \EE2[9]~33 = CARRY((EE2[9]) # (!\EE2[8]~31 )) + + .dataa(EE2[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[8]~31 ), + .combout(\EE2[9]~32_combout ), + .cout(\EE2[9]~33 )); +// synopsys translate_off +defparam \EE2[9]~32 .lut_mask = 16'hA5AF; +defparam \EE2[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N23 +dffeas \EE2[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[9]~32_combout ), + .asdata(EE1[9]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[9]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[9] .is_wysiwyg = "true"; +defparam \EE2[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N24 +cycloneive_lcell_comb \EE2[10]~34 ( +// Equation(s): +// \EE2[10]~34_combout = (EE2[10] & (!\EE2[9]~33 & VCC)) # (!EE2[10] & (\EE2[9]~33 $ (GND))) +// \EE2[10]~35 = CARRY((!EE2[10] & !\EE2[9]~33 )) + + .dataa(gnd), + .datab(EE2[10]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[9]~33 ), + .combout(\EE2[10]~34_combout ), + .cout(\EE2[10]~35 )); +// synopsys translate_off +defparam \EE2[10]~34 .lut_mask = 16'h3C03; +defparam \EE2[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N25 +dffeas \EE2[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[10]~34_combout ), + .asdata(EE1[10]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[10]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[10] .is_wysiwyg = "true"; +defparam \EE2[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N26 +cycloneive_lcell_comb \EE2[11]~36 ( +// Equation(s): +// \EE2[11]~36_combout = (EE2[11] & ((\EE2[10]~35 ) # (GND))) # (!EE2[11] & (!\EE2[10]~35 )) +// \EE2[11]~37 = CARRY((EE2[11]) # (!\EE2[10]~35 )) + + .dataa(EE2[11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\EE2[10]~35 ), + .combout(\EE2[11]~36_combout ), + .cout(\EE2[11]~37 )); +// synopsys translate_off +defparam \EE2[11]~36 .lut_mask = 16'hA5AF; +defparam \EE2[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N27 +dffeas \EE2[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[11]~36_combout ), + .asdata(EE1[11]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[11]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[11] .is_wysiwyg = "true"; +defparam \EE2[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N28 +cycloneive_lcell_comb \EE2[12]~38 ( +// Equation(s): +// \EE2[12]~38_combout = (EE2[12] & (!\EE2[11]~37 & VCC)) # (!EE2[12] & (\EE2[11]~37 $ (GND))) +// \EE2[12]~39 = CARRY((!EE2[12] & !\EE2[11]~37 )) + + .dataa(gnd), + .datab(EE2[12]), + .datac(gnd), + .datad(vcc), + .cin(\EE2[11]~37 ), + .combout(\EE2[12]~38_combout ), + .cout(\EE2[12]~39 )); +// synopsys translate_off +defparam \EE2[12]~38 .lut_mask = 16'h3C03; +defparam \EE2[12]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N29 +dffeas \EE2[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[12]~38_combout ), + .asdata(EE1[12]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[12]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[12] .is_wysiwyg = "true"; +defparam \EE2[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y14_N30 +cycloneive_lcell_comb \EE2[13]~40 ( +// Equation(s): +// \EE2[13]~40_combout = EE2[13] $ (!\EE2[12]~39 ) + + .dataa(EE2[13]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\EE2[12]~39 ), + .combout(\EE2[13]~40_combout ), + .cout()); +// synopsys translate_off +defparam \EE2[13]~40 .lut_mask = 16'hA5A5; +defparam \EE2[13]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X21_Y14_N31 +dffeas \EE2[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[13]~40_combout ), + .asdata(EE1[13]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[13]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[13] .is_wysiwyg = "true"; +defparam \EE2[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y14_N5 +dffeas \EE2[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\EE2[0]~14_combout ), + .asdata(EE1[0]), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(EE2[0]), + .prn(vcc)); +// synopsys translate_off +defparam \EE2[0] .is_wysiwyg = "true"; +defparam \EE2[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N15 +cycloneive_io_ibuf \Kd[0]~input ( + .i(Kd[0]), + .ibar(gnd), + .o(\Kd[0]~input_o )); +// synopsys translate_off +defparam \Kd[0]~input .bus_hold = "false"; +defparam \Kd[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N8 +cycloneive_io_ibuf \Kd[1]~input ( + .i(Kd[1]), + .ibar(gnd), + .o(\Kd[1]~input_o )); +// synopsys translate_off +defparam \Kd[1]~input .bus_hold = "false"; +defparam \Kd[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N1 +cycloneive_io_ibuf \Kd[2]~input ( + .i(Kd[2]), + .ibar(gnd), + .o(\Kd[2]~input_o )); +// synopsys translate_off +defparam \Kd[2]~input .bus_hold = "false"; +defparam \Kd[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N15 +cycloneive_io_ibuf \Kd[3]~input ( + .i(Kd[3]), + .ibar(gnd), + .o(\Kd[3]~input_o )); +// synopsys translate_off +defparam \Kd[3]~input .bus_hold = "false"; +defparam \Kd[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y10_N8 +cycloneive_io_ibuf \Kd[4]~input ( + .i(Kd[4]), + .ibar(gnd), + .o(\Kd[4]~input_o )); +// synopsys translate_off +defparam \Kd[4]~input .bus_hold = "false"; +defparam \Kd[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N8 +cycloneive_io_ibuf \Kd[5]~input ( + .i(Kd[5]), + .ibar(gnd), + .o(\Kd[5]~input_o )); +// synopsys translate_off +defparam \Kd[5]~input .bus_hold = "false"; +defparam \Kd[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N1 +cycloneive_io_ibuf \Kd[6]~input ( + .i(Kd[6]), + .ibar(gnd), + .o(\Kd[6]~input_o )); +// synopsys translate_off +defparam \Kd[6]~input .bus_hold = "false"; +defparam \Kd[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y0_N22 +cycloneive_io_ibuf \Kd[7]~input ( + .i(Kd[7]), + .ibar(gnd), + .o(\Kd[7]~input_o )); +// synopsys translate_off +defparam \Kd[7]~input .bus_hold = "false"; +defparam \Kd[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y14_N0 +cycloneive_mac_mult \Mult2|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({EE2[11],EE2[10],EE2[9],EE2[8],EE2[7],EE2[6],EE2[5],EE2[4],EE2[3],EE2[2],EE2[1],EE2[0],gnd,gnd,gnd,gnd,gnd,gnd}), + .datab({\Kd[7]~input_o ,\Kd[6]~input_o ,\Kd[5]~input_o ,\Kd[4]~input_o ,\Kd[3]~input_o ,\Kd[2]~input_o ,\Kd[1]~input_o ,\Kd[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult2|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult2|auto_generated|mac_mult1 .dataa_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult2|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult2|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult2|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y14_N2 +cycloneive_mac_out \Mult2|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult2|auto_generated|mac_mult1~DATAOUT19 ,\Mult2|auto_generated|mac_mult1~DATAOUT18 ,\Mult2|auto_generated|mac_mult1~DATAOUT17 ,\Mult2|auto_generated|mac_mult1~DATAOUT16 ,\Mult2|auto_generated|mac_mult1~DATAOUT15 ,\Mult2|auto_generated|mac_mult1~DATAOUT14 , +\Mult2|auto_generated|mac_mult1~DATAOUT13 ,\Mult2|auto_generated|mac_mult1~DATAOUT12 ,\Mult2|auto_generated|mac_mult1~DATAOUT11 ,\Mult2|auto_generated|mac_mult1~DATAOUT10 ,\Mult2|auto_generated|mac_mult1~DATAOUT9 ,\Mult2|auto_generated|mac_mult1~DATAOUT8 , +\Mult2|auto_generated|mac_mult1~DATAOUT7 ,\Mult2|auto_generated|mac_mult1~DATAOUT6 ,\Mult2|auto_generated|mac_mult1~DATAOUT5 ,\Mult2|auto_generated|mac_mult1~DATAOUT4 ,\Mult2|auto_generated|mac_mult1~DATAOUT3 ,\Mult2|auto_generated|mac_mult1~DATAOUT2 , +\Mult2|auto_generated|mac_mult1~DATAOUT1 ,\Mult2|auto_generated|mac_mult1~dataout ,\Mult2|auto_generated|mac_mult1~15 ,\Mult2|auto_generated|mac_mult1~14 ,\Mult2|auto_generated|mac_mult1~13 ,\Mult2|auto_generated|mac_mult1~12 ,\Mult2|auto_generated|mac_mult1~11 , +\Mult2|auto_generated|mac_mult1~10 ,\Mult2|auto_generated|mac_mult1~9 ,\Mult2|auto_generated|mac_mult1~8 ,\Mult2|auto_generated|mac_mult1~7 ,\Mult2|auto_generated|mac_mult1~6 ,\Mult2|auto_generated|mac_mult1~5 ,\Mult2|auto_generated|mac_mult1~4 , +\Mult2|auto_generated|mac_mult1~3 ,\Mult2|auto_generated|mac_mult1~2 ,\Mult2|auto_generated|mac_mult1~1 ,\Mult2|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult2|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult2|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult2|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y14_N13 +dffeas \Kd_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[0]~21_combout ), + .asdata(\Mult2|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[0] .is_wysiwyg = "true"; +defparam \Kd_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N14 +cycloneive_lcell_comb \Kd_Out[1]~23 ( +// Equation(s): +// \Kd_Out[1]~23_combout = (Kd_Out[1] & ((\Kd_Out[0]~22 ) # (GND))) # (!Kd_Out[1] & (!\Kd_Out[0]~22 )) +// \Kd_Out[1]~24 = CARRY((Kd_Out[1]) # (!\Kd_Out[0]~22 )) + + .dataa(gnd), + .datab(Kd_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[0]~22 ), + .combout(\Kd_Out[1]~23_combout ), + .cout(\Kd_Out[1]~24 )); +// synopsys translate_off +defparam \Kd_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Kd_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N15 +dffeas \Kd_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[1]~23_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[1] .is_wysiwyg = "true"; +defparam \Kd_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N16 +cycloneive_lcell_comb \Kd_Out[2]~25 ( +// Equation(s): +// \Kd_Out[2]~25_combout = (Kd_Out[2] & (!\Kd_Out[1]~24 & VCC)) # (!Kd_Out[2] & (\Kd_Out[1]~24 $ (GND))) +// \Kd_Out[2]~26 = CARRY((!Kd_Out[2] & !\Kd_Out[1]~24 )) + + .dataa(gnd), + .datab(Kd_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[1]~24 ), + .combout(\Kd_Out[2]~25_combout ), + .cout(\Kd_Out[2]~26 )); +// synopsys translate_off +defparam \Kd_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Kd_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N17 +dffeas \Kd_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[2]~25_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[2] .is_wysiwyg = "true"; +defparam \Kd_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N18 +cycloneive_lcell_comb \Kd_Out[3]~27 ( +// Equation(s): +// \Kd_Out[3]~27_combout = (Kd_Out[3] & ((\Kd_Out[2]~26 ) # (GND))) # (!Kd_Out[3] & (!\Kd_Out[2]~26 )) +// \Kd_Out[3]~28 = CARRY((Kd_Out[3]) # (!\Kd_Out[2]~26 )) + + .dataa(gnd), + .datab(Kd_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[2]~26 ), + .combout(\Kd_Out[3]~27_combout ), + .cout(\Kd_Out[3]~28 )); +// synopsys translate_off +defparam \Kd_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Kd_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N19 +dffeas \Kd_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[3]~27_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[3] .is_wysiwyg = "true"; +defparam \Kd_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N20 +cycloneive_lcell_comb \Kd_Out[4]~29 ( +// Equation(s): +// \Kd_Out[4]~29_combout = (Kd_Out[4] & (!\Kd_Out[3]~28 & VCC)) # (!Kd_Out[4] & (\Kd_Out[3]~28 $ (GND))) +// \Kd_Out[4]~30 = CARRY((!Kd_Out[4] & !\Kd_Out[3]~28 )) + + .dataa(gnd), + .datab(Kd_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[3]~28 ), + .combout(\Kd_Out[4]~29_combout ), + .cout(\Kd_Out[4]~30 )); +// synopsys translate_off +defparam \Kd_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Kd_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N21 +dffeas \Kd_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[4]~29_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[4] .is_wysiwyg = "true"; +defparam \Kd_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N22 +cycloneive_lcell_comb \Kd_Out[5]~31 ( +// Equation(s): +// \Kd_Out[5]~31_combout = (Kd_Out[5] & ((\Kd_Out[4]~30 ) # (GND))) # (!Kd_Out[5] & (!\Kd_Out[4]~30 )) +// \Kd_Out[5]~32 = CARRY((Kd_Out[5]) # (!\Kd_Out[4]~30 )) + + .dataa(Kd_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[4]~30 ), + .combout(\Kd_Out[5]~31_combout ), + .cout(\Kd_Out[5]~32 )); +// synopsys translate_off +defparam \Kd_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Kd_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N23 +dffeas \Kd_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[5]~31_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[5] .is_wysiwyg = "true"; +defparam \Kd_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N24 +cycloneive_lcell_comb \Kd_Out[6]~33 ( +// Equation(s): +// \Kd_Out[6]~33_combout = (Kd_Out[6] & (!\Kd_Out[5]~32 & VCC)) # (!Kd_Out[6] & (\Kd_Out[5]~32 $ (GND))) +// \Kd_Out[6]~34 = CARRY((!Kd_Out[6] & !\Kd_Out[5]~32 )) + + .dataa(gnd), + .datab(Kd_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[5]~32 ), + .combout(\Kd_Out[6]~33_combout ), + .cout(\Kd_Out[6]~34 )); +// synopsys translate_off +defparam \Kd_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Kd_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N25 +dffeas \Kd_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[6]~33_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[6] .is_wysiwyg = "true"; +defparam \Kd_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N26 +cycloneive_lcell_comb \Kd_Out[7]~35 ( +// Equation(s): +// \Kd_Out[7]~35_combout = (Kd_Out[7] & ((\Kd_Out[6]~34 ) # (GND))) # (!Kd_Out[7] & (!\Kd_Out[6]~34 )) +// \Kd_Out[7]~36 = CARRY((Kd_Out[7]) # (!\Kd_Out[6]~34 )) + + .dataa(Kd_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[6]~34 ), + .combout(\Kd_Out[7]~35_combout ), + .cout(\Kd_Out[7]~36 )); +// synopsys translate_off +defparam \Kd_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Kd_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N27 +dffeas \Kd_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[7]~35_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[7] .is_wysiwyg = "true"; +defparam \Kd_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N28 +cycloneive_lcell_comb \Kd_Out[8]~37 ( +// Equation(s): +// \Kd_Out[8]~37_combout = (Kd_Out[8] & (!\Kd_Out[7]~36 & VCC)) # (!Kd_Out[8] & (\Kd_Out[7]~36 $ (GND))) +// \Kd_Out[8]~38 = CARRY((!Kd_Out[8] & !\Kd_Out[7]~36 )) + + .dataa(gnd), + .datab(Kd_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[7]~36 ), + .combout(\Kd_Out[8]~37_combout ), + .cout(\Kd_Out[8]~38 )); +// synopsys translate_off +defparam \Kd_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Kd_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N29 +dffeas \Kd_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[8]~37_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[8] .is_wysiwyg = "true"; +defparam \Kd_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N30 +cycloneive_lcell_comb \Kd_Out[9]~39 ( +// Equation(s): +// \Kd_Out[9]~39_combout = (Kd_Out[9] & ((\Kd_Out[8]~38 ) # (GND))) # (!Kd_Out[9] & (!\Kd_Out[8]~38 )) +// \Kd_Out[9]~40 = CARRY((Kd_Out[9]) # (!\Kd_Out[8]~38 )) + + .dataa(Kd_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[8]~38 ), + .combout(\Kd_Out[9]~39_combout ), + .cout(\Kd_Out[9]~40 )); +// synopsys translate_off +defparam \Kd_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Kd_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y14_N31 +dffeas \Kd_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[9]~39_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[9] .is_wysiwyg = "true"; +defparam \Kd_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N0 +cycloneive_lcell_comb \Kd_Out[10]~41 ( +// Equation(s): +// \Kd_Out[10]~41_combout = (Kd_Out[10] & (!\Kd_Out[9]~40 & VCC)) # (!Kd_Out[10] & (\Kd_Out[9]~40 $ (GND))) +// \Kd_Out[10]~42 = CARRY((!Kd_Out[10] & !\Kd_Out[9]~40 )) + + .dataa(gnd), + .datab(Kd_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[9]~40 ), + .combout(\Kd_Out[10]~41_combout ), + .cout(\Kd_Out[10]~42 )); +// synopsys translate_off +defparam \Kd_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Kd_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N1 +dffeas \Kd_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[10]~41_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[10] .is_wysiwyg = "true"; +defparam \Kd_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N2 +cycloneive_lcell_comb \Kd_Out[11]~43 ( +// Equation(s): +// \Kd_Out[11]~43_combout = (Kd_Out[11] & ((\Kd_Out[10]~42 ) # (GND))) # (!Kd_Out[11] & (!\Kd_Out[10]~42 )) +// \Kd_Out[11]~44 = CARRY((Kd_Out[11]) # (!\Kd_Out[10]~42 )) + + .dataa(gnd), + .datab(Kd_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[10]~42 ), + .combout(\Kd_Out[11]~43_combout ), + .cout(\Kd_Out[11]~44 )); +// synopsys translate_off +defparam \Kd_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Kd_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N0 +cycloneive_lcell_comb \Kd_Out[11]~feeder ( +// Equation(s): +// \Kd_Out[11]~feeder_combout = \Kd_Out[11]~43_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[11]~43_combout ), + .cin(gnd), + .combout(\Kd_Out[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[11]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N1 +dffeas \Kd_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[11]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[11] .is_wysiwyg = "true"; +defparam \Kd_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N4 +cycloneive_lcell_comb \Kd_Out[12]~45 ( +// Equation(s): +// \Kd_Out[12]~45_combout = (Kd_Out[12] & (!\Kd_Out[11]~44 & VCC)) # (!Kd_Out[12] & (\Kd_Out[11]~44 $ (GND))) +// \Kd_Out[12]~46 = CARRY((!Kd_Out[12] & !\Kd_Out[11]~44 )) + + .dataa(gnd), + .datab(Kd_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[11]~44 ), + .combout(\Kd_Out[12]~45_combout ), + .cout(\Kd_Out[12]~46 )); +// synopsys translate_off +defparam \Kd_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Kd_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N5 +dffeas \Kd_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[12]~45_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[12] .is_wysiwyg = "true"; +defparam \Kd_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N6 +cycloneive_lcell_comb \Kd_Out[13]~47 ( +// Equation(s): +// \Kd_Out[13]~47_combout = (Kd_Out[13] & ((\Kd_Out[12]~46 ) # (GND))) # (!Kd_Out[13] & (!\Kd_Out[12]~46 )) +// \Kd_Out[13]~48 = CARRY((Kd_Out[13]) # (!\Kd_Out[12]~46 )) + + .dataa(Kd_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[12]~46 ), + .combout(\Kd_Out[13]~47_combout ), + .cout(\Kd_Out[13]~48 )); +// synopsys translate_off +defparam \Kd_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Kd_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N7 +dffeas \Kd_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[13]~47_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[13] .is_wysiwyg = "true"; +defparam \Kd_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N8 +cycloneive_lcell_comb \Kd_Out[14]~49 ( +// Equation(s): +// \Kd_Out[14]~49_combout = (Kd_Out[14] & (!\Kd_Out[13]~48 & VCC)) # (!Kd_Out[14] & (\Kd_Out[13]~48 $ (GND))) +// \Kd_Out[14]~50 = CARRY((!Kd_Out[14] & !\Kd_Out[13]~48 )) + + .dataa(gnd), + .datab(Kd_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[13]~48 ), + .combout(\Kd_Out[14]~49_combout ), + .cout(\Kd_Out[14]~50 )); +// synopsys translate_off +defparam \Kd_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Kd_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N6 +cycloneive_lcell_comb \Kd_Out[14]~feeder ( +// Equation(s): +// \Kd_Out[14]~feeder_combout = \Kd_Out[14]~49_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[14]~49_combout ), + .cin(gnd), + .combout(\Kd_Out[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[14]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N7 +dffeas \Kd_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[14]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[14] .is_wysiwyg = "true"; +defparam \Kd_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N10 +cycloneive_lcell_comb \Kd_Out[15]~51 ( +// Equation(s): +// \Kd_Out[15]~51_combout = (Kd_Out[15] & ((\Kd_Out[14]~50 ) # (GND))) # (!Kd_Out[15] & (!\Kd_Out[14]~50 )) +// \Kd_Out[15]~52 = CARRY((Kd_Out[15]) # (!\Kd_Out[14]~50 )) + + .dataa(Kd_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[14]~50 ), + .combout(\Kd_Out[15]~51_combout ), + .cout(\Kd_Out[15]~52 )); +// synopsys translate_off +defparam \Kd_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Kd_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N4 +cycloneive_lcell_comb \Kd_Out[15]~feeder ( +// Equation(s): +// \Kd_Out[15]~feeder_combout = \Kd_Out[15]~51_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[15]~51_combout ), + .cin(gnd), + .combout(\Kd_Out[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[15]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N5 +dffeas \Kd_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[15]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[15] .is_wysiwyg = "true"; +defparam \Kd_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N12 +cycloneive_lcell_comb \Kd_Out[16]~53 ( +// Equation(s): +// \Kd_Out[16]~53_combout = (Kd_Out[16] & (!\Kd_Out[15]~52 & VCC)) # (!Kd_Out[16] & (\Kd_Out[15]~52 $ (GND))) +// \Kd_Out[16]~54 = CARRY((!Kd_Out[16] & !\Kd_Out[15]~52 )) + + .dataa(Kd_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[15]~52 ), + .combout(\Kd_Out[16]~53_combout ), + .cout(\Kd_Out[16]~54 )); +// synopsys translate_off +defparam \Kd_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Kd_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y13_N13 +dffeas \Kd_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[16]~53_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[16] .is_wysiwyg = "true"; +defparam \Kd_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N14 +cycloneive_lcell_comb \Kd_Out[17]~55 ( +// Equation(s): +// \Kd_Out[17]~55_combout = (Kd_Out[17] & ((\Kd_Out[16]~54 ) # (GND))) # (!Kd_Out[17] & (!\Kd_Out[16]~54 )) +// \Kd_Out[17]~56 = CARRY((Kd_Out[17]) # (!\Kd_Out[16]~54 )) + + .dataa(Kd_Out[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[16]~54 ), + .combout(\Kd_Out[17]~55_combout ), + .cout(\Kd_Out[17]~56 )); +// synopsys translate_off +defparam \Kd_Out[17]~55 .lut_mask = 16'hA5AF; +defparam \Kd_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N10 +cycloneive_lcell_comb \Kd_Out[17]~feeder ( +// Equation(s): +// \Kd_Out[17]~feeder_combout = \Kd_Out[17]~55_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[17]~55_combout ), + .cin(gnd), + .combout(\Kd_Out[17]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[17]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[17]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N11 +dffeas \Kd_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[17]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[17] .is_wysiwyg = "true"; +defparam \Kd_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N16 +cycloneive_lcell_comb \Kd_Out[18]~57 ( +// Equation(s): +// \Kd_Out[18]~57_combout = (Kd_Out[18] & (!\Kd_Out[17]~56 & VCC)) # (!Kd_Out[18] & (\Kd_Out[17]~56 $ (GND))) +// \Kd_Out[18]~58 = CARRY((!Kd_Out[18] & !\Kd_Out[17]~56 )) + + .dataa(gnd), + .datab(Kd_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[17]~56 ), + .combout(\Kd_Out[18]~57_combout ), + .cout(\Kd_Out[18]~58 )); +// synopsys translate_off +defparam \Kd_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Kd_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N8 +cycloneive_lcell_comb \Kd_Out[18]~feeder ( +// Equation(s): +// \Kd_Out[18]~feeder_combout = \Kd_Out[18]~57_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[18]~57_combout ), + .cin(gnd), + .combout(\Kd_Out[18]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[18]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[18]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N9 +dffeas \Kd_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[18]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[18] .is_wysiwyg = "true"; +defparam \Kd_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N18 +cycloneive_lcell_comb \Kd_Out[19]~59 ( +// Equation(s): +// \Kd_Out[19]~59_combout = (Kd_Out[19] & ((\Kd_Out[18]~58 ) # (GND))) # (!Kd_Out[19] & (!\Kd_Out[18]~58 )) +// \Kd_Out[19]~60 = CARRY((Kd_Out[19]) # (!\Kd_Out[18]~58 )) + + .dataa(gnd), + .datab(Kd_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Kd_Out[18]~58 ), + .combout(\Kd_Out[19]~59_combout ), + .cout(\Kd_Out[19]~60 )); +// synopsys translate_off +defparam \Kd_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Kd_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y14_N2 +cycloneive_lcell_comb \Kd_Out[19]~feeder ( +// Equation(s): +// \Kd_Out[19]~feeder_combout = \Kd_Out[19]~59_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\Kd_Out[19]~59_combout ), + .cin(gnd), + .combout(\Kd_Out[19]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[19]~feeder .lut_mask = 16'hFF00; +defparam \Kd_Out[19]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y14_N3 +dffeas \Kd_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[19]~feeder_combout ), + .asdata(\Mult2|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[19] .is_wysiwyg = "true"; +defparam \Kd_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y13_N20 +cycloneive_lcell_comb \Kd_Out[20]~61 ( +// Equation(s): +// \Kd_Out[20]~61_combout = \Kd_Out[19]~60 $ (Kd_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[20]), + .cin(\Kd_Out[19]~60 ), + .combout(\Kd_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Kd_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Kd_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N26 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y13_N21 +dffeas \Kd_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kd_Out[20]~61_combout ), + .asdata(\~GND~combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE2[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kd_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Kd_Out[20] .is_wysiwyg = "true"; +defparam \Kd_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N30 +cycloneive_lcell_comb \Add7~20 ( +// Equation(s): +// \Add7~20_combout = (Kd_Out[20] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[20]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~20 .lut_mask = 16'h00F0; +defparam \Add7~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N12 +cycloneive_lcell_comb \Ki_Out[0]~21 ( +// Equation(s): +// \Ki_Out[0]~21_combout = Ki_Out[0] $ (GND) +// \Ki_Out[0]~22 = CARRY(!Ki_Out[0]) + + .dataa(Ki_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Ki_Out[0]~21_combout ), + .cout(\Ki_Out[0]~22 )); +// synopsys translate_off +defparam \Ki_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Ki_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y17_N22 +cycloneive_io_ibuf \Ki[0]~input ( + .i(Ki[0]), + .ibar(gnd), + .o(\Ki[0]~input_o )); +// synopsys translate_off +defparam \Ki[0]~input .bus_hold = "false"; +defparam \Ki[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N1 +cycloneive_io_ibuf \Ki[1]~input ( + .i(Ki[1]), + .ibar(gnd), + .o(\Ki[1]~input_o )); +// synopsys translate_off +defparam \Ki[1]~input .bus_hold = "false"; +defparam \Ki[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N22 +cycloneive_io_ibuf \Ki[2]~input ( + .i(Ki[2]), + .ibar(gnd), + .o(\Ki[2]~input_o )); +// synopsys translate_off +defparam \Ki[2]~input .bus_hold = "false"; +defparam \Ki[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N15 +cycloneive_io_ibuf \Ki[3]~input ( + .i(Ki[3]), + .ibar(gnd), + .o(\Ki[3]~input_o )); +// synopsys translate_off +defparam \Ki[3]~input .bus_hold = "false"; +defparam \Ki[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N15 +cycloneive_io_ibuf \Ki[4]~input ( + .i(Ki[4]), + .ibar(gnd), + .o(\Ki[4]~input_o )); +// synopsys translate_off +defparam \Ki[4]~input .bus_hold = "false"; +defparam \Ki[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y11_N8 +cycloneive_io_ibuf \Ki[5]~input ( + .i(Ki[5]), + .ibar(gnd), + .o(\Ki[5]~input_o )); +// synopsys translate_off +defparam \Ki[5]~input .bus_hold = "false"; +defparam \Ki[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N1 +cycloneive_io_ibuf \Ki[6]~input ( + .i(Ki[6]), + .ibar(gnd), + .o(\Ki[6]~input_o )); +// synopsys translate_off +defparam \Ki[6]~input .bus_hold = "false"; +defparam \Ki[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N8 +cycloneive_io_ibuf \Ki[7]~input ( + .i(Ki[7]), + .ibar(gnd), + .o(\Ki[7]~input_o )); +// synopsys translate_off +defparam \Ki[7]~input .bus_hold = "false"; +defparam \Ki[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y17_N0 +cycloneive_mac_mult \Mult1|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({EE1[11],EE1[10],EE1[9],EE1[8],EE1[7],EE1[6],EE1[5],EE1[4],EE1[3],EE1[2],EE1[1],EE1[0],gnd,gnd,gnd,gnd,gnd,gnd}), + .datab({\Ki[7]~input_o ,\Ki[6]~input_o ,\Ki[5]~input_o ,\Ki[4]~input_o ,\Ki[3]~input_o ,\Ki[2]~input_o ,\Ki[1]~input_o ,\Ki[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult1|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult1|auto_generated|mac_mult1 .dataa_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult1|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult1|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult1|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y17_N2 +cycloneive_mac_out \Mult1|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult1|auto_generated|mac_mult1~DATAOUT19 ,\Mult1|auto_generated|mac_mult1~DATAOUT18 ,\Mult1|auto_generated|mac_mult1~DATAOUT17 ,\Mult1|auto_generated|mac_mult1~DATAOUT16 ,\Mult1|auto_generated|mac_mult1~DATAOUT15 ,\Mult1|auto_generated|mac_mult1~DATAOUT14 , +\Mult1|auto_generated|mac_mult1~DATAOUT13 ,\Mult1|auto_generated|mac_mult1~DATAOUT12 ,\Mult1|auto_generated|mac_mult1~DATAOUT11 ,\Mult1|auto_generated|mac_mult1~DATAOUT10 ,\Mult1|auto_generated|mac_mult1~DATAOUT9 ,\Mult1|auto_generated|mac_mult1~DATAOUT8 , +\Mult1|auto_generated|mac_mult1~DATAOUT7 ,\Mult1|auto_generated|mac_mult1~DATAOUT6 ,\Mult1|auto_generated|mac_mult1~DATAOUT5 ,\Mult1|auto_generated|mac_mult1~DATAOUT4 ,\Mult1|auto_generated|mac_mult1~DATAOUT3 ,\Mult1|auto_generated|mac_mult1~DATAOUT2 , +\Mult1|auto_generated|mac_mult1~DATAOUT1 ,\Mult1|auto_generated|mac_mult1~dataout ,\Mult1|auto_generated|mac_mult1~15 ,\Mult1|auto_generated|mac_mult1~14 ,\Mult1|auto_generated|mac_mult1~13 ,\Mult1|auto_generated|mac_mult1~12 ,\Mult1|auto_generated|mac_mult1~11 , +\Mult1|auto_generated|mac_mult1~10 ,\Mult1|auto_generated|mac_mult1~9 ,\Mult1|auto_generated|mac_mult1~8 ,\Mult1|auto_generated|mac_mult1~7 ,\Mult1|auto_generated|mac_mult1~6 ,\Mult1|auto_generated|mac_mult1~5 ,\Mult1|auto_generated|mac_mult1~4 , +\Mult1|auto_generated|mac_mult1~3 ,\Mult1|auto_generated|mac_mult1~2 ,\Mult1|auto_generated|mac_mult1~1 ,\Mult1|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult1|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult1|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult1|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y18_N13 +dffeas \Ki_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[0]~21_combout ), + .asdata(\Mult1|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[0] .is_wysiwyg = "true"; +defparam \Ki_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N14 +cycloneive_lcell_comb \Ki_Out[1]~23 ( +// Equation(s): +// \Ki_Out[1]~23_combout = (Ki_Out[1] & ((\Ki_Out[0]~22 ) # (GND))) # (!Ki_Out[1] & (!\Ki_Out[0]~22 )) +// \Ki_Out[1]~24 = CARRY((Ki_Out[1]) # (!\Ki_Out[0]~22 )) + + .dataa(gnd), + .datab(Ki_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[0]~22 ), + .combout(\Ki_Out[1]~23_combout ), + .cout(\Ki_Out[1]~24 )); +// synopsys translate_off +defparam \Ki_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Ki_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N15 +dffeas \Ki_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[1]~23_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[1] .is_wysiwyg = "true"; +defparam \Ki_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N16 +cycloneive_lcell_comb \Ki_Out[2]~25 ( +// Equation(s): +// \Ki_Out[2]~25_combout = (Ki_Out[2] & (!\Ki_Out[1]~24 & VCC)) # (!Ki_Out[2] & (\Ki_Out[1]~24 $ (GND))) +// \Ki_Out[2]~26 = CARRY((!Ki_Out[2] & !\Ki_Out[1]~24 )) + + .dataa(gnd), + .datab(Ki_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[1]~24 ), + .combout(\Ki_Out[2]~25_combout ), + .cout(\Ki_Out[2]~26 )); +// synopsys translate_off +defparam \Ki_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Ki_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N17 +dffeas \Ki_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[2]~25_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[2] .is_wysiwyg = "true"; +defparam \Ki_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N18 +cycloneive_lcell_comb \Ki_Out[3]~27 ( +// Equation(s): +// \Ki_Out[3]~27_combout = (Ki_Out[3] & ((\Ki_Out[2]~26 ) # (GND))) # (!Ki_Out[3] & (!\Ki_Out[2]~26 )) +// \Ki_Out[3]~28 = CARRY((Ki_Out[3]) # (!\Ki_Out[2]~26 )) + + .dataa(gnd), + .datab(Ki_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[2]~26 ), + .combout(\Ki_Out[3]~27_combout ), + .cout(\Ki_Out[3]~28 )); +// synopsys translate_off +defparam \Ki_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Ki_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N19 +dffeas \Ki_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[3]~27_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[3] .is_wysiwyg = "true"; +defparam \Ki_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N20 +cycloneive_lcell_comb \Ki_Out[4]~29 ( +// Equation(s): +// \Ki_Out[4]~29_combout = (Ki_Out[4] & (!\Ki_Out[3]~28 & VCC)) # (!Ki_Out[4] & (\Ki_Out[3]~28 $ (GND))) +// \Ki_Out[4]~30 = CARRY((!Ki_Out[4] & !\Ki_Out[3]~28 )) + + .dataa(gnd), + .datab(Ki_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[3]~28 ), + .combout(\Ki_Out[4]~29_combout ), + .cout(\Ki_Out[4]~30 )); +// synopsys translate_off +defparam \Ki_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Ki_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N21 +dffeas \Ki_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[4]~29_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[4] .is_wysiwyg = "true"; +defparam \Ki_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N22 +cycloneive_lcell_comb \Ki_Out[5]~31 ( +// Equation(s): +// \Ki_Out[5]~31_combout = (Ki_Out[5] & ((\Ki_Out[4]~30 ) # (GND))) # (!Ki_Out[5] & (!\Ki_Out[4]~30 )) +// \Ki_Out[5]~32 = CARRY((Ki_Out[5]) # (!\Ki_Out[4]~30 )) + + .dataa(Ki_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[4]~30 ), + .combout(\Ki_Out[5]~31_combout ), + .cout(\Ki_Out[5]~32 )); +// synopsys translate_off +defparam \Ki_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Ki_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N23 +dffeas \Ki_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[5]~31_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[5] .is_wysiwyg = "true"; +defparam \Ki_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N24 +cycloneive_lcell_comb \Ki_Out[6]~33 ( +// Equation(s): +// \Ki_Out[6]~33_combout = (Ki_Out[6] & (!\Ki_Out[5]~32 & VCC)) # (!Ki_Out[6] & (\Ki_Out[5]~32 $ (GND))) +// \Ki_Out[6]~34 = CARRY((!Ki_Out[6] & !\Ki_Out[5]~32 )) + + .dataa(gnd), + .datab(Ki_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[5]~32 ), + .combout(\Ki_Out[6]~33_combout ), + .cout(\Ki_Out[6]~34 )); +// synopsys translate_off +defparam \Ki_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Ki_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N25 +dffeas \Ki_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[6]~33_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[6] .is_wysiwyg = "true"; +defparam \Ki_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N26 +cycloneive_lcell_comb \Ki_Out[7]~35 ( +// Equation(s): +// \Ki_Out[7]~35_combout = (Ki_Out[7] & ((\Ki_Out[6]~34 ) # (GND))) # (!Ki_Out[7] & (!\Ki_Out[6]~34 )) +// \Ki_Out[7]~36 = CARRY((Ki_Out[7]) # (!\Ki_Out[6]~34 )) + + .dataa(Ki_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[6]~34 ), + .combout(\Ki_Out[7]~35_combout ), + .cout(\Ki_Out[7]~36 )); +// synopsys translate_off +defparam \Ki_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Ki_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N27 +dffeas \Ki_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[7]~35_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[7] .is_wysiwyg = "true"; +defparam \Ki_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N28 +cycloneive_lcell_comb \Ki_Out[8]~37 ( +// Equation(s): +// \Ki_Out[8]~37_combout = (Ki_Out[8] & (!\Ki_Out[7]~36 & VCC)) # (!Ki_Out[8] & (\Ki_Out[7]~36 $ (GND))) +// \Ki_Out[8]~38 = CARRY((!Ki_Out[8] & !\Ki_Out[7]~36 )) + + .dataa(gnd), + .datab(Ki_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[7]~36 ), + .combout(\Ki_Out[8]~37_combout ), + .cout(\Ki_Out[8]~38 )); +// synopsys translate_off +defparam \Ki_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Ki_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N29 +dffeas \Ki_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[8]~37_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[8] .is_wysiwyg = "true"; +defparam \Ki_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N30 +cycloneive_lcell_comb \Ki_Out[9]~39 ( +// Equation(s): +// \Ki_Out[9]~39_combout = (Ki_Out[9] & ((\Ki_Out[8]~38 ) # (GND))) # (!Ki_Out[9] & (!\Ki_Out[8]~38 )) +// \Ki_Out[9]~40 = CARRY((Ki_Out[9]) # (!\Ki_Out[8]~38 )) + + .dataa(Ki_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[8]~38 ), + .combout(\Ki_Out[9]~39_combout ), + .cout(\Ki_Out[9]~40 )); +// synopsys translate_off +defparam \Ki_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Ki_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y18_N31 +dffeas \Ki_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[9]~39_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[9] .is_wysiwyg = "true"; +defparam \Ki_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N0 +cycloneive_lcell_comb \Ki_Out[10]~41 ( +// Equation(s): +// \Ki_Out[10]~41_combout = (Ki_Out[10] & (!\Ki_Out[9]~40 & VCC)) # (!Ki_Out[10] & (\Ki_Out[9]~40 $ (GND))) +// \Ki_Out[10]~42 = CARRY((!Ki_Out[10] & !\Ki_Out[9]~40 )) + + .dataa(gnd), + .datab(Ki_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[9]~40 ), + .combout(\Ki_Out[10]~41_combout ), + .cout(\Ki_Out[10]~42 )); +// synopsys translate_off +defparam \Ki_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Ki_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N1 +dffeas \Ki_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[10]~41_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[10] .is_wysiwyg = "true"; +defparam \Ki_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N2 +cycloneive_lcell_comb \Ki_Out[11]~43 ( +// Equation(s): +// \Ki_Out[11]~43_combout = (Ki_Out[11] & ((\Ki_Out[10]~42 ) # (GND))) # (!Ki_Out[11] & (!\Ki_Out[10]~42 )) +// \Ki_Out[11]~44 = CARRY((Ki_Out[11]) # (!\Ki_Out[10]~42 )) + + .dataa(gnd), + .datab(Ki_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[10]~42 ), + .combout(\Ki_Out[11]~43_combout ), + .cout(\Ki_Out[11]~44 )); +// synopsys translate_off +defparam \Ki_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Ki_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N3 +dffeas \Ki_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[11]~43_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[11] .is_wysiwyg = "true"; +defparam \Ki_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N4 +cycloneive_lcell_comb \Ki_Out[12]~45 ( +// Equation(s): +// \Ki_Out[12]~45_combout = (Ki_Out[12] & (!\Ki_Out[11]~44 & VCC)) # (!Ki_Out[12] & (\Ki_Out[11]~44 $ (GND))) +// \Ki_Out[12]~46 = CARRY((!Ki_Out[12] & !\Ki_Out[11]~44 )) + + .dataa(gnd), + .datab(Ki_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[11]~44 ), + .combout(\Ki_Out[12]~45_combout ), + .cout(\Ki_Out[12]~46 )); +// synopsys translate_off +defparam \Ki_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Ki_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N5 +dffeas \Ki_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[12]~45_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[12] .is_wysiwyg = "true"; +defparam \Ki_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N6 +cycloneive_lcell_comb \Ki_Out[13]~47 ( +// Equation(s): +// \Ki_Out[13]~47_combout = (Ki_Out[13] & ((\Ki_Out[12]~46 ) # (GND))) # (!Ki_Out[13] & (!\Ki_Out[12]~46 )) +// \Ki_Out[13]~48 = CARRY((Ki_Out[13]) # (!\Ki_Out[12]~46 )) + + .dataa(Ki_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[12]~46 ), + .combout(\Ki_Out[13]~47_combout ), + .cout(\Ki_Out[13]~48 )); +// synopsys translate_off +defparam \Ki_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Ki_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N7 +dffeas \Ki_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[13]~47_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[13] .is_wysiwyg = "true"; +defparam \Ki_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N8 +cycloneive_lcell_comb \Ki_Out[14]~49 ( +// Equation(s): +// \Ki_Out[14]~49_combout = (Ki_Out[14] & (!\Ki_Out[13]~48 & VCC)) # (!Ki_Out[14] & (\Ki_Out[13]~48 $ (GND))) +// \Ki_Out[14]~50 = CARRY((!Ki_Out[14] & !\Ki_Out[13]~48 )) + + .dataa(gnd), + .datab(Ki_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[13]~48 ), + .combout(\Ki_Out[14]~49_combout ), + .cout(\Ki_Out[14]~50 )); +// synopsys translate_off +defparam \Ki_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Ki_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N9 +dffeas \Ki_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[14]~49_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[14] .is_wysiwyg = "true"; +defparam \Ki_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N10 +cycloneive_lcell_comb \Ki_Out[15]~51 ( +// Equation(s): +// \Ki_Out[15]~51_combout = (Ki_Out[15] & ((\Ki_Out[14]~50 ) # (GND))) # (!Ki_Out[15] & (!\Ki_Out[14]~50 )) +// \Ki_Out[15]~52 = CARRY((Ki_Out[15]) # (!\Ki_Out[14]~50 )) + + .dataa(Ki_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[14]~50 ), + .combout(\Ki_Out[15]~51_combout ), + .cout(\Ki_Out[15]~52 )); +// synopsys translate_off +defparam \Ki_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Ki_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N11 +dffeas \Ki_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[15]~51_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[15] .is_wysiwyg = "true"; +defparam \Ki_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N12 +cycloneive_lcell_comb \Ki_Out[16]~53 ( +// Equation(s): +// \Ki_Out[16]~53_combout = (Ki_Out[16] & (!\Ki_Out[15]~52 & VCC)) # (!Ki_Out[16] & (\Ki_Out[15]~52 $ (GND))) +// \Ki_Out[16]~54 = CARRY((!Ki_Out[16] & !\Ki_Out[15]~52 )) + + .dataa(Ki_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[15]~52 ), + .combout(\Ki_Out[16]~53_combout ), + .cout(\Ki_Out[16]~54 )); +// synopsys translate_off +defparam \Ki_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Ki_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N13 +dffeas \Ki_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[16]~53_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[16] .is_wysiwyg = "true"; +defparam \Ki_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N14 +cycloneive_lcell_comb \Ki_Out[17]~55 ( +// Equation(s): +// \Ki_Out[17]~55_combout = (Ki_Out[17] & ((\Ki_Out[16]~54 ) # (GND))) # (!Ki_Out[17] & (!\Ki_Out[16]~54 )) +// \Ki_Out[17]~56 = CARRY((Ki_Out[17]) # (!\Ki_Out[16]~54 )) + + .dataa(gnd), + .datab(Ki_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[16]~54 ), + .combout(\Ki_Out[17]~55_combout ), + .cout(\Ki_Out[17]~56 )); +// synopsys translate_off +defparam \Ki_Out[17]~55 .lut_mask = 16'hC3CF; +defparam \Ki_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N15 +dffeas \Ki_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[17]~55_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[17] .is_wysiwyg = "true"; +defparam \Ki_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N16 +cycloneive_lcell_comb \Ki_Out[18]~57 ( +// Equation(s): +// \Ki_Out[18]~57_combout = (Ki_Out[18] & (!\Ki_Out[17]~56 & VCC)) # (!Ki_Out[18] & (\Ki_Out[17]~56 $ (GND))) +// \Ki_Out[18]~58 = CARRY((!Ki_Out[18] & !\Ki_Out[17]~56 )) + + .dataa(gnd), + .datab(Ki_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[17]~56 ), + .combout(\Ki_Out[18]~57_combout ), + .cout(\Ki_Out[18]~58 )); +// synopsys translate_off +defparam \Ki_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Ki_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N17 +dffeas \Ki_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[18]~57_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[18] .is_wysiwyg = "true"; +defparam \Ki_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N18 +cycloneive_lcell_comb \Ki_Out[19]~59 ( +// Equation(s): +// \Ki_Out[19]~59_combout = (Ki_Out[19] & ((\Ki_Out[18]~58 ) # (GND))) # (!Ki_Out[19] & (!\Ki_Out[18]~58 )) +// \Ki_Out[19]~60 = CARRY((Ki_Out[19]) # (!\Ki_Out[18]~58 )) + + .dataa(gnd), + .datab(Ki_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Ki_Out[18]~58 ), + .combout(\Ki_Out[19]~59_combout ), + .cout(\Ki_Out[19]~60 )); +// synopsys translate_off +defparam \Ki_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Ki_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N19 +dffeas \Ki_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[19]~59_combout ), + .asdata(\Mult1|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[19] .is_wysiwyg = "true"; +defparam \Ki_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y17_N20 +cycloneive_lcell_comb \Ki_Out[20]~61 ( +// Equation(s): +// \Ki_Out[20]~61_combout = \Ki_Out[19]~60 $ (Ki_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Ki_Out[20]), + .cin(\Ki_Out[19]~60 ), + .combout(\Ki_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Ki_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Ki_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y17_N21 +dffeas \Ki_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Ki_Out[20]~61_combout ), + .asdata(\~GND~combout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!EE1[13]), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Ki_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Ki_Out[20] .is_wysiwyg = "true"; +defparam \Ki_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N12 +cycloneive_lcell_comb \Kp_Out[0]~21 ( +// Equation(s): +// \Kp_Out[0]~21_combout = Kp_Out[0] $ (GND) +// \Kp_Out[0]~22 = CARRY(!Kp_Out[0]) + + .dataa(Kp_Out[0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Kp_Out[0]~21_combout ), + .cout(\Kp_Out[0]~22 )); +// synopsys translate_off +defparam \Kp_Out[0]~21 .lut_mask = 16'hAA55; +defparam \Kp_Out[0]~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \Kp[0]~input ( + .i(Kp[0]), + .ibar(gnd), + .o(\Kp[0]~input_o )); +// synopsys translate_off +defparam \Kp[0]~input .bus_hold = "false"; +defparam \Kp[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N22 +cycloneive_io_ibuf \Kp[1]~input ( + .i(Kp[1]), + .ibar(gnd), + .o(\Kp[1]~input_o )); +// synopsys translate_off +defparam \Kp[1]~input .bus_hold = "false"; +defparam \Kp[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N22 +cycloneive_io_ibuf \Kp[2]~input ( + .i(Kp[2]), + .ibar(gnd), + .o(\Kp[2]~input_o )); +// synopsys translate_off +defparam \Kp[2]~input .bus_hold = "false"; +defparam \Kp[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N22 +cycloneive_io_ibuf \Kp[3]~input ( + .i(Kp[3]), + .ibar(gnd), + .o(\Kp[3]~input_o )); +// synopsys translate_off +defparam \Kp[3]~input .bus_hold = "false"; +defparam \Kp[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N15 +cycloneive_io_ibuf \Kp[4]~input ( + .i(Kp[4]), + .ibar(gnd), + .o(\Kp[4]~input_o )); +// synopsys translate_off +defparam \Kp[4]~input .bus_hold = "false"; +defparam \Kp[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N15 +cycloneive_io_ibuf \Kp[5]~input ( + .i(Kp[5]), + .ibar(gnd), + .o(\Kp[5]~input_o )); +// synopsys translate_off +defparam \Kp[5]~input .bus_hold = "false"; +defparam \Kp[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N1 +cycloneive_io_ibuf \Kp[6]~input ( + .i(Kp[6]), + .ibar(gnd), + .o(\Kp[6]~input_o )); +// synopsys translate_off +defparam \Kp[6]~input .bus_hold = "false"; +defparam \Kp[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N22 +cycloneive_io_ibuf \Kp[7]~input ( + .i(Kp[7]), + .ibar(gnd), + .o(\Kp[7]~input_o )); +// synopsys translate_off +defparam \Kp[7]~input .bus_hold = "false"; +defparam \Kp[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: DSPMULT_X20_Y18_N0 +cycloneive_mac_mult \Mult0|auto_generated|mac_mult1 ( + .signa(gnd), + .signb(gnd), + .clk(\clk~inputclkctrl_outclk ), + .aclr(!\rst_n~inputclkctrl_outclk ), + .ena(\Clk_Ctrl~q ), + .dataa({\EE0[13]~42_combout ,\EE0[12]~40_combout ,\EE0[11]~38_combout ,\EE0[10]~36_combout ,\EE0[9]~34_combout ,\EE0[8]~32_combout ,\EE0[7]~30_combout ,\EE0[6]~28_combout ,\EE0[5]~26_combout ,\EE0[4]~24_combout ,\EE0[3]~22_combout ,\EE0[2]~20_combout ,\EE0[1]~18_combout , +\EE0[0]~16_combout ,gnd,gnd,gnd,gnd}), + .datab({\Kp[7]~input_o ,\Kp[6]~input_o ,\Kp[5]~input_o ,\Kp[4]~input_o ,\Kp[3]~input_o ,\Kp[2]~input_o ,\Kp[1]~input_o ,\Kp[0]~input_o ,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd}), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult0|auto_generated|mac_mult1_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult0|auto_generated|mac_mult1 .dataa_clock = "0"; +defparam \Mult0|auto_generated|mac_mult1 .dataa_width = 18; +defparam \Mult0|auto_generated|mac_mult1 .datab_clock = "none"; +defparam \Mult0|auto_generated|mac_mult1 .datab_width = 18; +defparam \Mult0|auto_generated|mac_mult1 .signa_clock = "none"; +defparam \Mult0|auto_generated|mac_mult1 .signb_clock = "none"; +// synopsys translate_on + +// Location: DSPOUT_X20_Y18_N2 +cycloneive_mac_out \Mult0|auto_generated|mac_out2 ( + .clk(gnd), + .aclr(gnd), + .ena(vcc), + .dataa({\Mult0|auto_generated|mac_mult1~DATAOUT21 ,\Mult0|auto_generated|mac_mult1~DATAOUT20 ,\Mult0|auto_generated|mac_mult1~DATAOUT19 ,\Mult0|auto_generated|mac_mult1~DATAOUT18 ,\Mult0|auto_generated|mac_mult1~DATAOUT17 ,\Mult0|auto_generated|mac_mult1~DATAOUT16 , +\Mult0|auto_generated|mac_mult1~DATAOUT15 ,\Mult0|auto_generated|mac_mult1~DATAOUT14 ,\Mult0|auto_generated|mac_mult1~DATAOUT13 ,\Mult0|auto_generated|mac_mult1~DATAOUT12 ,\Mult0|auto_generated|mac_mult1~DATAOUT11 ,\Mult0|auto_generated|mac_mult1~DATAOUT10 , +\Mult0|auto_generated|mac_mult1~DATAOUT9 ,\Mult0|auto_generated|mac_mult1~DATAOUT8 ,\Mult0|auto_generated|mac_mult1~DATAOUT7 ,\Mult0|auto_generated|mac_mult1~DATAOUT6 ,\Mult0|auto_generated|mac_mult1~DATAOUT5 ,\Mult0|auto_generated|mac_mult1~DATAOUT4 , +\Mult0|auto_generated|mac_mult1~DATAOUT3 ,\Mult0|auto_generated|mac_mult1~DATAOUT2 ,\Mult0|auto_generated|mac_mult1~DATAOUT1 ,\Mult0|auto_generated|mac_mult1~dataout ,\Mult0|auto_generated|mac_mult1~13 ,\Mult0|auto_generated|mac_mult1~12 , +\Mult0|auto_generated|mac_mult1~11 ,\Mult0|auto_generated|mac_mult1~10 ,\Mult0|auto_generated|mac_mult1~9 ,\Mult0|auto_generated|mac_mult1~8 ,\Mult0|auto_generated|mac_mult1~7 ,\Mult0|auto_generated|mac_mult1~6 ,\Mult0|auto_generated|mac_mult1~5 , +\Mult0|auto_generated|mac_mult1~4 ,\Mult0|auto_generated|mac_mult1~3 ,\Mult0|auto_generated|mac_mult1~2 ,\Mult0|auto_generated|mac_mult1~1 ,\Mult0|auto_generated|mac_mult1~0 }), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\Mult0|auto_generated|mac_out2_DATAOUT_bus )); +// synopsys translate_off +defparam \Mult0|auto_generated|mac_out2 .dataa_width = 36; +defparam \Mult0|auto_generated|mac_out2 .output_clock = "none"; +// synopsys translate_on + +// Location: FF_X19_Y16_N13 +dffeas \Kp_Out[0] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[0]~21_combout ), + .asdata(\Mult0|auto_generated|mac_out2~dataout ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[0]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[0] .is_wysiwyg = "true"; +defparam \Kp_Out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N14 +cycloneive_lcell_comb \Kp_Out[1]~23 ( +// Equation(s): +// \Kp_Out[1]~23_combout = (Kp_Out[1] & ((\Kp_Out[0]~22 ) # (GND))) # (!Kp_Out[1] & (!\Kp_Out[0]~22 )) +// \Kp_Out[1]~24 = CARRY((Kp_Out[1]) # (!\Kp_Out[0]~22 )) + + .dataa(gnd), + .datab(Kp_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[0]~22 ), + .combout(\Kp_Out[1]~23_combout ), + .cout(\Kp_Out[1]~24 )); +// synopsys translate_off +defparam \Kp_Out[1]~23 .lut_mask = 16'hC3CF; +defparam \Kp_Out[1]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N15 +dffeas \Kp_Out[1] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[1]~23_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT1 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[1]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[1] .is_wysiwyg = "true"; +defparam \Kp_Out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N16 +cycloneive_lcell_comb \Kp_Out[2]~25 ( +// Equation(s): +// \Kp_Out[2]~25_combout = (Kp_Out[2] & (!\Kp_Out[1]~24 & VCC)) # (!Kp_Out[2] & (\Kp_Out[1]~24 $ (GND))) +// \Kp_Out[2]~26 = CARRY((!Kp_Out[2] & !\Kp_Out[1]~24 )) + + .dataa(gnd), + .datab(Kp_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[1]~24 ), + .combout(\Kp_Out[2]~25_combout ), + .cout(\Kp_Out[2]~26 )); +// synopsys translate_off +defparam \Kp_Out[2]~25 .lut_mask = 16'h3C03; +defparam \Kp_Out[2]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N17 +dffeas \Kp_Out[2] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[2]~25_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT2 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[2]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[2] .is_wysiwyg = "true"; +defparam \Kp_Out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N18 +cycloneive_lcell_comb \Kp_Out[3]~27 ( +// Equation(s): +// \Kp_Out[3]~27_combout = (Kp_Out[3] & ((\Kp_Out[2]~26 ) # (GND))) # (!Kp_Out[3] & (!\Kp_Out[2]~26 )) +// \Kp_Out[3]~28 = CARRY((Kp_Out[3]) # (!\Kp_Out[2]~26 )) + + .dataa(gnd), + .datab(Kp_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[2]~26 ), + .combout(\Kp_Out[3]~27_combout ), + .cout(\Kp_Out[3]~28 )); +// synopsys translate_off +defparam \Kp_Out[3]~27 .lut_mask = 16'hC3CF; +defparam \Kp_Out[3]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N19 +dffeas \Kp_Out[3] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[3]~27_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT3 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[3]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[3] .is_wysiwyg = "true"; +defparam \Kp_Out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N20 +cycloneive_lcell_comb \Kp_Out[4]~29 ( +// Equation(s): +// \Kp_Out[4]~29_combout = (Kp_Out[4] & (!\Kp_Out[3]~28 & VCC)) # (!Kp_Out[4] & (\Kp_Out[3]~28 $ (GND))) +// \Kp_Out[4]~30 = CARRY((!Kp_Out[4] & !\Kp_Out[3]~28 )) + + .dataa(gnd), + .datab(Kp_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[3]~28 ), + .combout(\Kp_Out[4]~29_combout ), + .cout(\Kp_Out[4]~30 )); +// synopsys translate_off +defparam \Kp_Out[4]~29 .lut_mask = 16'h3C03; +defparam \Kp_Out[4]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N21 +dffeas \Kp_Out[4] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[4]~29_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT4 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[4]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[4] .is_wysiwyg = "true"; +defparam \Kp_Out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N22 +cycloneive_lcell_comb \Kp_Out[5]~31 ( +// Equation(s): +// \Kp_Out[5]~31_combout = (Kp_Out[5] & ((\Kp_Out[4]~30 ) # (GND))) # (!Kp_Out[5] & (!\Kp_Out[4]~30 )) +// \Kp_Out[5]~32 = CARRY((Kp_Out[5]) # (!\Kp_Out[4]~30 )) + + .dataa(Kp_Out[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[4]~30 ), + .combout(\Kp_Out[5]~31_combout ), + .cout(\Kp_Out[5]~32 )); +// synopsys translate_off +defparam \Kp_Out[5]~31 .lut_mask = 16'hA5AF; +defparam \Kp_Out[5]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N23 +dffeas \Kp_Out[5] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[5]~31_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT5 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[5]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[5] .is_wysiwyg = "true"; +defparam \Kp_Out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N24 +cycloneive_lcell_comb \Kp_Out[6]~33 ( +// Equation(s): +// \Kp_Out[6]~33_combout = (Kp_Out[6] & (!\Kp_Out[5]~32 & VCC)) # (!Kp_Out[6] & (\Kp_Out[5]~32 $ (GND))) +// \Kp_Out[6]~34 = CARRY((!Kp_Out[6] & !\Kp_Out[5]~32 )) + + .dataa(gnd), + .datab(Kp_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[5]~32 ), + .combout(\Kp_Out[6]~33_combout ), + .cout(\Kp_Out[6]~34 )); +// synopsys translate_off +defparam \Kp_Out[6]~33 .lut_mask = 16'h3C03; +defparam \Kp_Out[6]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N25 +dffeas \Kp_Out[6] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[6]~33_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT6 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[6]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[6] .is_wysiwyg = "true"; +defparam \Kp_Out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N26 +cycloneive_lcell_comb \Kp_Out[7]~35 ( +// Equation(s): +// \Kp_Out[7]~35_combout = (Kp_Out[7] & ((\Kp_Out[6]~34 ) # (GND))) # (!Kp_Out[7] & (!\Kp_Out[6]~34 )) +// \Kp_Out[7]~36 = CARRY((Kp_Out[7]) # (!\Kp_Out[6]~34 )) + + .dataa(Kp_Out[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[6]~34 ), + .combout(\Kp_Out[7]~35_combout ), + .cout(\Kp_Out[7]~36 )); +// synopsys translate_off +defparam \Kp_Out[7]~35 .lut_mask = 16'hA5AF; +defparam \Kp_Out[7]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N27 +dffeas \Kp_Out[7] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[7]~35_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT7 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[7]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[7] .is_wysiwyg = "true"; +defparam \Kp_Out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N28 +cycloneive_lcell_comb \Kp_Out[8]~37 ( +// Equation(s): +// \Kp_Out[8]~37_combout = (Kp_Out[8] & (!\Kp_Out[7]~36 & VCC)) # (!Kp_Out[8] & (\Kp_Out[7]~36 $ (GND))) +// \Kp_Out[8]~38 = CARRY((!Kp_Out[8] & !\Kp_Out[7]~36 )) + + .dataa(gnd), + .datab(Kp_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[7]~36 ), + .combout(\Kp_Out[8]~37_combout ), + .cout(\Kp_Out[8]~38 )); +// synopsys translate_off +defparam \Kp_Out[8]~37 .lut_mask = 16'h3C03; +defparam \Kp_Out[8]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N29 +dffeas \Kp_Out[8] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[8]~37_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT8 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[8]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[8] .is_wysiwyg = "true"; +defparam \Kp_Out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y16_N30 +cycloneive_lcell_comb \Kp_Out[9]~39 ( +// Equation(s): +// \Kp_Out[9]~39_combout = (Kp_Out[9] & ((\Kp_Out[8]~38 ) # (GND))) # (!Kp_Out[9] & (!\Kp_Out[8]~38 )) +// \Kp_Out[9]~40 = CARRY((Kp_Out[9]) # (!\Kp_Out[8]~38 )) + + .dataa(Kp_Out[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[8]~38 ), + .combout(\Kp_Out[9]~39_combout ), + .cout(\Kp_Out[9]~40 )); +// synopsys translate_off +defparam \Kp_Out[9]~39 .lut_mask = 16'hA5AF; +defparam \Kp_Out[9]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y16_N31 +dffeas \Kp_Out[9] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[9]~39_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT9 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[9]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[9] .is_wysiwyg = "true"; +defparam \Kp_Out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N0 +cycloneive_lcell_comb \Kp_Out[10]~41 ( +// Equation(s): +// \Kp_Out[10]~41_combout = (Kp_Out[10] & (!\Kp_Out[9]~40 & VCC)) # (!Kp_Out[10] & (\Kp_Out[9]~40 $ (GND))) +// \Kp_Out[10]~42 = CARRY((!Kp_Out[10] & !\Kp_Out[9]~40 )) + + .dataa(gnd), + .datab(Kp_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[9]~40 ), + .combout(\Kp_Out[10]~41_combout ), + .cout(\Kp_Out[10]~42 )); +// synopsys translate_off +defparam \Kp_Out[10]~41 .lut_mask = 16'h3C03; +defparam \Kp_Out[10]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N1 +dffeas \Kp_Out[10] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[10]~41_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT10 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[10]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[10] .is_wysiwyg = "true"; +defparam \Kp_Out[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N2 +cycloneive_lcell_comb \Kp_Out[11]~43 ( +// Equation(s): +// \Kp_Out[11]~43_combout = (Kp_Out[11] & ((\Kp_Out[10]~42 ) # (GND))) # (!Kp_Out[11] & (!\Kp_Out[10]~42 )) +// \Kp_Out[11]~44 = CARRY((Kp_Out[11]) # (!\Kp_Out[10]~42 )) + + .dataa(gnd), + .datab(Kp_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[10]~42 ), + .combout(\Kp_Out[11]~43_combout ), + .cout(\Kp_Out[11]~44 )); +// synopsys translate_off +defparam \Kp_Out[11]~43 .lut_mask = 16'hC3CF; +defparam \Kp_Out[11]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N3 +dffeas \Kp_Out[11] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[11]~43_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT11 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[11]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[11] .is_wysiwyg = "true"; +defparam \Kp_Out[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N4 +cycloneive_lcell_comb \Kp_Out[12]~45 ( +// Equation(s): +// \Kp_Out[12]~45_combout = (Kp_Out[12] & (!\Kp_Out[11]~44 & VCC)) # (!Kp_Out[12] & (\Kp_Out[11]~44 $ (GND))) +// \Kp_Out[12]~46 = CARRY((!Kp_Out[12] & !\Kp_Out[11]~44 )) + + .dataa(gnd), + .datab(Kp_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[11]~44 ), + .combout(\Kp_Out[12]~45_combout ), + .cout(\Kp_Out[12]~46 )); +// synopsys translate_off +defparam \Kp_Out[12]~45 .lut_mask = 16'h3C03; +defparam \Kp_Out[12]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N5 +dffeas \Kp_Out[12] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[12]~45_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT12 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[12]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[12] .is_wysiwyg = "true"; +defparam \Kp_Out[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N6 +cycloneive_lcell_comb \Kp_Out[13]~47 ( +// Equation(s): +// \Kp_Out[13]~47_combout = (Kp_Out[13] & ((\Kp_Out[12]~46 ) # (GND))) # (!Kp_Out[13] & (!\Kp_Out[12]~46 )) +// \Kp_Out[13]~48 = CARRY((Kp_Out[13]) # (!\Kp_Out[12]~46 )) + + .dataa(Kp_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[12]~46 ), + .combout(\Kp_Out[13]~47_combout ), + .cout(\Kp_Out[13]~48 )); +// synopsys translate_off +defparam \Kp_Out[13]~47 .lut_mask = 16'hA5AF; +defparam \Kp_Out[13]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N7 +dffeas \Kp_Out[13] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[13]~47_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT13 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[13]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[13] .is_wysiwyg = "true"; +defparam \Kp_Out[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N8 +cycloneive_lcell_comb \Kp_Out[14]~49 ( +// Equation(s): +// \Kp_Out[14]~49_combout = (Kp_Out[14] & (!\Kp_Out[13]~48 & VCC)) # (!Kp_Out[14] & (\Kp_Out[13]~48 $ (GND))) +// \Kp_Out[14]~50 = CARRY((!Kp_Out[14] & !\Kp_Out[13]~48 )) + + .dataa(gnd), + .datab(Kp_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[13]~48 ), + .combout(\Kp_Out[14]~49_combout ), + .cout(\Kp_Out[14]~50 )); +// synopsys translate_off +defparam \Kp_Out[14]~49 .lut_mask = 16'h3C03; +defparam \Kp_Out[14]~49 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N9 +dffeas \Kp_Out[14] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[14]~49_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT14 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[14]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[14] .is_wysiwyg = "true"; +defparam \Kp_Out[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N10 +cycloneive_lcell_comb \Kp_Out[15]~51 ( +// Equation(s): +// \Kp_Out[15]~51_combout = (Kp_Out[15] & ((\Kp_Out[14]~50 ) # (GND))) # (!Kp_Out[15] & (!\Kp_Out[14]~50 )) +// \Kp_Out[15]~52 = CARRY((Kp_Out[15]) # (!\Kp_Out[14]~50 )) + + .dataa(Kp_Out[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[14]~50 ), + .combout(\Kp_Out[15]~51_combout ), + .cout(\Kp_Out[15]~52 )); +// synopsys translate_off +defparam \Kp_Out[15]~51 .lut_mask = 16'hA5AF; +defparam \Kp_Out[15]~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N11 +dffeas \Kp_Out[15] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[15]~51_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT15 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[15]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[15] .is_wysiwyg = "true"; +defparam \Kp_Out[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N12 +cycloneive_lcell_comb \Kp_Out[16]~53 ( +// Equation(s): +// \Kp_Out[16]~53_combout = (Kp_Out[16] & (!\Kp_Out[15]~52 & VCC)) # (!Kp_Out[16] & (\Kp_Out[15]~52 $ (GND))) +// \Kp_Out[16]~54 = CARRY((!Kp_Out[16] & !\Kp_Out[15]~52 )) + + .dataa(Kp_Out[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[15]~52 ), + .combout(\Kp_Out[16]~53_combout ), + .cout(\Kp_Out[16]~54 )); +// synopsys translate_off +defparam \Kp_Out[16]~53 .lut_mask = 16'h5A05; +defparam \Kp_Out[16]~53 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N13 +dffeas \Kp_Out[16] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[16]~53_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT16 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[16]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[16] .is_wysiwyg = "true"; +defparam \Kp_Out[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N14 +cycloneive_lcell_comb \Kp_Out[17]~55 ( +// Equation(s): +// \Kp_Out[17]~55_combout = (Kp_Out[17] & ((\Kp_Out[16]~54 ) # (GND))) # (!Kp_Out[17] & (!\Kp_Out[16]~54 )) +// \Kp_Out[17]~56 = CARRY((Kp_Out[17]) # (!\Kp_Out[16]~54 )) + + .dataa(gnd), + .datab(Kp_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[16]~54 ), + .combout(\Kp_Out[17]~55_combout ), + .cout(\Kp_Out[17]~56 )); +// synopsys translate_off +defparam \Kp_Out[17]~55 .lut_mask = 16'hC3CF; +defparam \Kp_Out[17]~55 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N15 +dffeas \Kp_Out[17] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[17]~55_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT17 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[17]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[17] .is_wysiwyg = "true"; +defparam \Kp_Out[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N16 +cycloneive_lcell_comb \Kp_Out[18]~57 ( +// Equation(s): +// \Kp_Out[18]~57_combout = (Kp_Out[18] & (!\Kp_Out[17]~56 & VCC)) # (!Kp_Out[18] & (\Kp_Out[17]~56 $ (GND))) +// \Kp_Out[18]~58 = CARRY((!Kp_Out[18] & !\Kp_Out[17]~56 )) + + .dataa(gnd), + .datab(Kp_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[17]~56 ), + .combout(\Kp_Out[18]~57_combout ), + .cout(\Kp_Out[18]~58 )); +// synopsys translate_off +defparam \Kp_Out[18]~57 .lut_mask = 16'h3C03; +defparam \Kp_Out[18]~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N17 +dffeas \Kp_Out[18] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[18]~57_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT18 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[18]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[18] .is_wysiwyg = "true"; +defparam \Kp_Out[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N18 +cycloneive_lcell_comb \Kp_Out[19]~59 ( +// Equation(s): +// \Kp_Out[19]~59_combout = (Kp_Out[19] & ((\Kp_Out[18]~58 ) # (GND))) # (!Kp_Out[19] & (!\Kp_Out[18]~58 )) +// \Kp_Out[19]~60 = CARRY((Kp_Out[19]) # (!\Kp_Out[18]~58 )) + + .dataa(gnd), + .datab(Kp_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Kp_Out[18]~58 ), + .combout(\Kp_Out[19]~59_combout ), + .cout(\Kp_Out[19]~60 )); +// synopsys translate_off +defparam \Kp_Out[19]~59 .lut_mask = 16'hC3CF; +defparam \Kp_Out[19]~59 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N19 +dffeas \Kp_Out[19] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[19]~59_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT19 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[19]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[19] .is_wysiwyg = "true"; +defparam \Kp_Out[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y15_N20 +cycloneive_lcell_comb \Kp_Out[20]~61 ( +// Equation(s): +// \Kp_Out[20]~61_combout = \Kp_Out[19]~60 $ (Kp_Out[20]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(Kp_Out[20]), + .cin(\Kp_Out[19]~60 ), + .combout(\Kp_Out[20]~61_combout ), + .cout()); +// synopsys translate_off +defparam \Kp_Out[20]~61 .lut_mask = 16'h0FF0; +defparam \Kp_Out[20]~61 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X19_Y15_N21 +dffeas \Kp_Out[20] ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Kp_Out[20]~61_combout ), + .asdata(\Mult0|auto_generated|mac_out2~DATAOUT20 ), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\EE0[13]~_Duplicate_1_q ), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(Kp_Out[20]), + .prn(vcc)); +// synopsys translate_off +defparam \Kp_Out[20] .is_wysiwyg = "true"; +defparam \Kp_Out[20] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N12 +cycloneive_lcell_comb \Add5~0 ( +// Equation(s): +// \Add5~0_combout = (Kp_Out[0] & ((GND) # (!Ki_Out[0]))) # (!Kp_Out[0] & (Ki_Out[0] $ (GND))) +// \Add5~1 = CARRY((Kp_Out[0]) # (!Ki_Out[0])) + + .dataa(Kp_Out[0]), + .datab(Ki_Out[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add5~0_combout ), + .cout(\Add5~1 )); +// synopsys translate_off +defparam \Add5~0 .lut_mask = 16'h66BB; +defparam \Add5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N14 +cycloneive_lcell_comb \Add5~2 ( +// Equation(s): +// \Add5~2_combout = (Ki_Out[1] & ((Kp_Out[1] & (!\Add5~1 )) # (!Kp_Out[1] & ((\Add5~1 ) # (GND))))) # (!Ki_Out[1] & ((Kp_Out[1] & (\Add5~1 & VCC)) # (!Kp_Out[1] & (!\Add5~1 )))) +// \Add5~3 = CARRY((Ki_Out[1] & ((!\Add5~1 ) # (!Kp_Out[1]))) # (!Ki_Out[1] & (!Kp_Out[1] & !\Add5~1 ))) + + .dataa(Ki_Out[1]), + .datab(Kp_Out[1]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~1 ), + .combout(\Add5~2_combout ), + .cout(\Add5~3 )); +// synopsys translate_off +defparam \Add5~2 .lut_mask = 16'h692B; +defparam \Add5~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N16 +cycloneive_lcell_comb \Add5~4 ( +// Equation(s): +// \Add5~4_combout = ((Kp_Out[2] $ (Ki_Out[2] $ (\Add5~3 )))) # (GND) +// \Add5~5 = CARRY((Kp_Out[2] & ((!\Add5~3 ) # (!Ki_Out[2]))) # (!Kp_Out[2] & (!Ki_Out[2] & !\Add5~3 ))) + + .dataa(Kp_Out[2]), + .datab(Ki_Out[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~3 ), + .combout(\Add5~4_combout ), + .cout(\Add5~5 )); +// synopsys translate_off +defparam \Add5~4 .lut_mask = 16'h962B; +defparam \Add5~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N18 +cycloneive_lcell_comb \Add5~6 ( +// Equation(s): +// \Add5~6_combout = (Kp_Out[3] & ((Ki_Out[3] & (!\Add5~5 )) # (!Ki_Out[3] & (\Add5~5 & VCC)))) # (!Kp_Out[3] & ((Ki_Out[3] & ((\Add5~5 ) # (GND))) # (!Ki_Out[3] & (!\Add5~5 )))) +// \Add5~7 = CARRY((Kp_Out[3] & (Ki_Out[3] & !\Add5~5 )) # (!Kp_Out[3] & ((Ki_Out[3]) # (!\Add5~5 )))) + + .dataa(Kp_Out[3]), + .datab(Ki_Out[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~5 ), + .combout(\Add5~6_combout ), + .cout(\Add5~7 )); +// synopsys translate_off +defparam \Add5~6 .lut_mask = 16'h694D; +defparam \Add5~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N20 +cycloneive_lcell_comb \Add5~8 ( +// Equation(s): +// \Add5~8_combout = ((Ki_Out[4] $ (Kp_Out[4] $ (\Add5~7 )))) # (GND) +// \Add5~9 = CARRY((Ki_Out[4] & (Kp_Out[4] & !\Add5~7 )) # (!Ki_Out[4] & ((Kp_Out[4]) # (!\Add5~7 )))) + + .dataa(Ki_Out[4]), + .datab(Kp_Out[4]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~7 ), + .combout(\Add5~8_combout ), + .cout(\Add5~9 )); +// synopsys translate_off +defparam \Add5~8 .lut_mask = 16'h964D; +defparam \Add5~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N22 +cycloneive_lcell_comb \Add5~10 ( +// Equation(s): +// \Add5~10_combout = (Ki_Out[5] & ((Kp_Out[5] & (!\Add5~9 )) # (!Kp_Out[5] & ((\Add5~9 ) # (GND))))) # (!Ki_Out[5] & ((Kp_Out[5] & (\Add5~9 & VCC)) # (!Kp_Out[5] & (!\Add5~9 )))) +// \Add5~11 = CARRY((Ki_Out[5] & ((!\Add5~9 ) # (!Kp_Out[5]))) # (!Ki_Out[5] & (!Kp_Out[5] & !\Add5~9 ))) + + .dataa(Ki_Out[5]), + .datab(Kp_Out[5]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~9 ), + .combout(\Add5~10_combout ), + .cout(\Add5~11 )); +// synopsys translate_off +defparam \Add5~10 .lut_mask = 16'h692B; +defparam \Add5~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N24 +cycloneive_lcell_comb \Add5~12 ( +// Equation(s): +// \Add5~12_combout = ((Ki_Out[6] $ (Kp_Out[6] $ (\Add5~11 )))) # (GND) +// \Add5~13 = CARRY((Ki_Out[6] & (Kp_Out[6] & !\Add5~11 )) # (!Ki_Out[6] & ((Kp_Out[6]) # (!\Add5~11 )))) + + .dataa(Ki_Out[6]), + .datab(Kp_Out[6]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~11 ), + .combout(\Add5~12_combout ), + .cout(\Add5~13 )); +// synopsys translate_off +defparam \Add5~12 .lut_mask = 16'h964D; +defparam \Add5~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N26 +cycloneive_lcell_comb \Add5~14 ( +// Equation(s): +// \Add5~14_combout = (Kp_Out[7] & ((Ki_Out[7] & (!\Add5~13 )) # (!Ki_Out[7] & (\Add5~13 & VCC)))) # (!Kp_Out[7] & ((Ki_Out[7] & ((\Add5~13 ) # (GND))) # (!Ki_Out[7] & (!\Add5~13 )))) +// \Add5~15 = CARRY((Kp_Out[7] & (Ki_Out[7] & !\Add5~13 )) # (!Kp_Out[7] & ((Ki_Out[7]) # (!\Add5~13 )))) + + .dataa(Kp_Out[7]), + .datab(Ki_Out[7]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~13 ), + .combout(\Add5~14_combout ), + .cout(\Add5~15 )); +// synopsys translate_off +defparam \Add5~14 .lut_mask = 16'h694D; +defparam \Add5~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N28 +cycloneive_lcell_comb \Add5~24 ( +// Equation(s): +// \Add5~24_combout = ((Kp_Out[8] $ (Ki_Out[8] $ (\Add5~15 )))) # (GND) +// \Add5~25 = CARRY((Kp_Out[8] & ((!\Add5~15 ) # (!Ki_Out[8]))) # (!Kp_Out[8] & (!Ki_Out[8] & !\Add5~15 ))) + + .dataa(Kp_Out[8]), + .datab(Ki_Out[8]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~15 ), + .combout(\Add5~24_combout ), + .cout(\Add5~25 )); +// synopsys translate_off +defparam \Add5~24 .lut_mask = 16'h962B; +defparam \Add5~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N30 +cycloneive_lcell_comb \Add5~27 ( +// Equation(s): +// \Add5~27_combout = (Ki_Out[9] & ((Kp_Out[9] & (!\Add5~25 )) # (!Kp_Out[9] & ((\Add5~25 ) # (GND))))) # (!Ki_Out[9] & ((Kp_Out[9] & (\Add5~25 & VCC)) # (!Kp_Out[9] & (!\Add5~25 )))) +// \Add5~28 = CARRY((Ki_Out[9] & ((!\Add5~25 ) # (!Kp_Out[9]))) # (!Ki_Out[9] & (!Kp_Out[9] & !\Add5~25 ))) + + .dataa(Ki_Out[9]), + .datab(Kp_Out[9]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~25 ), + .combout(\Add5~27_combout ), + .cout(\Add5~28 )); +// synopsys translate_off +defparam \Add5~27 .lut_mask = 16'h692B; +defparam \Add5~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N0 +cycloneive_lcell_comb \Add5~30 ( +// Equation(s): +// \Add5~30_combout = ((Kp_Out[10] $ (Ki_Out[10] $ (\Add5~28 )))) # (GND) +// \Add5~31 = CARRY((Kp_Out[10] & ((!\Add5~28 ) # (!Ki_Out[10]))) # (!Kp_Out[10] & (!Ki_Out[10] & !\Add5~28 ))) + + .dataa(Kp_Out[10]), + .datab(Ki_Out[10]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~28 ), + .combout(\Add5~30_combout ), + .cout(\Add5~31 )); +// synopsys translate_off +defparam \Add5~30 .lut_mask = 16'h962B; +defparam \Add5~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N2 +cycloneive_lcell_comb \Add5~33 ( +// Equation(s): +// \Add5~33_combout = (Ki_Out[11] & ((Kp_Out[11] & (!\Add5~31 )) # (!Kp_Out[11] & ((\Add5~31 ) # (GND))))) # (!Ki_Out[11] & ((Kp_Out[11] & (\Add5~31 & VCC)) # (!Kp_Out[11] & (!\Add5~31 )))) +// \Add5~34 = CARRY((Ki_Out[11] & ((!\Add5~31 ) # (!Kp_Out[11]))) # (!Ki_Out[11] & (!Kp_Out[11] & !\Add5~31 ))) + + .dataa(Ki_Out[11]), + .datab(Kp_Out[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~31 ), + .combout(\Add5~33_combout ), + .cout(\Add5~34 )); +// synopsys translate_off +defparam \Add5~33 .lut_mask = 16'h692B; +defparam \Add5~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N4 +cycloneive_lcell_comb \Add5~36 ( +// Equation(s): +// \Add5~36_combout = ((Ki_Out[12] $ (Kp_Out[12] $ (\Add5~34 )))) # (GND) +// \Add5~37 = CARRY((Ki_Out[12] & (Kp_Out[12] & !\Add5~34 )) # (!Ki_Out[12] & ((Kp_Out[12]) # (!\Add5~34 )))) + + .dataa(Ki_Out[12]), + .datab(Kp_Out[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~34 ), + .combout(\Add5~36_combout ), + .cout(\Add5~37 )); +// synopsys translate_off +defparam \Add5~36 .lut_mask = 16'h964D; +defparam \Add5~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N6 +cycloneive_lcell_comb \Add5~39 ( +// Equation(s): +// \Add5~39_combout = (Ki_Out[13] & ((Kp_Out[13] & (!\Add5~37 )) # (!Kp_Out[13] & ((\Add5~37 ) # (GND))))) # (!Ki_Out[13] & ((Kp_Out[13] & (\Add5~37 & VCC)) # (!Kp_Out[13] & (!\Add5~37 )))) +// \Add5~40 = CARRY((Ki_Out[13] & ((!\Add5~37 ) # (!Kp_Out[13]))) # (!Ki_Out[13] & (!Kp_Out[13] & !\Add5~37 ))) + + .dataa(Ki_Out[13]), + .datab(Kp_Out[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~37 ), + .combout(\Add5~39_combout ), + .cout(\Add5~40 )); +// synopsys translate_off +defparam \Add5~39 .lut_mask = 16'h692B; +defparam \Add5~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N8 +cycloneive_lcell_comb \Add5~42 ( +// Equation(s): +// \Add5~42_combout = ((Kp_Out[14] $ (Ki_Out[14] $ (\Add5~40 )))) # (GND) +// \Add5~43 = CARRY((Kp_Out[14] & ((!\Add5~40 ) # (!Ki_Out[14]))) # (!Kp_Out[14] & (!Ki_Out[14] & !\Add5~40 ))) + + .dataa(Kp_Out[14]), + .datab(Ki_Out[14]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~40 ), + .combout(\Add5~42_combout ), + .cout(\Add5~43 )); +// synopsys translate_off +defparam \Add5~42 .lut_mask = 16'h962B; +defparam \Add5~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N10 +cycloneive_lcell_comb \Add5~45 ( +// Equation(s): +// \Add5~45_combout = (Ki_Out[15] & ((Kp_Out[15] & (!\Add5~43 )) # (!Kp_Out[15] & ((\Add5~43 ) # (GND))))) # (!Ki_Out[15] & ((Kp_Out[15] & (\Add5~43 & VCC)) # (!Kp_Out[15] & (!\Add5~43 )))) +// \Add5~46 = CARRY((Ki_Out[15] & ((!\Add5~43 ) # (!Kp_Out[15]))) # (!Ki_Out[15] & (!Kp_Out[15] & !\Add5~43 ))) + + .dataa(Ki_Out[15]), + .datab(Kp_Out[15]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~43 ), + .combout(\Add5~45_combout ), + .cout(\Add5~46 )); +// synopsys translate_off +defparam \Add5~45 .lut_mask = 16'h692B; +defparam \Add5~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N12 +cycloneive_lcell_comb \Add5~48 ( +// Equation(s): +// \Add5~48_combout = ((Ki_Out[16] $ (Kp_Out[16] $ (\Add5~46 )))) # (GND) +// \Add5~49 = CARRY((Ki_Out[16] & (Kp_Out[16] & !\Add5~46 )) # (!Ki_Out[16] & ((Kp_Out[16]) # (!\Add5~46 )))) + + .dataa(Ki_Out[16]), + .datab(Kp_Out[16]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~46 ), + .combout(\Add5~48_combout ), + .cout(\Add5~49 )); +// synopsys translate_off +defparam \Add5~48 .lut_mask = 16'h964D; +defparam \Add5~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N14 +cycloneive_lcell_comb \Add5~51 ( +// Equation(s): +// \Add5~51_combout = (Kp_Out[17] & ((Ki_Out[17] & (!\Add5~49 )) # (!Ki_Out[17] & (\Add5~49 & VCC)))) # (!Kp_Out[17] & ((Ki_Out[17] & ((\Add5~49 ) # (GND))) # (!Ki_Out[17] & (!\Add5~49 )))) +// \Add5~52 = CARRY((Kp_Out[17] & (Ki_Out[17] & !\Add5~49 )) # (!Kp_Out[17] & ((Ki_Out[17]) # (!\Add5~49 )))) + + .dataa(Kp_Out[17]), + .datab(Ki_Out[17]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~49 ), + .combout(\Add5~51_combout ), + .cout(\Add5~52 )); +// synopsys translate_off +defparam \Add5~51 .lut_mask = 16'h694D; +defparam \Add5~51 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N16 +cycloneive_lcell_comb \Add5~54 ( +// Equation(s): +// \Add5~54_combout = ((Kp_Out[18] $ (Ki_Out[18] $ (\Add5~52 )))) # (GND) +// \Add5~55 = CARRY((Kp_Out[18] & ((!\Add5~52 ) # (!Ki_Out[18]))) # (!Kp_Out[18] & (!Ki_Out[18] & !\Add5~52 ))) + + .dataa(Kp_Out[18]), + .datab(Ki_Out[18]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~52 ), + .combout(\Add5~54_combout ), + .cout(\Add5~55 )); +// synopsys translate_off +defparam \Add5~54 .lut_mask = 16'h962B; +defparam \Add5~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N18 +cycloneive_lcell_comb \Add5~57 ( +// Equation(s): +// \Add5~57_combout = (Kp_Out[19] & ((Ki_Out[19] & (!\Add5~55 )) # (!Ki_Out[19] & (\Add5~55 & VCC)))) # (!Kp_Out[19] & ((Ki_Out[19] & ((\Add5~55 ) # (GND))) # (!Ki_Out[19] & (!\Add5~55 )))) +// \Add5~58 = CARRY((Kp_Out[19] & (Ki_Out[19] & !\Add5~55 )) # (!Kp_Out[19] & ((Ki_Out[19]) # (!\Add5~55 )))) + + .dataa(Kp_Out[19]), + .datab(Ki_Out[19]), + .datac(gnd), + .datad(vcc), + .cin(\Add5~55 ), + .combout(\Add5~57_combout ), + .cout(\Add5~58 )); +// synopsys translate_off +defparam \Add5~57 .lut_mask = 16'h694D; +defparam \Add5~57 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N20 +cycloneive_lcell_comb \Add5~60 ( +// Equation(s): +// \Add5~60_combout = Ki_Out[20] $ (\Add5~58 $ (Kp_Out[20])) + + .dataa(Ki_Out[20]), + .datab(gnd), + .datac(gnd), + .datad(Kp_Out[20]), + .cin(\Add5~58 ), + .combout(\Add5~60_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~60 .lut_mask = 16'hA55A; +defparam \Add5~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N12 +cycloneive_lcell_comb \Add5~62 ( +// Equation(s): +// \Add5~62_combout = (!\Vout[13]~reg0_q & \Add5~60_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~60_combout ), + .cin(gnd), + .combout(\Add5~62_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~62 .lut_mask = 16'h0F00; +defparam \Add5~62 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N10 +cycloneive_lcell_comb \Add7~19 ( +// Equation(s): +// \Add7~19_combout = (!\Vout[13]~reg0_q & Kd_Out[19]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[19]), + .cin(gnd), + .combout(\Add7~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~19 .lut_mask = 16'h0F00; +defparam \Add7~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N16 +cycloneive_lcell_comb \Add7~18 ( +// Equation(s): +// \Add7~18_combout = (!\Vout[13]~reg0_q & Kd_Out[18]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[18]), + .cin(gnd), + .combout(\Add7~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~18 .lut_mask = 16'h0F00; +defparam \Add7~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N10 +cycloneive_lcell_comb \Add7~17 ( +// Equation(s): +// \Add7~17_combout = (Kd_Out[17] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[17]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~17 .lut_mask = 16'h00F0; +defparam \Add7~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N20 +cycloneive_lcell_comb \Add7~16 ( +// Equation(s): +// \Add7~16_combout = (Kd_Out[16] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[16]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~16 .lut_mask = 16'h00F0; +defparam \Add7~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N26 +cycloneive_lcell_comb \Add7~15 ( +// Equation(s): +// \Add7~15_combout = (!\Vout[13]~reg0_q & Kd_Out[15]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[15]), + .cin(gnd), + .combout(\Add7~15_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~15 .lut_mask = 16'h0F00; +defparam \Add7~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N4 +cycloneive_lcell_comb \Add7~14 ( +// Equation(s): +// \Add7~14_combout = (!\Vout[13]~reg0_q & Kd_Out[14]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[14]), + .cin(gnd), + .combout(\Add7~14_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~14 .lut_mask = 16'h0F00; +defparam \Add7~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N2 +cycloneive_lcell_comb \Add7~13 ( +// Equation(s): +// \Add7~13_combout = (Kd_Out[13] & !\Vout[13]~reg0_q ) + + .dataa(Kd_Out[13]), + .datab(gnd), + .datac(gnd), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~13_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~13 .lut_mask = 16'h00AA; +defparam \Add7~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N14 +cycloneive_lcell_comb \Add7~12 ( +// Equation(s): +// \Add7~12_combout = (Kd_Out[12] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(Kd_Out[12]), + .datac(\Vout[13]~reg0_q ), + .datad(gnd), + .cin(gnd), + .combout(\Add7~12_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~12 .lut_mask = 16'h0C0C; +defparam \Add7~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y17_N20 +cycloneive_lcell_comb \Add7~11 ( +// Equation(s): +// \Add7~11_combout = (!\Vout[13]~reg0_q & Kd_Out[11]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[11]), + .cin(gnd), + .combout(\Add7~11_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~11 .lut_mask = 16'h0F00; +defparam \Add7~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y13_N16 +cycloneive_lcell_comb \Add7~10 ( +// Equation(s): +// \Add7~10_combout = (Kd_Out[10] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[10]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~10_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~10 .lut_mask = 16'h00F0; +defparam \Add7~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N12 +cycloneive_lcell_comb \Add7~9 ( +// Equation(s): +// \Add7~9_combout = (Kd_Out[9] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[9]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~9_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~9 .lut_mask = 16'h00F0; +defparam \Add7~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N16 +cycloneive_lcell_comb \Add7~8 ( +// Equation(s): +// \Add7~8_combout = (!\Vout[13]~reg0_q & Kd_Out[8]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[8]), + .cin(gnd), + .combout(\Add7~8_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~8 .lut_mask = 16'h5500; +defparam \Add7~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N8 +cycloneive_lcell_comb \Add5~16 ( +// Equation(s): +// \Add5~16_combout = (\Vout[13]~reg0_q & (!\Vout[0]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~14_combout ))) + + .dataa(\Vout[0]~reg0_q ), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~14_combout ), + .cin(gnd), + .combout(\Add5~16_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~16 .lut_mask = 16'h5F50; +defparam \Add5~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y14_N0 +cycloneive_lcell_comb \Add7~1 ( +// Equation(s): +// \Add7~1_combout = (!\Vout[13]~reg0_q & Kd_Out[6]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[6]), + .cin(gnd), + .combout(\Add7~1_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~1 .lut_mask = 16'h0F00; +defparam \Add7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N0 +cycloneive_lcell_comb \Add5~17 ( +// Equation(s): +// \Add5~17_combout = (!\Vout[13]~reg0_q & \Add5~12_combout ) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\Add5~12_combout ), + .cin(gnd), + .combout(\Add5~17_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~17 .lut_mask = 16'h5500; +defparam \Add5~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N8 +cycloneive_lcell_comb \Add7~2 ( +// Equation(s): +// \Add7~2_combout = (!\Vout[13]~reg0_q & Kd_Out[5]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[5]), + .cin(gnd), + .combout(\Add7~2_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~2 .lut_mask = 16'h5500; +defparam \Add7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N10 +cycloneive_lcell_comb \Add5~18 ( +// Equation(s): +// \Add5~18_combout = (\Add5~10_combout & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Add5~10_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~18_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~18 .lut_mask = 16'h00F0; +defparam \Add5~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N4 +cycloneive_lcell_comb \Add7~3 ( +// Equation(s): +// \Add7~3_combout = (Kd_Out[4] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(Kd_Out[4]), + .datac(gnd), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~3_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~3 .lut_mask = 16'h00CC; +defparam \Add7~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N2 +cycloneive_lcell_comb \Add5~19 ( +// Equation(s): +// \Add5~19_combout = (!\Vout[13]~reg0_q & \Add5~8_combout ) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~8_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~19_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~19 .lut_mask = 16'h3030; +defparam \Add5~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N2 +cycloneive_lcell_comb \Add5~20 ( +// Equation(s): +// \Add5~20_combout = (!\Vout[13]~reg0_q & \Add5~6_combout ) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\Add5~6_combout ), + .cin(gnd), + .combout(\Add5~20_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~20 .lut_mask = 16'h5500; +defparam \Add5~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y18_N8 +cycloneive_lcell_comb \Add7~4 ( +// Equation(s): +// \Add7~4_combout = (!\Vout[13]~reg0_q & Kd_Out[3]) + + .dataa(\Vout[13]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(Kd_Out[3]), + .cin(gnd), + .combout(\Add7~4_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~4 .lut_mask = 16'h5500; +defparam \Add7~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y18_N14 +cycloneive_lcell_comb \Add7~5 ( +// Equation(s): +// \Add7~5_combout = (Kd_Out[2] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[2]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~5_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~5 .lut_mask = 16'h00F0; +defparam \Add7~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N0 +cycloneive_lcell_comb \Add5~21 ( +// Equation(s): +// \Add5~21_combout = (!\Vout[13]~reg0_q & \Add5~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~4_combout ), + .cin(gnd), + .combout(\Add5~21_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~21 .lut_mask = 16'h0F00; +defparam \Add5~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N6 +cycloneive_lcell_comb \Add7~6 ( +// Equation(s): +// \Add7~6_combout = (Kd_Out[1] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[1]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~6_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~6 .lut_mask = 16'h00F0; +defparam \Add7~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y18_N8 +cycloneive_lcell_comb \Add5~22 ( +// Equation(s): +// \Add5~22_combout = (\Add5~2_combout & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(\Add5~2_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~22_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~22 .lut_mask = 16'h00F0; +defparam \Add5~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N10 +cycloneive_lcell_comb \Add5~23 ( +// Equation(s): +// \Add5~23_combout = (!\Vout[13]~reg0_q & \Add5~0_combout ) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~23_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~23 .lut_mask = 16'h3030; +defparam \Add5~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N22 +cycloneive_lcell_comb \Add7~7 ( +// Equation(s): +// \Add7~7_combout = (Kd_Out[0] & !\Vout[13]~reg0_q ) + + .dataa(gnd), + .datab(gnd), + .datac(Kd_Out[0]), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add7~7_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~7 .lut_mask = 16'h00F0; +defparam \Add7~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N12 +cycloneive_lcell_comb \Vout[0]~15 ( +// Equation(s): +// \Vout[0]~15_cout = CARRY((\Add5~23_combout & \Add7~7_combout )) + + .dataa(\Add5~23_combout ), + .datab(\Add7~7_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\Vout[0]~15_cout )); +// synopsys translate_off +defparam \Vout[0]~15 .lut_mask = 16'h0088; +defparam \Vout[0]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N14 +cycloneive_lcell_comb \Vout[0]~17 ( +// Equation(s): +// \Vout[0]~17_cout = CARRY((\Add7~6_combout & (!\Add5~22_combout & !\Vout[0]~15_cout )) # (!\Add7~6_combout & ((!\Vout[0]~15_cout ) # (!\Add5~22_combout )))) + + .dataa(\Add7~6_combout ), + .datab(\Add5~22_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~15_cout ), + .combout(), + .cout(\Vout[0]~17_cout )); +// synopsys translate_off +defparam \Vout[0]~17 .lut_mask = 16'h0017; +defparam \Vout[0]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N16 +cycloneive_lcell_comb \Vout[0]~19 ( +// Equation(s): +// \Vout[0]~19_cout = CARRY((\Add7~5_combout & ((\Add5~21_combout ) # (!\Vout[0]~17_cout ))) # (!\Add7~5_combout & (\Add5~21_combout & !\Vout[0]~17_cout ))) + + .dataa(\Add7~5_combout ), + .datab(\Add5~21_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~17_cout ), + .combout(), + .cout(\Vout[0]~19_cout )); +// synopsys translate_off +defparam \Vout[0]~19 .lut_mask = 16'h008E; +defparam \Vout[0]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N18 +cycloneive_lcell_comb \Vout[0]~21 ( +// Equation(s): +// \Vout[0]~21_cout = CARRY((\Add5~20_combout & (!\Add7~4_combout & !\Vout[0]~19_cout )) # (!\Add5~20_combout & ((!\Vout[0]~19_cout ) # (!\Add7~4_combout )))) + + .dataa(\Add5~20_combout ), + .datab(\Add7~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~19_cout ), + .combout(), + .cout(\Vout[0]~21_cout )); +// synopsys translate_off +defparam \Vout[0]~21 .lut_mask = 16'h0017; +defparam \Vout[0]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N20 +cycloneive_lcell_comb \Vout[0]~23 ( +// Equation(s): +// \Vout[0]~23_cout = CARRY((\Add7~3_combout & ((\Add5~19_combout ) # (!\Vout[0]~21_cout ))) # (!\Add7~3_combout & (\Add5~19_combout & !\Vout[0]~21_cout ))) + + .dataa(\Add7~3_combout ), + .datab(\Add5~19_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~21_cout ), + .combout(), + .cout(\Vout[0]~23_cout )); +// synopsys translate_off +defparam \Vout[0]~23 .lut_mask = 16'h008E; +defparam \Vout[0]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N22 +cycloneive_lcell_comb \Vout[0]~25 ( +// Equation(s): +// \Vout[0]~25_cout = CARRY((\Add7~2_combout & (!\Add5~18_combout & !\Vout[0]~23_cout )) # (!\Add7~2_combout & ((!\Vout[0]~23_cout ) # (!\Add5~18_combout )))) + + .dataa(\Add7~2_combout ), + .datab(\Add5~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~23_cout ), + .combout(), + .cout(\Vout[0]~25_cout )); +// synopsys translate_off +defparam \Vout[0]~25 .lut_mask = 16'h0017; +defparam \Vout[0]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N24 +cycloneive_lcell_comb \Vout[0]~27 ( +// Equation(s): +// \Vout[0]~27_cout = CARRY((\Add7~1_combout & ((\Add5~17_combout ) # (!\Vout[0]~25_cout ))) # (!\Add7~1_combout & (\Add5~17_combout & !\Vout[0]~25_cout ))) + + .dataa(\Add7~1_combout ), + .datab(\Add5~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~25_cout ), + .combout(), + .cout(\Vout[0]~27_cout )); +// synopsys translate_off +defparam \Vout[0]~27 .lut_mask = 16'h008E; +defparam \Vout[0]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N26 +cycloneive_lcell_comb \Vout[0]~28 ( +// Equation(s): +// \Vout[0]~28_combout = (\Add7~0_combout & ((\Add5~16_combout & (\Vout[0]~27_cout & VCC)) # (!\Add5~16_combout & (!\Vout[0]~27_cout )))) # (!\Add7~0_combout & ((\Add5~16_combout & (!\Vout[0]~27_cout )) # (!\Add5~16_combout & ((\Vout[0]~27_cout ) # +// (GND))))) +// \Vout[0]~29 = CARRY((\Add7~0_combout & (!\Add5~16_combout & !\Vout[0]~27_cout )) # (!\Add7~0_combout & ((!\Vout[0]~27_cout ) # (!\Add5~16_combout )))) + + .dataa(\Add7~0_combout ), + .datab(\Add5~16_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~27_cout ), + .combout(\Vout[0]~28_combout ), + .cout(\Vout[0]~29 )); +// synopsys translate_off +defparam \Vout[0]~28 .lut_mask = 16'h9617; +defparam \Vout[0]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N28 +cycloneive_lcell_comb \Vout[1]~30 ( +// Equation(s): +// \Vout[1]~30_combout = ((\Add7~8_combout $ (\Add5~26_combout $ (!\Vout[0]~29 )))) # (GND) +// \Vout[1]~31 = CARRY((\Add7~8_combout & ((\Add5~26_combout ) # (!\Vout[0]~29 ))) # (!\Add7~8_combout & (\Add5~26_combout & !\Vout[0]~29 ))) + + .dataa(\Add7~8_combout ), + .datab(\Add5~26_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[0]~29 ), + .combout(\Vout[1]~30_combout ), + .cout(\Vout[1]~31 )); +// synopsys translate_off +defparam \Vout[1]~30 .lut_mask = 16'h698E; +defparam \Vout[1]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y18_N29 +dffeas \Vout[1]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[1]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[1]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[1]~reg0 .is_wysiwyg = "true"; +defparam \Vout[1]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N4 +cycloneive_lcell_comb \Add5~26 ( +// Equation(s): +// \Add5~26_combout = (\Vout[13]~reg0_q & (!\Vout[1]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~24_combout ))) + + .dataa(gnd), + .datab(\Vout[1]~reg0_q ), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~24_combout ), + .cin(gnd), + .combout(\Add5~26_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~26 .lut_mask = 16'h3F30; +defparam \Add5~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N30 +cycloneive_lcell_comb \Vout[2]~32 ( +// Equation(s): +// \Vout[2]~32_combout = (\Add5~29_combout & ((\Add7~9_combout & (\Vout[1]~31 & VCC)) # (!\Add7~9_combout & (!\Vout[1]~31 )))) # (!\Add5~29_combout & ((\Add7~9_combout & (!\Vout[1]~31 )) # (!\Add7~9_combout & ((\Vout[1]~31 ) # (GND))))) +// \Vout[2]~33 = CARRY((\Add5~29_combout & (!\Add7~9_combout & !\Vout[1]~31 )) # (!\Add5~29_combout & ((!\Vout[1]~31 ) # (!\Add7~9_combout )))) + + .dataa(\Add5~29_combout ), + .datab(\Add7~9_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[1]~31 ), + .combout(\Vout[2]~32_combout ), + .cout(\Vout[2]~33 )); +// synopsys translate_off +defparam \Vout[2]~32 .lut_mask = 16'h9617; +defparam \Vout[2]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y18_N31 +dffeas \Vout[2]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[2]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[2]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[2]~reg0 .is_wysiwyg = "true"; +defparam \Vout[2]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y18_N6 +cycloneive_lcell_comb \Add5~29 ( +// Equation(s): +// \Add5~29_combout = (\Vout[13]~reg0_q & (!\Vout[2]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~27_combout ))) + + .dataa(\Vout[2]~reg0_q ), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~27_combout ), + .datad(gnd), + .cin(gnd), + .combout(\Add5~29_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~29 .lut_mask = 16'h7474; +defparam \Add5~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N0 +cycloneive_lcell_comb \Vout[3]~34 ( +// Equation(s): +// \Vout[3]~34_combout = ((\Add5~32_combout $ (\Add7~10_combout $ (!\Vout[2]~33 )))) # (GND) +// \Vout[3]~35 = CARRY((\Add5~32_combout & ((\Add7~10_combout ) # (!\Vout[2]~33 ))) # (!\Add5~32_combout & (\Add7~10_combout & !\Vout[2]~33 ))) + + .dataa(\Add5~32_combout ), + .datab(\Add7~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[2]~33 ), + .combout(\Vout[3]~34_combout ), + .cout(\Vout[3]~35 )); +// synopsys translate_off +defparam \Vout[3]~34 .lut_mask = 16'h698E; +defparam \Vout[3]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N1 +dffeas \Vout[3]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[3]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[3]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[3]~reg0 .is_wysiwyg = "true"; +defparam \Vout[3]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N26 +cycloneive_lcell_comb \Add5~32 ( +// Equation(s): +// \Add5~32_combout = (\Vout[13]~reg0_q & ((!\Vout[3]~reg0_q ))) # (!\Vout[13]~reg0_q & (\Add5~30_combout )) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~30_combout ), + .datad(\Vout[3]~reg0_q ), + .cin(gnd), + .combout(\Add5~32_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~32 .lut_mask = 16'h30FC; +defparam \Add5~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N2 +cycloneive_lcell_comb \Vout[4]~36 ( +// Equation(s): +// \Vout[4]~36_combout = (\Add5~35_combout & ((\Add7~11_combout & (\Vout[3]~35 & VCC)) # (!\Add7~11_combout & (!\Vout[3]~35 )))) # (!\Add5~35_combout & ((\Add7~11_combout & (!\Vout[3]~35 )) # (!\Add7~11_combout & ((\Vout[3]~35 ) # (GND))))) +// \Vout[4]~37 = CARRY((\Add5~35_combout & (!\Add7~11_combout & !\Vout[3]~35 )) # (!\Add5~35_combout & ((!\Vout[3]~35 ) # (!\Add7~11_combout )))) + + .dataa(\Add5~35_combout ), + .datab(\Add7~11_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[3]~35 ), + .combout(\Vout[4]~36_combout ), + .cout(\Vout[4]~37 )); +// synopsys translate_off +defparam \Vout[4]~36 .lut_mask = 16'h9617; +defparam \Vout[4]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N3 +dffeas \Vout[4]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[4]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[4]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[4]~reg0 .is_wysiwyg = "true"; +defparam \Vout[4]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N30 +cycloneive_lcell_comb \Add5~35 ( +// Equation(s): +// \Add5~35_combout = (\Vout[13]~reg0_q & (!\Vout[4]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~33_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[4]~reg0_q ), + .datad(\Add5~33_combout ), + .cin(gnd), + .combout(\Add5~35_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~35 .lut_mask = 16'h3F0C; +defparam \Add5~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N4 +cycloneive_lcell_comb \Vout[5]~38 ( +// Equation(s): +// \Vout[5]~38_combout = ((\Add7~12_combout $ (\Add5~38_combout $ (!\Vout[4]~37 )))) # (GND) +// \Vout[5]~39 = CARRY((\Add7~12_combout & ((\Add5~38_combout ) # (!\Vout[4]~37 ))) # (!\Add7~12_combout & (\Add5~38_combout & !\Vout[4]~37 ))) + + .dataa(\Add7~12_combout ), + .datab(\Add5~38_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[4]~37 ), + .combout(\Vout[5]~38_combout ), + .cout(\Vout[5]~39 )); +// synopsys translate_off +defparam \Vout[5]~38 .lut_mask = 16'h698E; +defparam \Vout[5]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N5 +dffeas \Vout[5]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[5]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[5]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[5]~reg0 .is_wysiwyg = "true"; +defparam \Vout[5]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N28 +cycloneive_lcell_comb \Add5~38 ( +// Equation(s): +// \Add5~38_combout = (\Vout[13]~reg0_q & (!\Vout[5]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~36_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[5]~reg0_q ), + .datad(\Add5~36_combout ), + .cin(gnd), + .combout(\Add5~38_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~38 .lut_mask = 16'h3F0C; +defparam \Add5~38 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N6 +cycloneive_lcell_comb \Vout[6]~40 ( +// Equation(s): +// \Vout[6]~40_combout = (\Add7~13_combout & ((\Add5~41_combout & (\Vout[5]~39 & VCC)) # (!\Add5~41_combout & (!\Vout[5]~39 )))) # (!\Add7~13_combout & ((\Add5~41_combout & (!\Vout[5]~39 )) # (!\Add5~41_combout & ((\Vout[5]~39 ) # (GND))))) +// \Vout[6]~41 = CARRY((\Add7~13_combout & (!\Add5~41_combout & !\Vout[5]~39 )) # (!\Add7~13_combout & ((!\Vout[5]~39 ) # (!\Add5~41_combout )))) + + .dataa(\Add7~13_combout ), + .datab(\Add5~41_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[5]~39 ), + .combout(\Vout[6]~40_combout ), + .cout(\Vout[6]~41 )); +// synopsys translate_off +defparam \Vout[6]~40 .lut_mask = 16'h9617; +defparam \Vout[6]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N7 +dffeas \Vout[6]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[6]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[6]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[6]~reg0 .is_wysiwyg = "true"; +defparam \Vout[6]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N24 +cycloneive_lcell_comb \Add5~41 ( +// Equation(s): +// \Add5~41_combout = (\Vout[13]~reg0_q & (!\Vout[6]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~39_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[6]~reg0_q ), + .datad(\Add5~39_combout ), + .cin(gnd), + .combout(\Add5~41_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~41 .lut_mask = 16'h3F0C; +defparam \Add5~41 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N8 +cycloneive_lcell_comb \Vout[7]~42 ( +// Equation(s): +// \Vout[7]~42_combout = ((\Add5~44_combout $ (\Add7~14_combout $ (!\Vout[6]~41 )))) # (GND) +// \Vout[7]~43 = CARRY((\Add5~44_combout & ((\Add7~14_combout ) # (!\Vout[6]~41 ))) # (!\Add5~44_combout & (\Add7~14_combout & !\Vout[6]~41 ))) + + .dataa(\Add5~44_combout ), + .datab(\Add7~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[6]~41 ), + .combout(\Vout[7]~42_combout ), + .cout(\Vout[7]~43 )); +// synopsys translate_off +defparam \Vout[7]~42 .lut_mask = 16'h698E; +defparam \Vout[7]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N9 +dffeas \Vout[7]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[7]~42_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[7]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[7]~reg0 .is_wysiwyg = "true"; +defparam \Vout[7]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N30 +cycloneive_lcell_comb \Add5~44 ( +// Equation(s): +// \Add5~44_combout = (\Vout[13]~reg0_q & (!\Vout[7]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~42_combout ))) + + .dataa(gnd), + .datab(\Vout[7]~reg0_q ), + .datac(\Add5~42_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~44_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~44 .lut_mask = 16'h33F0; +defparam \Add5~44 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N10 +cycloneive_lcell_comb \Vout[8]~44 ( +// Equation(s): +// \Vout[8]~44_combout = (\Add7~15_combout & ((\Add5~47_combout & (\Vout[7]~43 & VCC)) # (!\Add5~47_combout & (!\Vout[7]~43 )))) # (!\Add7~15_combout & ((\Add5~47_combout & (!\Vout[7]~43 )) # (!\Add5~47_combout & ((\Vout[7]~43 ) # (GND))))) +// \Vout[8]~45 = CARRY((\Add7~15_combout & (!\Add5~47_combout & !\Vout[7]~43 )) # (!\Add7~15_combout & ((!\Vout[7]~43 ) # (!\Add5~47_combout )))) + + .dataa(\Add7~15_combout ), + .datab(\Add5~47_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[7]~43 ), + .combout(\Vout[8]~44_combout ), + .cout(\Vout[8]~45 )); +// synopsys translate_off +defparam \Vout[8]~44 .lut_mask = 16'h9617; +defparam \Vout[8]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N11 +dffeas \Vout[8]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[8]~44_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[8]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[8]~reg0 .is_wysiwyg = "true"; +defparam \Vout[8]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N26 +cycloneive_lcell_comb \Add5~47 ( +// Equation(s): +// \Add5~47_combout = (\Vout[13]~reg0_q & (!\Vout[8]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~45_combout ))) + + .dataa(\Vout[8]~reg0_q ), + .datab(\Vout[13]~reg0_q ), + .datac(gnd), + .datad(\Add5~45_combout ), + .cin(gnd), + .combout(\Add5~47_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~47 .lut_mask = 16'h7744; +defparam \Add5~47 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N12 +cycloneive_lcell_comb \Vout[9]~46 ( +// Equation(s): +// \Vout[9]~46_combout = ((\Add7~16_combout $ (\Add5~50_combout $ (!\Vout[8]~45 )))) # (GND) +// \Vout[9]~47 = CARRY((\Add7~16_combout & ((\Add5~50_combout ) # (!\Vout[8]~45 ))) # (!\Add7~16_combout & (\Add5~50_combout & !\Vout[8]~45 ))) + + .dataa(\Add7~16_combout ), + .datab(\Add5~50_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[8]~45 ), + .combout(\Vout[9]~46_combout ), + .cout(\Vout[9]~47 )); +// synopsys translate_off +defparam \Vout[9]~46 .lut_mask = 16'h698E; +defparam \Vout[9]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N13 +dffeas \Vout[9]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[9]~46_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[9]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[9]~reg0 .is_wysiwyg = "true"; +defparam \Vout[9]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N24 +cycloneive_lcell_comb \Add5~50 ( +// Equation(s): +// \Add5~50_combout = (\Vout[13]~reg0_q & ((!\Vout[9]~reg0_q ))) # (!\Vout[13]~reg0_q & (\Add5~48_combout )) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Add5~48_combout ), + .datad(\Vout[9]~reg0_q ), + .cin(gnd), + .combout(\Add5~50_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~50 .lut_mask = 16'h30FC; +defparam \Add5~50 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N14 +cycloneive_lcell_comb \Vout[10]~48 ( +// Equation(s): +// \Vout[10]~48_combout = (\Add5~53_combout & ((\Add7~17_combout & (\Vout[9]~47 & VCC)) # (!\Add7~17_combout & (!\Vout[9]~47 )))) # (!\Add5~53_combout & ((\Add7~17_combout & (!\Vout[9]~47 )) # (!\Add7~17_combout & ((\Vout[9]~47 ) # (GND))))) +// \Vout[10]~49 = CARRY((\Add5~53_combout & (!\Add7~17_combout & !\Vout[9]~47 )) # (!\Add5~53_combout & ((!\Vout[9]~47 ) # (!\Add7~17_combout )))) + + .dataa(\Add5~53_combout ), + .datab(\Add7~17_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[9]~47 ), + .combout(\Vout[10]~48_combout ), + .cout(\Vout[10]~49 )); +// synopsys translate_off +defparam \Vout[10]~48 .lut_mask = 16'h9617; +defparam \Vout[10]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N15 +dffeas \Vout[10]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[10]~48_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[10]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[10]~reg0 .is_wysiwyg = "true"; +defparam \Vout[10]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N22 +cycloneive_lcell_comb \Add5~53 ( +// Equation(s): +// \Add5~53_combout = (\Vout[13]~reg0_q & (!\Vout[10]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~51_combout ))) + + .dataa(gnd), + .datab(\Vout[10]~reg0_q ), + .datac(\Add5~51_combout ), + .datad(\Vout[13]~reg0_q ), + .cin(gnd), + .combout(\Add5~53_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~53 .lut_mask = 16'h33F0; +defparam \Add5~53 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N16 +cycloneive_lcell_comb \Vout[11]~50 ( +// Equation(s): +// \Vout[11]~50_combout = ((\Add7~18_combout $ (\Add5~56_combout $ (!\Vout[10]~49 )))) # (GND) +// \Vout[11]~51 = CARRY((\Add7~18_combout & ((\Add5~56_combout ) # (!\Vout[10]~49 ))) # (!\Add7~18_combout & (\Add5~56_combout & !\Vout[10]~49 ))) + + .dataa(\Add7~18_combout ), + .datab(\Add5~56_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[10]~49 ), + .combout(\Vout[11]~50_combout ), + .cout(\Vout[11]~51 )); +// synopsys translate_off +defparam \Vout[11]~50 .lut_mask = 16'h698E; +defparam \Vout[11]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N17 +dffeas \Vout[11]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[11]~50_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[11]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[11]~reg0 .is_wysiwyg = "true"; +defparam \Vout[11]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N28 +cycloneive_lcell_comb \Add5~56 ( +// Equation(s): +// \Add5~56_combout = (\Vout[13]~reg0_q & (!\Vout[11]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~54_combout ))) + + .dataa(gnd), + .datab(\Vout[13]~reg0_q ), + .datac(\Vout[11]~reg0_q ), + .datad(\Add5~54_combout ), + .cin(gnd), + .combout(\Add5~56_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~56 .lut_mask = 16'h3F0C; +defparam \Add5~56 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N18 +cycloneive_lcell_comb \Vout[12]~52 ( +// Equation(s): +// \Vout[12]~52_combout = (\Add7~19_combout & ((\Add5~59_combout & (\Vout[11]~51 & VCC)) # (!\Add5~59_combout & (!\Vout[11]~51 )))) # (!\Add7~19_combout & ((\Add5~59_combout & (!\Vout[11]~51 )) # (!\Add5~59_combout & ((\Vout[11]~51 ) # (GND))))) +// \Vout[12]~53 = CARRY((\Add7~19_combout & (!\Add5~59_combout & !\Vout[11]~51 )) # (!\Add7~19_combout & ((!\Vout[11]~51 ) # (!\Add5~59_combout )))) + + .dataa(\Add7~19_combout ), + .datab(\Add5~59_combout ), + .datac(gnd), + .datad(vcc), + .cin(\Vout[11]~51 ), + .combout(\Vout[12]~52_combout ), + .cout(\Vout[12]~53 )); +// synopsys translate_off +defparam \Vout[12]~52 .lut_mask = 16'h9617; +defparam \Vout[12]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N19 +dffeas \Vout[12]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[12]~52_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[12]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[12]~reg0 .is_wysiwyg = "true"; +defparam \Vout[12]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y17_N22 +cycloneive_lcell_comb \Add5~59 ( +// Equation(s): +// \Add5~59_combout = (\Vout[13]~reg0_q & (!\Vout[12]~reg0_q )) # (!\Vout[13]~reg0_q & ((\Add5~57_combout ))) + + .dataa(gnd), + .datab(\Vout[12]~reg0_q ), + .datac(\Vout[13]~reg0_q ), + .datad(\Add5~57_combout ), + .cin(gnd), + .combout(\Add5~59_combout ), + .cout()); +// synopsys translate_off +defparam \Add5~59 .lut_mask = 16'h3F30; +defparam \Add5~59 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y17_N20 +cycloneive_lcell_comb \Vout[13]~54 ( +// Equation(s): +// \Vout[13]~54_combout = \Add7~20_combout $ (\Vout[12]~53 $ (!\Add5~62_combout )) + + .dataa(gnd), + .datab(\Add7~20_combout ), + .datac(gnd), + .datad(\Add5~62_combout ), + .cin(\Vout[12]~53 ), + .combout(\Vout[13]~54_combout ), + .cout()); +// synopsys translate_off +defparam \Vout[13]~54 .lut_mask = 16'h3CC3; +defparam \Vout[13]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y17_N21 +dffeas \Vout[13]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[13]~54_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[13]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[13]~reg0 .is_wysiwyg = "true"; +defparam \Vout[13]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X18_Y14_N20 +cycloneive_lcell_comb \Add7~0 ( +// Equation(s): +// \Add7~0_combout = (\Vout[13]~reg0_q ) # (Kd_Out[7]) + + .dataa(gnd), + .datab(gnd), + .datac(\Vout[13]~reg0_q ), + .datad(Kd_Out[7]), + .cin(gnd), + .combout(\Add7~0_combout ), + .cout()); +// synopsys translate_off +defparam \Add7~0 .lut_mask = 16'hFFF0; +defparam \Add7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y18_N27 +dffeas \Vout[0]~reg0 ( + .clk(\clk~inputclkctrl_outclk ), + .d(\Vout[0]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\Clk_Ctrl~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\Vout[0]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \Vout[0]~reg0 .is_wysiwyg = "true"; +defparam \Vout[0]~reg0 .power_up = "low"; +// synopsys translate_on + +assign Vout[0] = \Vout[0]~output_o ; + +assign Vout[1] = \Vout[1]~output_o ; + +assign Vout[2] = \Vout[2]~output_o ; + +assign Vout[3] = \Vout[3]~output_o ; + +assign Vout[4] = \Vout[4]~output_o ; + +assign Vout[5] = \Vout[5]~output_o ; + +assign Vout[6] = \Vout[6]~output_o ; + +assign Vout[7] = \Vout[7]~output_o ; + +assign Vout[8] = \Vout[8]~output_o ; + +assign Vout[9] = \Vout[9]~output_o ; + +assign Vout[10] = \Vout[10]~output_o ; + +assign Vout[11] = \Vout[11]~output_o ; + +assign Vout[12] = \Vout[12]~output_o ; + +assign Vout[13] = \Vout[13]~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_DATA0~~ibuf_o ; + + +endmodule diff --git a/pid/simulation/modelsim/pid_min_1200mv_0c_v_fast.sdo b/pid/simulation/modelsim/pid_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..801d148 --- /dev/null +++ b/pid/simulation/modelsim/pid_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,6913 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE10F17C8, +// with speed grade M, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "pid") + (DATE "12/04/2018 14:36:39") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1086:1086:1086) (1266:1266:1266)) + (IOPATH i o (1602:1602:1602) (1605:1605:1605)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (671:671:671) (774:774:774)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (964:964:964) (1086:1086:1086)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (612:612:612) (695:695:695)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (643:643:643) (743:743:743)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (755:755:755) (857:857:857)) + (IOPATH i o (1582:1582:1582) (1585:1585:1585)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (549:549:549) (645:645:645)) + (IOPATH i o (1589:1589:1589) (1614:1614:1614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (748:748:748) (853:853:853)) + (IOPATH i o (1602:1602:1602) (1605:1605:1605)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (882:882:882) (1038:1038:1038)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (776:776:776) (877:877:877)) + (IOPATH i o (1545:1545:1545) (1550:1550:1550)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (744:744:744) (842:842:842)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (839:839:839) (977:977:977)) + (IOPATH i o (1589:1589:1589) (1614:1614:1614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1070:1070:1070) (1242:1242:1242)) + (IOPATH i o (1572:1572:1572) (1575:1575:1575)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (677:677:677) (783:783:783)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (108:108:108) (89:89:89)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (190:190:190)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (153:153:153) (200:200:200)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~1) + (DELAY + (ABSOLUTE + (PORT datac (409:409:409) (496:496:496)) + (PORT datad (1743:1743:1743) (1947:1947:1947)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (657:657:657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~0) + (DELAY + (ABSOLUTE + (PORT datac (409:409:409) (496:496:496)) + (PORT datad (1907:1907:1907) (2156:2156:2156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~2) + (DELAY + (ABSOLUTE + (PORT datac (1788:1788:1788) (2004:2004:2004)) + (PORT datad (309:309:309) (365:365:365)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1914:1914:1914) (2142:2142:2142)) + (PORT datac (414:414:414) (501:501:501)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (697:697:697)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~6) + (DELAY + (ABSOLUTE + (PORT datac (1701:1701:1701) (1916:1916:1916)) + (PORT datad (308:308:308) (364:364:364)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~8) + (DELAY + (ABSOLUTE + (PORT datac (413:413:413) (500:500:500)) + (PORT datad (1723:1723:1723) (1912:1912:1912)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (338:338:338) (717:717:717)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~10) + (DELAY + (ABSOLUTE + (PORT datac (413:413:413) (501:501:501)) + (PORT datad (1606:1606:1606) (1785:1785:1785)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~12) + (DELAY + (ABSOLUTE + (PORT datac (410:410:410) (496:496:496)) + (PORT datad (1716:1716:1716) (1915:1915:1915)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (657:657:657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (658:658:658)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (1820:1820:1820) (2043:2043:2043)) + (PORT datad (271:271:271) (331:331:331)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~16) + (DELAY + (ABSOLUTE + (PORT datac (411:411:411) (498:498:498)) + (PORT datad (1914:1914:1914) (2124:2124:2124)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (1778:1778:1778) (1995:1995:1995)) + (PORT datad (274:274:274) (334:334:334)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (697:697:697)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~20) + (DELAY + (ABSOLUTE + (PORT datac (1729:1729:1729) (1948:1948:1948)) + (PORT datad (282:282:282) (343:343:343)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~22) + (DELAY + (ABSOLUTE + (PORT datac (1707:1707:1707) (1924:1924:1924)) + (PORT datad (277:277:277) (337:337:337)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (688:688:688)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~24) + (DELAY + (ABSOLUTE + (PORT datac (1812:1812:1812) (2037:2037:2037)) + (PORT datad (283:283:283) (344:344:344)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~26) + (DELAY + (ABSOLUTE + (PORT datac (893:893:893) (799:799:799)) + (PORT datad (278:278:278) (339:339:339)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (225:225:225) (286:286:286)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (218:218:218)) + (PORT datab (190:190:190) (229:229:229)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (193:193:193) (233:233:233)) + (PORT datab (177:177:177) (218:218:218)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (108:108:108) (89:89:89)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (210:210:210) (262:262:262)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~3) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (240:240:240)) + (PORT datab (211:211:211) (251:251:251)) + (PORT datac (263:263:263) (299:299:299)) + (PORT datad (109:109:109) (129:129:129)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (767:767:767)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (759:759:759) (731:731:731)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (749:749:749) (768:768:768)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (760:760:760) (732:732:732)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (749:749:749) (768:768:768)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (760:760:760) (732:732:732)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (196:196:196)) + (PORT datac (213:213:213) (266:266:266)) + (PORT datad (202:202:202) (248:248:248)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (186:186:186)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~2) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (241:241:241)) + (PORT datab (122:122:122) (154:154:154)) + (PORT datac (116:116:116) (143:143:143)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (749:749:749) (768:768:768)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (760:760:760) (732:732:732)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (186:186:186)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (749:749:749) (768:768:768)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (760:760:760) (732:732:732)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (749:749:749) (768:768:768)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (760:760:760) (732:732:732)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (192:192:192)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~0) + (DELAY + (ABSOLUTE + (PORT dataa (127:127:127) (162:162:162)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (184:184:184) (216:216:216)) + (PORT datad (116:116:116) (138:138:138)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (749:749:749) (768:768:768)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (760:760:760) (732:732:732)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (749:749:749) (768:768:768)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (760:760:760) (732:732:732)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (188:188:188)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (749:749:749) (768:768:768)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (760:760:760) (732:732:732)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~20) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (749:749:749) (768:768:768)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (760:760:760) (732:732:732)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (271:271:271)) + (PORT datab (136:136:136) (185:185:185)) + (PORT datac (122:122:122) (165:165:165)) + (PORT datad (121:121:121) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~1) + (DELAY + (ABSOLUTE + (PORT dataa (126:126:126) (162:162:162)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (184:184:184) (216:216:216)) + (PORT datad (116:116:116) (138:138:138)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (749:749:749) (768:768:768)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (760:760:760) (732:732:732)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (195:195:195)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (122:122:122) (165:165:165)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (239:239:239)) + (PORT datab (123:123:123) (153:153:153)) + (PORT datad (194:194:194) (227:227:227)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Clk_Ctrl) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (767:767:767)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (759:759:759) (731:731:731)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[1\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~25) + (DELAY + (ABSOLUTE + (PORT datab (1704:1704:1704) (1908:1908:1908)) + (PORT datac (289:289:289) (345:345:345)) + (PORT datad (280:280:280) (340:340:340)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (139:139:139)) + (PORT datab (190:190:190) (229:229:229)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[2\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~23) + (DELAY + (ABSOLUTE + (PORT datab (1720:1720:1720) (1943:1943:1943)) + (PORT datad (132:132:132) (169:169:169)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (218:218:218)) + (PORT datab (177:177:177) (216:216:216)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[3\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (267:267:267)) + (PORT datac (1769:1769:1769) (2008:2008:2008)) + (PORT datad (267:267:267) (327:327:327)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (392:392:392)) + (PORT datab (174:174:174) (213:213:213)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[4\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (1608:1608:1608) (1795:1795:1795)) + (PORT datac (414:414:414) (501:501:501)) + (PORT datad (345:345:345) (414:414:414)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[5\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (406:406:406)) + (PORT datab (190:190:190) (228:228:228)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[5\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (281:281:281)) + (PORT datac (1687:1687:1687) (1894:1894:1894)) + (PORT datad (273:273:273) (333:333:333)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (217:217:217)) + (PORT datab (190:190:190) (229:229:229)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[6\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~15) + (DELAY + (ABSOLUTE + (PORT datab (288:288:288) (360:360:360)) + (PORT datac (1925:1925:1925) (2196:2196:2196)) + (PORT datad (311:311:311) (373:373:373)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[7\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (387:387:387)) + (PORT datab (190:190:190) (228:228:228)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[7\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~13) + (DELAY + (ABSOLUTE + (PORT datab (1922:1922:1922) (2196:2196:2196)) + (PORT datac (191:191:191) (240:240:240)) + (PORT datad (270:270:270) (329:329:329)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[8\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (235:235:235)) + (PORT datab (327:327:327) (384:384:384)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[8\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~11) + (DELAY + (ABSOLUTE + (PORT datab (283:283:283) (354:354:354)) + (PORT datac (1677:1677:1677) (1879:1879:1879)) + (PORT datad (189:189:189) (236:236:236)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[9\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (399:399:399)) + (PORT datab (191:191:191) (230:230:230)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[9\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~9) + (DELAY + (ABSOLUTE + (PORT datab (297:297:297) (370:370:370)) + (PORT datac (1702:1702:1702) (1895:1895:1895)) + (PORT datad (199:199:199) (250:250:250)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[10\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (341:341:341)) + (PORT datab (281:281:281) (325:325:325)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~7) + (DELAY + (ABSOLUTE + (PORT datab (285:285:285) (356:356:356)) + (PORT datac (1842:1842:1842) (2079:2079:2079)) + (PORT datad (191:191:191) (237:237:237)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[11\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (405:405:405)) + (PORT datab (286:286:286) (330:330:330)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[11\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1873:1873:1873) (2113:2113:2113)) + (PORT datac (224:224:224) (281:281:281)) + (PORT datad (355:355:355) (432:432:432)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[12\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (303:303:303) (353:353:353)) + (PORT datab (194:194:194) (234:234:234)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[12\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~3) + (DELAY + (ABSOLUTE + (PORT datab (1730:1730:1730) (1944:1944:1944)) + (PORT datac (292:292:292) (348:348:348)) + (PORT datad (286:286:286) (347:347:347)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[13\]\~42) + (DELAY + (ABSOLUTE + (PORT datab (486:486:486) (565:565:565)) + (PORT datad (323:323:323) (369:369:369)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[13\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT asdata (342:342:342) (368:368:368)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~27) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (277:277:277)) + (PORT datac (1896:1896:1896) (2137:2137:2137)) + (PORT datad (284:284:284) (345:345:345)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[0\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (764:764:764) (735:735:735)) + (PORT ena (998:998:998) (1126:1126:1126)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (153:153:153) (201:201:201)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (668:668:668) (750:750:750)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (205:205:205)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (627:627:627) (697:697:697)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (201:201:201)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (912:912:912) (1024:1024:1024)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (205:205:205)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (762:762:762) (861:861:861)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (204:204:204)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (625:625:625) (702:702:702)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[6\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (202:202:202)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (526:526:526) (598:598:598)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[7\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (202:202:202)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (537:537:537) (616:616:616)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[8\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (806:806:806) (916:916:916)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (202:202:202)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (889:889:889) (994:994:994)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (205:205:205)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (776:776:776) (880:880:880)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (202:202:202)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (774:774:774) (873:873:873)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[12\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (637:637:637) (720:720:720)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[13\]\~40) + (DELAY + (ABSOLUTE + (PORT datad (133:133:133) (172:172:172)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (407:407:407) (464:464:464)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (748:748:748) (769:769:769)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (528:528:528) (602:602:602)) + (PORT clrn (761:761:761) (731:731:731)) + (PORT sload (491:491:491) (463:463:463)) + (PORT ena (811:811:811) (903:903:903)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (560:560:560) (632:632:632)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (750:750:750) (825:825:825)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (558:558:558) (630:630:630)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (570:570:570) (638:638:638)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (562:562:562) (638:638:638)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[6\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (575:575:575) (655:655:655)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[7\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (780:780:780) (870:870:870)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[8\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (786:786:786) (876:876:876)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (556:556:556) (630:630:630)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (664:664:664) (741:741:741)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (759:759:759) (840:840:840)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[12\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (130:130:130) (178:178:178)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (644:644:644) (724:724:724)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[13\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (200:200:200)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (560:560:560) (640:640:640)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (656:656:656) (728:728:728)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (498:498:498) (466:466:466)) + (PORT ena (795:795:795) (885:885:885)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (668:668:668)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (668:668:668)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult2\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT dataa[6] (218:218:218) (260:260:260)) + (PORT dataa[7] (204:204:204) (241:241:241)) + (PORT dataa[8] (214:214:214) (254:254:254)) + (PORT dataa[9] (206:206:206) (245:245:245)) + (PORT dataa[10] (314:314:314) (358:358:358)) + (PORT dataa[11] (203:203:203) (240:240:240)) + (PORT dataa[12] (204:204:204) (243:243:243)) + (PORT dataa[13] (309:309:309) (350:350:350)) + (PORT dataa[14] (316:316:316) (365:365:365)) + (PORT dataa[15] (205:205:205) (244:244:244)) + (PORT dataa[16] (311:311:311) (352:352:352)) + (PORT dataa[17] (213:213:213) (253:253:253)) + (PORT datab[10] (1772:1772:1772) (2010:2010:2010)) + (PORT datab[11] (1878:1878:1878) (2106:2106:2106)) + (PORT datab[12] (1787:1787:1787) (1989:1989:1989)) + (PORT datab[13] (1902:1902:1902) (2130:2130:2130)) + (PORT datab[14] (1887:1887:1887) (2102:2102:2102)) + (PORT datab[15] (1846:1846:1846) (2055:2055:2055)) + (PORT datab[16] (1851:1851:1851) (2073:2073:2073)) + (PORT datab[17] (1864:1864:1864) (2095:2095:2095)) + (IOPATH dataa dataout (1719:1719:1719) (1719:1719:1719)) + (IOPATH datab dataout (1676:1676:1676) (1676:1676:1676)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult2\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (61:61:61) (64:64:64)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (559:559:559) (619:619:619)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (451:451:451) (491:491:491)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (455:455:455) (495:495:495)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (452:452:452) (497:497:497)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (463:463:463) (506:506:506)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (461:461:461) (501:501:501)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (476:476:476) (529:529:529)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (474:474:474) (527:527:527)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (472:472:472) (525:525:525)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (192:192:192)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (469:469:469) (517:517:517)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (188:188:188)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (965:965:965)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (597:597:597) (664:664:664)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (682:682:682) (639:639:639)) + (PORT ena (814:814:814) (920:920:920)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (380:380:380) (457:457:457)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (310:310:310) (358:358:358)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (449:449:449) (491:491:491)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (965:965:965)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (496:496:496) (558:558:558)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (682:682:682) (639:639:639)) + (PORT ena (814:814:814) (920:920:920)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (965:965:965)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (487:487:487) (546:546:546)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (682:682:682) (639:639:639)) + (PORT ena (814:814:814) (920:920:920)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (432:432:432)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (350:350:350)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (554:554:554) (604:604:604)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (453:453:453)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (312:312:312) (360:360:360)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (337:337:337) (372:372:372)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (928:928:928) (965:965:965)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (472:472:472) (525:525:525)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (682:682:682) (639:639:639)) + (PORT ena (814:814:814) (920:920:920)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (450:450:450)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[17\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (351:351:351)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (576:576:576) (641:641:641)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (363:363:363) (442:442:442)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[18\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (314:314:314) (368:368:368)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (462:462:462) (510:510:510)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (454:454:454)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[19\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (323:323:323) (380:380:380)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (926:926:926) (959:959:959)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (561:561:561) (615:615:615)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (880:880:880) (805:805:805)) + (PORT ena (774:774:774) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (742:742:742) (762:762:762)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (526:526:526) (579:579:579)) + (PORT clrn (754:754:754) (725:725:725)) + (PORT sload (682:682:682) (639:639:639)) + (PORT ena (795:795:795) (887:887:887)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~20) + (DELAY + (ABSOLUTE + (PORT datac (199:199:199) (249:249:249)) + (PORT datad (642:642:642) (777:777:777)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (688:688:688)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult1\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT dataa[6] (220:220:220) (260:260:260)) + (PORT dataa[7] (227:227:227) (268:268:268)) + (PORT dataa[8] (317:317:317) (363:363:363)) + (PORT dataa[9] (229:229:229) (271:271:271)) + (PORT dataa[10] (332:332:332) (384:384:384)) + (PORT dataa[11] (225:225:225) (265:265:265)) + (PORT dataa[12] (217:217:217) (255:255:255)) + (PORT dataa[13] (320:320:320) (360:360:360)) + (PORT dataa[14] (221:221:221) (266:266:266)) + (PORT dataa[15] (219:219:219) (257:257:257)) + (PORT dataa[16] (321:321:321) (362:362:362)) + (PORT dataa[17] (226:226:226) (265:265:265)) + (PORT datab[10] (1744:1744:1744) (1938:1938:1938)) + (PORT datab[11] (1921:1921:1921) (2153:2153:2153)) + (PORT datab[12] (1965:1965:1965) (2227:2227:2227)) + (PORT datab[13] (1912:1912:1912) (2167:2167:2167)) + (PORT datab[14] (1918:1918:1918) (2140:2140:2140)) + (PORT datab[15] (1950:1950:1950) (2182:2182:2182)) + (PORT datab[16] (1775:1775:1775) (1964:1964:1964)) + (PORT datab[17] (1751:1751:1751) (1957:1957:1957)) + (IOPATH dataa dataout (1719:1719:1719) (1719:1719:1719)) + (IOPATH datab dataout (1676:1676:1676) (1676:1676:1676)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult1\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (61:61:61) (64:64:64)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (934:934:934) (971:971:971)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (585:585:585) (644:644:644)) + (PORT clrn (761:761:761) (732:732:732)) + (PORT sload (1074:1074:1074) (970:970:970)) + (PORT ena (932:932:932) (1039:1039:1039)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (934:934:934) (971:971:971)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (618:618:618) (693:693:693)) + (PORT clrn (761:761:761) (732:732:732)) + (PORT sload (1074:1074:1074) (970:970:970)) + (PORT ena (932:932:932) (1039:1039:1039)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (934:934:934) (971:971:971)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (620:620:620) (680:680:680)) + (PORT clrn (761:761:761) (732:732:732)) + (PORT sload (1074:1074:1074) (970:970:970)) + (PORT ena (932:932:932) (1039:1039:1039)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (934:934:934) (971:971:971)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (616:616:616) (685:685:685)) + (PORT clrn (761:761:761) (732:732:732)) + (PORT sload (1074:1074:1074) (970:970:970)) + (PORT ena (932:932:932) (1039:1039:1039)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (934:934:934) (971:971:971)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (603:603:603) (670:670:670)) + (PORT clrn (761:761:761) (732:732:732)) + (PORT sload (1074:1074:1074) (970:970:970)) + (PORT ena (932:932:932) (1039:1039:1039)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (934:934:934) (971:971:971)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (603:603:603) (665:665:665)) + (PORT clrn (761:761:761) (732:732:732)) + (PORT sload (1074:1074:1074) (970:970:970)) + (PORT ena (932:932:932) (1039:1039:1039)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (934:934:934) (971:971:971)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (602:602:602) (665:665:665)) + (PORT clrn (761:761:761) (732:732:732)) + (PORT sload (1074:1074:1074) (970:970:970)) + (PORT ena (932:932:932) (1039:1039:1039)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (934:934:934) (971:971:971)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (602:602:602) (664:664:664)) + (PORT clrn (761:761:761) (732:732:732)) + (PORT sload (1074:1074:1074) (970:970:970)) + (PORT ena (932:932:932) (1039:1039:1039)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (934:934:934) (971:971:971)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (622:622:622) (698:698:698)) + (PORT clrn (761:761:761) (732:732:732)) + (PORT sload (1074:1074:1074) (970:970:970)) + (PORT ena (932:932:932) (1039:1039:1039)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (192:192:192)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (934:934:934) (971:971:971)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (630:630:630) (710:710:710)) + (PORT clrn (761:761:761) (732:732:732)) + (PORT sload (1074:1074:1074) (970:970:970)) + (PORT ena (932:932:932) (1039:1039:1039)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (929:929:929) (963:963:963)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (569:569:569) (624:624:624)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (1080:1080:1080) (976:976:976)) + (PORT ena (940:940:940) (1052:1052:1052)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (929:929:929) (963:963:963)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (337:337:337) (373:373:373)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (1080:1080:1080) (976:976:976)) + (PORT ena (940:940:940) (1052:1052:1052)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (929:929:929) (963:963:963)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (439:439:439) (479:479:479)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (1080:1080:1080) (976:976:976)) + (PORT ena (940:940:940) (1052:1052:1052)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (929:929:929) (963:963:963)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (336:336:336) (372:372:372)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (1080:1080:1080) (976:976:976)) + (PORT ena (940:940:940) (1052:1052:1052)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (929:929:929) (963:963:963)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (442:442:442) (482:482:482)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (1080:1080:1080) (976:976:976)) + (PORT ena (940:940:940) (1052:1052:1052)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (929:929:929) (963:963:963)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (336:336:336) (372:372:372)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (1080:1080:1080) (976:976:976)) + (PORT ena (940:940:940) (1052:1052:1052)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (929:929:929) (963:963:963)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (338:338:338) (374:374:374)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (1080:1080:1080) (976:976:976)) + (PORT ena (940:940:940) (1052:1052:1052)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (191:191:191)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (929:929:929) (963:963:963)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (440:440:440) (479:479:479)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (1080:1080:1080) (976:976:976)) + (PORT ena (940:940:940) (1052:1052:1052)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (191:191:191)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (929:929:929) (963:963:963)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (460:460:460) (507:507:507)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (1080:1080:1080) (976:976:976)) + (PORT ena (940:940:940) (1052:1052:1052)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (929:929:929) (963:963:963)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (336:336:336) (372:372:372)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (1080:1080:1080) (976:976:976)) + (PORT ena (940:940:940) (1052:1052:1052)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (745:745:745) (765:765:765)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (280:280:280) (299:299:299)) + (PORT clrn (757:757:757) (728:728:728)) + (PORT sload (1080:1080:1080) (976:976:976)) + (PORT ena (908:908:908) (1010:1010:1010)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (657:657:657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_data_reg") + (INSTANCE Mult0\|auto_generated\|mac_mult1.dataa_reg) + (DELAY + (ABSOLUTE + (PORT data[0] (110:110:110) (112:112:112)) + (PORT data[1] (110:110:110) (112:112:112)) + (PORT data[2] (110:110:110) (112:112:112)) + (PORT data[3] (110:110:110) (112:112:112)) + (PORT data[4] (278:278:278) (301:301:301)) + (PORT data[5] (379:379:379) (413:413:413)) + (PORT data[6] (277:277:277) (302:302:302)) + (PORT data[7] (408:408:408) (438:438:438)) + (PORT data[8] (274:274:274) (296:296:296)) + (PORT data[9] (290:290:290) (318:318:318)) + (PORT data[10] (381:381:381) (415:415:415)) + (PORT data[11] (274:274:274) (295:295:295)) + (PORT data[12] (289:289:289) (316:316:316)) + (PORT data[13] (275:275:275) (296:296:296)) + (PORT data[14] (275:275:275) (296:296:296)) + (PORT data[15] (290:290:290) (317:317:317)) + (PORT data[16] (381:381:381) (407:407:407)) + (PORT data[17] (278:278:278) (301:301:301)) + (PORT clk (711:711:711) (747:747:747)) + (PORT ena (1003:1003:1003) (1099:1099:1099)) + (PORT aclr (806:806:806) (796:796:796)) + (IOPATH (posedge aclr) dataout (110:110:110) (110:110:110)) + (IOPATH (posedge clk) dataout (146:146:146) (146:146:146)) + ) + ) + (TIMINGCHECK + (SETUP data (posedge clk) (108:108:108)) + (SETUP ena (posedge clk) (108:108:108)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult0\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT datab[10] (1801:1801:1801) (1994:1994:1994)) + (PORT datab[11] (2002:2002:2002) (2245:2245:2245)) + (PORT datab[12] (1805:1805:1805) (2036:2036:2036)) + (PORT datab[13] (1768:1768:1768) (1972:1972:1972)) + (PORT datab[14] (1685:1685:1685) (1883:1883:1883)) + (PORT datab[15] (1810:1810:1810) (2037:2037:2037)) + (PORT datab[16] (1894:1894:1894) (2129:2129:2129)) + (PORT datab[17] (1771:1771:1771) (1985:1985:1985)) + (IOPATH dataa dataout (1606:1606:1606) (1606:1606:1606)) + (IOPATH datab dataout (1676:1676:1676) (1676:1676:1676)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult0\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (61:61:61) (64:64:64)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (740:740:740) (759:759:759)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (619:619:619) (691:691:691)) + (PORT clrn (751:751:751) (723:723:723)) + (PORT sload (863:863:863) (795:795:795)) + (PORT ena (973:973:973) (1098:1098:1098)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (740:740:740) (759:759:759)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (628:628:628) (699:699:699)) + (PORT clrn (751:751:751) (723:723:723)) + (PORT sload (863:863:863) (795:795:795)) + (PORT ena (973:973:973) (1098:1098:1098)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (740:740:740) (759:759:759)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (620:620:620) (691:691:691)) + (PORT clrn (751:751:751) (723:723:723)) + (PORT sload (863:863:863) (795:795:795)) + (PORT ena (973:973:973) (1098:1098:1098)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (740:740:740) (759:759:759)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (637:637:637) (719:719:719)) + (PORT clrn (751:751:751) (723:723:723)) + (PORT sload (863:863:863) (795:795:795)) + (PORT ena (973:973:973) (1098:1098:1098)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (740:740:740) (759:759:759)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (624:624:624) (696:696:696)) + (PORT clrn (751:751:751) (723:723:723)) + (PORT sload (863:863:863) (795:795:795)) + (PORT ena (973:973:973) (1098:1098:1098)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (740:740:740) (759:759:759)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (614:614:614) (682:682:682)) + (PORT clrn (751:751:751) (723:723:723)) + (PORT sload (863:863:863) (795:795:795)) + (PORT ena (973:973:973) (1098:1098:1098)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (740:740:740) (759:759:759)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (610:610:610) (678:678:678)) + (PORT clrn (751:751:751) (723:723:723)) + (PORT sload (863:863:863) (795:795:795)) + (PORT ena (973:973:973) (1098:1098:1098)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (740:740:740) (759:759:759)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (717:717:717) (800:800:800)) + (PORT clrn (751:751:751) (723:723:723)) + (PORT sload (863:863:863) (795:795:795)) + (PORT ena (973:973:973) (1098:1098:1098)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (740:740:740) (759:759:759)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (638:638:638) (703:703:703)) + (PORT clrn (751:751:751) (723:723:723)) + (PORT sload (863:863:863) (795:795:795)) + (PORT ena (973:973:973) (1098:1098:1098)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (192:192:192)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (740:740:740) (759:759:759)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (607:607:607) (670:670:670)) + (PORT clrn (751:751:751) (723:723:723)) + (PORT sload (863:863:863) (795:795:795)) + (PORT ena (973:973:973) (1098:1098:1098)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (741:741:741) (761:761:761)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (616:616:616) (680:680:680)) + (PORT clrn (753:753:753) (724:724:724)) + (PORT sload (893:893:893) (816:816:816)) + (PORT ena (945:945:945) (1059:1059:1059)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (741:741:741) (761:761:761)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (697:697:697) (766:766:766)) + (PORT clrn (753:753:753) (724:724:724)) + (PORT sload (893:893:893) (816:816:816)) + (PORT ena (945:945:945) (1059:1059:1059)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (741:741:741) (761:761:761)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (479:479:479) (533:533:533)) + (PORT clrn (753:753:753) (724:724:724)) + (PORT sload (893:893:893) (816:816:816)) + (PORT ena (945:945:945) (1059:1059:1059)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (741:741:741) (761:761:761)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (487:487:487) (542:542:542)) + (PORT clrn (753:753:753) (724:724:724)) + (PORT sload (893:893:893) (816:816:816)) + (PORT ena (945:945:945) (1059:1059:1059)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (741:741:741) (761:761:761)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (598:598:598) (659:659:659)) + (PORT clrn (753:753:753) (724:724:724)) + (PORT sload (893:893:893) (816:816:816)) + (PORT ena (945:945:945) (1059:1059:1059)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (741:741:741) (761:761:761)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (497:497:497) (554:554:554)) + (PORT clrn (753:753:753) (724:724:724)) + (PORT sload (893:893:893) (816:816:816)) + (PORT ena (945:945:945) (1059:1059:1059)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (741:741:741) (761:761:761)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (610:610:610) (674:674:674)) + (PORT clrn (753:753:753) (724:724:724)) + (PORT sload (893:893:893) (816:816:816)) + (PORT ena (945:945:945) (1059:1059:1059)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (191:191:191)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (741:741:741) (761:761:761)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (495:495:495) (552:552:552)) + (PORT clrn (753:753:753) (724:724:724)) + (PORT sload (893:893:893) (816:816:816)) + (PORT ena (945:945:945) (1059:1059:1059)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (191:191:191)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (741:741:741) (761:761:761)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (749:749:749) (834:834:834)) + (PORT clrn (753:753:753) (724:724:724)) + (PORT sload (893:893:893) (816:816:816)) + (PORT ena (945:945:945) (1059:1059:1059)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (741:741:741) (761:761:761)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (603:603:603) (663:663:663)) + (PORT clrn (753:753:753) (724:724:724)) + (PORT sload (893:893:893) (816:816:816)) + (PORT ena (945:945:945) (1059:1059:1059)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (741:741:741) (761:761:761)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (630:630:630) (694:694:694)) + (PORT clrn (753:753:753) (724:724:724)) + (PORT sload (893:893:893) (816:816:816)) + (PORT ena (945:945:945) (1059:1059:1059)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (445:445:445)) + (PORT datab (335:335:335) (399:399:399)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (433:433:433)) + (PORT datab (377:377:377) (452:452:452)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~4) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (445:445:445)) + (PORT datab (212:212:212) (268:268:268)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~6) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (603:603:603)) + (PORT datab (227:227:227) (283:283:283)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~8) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (272:272:272)) + (PORT datab (382:382:382) (459:459:459)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~10) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (402:402:402)) + (PORT datab (381:381:381) (458:458:458)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~12) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (403:403:403)) + (PORT datab (512:512:512) (610:610:610)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~14) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (572:572:572)) + (PORT datab (338:338:338) (409:409:409)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~24) + (DELAY + (ABSOLUTE + (PORT dataa (501:501:501) (589:589:589)) + (PORT datab (212:212:212) (268:268:268)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~27) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (289:289:289)) + (PORT datab (493:493:493) (578:578:578)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~30) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (692:692:692)) + (PORT datab (227:227:227) (283:283:283)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~33) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (274:274:274)) + (PORT datab (369:369:369) (447:447:447)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~36) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (287:287:287)) + (PORT datab (380:380:380) (456:456:456)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~39) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (275:275:275)) + (PORT datab (382:382:382) (459:459:459)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~42) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (818:818:818)) + (PORT datab (227:227:227) (283:283:283)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~45) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (428:428:428)) + (PORT datab (489:489:489) (574:574:574)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~48) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (436:436:436)) + (PORT datab (508:508:508) (614:614:614)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) 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(63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~57) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (608:608:608)) + (PORT datab (357:357:357) (427:427:427)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~60) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (273:273:273)) + (PORT datad (468:468:468) (545:545:545)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + 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"cycloneive_lcell_comb") + (INSTANCE Add7\~6) + (DELAY + (ABSOLUTE + (PORT datac (460:460:460) (538:538:538)) + (PORT datad (563:563:563) (661:661:661)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~22) + (DELAY + (ABSOLUTE + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (563:563:563) (661:661:661)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~23) + (DELAY + (ABSOLUTE + (PORT datab (541:541:541) (640:640:640)) + (PORT datac (223:223:223) (272:272:272)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~7) + (DELAY + (ABSOLUTE + (PORT datac (214:214:214) (267:267:267)) + (PORT datad (637:637:637) (771:771:771)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (593:593:593) (704:704:704)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (281:281:281)) + (PORT datab (240:240:240) (293:293:293)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (211:211:211)) + (PORT datab (104:104:104) (133:133:133)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (286:286:286)) + (PORT datab (317:317:317) (368:368:368)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (297:297:297)) + (PORT datab (104:104:104) (133:133:133)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (213:213:213)) + (PORT datab (224:224:224) (277:277:277)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (429:429:429)) + (PORT datab (242:242:242) (295:295:295)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (528:528:528) (628:628:628)) + (PORT datab (104:104:104) (133:133:133)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + 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(INSTANCE Add5\~26) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (193:193:193)) + (PORT datac (524:524:524) (619:619:619)) + (PORT datad (215:215:215) (258:258:258)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (576:576:576) (686:686:686)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[2\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (759:759:759) (780:780:780)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (772:772:772) (742:742:742)) + (PORT ena (965:965:965) (1076:1076:1076)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~29) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (197:197:197)) + (PORT datab (541:541:541) (640:640:640)) + (PORT datac (226:226:226) (275:275:275)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (527:527:527) (616:616:616)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[3\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (1006:1006:1006)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (769:769:769) (739:739:739)) + (PORT ena (952:952:952) (1051:1051:1051)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~32) + (DELAY + (ABSOLUTE + (PORT datab (174:174:174) (228:228:228)) + (PORT datac (227:227:227) (277:277:277)) + (PORT datad (132:132:132) (170:170:170)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[4\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (299:299:299)) + (PORT datab (190:190:190) (227:227:227)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[4\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (756:756:756) (777:777:777)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (769:769:769) (739:739:739)) + (PORT ena (1146:1146:1146) (1293:1293:1293)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~35) + (DELAY + (ABSOLUTE + (PORT datab (316:316:316) (396:396:396)) + (PORT datac (349:349:349) (414:414:414)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[5\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (211:211:211)) + (PORT datab (105:105:105) (134:134:134)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[5\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (756:756:756) (777:777:777)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (769:769:769) (739:739:739)) + (PORT ena (1146:1146:1146) (1293:1293:1293)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~38) + (DELAY + (ABSOLUTE + (PORT datab (174:174:174) (229:229:229)) + (PORT datac (131:131:131) (173:173:173)) + (PORT datad (225:225:225) (272:272:272)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[6\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (693:693:693)) + (PORT datab (239:239:239) (291:291:291)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[6\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (1006:1006:1006)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (769:769:769) (739:739:739)) + (PORT ena (952:952:952) (1051:1051:1051)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~41) + (DELAY + (ABSOLUTE + (PORT datab (316:316:316) (396:396:396)) + (PORT datac (241:241:241) (304:304:304)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[7\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (170:170:170) (206:206:206)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[7\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (1006:1006:1006)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (769:769:769) (739:739:739)) + (PORT ena (952:952:952) (1051:1051:1051)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~44) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (193:193:193)) + (PORT datac (225:225:225) (274:274:274)) + (PORT datad (160:160:160) (206:206:206)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[8\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (228:228:228)) + (PORT datab (371:371:371) (444:444:444)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[8\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (1006:1006:1006)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (769:769:769) (739:739:739)) + (PORT ena (952:952:952) (1051:1051:1051)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~47) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (345:345:345)) + (PORT datab (316:316:316) (396:396:396)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[9\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (688:688:688)) + (PORT datab (103:103:103) (133:133:133)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[9\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (1006:1006:1006)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (769:769:769) (739:739:739)) + (PORT ena (952:952:952) (1051:1051:1051)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~50) + (DELAY + (ABSOLUTE + (PORT datab (174:174:174) (228:228:228)) + (PORT datac (223:223:223) (273:273:273)) + (PORT datad (130:130:130) (167:167:167)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[10\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (574:574:574) (686:686:686)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[10\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (1006:1006:1006)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (769:769:769) (739:739:739)) + (PORT ena (952:952:952) (1051:1051:1051)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~53) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (191:191:191)) + (PORT datac (222:222:222) (271:271:271)) + (PORT datad (160:160:160) (204:204:204)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[11\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (229:229:229)) + (PORT datab (224:224:224) (276:276:276)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[11\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (1006:1006:1006)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (769:769:769) (739:739:739)) + (PORT ena (952:952:952) (1051:1051:1051)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~56) + (DELAY + (ABSOLUTE + (PORT datab (316:316:316) (397:397:397)) + (PORT datac (246:246:246) (308:308:308)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[12\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (226:226:226)) + (PORT datab (238:238:238) (289:289:289)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[12\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (1006:1006:1006)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (769:769:769) (739:739:739)) + (PORT ena (952:952:952) (1051:1051:1051)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~59) + (DELAY + (ABSOLUTE + (PORT datab (251:251:251) (325:325:325)) + (PORT datac (377:377:377) (444:444:444)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[13\]\~54) + (DELAY + (ABSOLUTE + (PORT datab (536:536:536) (627:627:627)) + (PORT datad (168:168:168) (196:196:196)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[13\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (1006:1006:1006)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (769:769:769) (739:739:739)) + (PORT ena (952:952:952) (1051:1051:1051)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~0) + (DELAY + (ABSOLUTE + (PORT datac (587:587:587) (699:699:699)) + (PORT datad (209:209:209) (258:258:258)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[0\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (962:962:962) (1010:1010:1010)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (772:772:772) (742:742:742)) + (PORT ena (1152:1152:1152) (1290:1290:1290)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) +) diff --git a/pid/simulation/modelsim/pid_modelsim.xrf b/pid/simulation/modelsim/pid_modelsim.xrf new file mode 100644 index 0000000..1a62512 --- /dev/null +++ b/pid/simulation/modelsim/pid_modelsim.xrf @@ -0,0 +1,467 @@ +vendor_name = ModelSim +source_file = 1, F:/Code/FPGA/reserve/pid/rtl/pid.v +source_file = 1, F:/Code/FPGA/reserve/pid/testbench/pid_tb.v +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/aglobal181.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/multcore.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/bypassff.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/altshift.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/cbx.lst +source_file = 1, F:/Code/FPGA/reserve/pid/db/mult_gbt.tdf +source_file = 1, F:/Code/FPGA/reserve/pid/db/mult_kbt.tdf +design_name = pid +instance = comp, \Vout[0]~output , Vout[0]~output, pid, 1 +instance = comp, \Vout[1]~output , Vout[1]~output, pid, 1 +instance = comp, \Vout[2]~output , Vout[2]~output, pid, 1 +instance = comp, \Vout[3]~output , Vout[3]~output, pid, 1 +instance = comp, \Vout[4]~output , Vout[4]~output, pid, 1 +instance = comp, \Vout[5]~output , Vout[5]~output, pid, 1 +instance = comp, \Vout[6]~output , Vout[6]~output, pid, 1 +instance = comp, \Vout[7]~output , Vout[7]~output, pid, 1 +instance = comp, \Vout[8]~output , Vout[8]~output, pid, 1 +instance = comp, \Vout[9]~output , Vout[9]~output, pid, 1 +instance = comp, \Vout[10]~output , Vout[10]~output, pid, 1 +instance = comp, \Vout[11]~output , Vout[11]~output, pid, 1 +instance = comp, \Vout[12]~output , Vout[12]~output, pid, 1 +instance = comp, \Vout[13]~output , Vout[13]~output, pid, 1 +instance = comp, \clk~input , clk~input, pid, 1 +instance = comp, \clk~inputclkctrl , clk~inputclkctrl, pid, 1 +instance = comp, \Kd_Out[0]~21 , Kd_Out[0]~21, pid, 1 +instance = comp, \EE2[0]~14 , EE2[0]~14, pid, 1 +instance = comp, \EE1[0]~14 , EE1[0]~14, pid, 1 +instance = comp, \SetPoint[0]~input , SetPoint[0]~input, pid, 1 +instance = comp, \Sample[13]~input , Sample[13]~input, pid, 1 +instance = comp, \Add1~1 , Add1~1, pid, 1 +instance = comp, \SetPoint[13]~input , SetPoint[13]~input, pid, 1 +instance = comp, \Add1~0 , Add1~0, pid, 1 +instance = comp, \Sample[12]~input , Sample[12]~input, pid, 1 +instance = comp, \Add1~2 , Add1~2, pid, 1 +instance = comp, \SetPoint[12]~input , SetPoint[12]~input, pid, 1 +instance = comp, \Sample[11]~input , Sample[11]~input, pid, 1 +instance = comp, \Add1~4 , Add1~4, pid, 1 +instance = comp, \SetPoint[11]~input , SetPoint[11]~input, pid, 1 +instance = comp, \SetPoint[10]~input , SetPoint[10]~input, pid, 1 +instance = comp, \Sample[10]~input , Sample[10]~input, pid, 1 +instance = comp, \Add1~6 , Add1~6, pid, 1 +instance = comp, \Sample[9]~input , Sample[9]~input, pid, 1 +instance = comp, \Add1~8 , Add1~8, pid, 1 +instance = comp, \SetPoint[9]~input , SetPoint[9]~input, pid, 1 +instance = comp, \SetPoint[8]~input , SetPoint[8]~input, pid, 1 +instance = comp, \Sample[8]~input , Sample[8]~input, pid, 1 +instance = comp, \Add1~10 , Add1~10, pid, 1 +instance = comp, \Sample[7]~input , Sample[7]~input, pid, 1 +instance = comp, \Add1~12 , Add1~12, pid, 1 +instance = comp, \SetPoint[7]~input , SetPoint[7]~input, pid, 1 +instance = comp, \SetPoint[6]~input , SetPoint[6]~input, pid, 1 +instance = comp, \Sample[6]~input , Sample[6]~input, pid, 1 +instance = comp, \Add1~14 , Add1~14, pid, 1 +instance = comp, \Sample[5]~input , Sample[5]~input, pid, 1 +instance = comp, \Add1~16 , Add1~16, pid, 1 +instance = comp, \SetPoint[4]~input , SetPoint[4]~input, pid, 1 +instance = comp, \Sample[4]~input , Sample[4]~input, pid, 1 +instance = comp, \Add1~18 , Add1~18, pid, 1 +instance = comp, \Sample[3]~input , Sample[3]~input, pid, 1 +instance = comp, \Add1~20 , Add1~20, pid, 1 +instance = comp, \SetPoint[2]~input , SetPoint[2]~input, pid, 1 +instance = comp, \Sample[2]~input , Sample[2]~input, pid, 1 +instance = comp, \Add1~22 , Add1~22, pid, 1 +instance = comp, \Sample[1]~input , Sample[1]~input, pid, 1 +instance = comp, \Add1~24 , Add1~24, pid, 1 +instance = comp, \SetPoint[1]~input , SetPoint[1]~input, pid, 1 +instance = comp, \Sample[0]~input , Sample[0]~input, pid, 1 +instance = comp, \Add1~26 , Add1~26, pid, 1 +instance = comp, \EE0[0]~15 , EE0[0]~15, pid, 1 +instance = comp, \EE0[0]~16 , EE0[0]~16, pid, 1 +instance = comp, \EE0[1]~18 , EE0[1]~18, pid, 1 +instance = comp, \rst_n~input , rst_n~input, pid, 1 +instance = comp, \rst_n~inputclkctrl , rst_n~inputclkctrl, pid, 1 +instance = comp, \Add0~0 , Add0~0, pid, 1 +instance = comp, \period~3 , period~3, pid, 1 +instance = comp, \period[0] , period[0], pid, 1 +instance = comp, \Add0~2 , Add0~2, pid, 1 +instance = comp, \period[1] , period[1], pid, 1 +instance = comp, \Add0~4 , Add0~4, pid, 1 +instance = comp, \period[2] , period[2], pid, 1 +instance = comp, \Equal0~2 , Equal0~2, pid, 1 +instance = comp, \Add0~6 , Add0~6, pid, 1 +instance = comp, \period~2 , period~2, pid, 1 +instance = comp, \period[3] , period[3], pid, 1 +instance = comp, \Add0~8 , Add0~8, pid, 1 +instance = comp, \period[4] , period[4], pid, 1 +instance = comp, \Add0~10 , Add0~10, pid, 1 +instance = comp, \period[5] , period[5], pid, 1 +instance = comp, \Add0~12 , Add0~12, pid, 1 +instance = comp, \Add0~14 , Add0~14, pid, 1 +instance = comp, \period~0 , period~0, pid, 1 +instance = comp, \period[7] , period[7], pid, 1 +instance = comp, \Add0~16 , Add0~16, pid, 1 +instance = comp, \period[8] , period[8], pid, 1 +instance = comp, \Add0~18 , Add0~18, pid, 1 +instance = comp, \period[9] , period[9], pid, 1 +instance = comp, \Add0~20 , Add0~20, pid, 1 +instance = comp, \period[10] , period[10], pid, 1 +instance = comp, \Equal0~0 , Equal0~0, pid, 1 +instance = comp, \period~1 , period~1, pid, 1 +instance = comp, \period[6] , period[6], pid, 1 +instance = comp, \Equal0~1 , Equal0~1, pid, 1 +instance = comp, \Equal0~3 , Equal0~3, pid, 1 +instance = comp, \EE0[1]~_Duplicate_1 , EE0[1]~_Duplicate_1, pid, 1 +instance = comp, \Add1~25 , Add1~25, pid, 1 +instance = comp, \EE0[2]~20 , EE0[2]~20, pid, 1 +instance = comp, \EE0[2]~_Duplicate_1 , EE0[2]~_Duplicate_1, pid, 1 +instance = comp, \Add1~23 , Add1~23, pid, 1 +instance = comp, \EE0[3]~22 , EE0[3]~22, pid, 1 +instance = comp, \EE0[3]~_Duplicate_1 , EE0[3]~_Duplicate_1, pid, 1 +instance = comp, \SetPoint[3]~input , SetPoint[3]~input, pid, 1 +instance = comp, \Add1~21 , Add1~21, pid, 1 +instance = comp, \EE0[4]~24 , EE0[4]~24, pid, 1 +instance = comp, \EE0[4]~_Duplicate_1 , EE0[4]~_Duplicate_1, pid, 1 +instance = comp, \Add1~19 , Add1~19, pid, 1 +instance = comp, \EE0[5]~26 , EE0[5]~26, pid, 1 +instance = comp, \EE0[5]~_Duplicate_1 , EE0[5]~_Duplicate_1, pid, 1 +instance = comp, \SetPoint[5]~input , SetPoint[5]~input, pid, 1 +instance = comp, \Add1~17 , Add1~17, pid, 1 +instance = comp, \EE0[6]~28 , EE0[6]~28, pid, 1 +instance = comp, \EE0[6]~_Duplicate_1 , EE0[6]~_Duplicate_1, pid, 1 +instance = comp, \Add1~15 , Add1~15, pid, 1 +instance = comp, \EE0[7]~30 , EE0[7]~30, pid, 1 +instance = comp, \EE0[7]~_Duplicate_1 , EE0[7]~_Duplicate_1, pid, 1 +instance = comp, \Add1~13 , Add1~13, pid, 1 +instance = comp, \EE0[8]~32 , EE0[8]~32, pid, 1 +instance = comp, \EE0[8]~_Duplicate_1 , EE0[8]~_Duplicate_1, pid, 1 +instance = comp, \Add1~11 , Add1~11, pid, 1 +instance = comp, \EE0[9]~34 , EE0[9]~34, pid, 1 +instance = comp, \EE0[9]~_Duplicate_1 , EE0[9]~_Duplicate_1, pid, 1 +instance = comp, \Add1~9 , Add1~9, pid, 1 +instance = comp, \EE0[10]~36 , EE0[10]~36, pid, 1 +instance = comp, \EE0[10]~_Duplicate_1 , EE0[10]~_Duplicate_1, pid, 1 +instance = comp, \Add1~7 , Add1~7, pid, 1 +instance = comp, \EE0[11]~38 , EE0[11]~38, pid, 1 +instance = comp, \EE0[11]~_Duplicate_1 , EE0[11]~_Duplicate_1, pid, 1 +instance = comp, \Add1~5 , Add1~5, pid, 1 +instance = comp, \EE0[12]~40 , EE0[12]~40, pid, 1 +instance = comp, \EE0[12]~_Duplicate_1 , EE0[12]~_Duplicate_1, pid, 1 +instance = comp, \Add1~3 , Add1~3, pid, 1 +instance = comp, \EE0[13]~42 , EE0[13]~42, pid, 1 +instance = comp, \EE0[13]~_Duplicate_1 , EE0[13]~_Duplicate_1, pid, 1 +instance = comp, \Add1~27 , Add1~27, pid, 1 +instance = comp, \EE0[0]~_Duplicate_1 , EE0[0]~_Duplicate_1, pid, 1 +instance = comp, \EE1[1]~16 , EE1[1]~16, pid, 1 +instance = comp, \EE1[1] , EE1[1], pid, 1 +instance = comp, \EE1[2]~18 , EE1[2]~18, pid, 1 +instance = comp, \EE1[2] , EE1[2], pid, 1 +instance = comp, \EE1[3]~20 , EE1[3]~20, pid, 1 +instance = comp, \EE1[3] , EE1[3], pid, 1 +instance = comp, \EE1[4]~22 , EE1[4]~22, pid, 1 +instance = comp, \EE1[4] , EE1[4], pid, 1 +instance = comp, \EE1[5]~24 , EE1[5]~24, pid, 1 +instance = comp, \EE1[5] , EE1[5], pid, 1 +instance = comp, \EE1[6]~26 , EE1[6]~26, pid, 1 +instance = comp, \EE1[6] , EE1[6], pid, 1 +instance = comp, \EE1[7]~28 , EE1[7]~28, pid, 1 +instance = comp, \EE1[7] , EE1[7], pid, 1 +instance = comp, \EE1[8]~30 , EE1[8]~30, pid, 1 +instance = comp, \EE1[8] , EE1[8], pid, 1 +instance = comp, \EE1[9]~32 , EE1[9]~32, pid, 1 +instance = comp, \EE1[9] , EE1[9], pid, 1 +instance = comp, \EE1[10]~34 , EE1[10]~34, pid, 1 +instance = comp, \EE1[10] , EE1[10], pid, 1 +instance = comp, \EE1[11]~36 , EE1[11]~36, pid, 1 +instance = comp, \EE1[11] , EE1[11], pid, 1 +instance = comp, \EE1[12]~38 , EE1[12]~38, pid, 1 +instance = comp, \EE1[12] , EE1[12], pid, 1 +instance = comp, \EE1[13]~40 , EE1[13]~40, pid, 1 +instance = comp, \EE1[13] , EE1[13], pid, 1 +instance = comp, \EE1[0] , EE1[0], pid, 1 +instance = comp, \EE2[1]~16 , EE2[1]~16, pid, 1 +instance = comp, \EE2[1] , EE2[1], pid, 1 +instance = comp, \EE2[2]~18 , EE2[2]~18, pid, 1 +instance = comp, \EE2[2] , EE2[2], pid, 1 +instance = comp, \EE2[3]~20 , EE2[3]~20, pid, 1 +instance = comp, \EE2[3] , EE2[3], pid, 1 +instance = comp, \EE2[4]~22 , EE2[4]~22, pid, 1 +instance = comp, \EE2[4] , EE2[4], pid, 1 +instance = comp, \EE2[5]~24 , EE2[5]~24, pid, 1 +instance = comp, \EE2[5] , EE2[5], pid, 1 +instance = comp, \EE2[6]~26 , EE2[6]~26, pid, 1 +instance = comp, \EE2[6] , EE2[6], pid, 1 +instance = comp, \EE2[7]~28 , EE2[7]~28, pid, 1 +instance = comp, \EE2[7] , EE2[7], pid, 1 +instance = comp, \EE2[8]~30 , EE2[8]~30, pid, 1 +instance = comp, \EE2[8] , EE2[8], pid, 1 +instance = comp, \EE2[9]~32 , EE2[9]~32, pid, 1 +instance = comp, \EE2[9] , EE2[9], pid, 1 +instance = comp, \EE2[10]~34 , EE2[10]~34, pid, 1 +instance = comp, \EE2[10] , EE2[10], pid, 1 +instance = comp, \EE2[11]~36 , EE2[11]~36, pid, 1 +instance = comp, \EE2[11] , EE2[11], pid, 1 +instance = comp, \EE2[12]~38 , EE2[12]~38, pid, 1 +instance = comp, \EE2[12] , EE2[12], pid, 1 +instance = comp, \EE2[13]~40 , EE2[13]~40, pid, 1 +instance = comp, \EE2[13] , EE2[13], pid, 1 +instance = comp, \EE2[0] , EE2[0], pid, 1 +instance = comp, \Kd[0]~input , Kd[0]~input, pid, 1 +instance = comp, \Kd[1]~input , Kd[1]~input, pid, 1 +instance = comp, \Kd[2]~input , Kd[2]~input, pid, 1 +instance = comp, \Kd[3]~input , Kd[3]~input, pid, 1 +instance = comp, \Kd[4]~input , Kd[4]~input, pid, 1 +instance = comp, \Kd[5]~input , Kd[5]~input, pid, 1 +instance = comp, \Kd[6]~input , Kd[6]~input, pid, 1 +instance = comp, \Kd[7]~input , Kd[7]~input, pid, 1 +instance = comp, \Mult2|auto_generated|mac_mult1 , Mult2|auto_generated|mac_mult1, pid, 1 +instance = comp, \Mult2|auto_generated|mac_out2 , Mult2|auto_generated|mac_out2, pid, 1 +instance = comp, \Kd_Out[0] , Kd_Out[0], pid, 1 +instance = comp, \Kd_Out[1]~23 , Kd_Out[1]~23, pid, 1 +instance = comp, \Kd_Out[1] , Kd_Out[1], pid, 1 +instance = comp, \Kd_Out[2]~25 , Kd_Out[2]~25, pid, 1 +instance = comp, \Kd_Out[2] , Kd_Out[2], pid, 1 +instance = comp, \Kd_Out[3]~27 , Kd_Out[3]~27, pid, 1 +instance = comp, \Kd_Out[3] , Kd_Out[3], pid, 1 +instance = comp, \Kd_Out[4]~29 , Kd_Out[4]~29, pid, 1 +instance = comp, \Kd_Out[4] , Kd_Out[4], pid, 1 +instance = comp, \Kd_Out[5]~31 , Kd_Out[5]~31, pid, 1 +instance = comp, \Kd_Out[5] , Kd_Out[5], pid, 1 +instance = comp, \Kd_Out[6]~33 , Kd_Out[6]~33, pid, 1 +instance = comp, \Kd_Out[6] , Kd_Out[6], pid, 1 +instance = comp, \Kd_Out[7]~35 , Kd_Out[7]~35, pid, 1 +instance = comp, \Kd_Out[7] , Kd_Out[7], pid, 1 +instance = comp, \Kd_Out[8]~37 , Kd_Out[8]~37, pid, 1 +instance = comp, \Kd_Out[8] , Kd_Out[8], pid, 1 +instance = comp, \Kd_Out[9]~39 , Kd_Out[9]~39, pid, 1 +instance = comp, \Kd_Out[9] , Kd_Out[9], pid, 1 +instance = comp, \Kd_Out[10]~41 , Kd_Out[10]~41, pid, 1 +instance = comp, \Kd_Out[10] , Kd_Out[10], pid, 1 +instance = comp, \Kd_Out[11]~43 , Kd_Out[11]~43, pid, 1 +instance = comp, \Kd_Out[11]~feeder , Kd_Out[11]~feeder, pid, 1 +instance = comp, \Kd_Out[11] , Kd_Out[11], pid, 1 +instance = comp, \Kd_Out[12]~45 , Kd_Out[12]~45, pid, 1 +instance = comp, \Kd_Out[12] , Kd_Out[12], pid, 1 +instance = comp, \Kd_Out[13]~47 , Kd_Out[13]~47, pid, 1 +instance = comp, \Kd_Out[13] , Kd_Out[13], pid, 1 +instance = comp, \Kd_Out[14]~49 , Kd_Out[14]~49, pid, 1 +instance = comp, \Kd_Out[14]~feeder , Kd_Out[14]~feeder, pid, 1 +instance = comp, \Kd_Out[14] , Kd_Out[14], pid, 1 +instance = comp, \Kd_Out[15]~51 , Kd_Out[15]~51, pid, 1 +instance = comp, \Kd_Out[15]~feeder , Kd_Out[15]~feeder, pid, 1 +instance = comp, \Kd_Out[15] , Kd_Out[15], pid, 1 +instance = comp, \Kd_Out[16]~53 , Kd_Out[16]~53, pid, 1 +instance = comp, \Kd_Out[16] , Kd_Out[16], pid, 1 +instance = comp, \Kd_Out[17]~55 , Kd_Out[17]~55, pid, 1 +instance = comp, \Kd_Out[17]~feeder , Kd_Out[17]~feeder, pid, 1 +instance = comp, \Kd_Out[17] , Kd_Out[17], pid, 1 +instance = comp, \Kd_Out[18]~57 , Kd_Out[18]~57, pid, 1 +instance = comp, \Kd_Out[18]~feeder , Kd_Out[18]~feeder, pid, 1 +instance = comp, \Kd_Out[18] , Kd_Out[18], pid, 1 +instance = comp, \Kd_Out[19]~59 , Kd_Out[19]~59, pid, 1 +instance = comp, \Kd_Out[19]~feeder , Kd_Out[19]~feeder, pid, 1 +instance = comp, \Kd_Out[19] , Kd_Out[19], pid, 1 +instance = comp, \Kd_Out[20]~61 , Kd_Out[20]~61, pid, 1 +instance = comp, \~GND , ~GND, pid, 1 +instance = comp, \Kd_Out[20] , Kd_Out[20], pid, 1 +instance = comp, \Add7~20 , Add7~20, pid, 1 +instance = comp, \Ki_Out[0]~21 , Ki_Out[0]~21, pid, 1 +instance = comp, \Ki[0]~input , Ki[0]~input, pid, 1 +instance = comp, \Ki[1]~input , Ki[1]~input, pid, 1 +instance = comp, \Ki[2]~input , Ki[2]~input, pid, 1 +instance = comp, \Ki[3]~input , Ki[3]~input, pid, 1 +instance = comp, \Ki[4]~input , Ki[4]~input, pid, 1 +instance = comp, \Ki[5]~input , Ki[5]~input, pid, 1 +instance = comp, \Ki[6]~input , Ki[6]~input, pid, 1 +instance = comp, \Ki[7]~input , Ki[7]~input, pid, 1 +instance = comp, \Mult1|auto_generated|mac_mult1 , Mult1|auto_generated|mac_mult1, pid, 1 +instance = comp, \Mult1|auto_generated|mac_out2 , Mult1|auto_generated|mac_out2, pid, 1 +instance = comp, \Ki_Out[0] , Ki_Out[0], pid, 1 +instance = comp, \Ki_Out[1]~23 , Ki_Out[1]~23, pid, 1 +instance = comp, \Ki_Out[1] , Ki_Out[1], pid, 1 +instance = comp, \Ki_Out[2]~25 , Ki_Out[2]~25, pid, 1 +instance = comp, \Ki_Out[2] , Ki_Out[2], pid, 1 +instance = comp, \Ki_Out[3]~27 , Ki_Out[3]~27, pid, 1 +instance = comp, \Ki_Out[3] , Ki_Out[3], pid, 1 +instance = comp, \Ki_Out[4]~29 , Ki_Out[4]~29, pid, 1 +instance = comp, \Ki_Out[4] , Ki_Out[4], pid, 1 +instance = comp, \Ki_Out[5]~31 , Ki_Out[5]~31, pid, 1 +instance = comp, \Ki_Out[5] , Ki_Out[5], pid, 1 +instance = comp, \Ki_Out[6]~33 , Ki_Out[6]~33, pid, 1 +instance = comp, \Ki_Out[6] , Ki_Out[6], pid, 1 +instance = comp, \Ki_Out[7]~35 , Ki_Out[7]~35, pid, 1 +instance = comp, \Ki_Out[7] , Ki_Out[7], pid, 1 +instance = comp, \Ki_Out[8]~37 , Ki_Out[8]~37, pid, 1 +instance = comp, \Ki_Out[8] , Ki_Out[8], pid, 1 +instance = comp, \Ki_Out[9]~39 , Ki_Out[9]~39, pid, 1 +instance = comp, \Ki_Out[9] , Ki_Out[9], pid, 1 +instance = comp, \Ki_Out[10]~41 , Ki_Out[10]~41, pid, 1 +instance = comp, \Ki_Out[10] , Ki_Out[10], pid, 1 +instance = comp, \Ki_Out[11]~43 , Ki_Out[11]~43, pid, 1 +instance = comp, \Ki_Out[11] , Ki_Out[11], pid, 1 +instance = comp, \Ki_Out[12]~45 , Ki_Out[12]~45, pid, 1 +instance = comp, \Ki_Out[12] , Ki_Out[12], pid, 1 +instance = comp, \Ki_Out[13]~47 , Ki_Out[13]~47, pid, 1 +instance = comp, \Ki_Out[13] , Ki_Out[13], pid, 1 +instance = comp, \Ki_Out[14]~49 , Ki_Out[14]~49, pid, 1 +instance = comp, \Ki_Out[14] , Ki_Out[14], pid, 1 +instance = comp, \Ki_Out[15]~51 , Ki_Out[15]~51, pid, 1 +instance = comp, \Ki_Out[15] , Ki_Out[15], pid, 1 +instance = comp, \Ki_Out[16]~53 , Ki_Out[16]~53, pid, 1 +instance = comp, \Ki_Out[16] , Ki_Out[16], pid, 1 +instance = comp, \Ki_Out[17]~55 , Ki_Out[17]~55, pid, 1 +instance = comp, \Ki_Out[17] , Ki_Out[17], pid, 1 +instance = comp, \Ki_Out[18]~57 , Ki_Out[18]~57, pid, 1 +instance = comp, \Ki_Out[18] , Ki_Out[18], pid, 1 +instance = comp, \Ki_Out[19]~59 , Ki_Out[19]~59, pid, 1 +instance = comp, \Ki_Out[19] , Ki_Out[19], pid, 1 +instance = comp, \Ki_Out[20]~61 , Ki_Out[20]~61, pid, 1 +instance = comp, \Ki_Out[20] , Ki_Out[20], pid, 1 +instance = comp, \Kp_Out[0]~21 , Kp_Out[0]~21, pid, 1 +instance = comp, \Kp[0]~input , Kp[0]~input, pid, 1 +instance = comp, \Kp[1]~input , Kp[1]~input, pid, 1 +instance = comp, \Kp[2]~input , Kp[2]~input, pid, 1 +instance = comp, \Kp[3]~input , Kp[3]~input, pid, 1 +instance = comp, \Kp[4]~input , Kp[4]~input, pid, 1 +instance = comp, \Kp[5]~input , Kp[5]~input, pid, 1 +instance = comp, \Kp[6]~input , Kp[6]~input, pid, 1 +instance = comp, \Kp[7]~input , Kp[7]~input, pid, 1 +instance = comp, \Mult0|auto_generated|mac_mult1 , Mult0|auto_generated|mac_mult1, pid, 1 +instance = comp, \Mult0|auto_generated|mac_out2 , Mult0|auto_generated|mac_out2, pid, 1 +instance = comp, \Kp_Out[0] , Kp_Out[0], pid, 1 +instance = comp, \Kp_Out[1]~23 , Kp_Out[1]~23, pid, 1 +instance = comp, \Kp_Out[1] , Kp_Out[1], pid, 1 +instance = comp, \Kp_Out[2]~25 , Kp_Out[2]~25, pid, 1 +instance = comp, \Kp_Out[2] , Kp_Out[2], pid, 1 +instance = comp, \Kp_Out[3]~27 , Kp_Out[3]~27, pid, 1 +instance = comp, \Kp_Out[3] , Kp_Out[3], pid, 1 +instance = comp, \Kp_Out[4]~29 , Kp_Out[4]~29, pid, 1 +instance = comp, \Kp_Out[4] , Kp_Out[4], pid, 1 +instance = comp, \Kp_Out[5]~31 , Kp_Out[5]~31, pid, 1 +instance = comp, \Kp_Out[5] , Kp_Out[5], pid, 1 +instance = comp, \Kp_Out[6]~33 , Kp_Out[6]~33, pid, 1 +instance = comp, \Kp_Out[6] , Kp_Out[6], pid, 1 +instance = comp, \Kp_Out[7]~35 , Kp_Out[7]~35, pid, 1 +instance = comp, \Kp_Out[7] , Kp_Out[7], pid, 1 +instance = comp, \Kp_Out[8]~37 , Kp_Out[8]~37, pid, 1 +instance = comp, \Kp_Out[8] , Kp_Out[8], pid, 1 +instance = comp, \Kp_Out[9]~39 , Kp_Out[9]~39, pid, 1 +instance = comp, \Kp_Out[9] , Kp_Out[9], pid, 1 +instance = comp, \Kp_Out[10]~41 , Kp_Out[10]~41, pid, 1 +instance = comp, \Kp_Out[10] , Kp_Out[10], pid, 1 +instance = comp, \Kp_Out[11]~43 , Kp_Out[11]~43, pid, 1 +instance = comp, \Kp_Out[11] , Kp_Out[11], pid, 1 +instance = comp, \Kp_Out[12]~45 , Kp_Out[12]~45, pid, 1 +instance = comp, \Kp_Out[12] , Kp_Out[12], pid, 1 +instance = comp, \Kp_Out[13]~47 , Kp_Out[13]~47, pid, 1 +instance = comp, \Kp_Out[13] , Kp_Out[13], pid, 1 +instance = comp, \Kp_Out[14]~49 , Kp_Out[14]~49, pid, 1 +instance = comp, \Kp_Out[14] , Kp_Out[14], pid, 1 +instance = comp, \Kp_Out[15]~51 , Kp_Out[15]~51, pid, 1 +instance = comp, \Kp_Out[15] , Kp_Out[15], pid, 1 +instance = comp, \Kp_Out[16]~53 , Kp_Out[16]~53, pid, 1 +instance = comp, \Kp_Out[16] , Kp_Out[16], pid, 1 +instance = comp, \Kp_Out[17]~55 , Kp_Out[17]~55, pid, 1 +instance = comp, \Kp_Out[17] , Kp_Out[17], pid, 1 +instance = comp, \Kp_Out[18]~57 , Kp_Out[18]~57, pid, 1 +instance = comp, \Kp_Out[18] , Kp_Out[18], pid, 1 +instance = comp, \Kp_Out[19]~59 , Kp_Out[19]~59, pid, 1 +instance = comp, \Kp_Out[19] , Kp_Out[19], pid, 1 +instance = comp, \Kp_Out[20]~61 , Kp_Out[20]~61, pid, 1 +instance = comp, \Kp_Out[20] , Kp_Out[20], pid, 1 +instance = comp, \Add5~0 , Add5~0, pid, 1 +instance = comp, \Add5~2 , Add5~2, pid, 1 +instance = comp, \Add5~4 , Add5~4, pid, 1 +instance = comp, \Add5~6 , Add5~6, pid, 1 +instance = comp, \Add5~8 , Add5~8, pid, 1 +instance = comp, \Add5~10 , Add5~10, pid, 1 +instance = comp, \Add5~12 , Add5~12, pid, 1 +instance = comp, \Add5~14 , Add5~14, pid, 1 +instance = comp, \Add5~24 , Add5~24, pid, 1 +instance = comp, \Add5~27 , Add5~27, pid, 1 +instance = comp, \Add5~30 , Add5~30, pid, 1 +instance = comp, \Add5~33 , Add5~33, pid, 1 +instance = comp, \Add5~36 , Add5~36, pid, 1 +instance = comp, \Add5~39 , Add5~39, pid, 1 +instance = comp, \Add5~42 , Add5~42, pid, 1 +instance = comp, \Add5~45 , Add5~45, pid, 1 +instance = comp, \Add5~48 , Add5~48, pid, 1 +instance = comp, \Add5~51 , Add5~51, pid, 1 +instance = comp, \Add5~54 , Add5~54, pid, 1 +instance = comp, \Add5~57 , Add5~57, pid, 1 +instance = comp, \Add5~60 , Add5~60, pid, 1 +instance = comp, \Add5~62 , Add5~62, pid, 1 +instance = comp, \Add7~19 , Add7~19, pid, 1 +instance = comp, \Add7~18 , Add7~18, pid, 1 +instance = comp, \Add7~17 , Add7~17, pid, 1 +instance = comp, \Add7~16 , Add7~16, pid, 1 +instance = comp, \Add7~15 , Add7~15, pid, 1 +instance = comp, \Add7~14 , Add7~14, pid, 1 +instance = comp, \Add7~13 , Add7~13, pid, 1 +instance = comp, \Add7~12 , Add7~12, pid, 1 +instance = comp, \Add7~11 , Add7~11, pid, 1 +instance = comp, \Add7~10 , Add7~10, pid, 1 +instance = comp, \Add7~9 , Add7~9, pid, 1 +instance = comp, \Add7~8 , Add7~8, pid, 1 +instance = comp, \Add5~16 , Add5~16, pid, 1 +instance = comp, \Add7~1 , Add7~1, pid, 1 +instance = comp, \Add5~17 , Add5~17, pid, 1 +instance = comp, \Add7~2 , Add7~2, pid, 1 +instance = comp, \Add5~18 , Add5~18, pid, 1 +instance = comp, \Add7~3 , Add7~3, pid, 1 +instance = comp, \Add5~19 , Add5~19, pid, 1 +instance = comp, \Add5~20 , Add5~20, pid, 1 +instance = comp, \Add7~4 , Add7~4, pid, 1 +instance = comp, \Add7~5 , Add7~5, pid, 1 +instance = comp, \Add5~21 , Add5~21, pid, 1 +instance = comp, \Add7~6 , Add7~6, pid, 1 +instance = comp, \Add5~22 , Add5~22, pid, 1 +instance = comp, \Add5~23 , Add5~23, pid, 1 +instance = comp, \Add7~7 , Add7~7, pid, 1 +instance = comp, \Vout[0]~15 , Vout[0]~15, pid, 1 +instance = comp, \Vout[0]~17 , Vout[0]~17, pid, 1 +instance = comp, \Vout[0]~19 , Vout[0]~19, pid, 1 +instance = comp, \Vout[0]~21 , Vout[0]~21, pid, 1 +instance = comp, \Vout[0]~23 , Vout[0]~23, pid, 1 +instance = comp, \Vout[0]~25 , Vout[0]~25, pid, 1 +instance = comp, \Vout[0]~27 , Vout[0]~27, pid, 1 +instance = comp, \Vout[0]~28 , Vout[0]~28, pid, 1 +instance = comp, \Vout[1]~30 , Vout[1]~30, pid, 1 +instance = comp, \Vout[1]~reg0 , Vout[1]~reg0, pid, 1 +instance = comp, \Add5~26 , Add5~26, pid, 1 +instance = comp, \Vout[2]~32 , Vout[2]~32, pid, 1 +instance = comp, \Vout[2]~reg0 , Vout[2]~reg0, pid, 1 +instance = comp, \Add5~29 , Add5~29, pid, 1 +instance = comp, \Vout[3]~34 , Vout[3]~34, pid, 1 +instance = comp, \Vout[3]~reg0 , Vout[3]~reg0, pid, 1 +instance = comp, \Add5~32 , Add5~32, pid, 1 +instance = comp, \Vout[4]~36 , Vout[4]~36, pid, 1 +instance = comp, \Vout[4]~reg0 , Vout[4]~reg0, pid, 1 +instance = comp, \Add5~35 , Add5~35, pid, 1 +instance = comp, \Vout[5]~38 , Vout[5]~38, pid, 1 +instance = comp, \Vout[5]~reg0 , Vout[5]~reg0, pid, 1 +instance = comp, \Add5~38 , Add5~38, pid, 1 +instance = comp, \Vout[6]~40 , Vout[6]~40, pid, 1 +instance = comp, \Vout[6]~reg0 , Vout[6]~reg0, pid, 1 +instance = comp, \Add5~41 , Add5~41, pid, 1 +instance = comp, \Vout[7]~42 , Vout[7]~42, pid, 1 +instance = comp, \Vout[7]~reg0 , Vout[7]~reg0, pid, 1 +instance = comp, \Add5~44 , Add5~44, pid, 1 +instance = comp, \Vout[8]~44 , Vout[8]~44, pid, 1 +instance = comp, \Vout[8]~reg0 , Vout[8]~reg0, pid, 1 +instance = comp, \Add5~47 , Add5~47, pid, 1 +instance = comp, \Vout[9]~46 , Vout[9]~46, pid, 1 +instance = comp, \Vout[9]~reg0 , Vout[9]~reg0, pid, 1 +instance = comp, \Add5~50 , Add5~50, pid, 1 +instance = comp, \Vout[10]~48 , Vout[10]~48, pid, 1 +instance = comp, \Vout[10]~reg0 , Vout[10]~reg0, pid, 1 +instance = comp, \Add5~53 , Add5~53, pid, 1 +instance = comp, \Vout[11]~50 , Vout[11]~50, pid, 1 +instance = comp, \Vout[11]~reg0 , Vout[11]~reg0, pid, 1 +instance = comp, \Add5~56 , Add5~56, pid, 1 +instance = comp, \Vout[12]~52 , Vout[12]~52, pid, 1 +instance = comp, \Vout[12]~reg0 , Vout[12]~reg0, pid, 1 +instance = comp, \Add5~59 , Add5~59, pid, 1 +instance = comp, \Vout[13]~54 , Vout[13]~54, pid, 1 +instance = comp, \Vout[13]~reg0 , Vout[13]~reg0, pid, 1 +instance = comp, \Add7~0 , Add7~0, pid, 1 +instance = comp, \Vout[0]~reg0 , Vout[0]~reg0, pid, 1 +design_name = hard_block +instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, hard_block, 1 diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak1 b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak1 new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak1 @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak10 b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak10 new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak10 @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak2 b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak2 new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak2 @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak3 b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak3 new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak3 @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak4 b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak4 new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak4 @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak5 b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak5 new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak5 @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak6 b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak6 new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak6 @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak7 b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak7 new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak7 @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak8 b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak8 new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak8 @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak9 b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak9 new file mode 100644 index 0000000..5017058 --- /dev/null +++ b/pid/simulation/modelsim/pid_run_msim_rtl_verilog.do.bak9 @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/rtl {F:/Code/FPGA/reserve/pid/rtl/pid.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/pid/testbench {F:/Code/FPGA/reserve/pid/testbench/pid_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" pid_tb + +add wave * +view structure +view signals +run -all diff --git a/pid/simulation/modelsim/pid_v.sdo b/pid/simulation/modelsim/pid_v.sdo new file mode 100644 index 0000000..e8d3b00 --- /dev/null +++ b/pid/simulation/modelsim/pid_v.sdo @@ -0,0 +1,6913 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "pid") + (DATE "12/04/2018 14:36:39") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2429:2429:2429) (2385:2385:2385)) + (IOPATH i o (3147:3147:3147) (3095:3095:3095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1594:1594:1594) (1550:1550:1550)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2312:2312:2312) (2168:2168:2168)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1498:1498:1498) (1416:1416:1416)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1578:1578:1578) (1500:1500:1500)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1855:1855:1855) (1729:1729:1729)) + (IOPATH i o (3127:3127:3127) (3075:3075:3075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1304:1304:1304) (1310:1310:1310)) + (IOPATH i o (3128:3128:3128) (3105:3105:3105)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1839:1839:1839) (1715:1715:1715)) + (IOPATH i o (3147:3147:3147) (3095:3095:3095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1914:1914:1914) (1922:1922:1922)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1887:1887:1887) (1761:1761:1761)) + (IOPATH i o (3048:3048:3048) (3009:3009:3009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1851:1851:1851) (1712:1712:1712)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1994:1994:1994) (1932:1932:1932)) + (IOPATH i o (3128:3128:3128) (3105:3105:3105)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2370:2370:2370) (2343:2343:2343)) + (IOPATH i o (3117:3117:3117) (3065:3065:3065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE Vout\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1659:1659:1659) (1580:1580:1580)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[0\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (383:383:383) (459:459:459)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~1) + (DELAY + (ABSOLUTE + (PORT datac (1013:1013:1013) (1037:1037:1037)) + (PORT datad (3685:3685:3685) (3854:3854:3854)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~0) + (DELAY + (ABSOLUTE + (PORT datac (1013:1013:1013) (1037:1037:1037)) + (PORT datad (4040:4040:4040) (4269:4269:4269)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~2) + (DELAY + (ABSOLUTE + (PORT datac (3798:3798:3798) (3991:3991:3991)) + (PORT datad (809:809:809) (791:791:791)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (4099:4099:4099) (4236:4236:4236)) + (PORT datac (1017:1017:1017) (1042:1042:1042)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~6) + (DELAY + (ABSOLUTE + (PORT datac (3584:3584:3584) (3811:3811:3811)) + (PORT datad (808:808:808) (791:791:791)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~8) + (DELAY + (ABSOLUTE + (PORT datac (1016:1016:1016) (1041:1041:1041)) + (PORT datad (3611:3611:3611) (3785:3785:3785)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (784:784:784) (831:831:831)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~10) + (DELAY + (ABSOLUTE + (PORT datac (1017:1017:1017) (1041:1041:1041)) + (PORT datad (3306:3306:3306) (3534:3534:3534)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~12) + (DELAY + (ABSOLUTE + (PORT datac (1013:1013:1013) (1037:1037:1037)) + (PORT datad (3610:3610:3610) (3791:3791:3791)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (726:726:726) (772:772:772)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (3886:3886:3886) (4074:4074:4074)) + (PORT datad (692:692:692) (733:733:733)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~16) + (DELAY + (ABSOLUTE + (PORT datac (1014:1014:1014) (1039:1039:1039)) + (PORT datad (4006:4006:4006) (4168:4168:4168)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (3773:3773:3773) (3971:3971:3971)) + (PORT datad (695:695:695) (736:736:736)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~20) + (DELAY + (ABSOLUTE + (PORT datac (3630:3630:3630) (3856:3856:3856)) + (PORT datad (703:703:703) (745:745:745)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~22) + (DELAY + (ABSOLUTE + (PORT datac (3602:3602:3602) (3817:3817:3817)) + (PORT datad (698:698:698) (740:740:740)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~24) + (DELAY + (ABSOLUTE + (PORT datac (3836:3836:3836) (4046:4046:4046)) + (PORT datad (704:704:704) (746:746:746)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Sample\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~26) + (DELAY + (ABSOLUTE + (PORT datac (1743:1743:1743) (1897:1897:1897)) + (PORT datad (699:699:699) (741:741:741)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[0\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (583:583:583) (627:627:627)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (483:483:483)) + (PORT datab (543:543:543) (506:506:506)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (517:517:517)) + (PORT datab (491:491:491) (478:478:478)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (566:566:566) (585:585:585)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~3) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (526:526:526)) + (PORT datab (581:581:581) (543:543:543)) + (PORT datac (722:722:722) (660:660:660)) + (PORT datad (275:275:275) (300:300:300)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1640:1640:1640)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1670:1670:1670) (1620:1620:1620)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datac (579:579:579) (594:594:594)) + (PORT datad (536:536:536) (556:556:556)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~2) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (525:525:525)) + (PORT datab (320:320:320) (350:350:350)) + (PORT datac (284:284:284) (323:323:323)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~0) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (365:365:365)) + (PORT datab (277:277:277) (303:303:303)) + (PORT datac (496:496:496) (477:477:477)) + (PORT datad (286:286:286) (314:314:314)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add0\~20) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (392:392:392)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (606:606:606)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (301:301:301) (377:377:377)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE period\~1) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (365:365:365)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (496:496:496) (477:477:477)) + (PORT datad (287:287:287) (315:315:315)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE period\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1641:1641:1641)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1671:1671:1671) (1623:1623:1623)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (439:439:439)) + (PORT datab (341:341:341) (423:423:423)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (303:303:303) (379:379:379)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (526:526:526)) + (PORT datab (316:316:316) (344:344:344)) + (PORT datad (522:522:522) (495:495:495)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Clk_Ctrl) + (DELAY + (ABSOLUTE + (PORT clk (1605:1605:1605) (1640:1640:1640)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1670:1670:1670) (1620:1620:1620)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[1\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~25) + (DELAY + (ABSOLUTE + (PORT datab (3634:3634:3634) (3811:3811:3811)) + (PORT datac (773:773:773) (753:753:753)) + (PORT datad (700:700:700) (743:743:743)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (542:542:542) (504:504:504)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[2\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~23) + (DELAY + (ABSOLUTE + (PORT datab (3623:3623:3623) (3850:3850:3850)) + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (483:483:483)) + (PORT datab (488:488:488) (469:469:469)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[3\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~21) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (590:590:590)) + (PORT datac (3687:3687:3687) (3961:3961:3961)) + (PORT datad (688:688:688) (729:729:729)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (810:810:810)) + (PORT datab (484:484:484) (464:464:464)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[4\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~19) + (DELAY + (ABSOLUTE + (PORT dataa (3320:3320:3320) (3553:3553:3553)) + (PORT datac (1017:1017:1017) (1042:1042:1042)) + (PORT datad (864:864:864) (869:869:869)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[5\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (845:845:845)) + (PORT datab (540:540:540) (499:499:499)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[5\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE SetPoint\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~17) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (623:623:623)) + (PORT datac (3559:3559:3559) (3769:3769:3769)) + (PORT datad (694:694:694) (735:735:735)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (475:475:475)) + (PORT datab (541:541:541) (499:499:499)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[6\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~15) + (DELAY + (ABSOLUTE + (PORT datab (740:740:740) (788:788:788)) + (PORT datac (4095:4095:4095) (4327:4327:4327)) + (PORT datad (845:845:845) (809:809:809)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[7\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (805:805:805)) + (PORT datab (540:540:540) (499:499:499)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[7\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~13) + (DELAY + (ABSOLUTE + (PORT datab (4110:4110:4110) (4357:4357:4357)) + (PORT datac (514:514:514) (538:538:538)) + (PORT datad (691:691:691) (731:731:731)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[8\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (515:515:515)) + (PORT datab (835:835:835) (792:792:792)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[8\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~11) + (DELAY + (ABSOLUTE + (PORT datab (734:734:734) (782:782:782)) + (PORT datac (3518:3518:3518) (3726:3726:3726)) + (PORT datad (501:501:501) (529:529:529)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[9\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (829:829:829)) + (PORT datab (544:544:544) (506:506:506)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[9\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~9) + (DELAY + (ABSOLUTE + (PORT datab (749:749:749) (798:798:798)) + (PORT datac (3646:3646:3646) (3792:3792:3792)) + (PORT datad (537:537:537) (559:559:559)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[10\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (815:815:815) (742:742:742)) + (PORT datab (761:761:761) (691:691:691)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[10\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~7) + (DELAY + (ABSOLUTE + (PORT datab (737:737:737) (784:784:784)) + (PORT datac (3916:3916:3916) (4131:4131:4131)) + (PORT datad (505:505:505) (532:532:532)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[11\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (839:839:839)) + (PORT datab (799:799:799) (719:719:719)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[11\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (4004:4004:4004) (4179:4179:4179)) + (PORT datac (589:589:589) (624:624:624)) + (PORT datad (935:935:935) (922:922:922)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE0\[12\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (747:747:747)) + (PORT datab (548:548:548) (512:512:512)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[12\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~3) + (DELAY + (ABSOLUTE + (PORT datab (3681:3681:3681) (3863:3863:3863)) + (PORT datac (771:771:771) (757:757:757)) + (PORT datad (707:707:707) (749:749:749)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + 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(4018:4018:4018) (4233:4233:4233)) + (PORT datad (705:705:705) (748:748:748)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE0\[0\]\~_Duplicate_1) + (DELAY + (ABSOLUTE + (PORT clk (1615:1615:1615) (1656:1656:1656)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1686:1686:1686) (1630:1630:1630)) + (PORT ena (2483:2483:2483) (2389:2389:2389)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (383:383:383) (460:460:460)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1688:1688:1688) (1645:1645:1645)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (470:470:470)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1625:1625:1625) (1574:1574:1574)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (384:384:384) (461:461:461)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2292:2292:2292) (2182:2182:2182)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1971:1971:1971) (1878:1878:1878)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE 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(HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[7\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (462:462:462)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1414:1414:1414) (1393:1393:1393)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[8\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2077:2077:2077) (1980:1980:1980)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (462:462:462)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2305:2305:2305) (2153:2153:2153)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (472:472:472)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2048:2048:2048) (1923:1923:1923)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (462:462:462)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1987:1987:1987) (1904:1904:1904)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[12\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1682:1682:1682) (1615:1615:1615)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE1\[13\]\~40) + (DELAY + (ABSOLUTE + (PORT datad (331:331:331) (404:404:404)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1064:1064:1064) (1090:1090:1090)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1614:1614:1614) (1652:1652:1652)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1369:1369:1369) (1362:1362:1362)) + (PORT clrn (1682:1682:1682) (1629:1629:1629)) + (PORT sload (1202:1202:1202) (1186:1186:1186)) + (PORT ena (2025:2025:2025) (1948:1948:1948)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1431:1431:1431) (1419:1419:1419)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[2\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1949:1949:1949) (1826:1826:1826)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[3\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1428:1428:1428) (1412:1412:1412)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[4\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1449:1449:1449) (1428:1428:1428)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[5\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1435:1435:1435) (1431:1431:1431)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[6\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1480:1480:1480) (1463:1463:1463)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[7\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2042:2042:2042) (1915:1915:1915)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[8\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (2020:2020:2020) (1915:1915:1915)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1427:1427:1427) (1414:1414:1414)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1725:1725:1725) (1648:1648:1648)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1967:1967:1967) (1852:1852:1852)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[12\]\~38) + (DELAY + (ABSOLUTE + (PORT datab (333:333:333) (409:409:409)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1663:1663:1663) (1610:1610:1610)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE EE2\[13\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (462:462:462)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1454:1454:1454) (1437:1437:1437)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE EE2\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1637:1637:1637)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1697:1697:1697) (1621:1621:1621)) + (PORT clrn (1667:1667:1667) (1618:1618:1618)) + (PORT sload (1217:1217:1217) (1189:1189:1189)) + (PORT ena (2013:2013:2013) (1943:1943:1943)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kd\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult2\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT dataa[6] (570:570:570) (587:587:587)) + (PORT dataa[7] (532:532:532) (545:545:545)) + (PORT dataa[8] (561:561:561) (573:573:573)) + (PORT dataa[9] (538:538:538) (553:553:553)) + (PORT dataa[10] (814:814:814) (775:775:775)) + (PORT dataa[11] (531:531:531) (543:543:543)) + (PORT dataa[12] (531:531:531) (551:551:551)) + (PORT dataa[13] (806:806:806) (764:764:764)) + (PORT dataa[14] (817:817:817) (791:791:791)) + (PORT dataa[15] (533:533:533) (553:553:553)) + (PORT dataa[16] (811:811:811) (767:767:767)) + (PORT dataa[17] (556:556:556) (573:573:573)) + (PORT datab[10] (3685:3685:3685) (3935:3935:3935)) + (PORT datab[11] (3989:3989:3989) (4180:4180:4180)) + (PORT datab[12] (3751:3751:3751) (3950:3950:3950)) + (PORT datab[13] (3987:3987:3987) (4184:4184:4184)) + (PORT datab[14] (4019:4019:4019) (4168:4168:4168)) + (PORT datab[15] (3903:3903:3903) (4090:4090:4090)) + (PORT datab[16] (3905:3905:3905) (4113:4113:4113)) + (PORT datab[17] (3935:3935:3935) (4168:4168:4168)) + (IOPATH dataa dataout (3928:3928:3928) (3928:3928:3928)) + (IOPATH datab dataout (3863:3863:3863) (3863:3863:3863)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult2\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (139:139:139) (148:148:148)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1518:1518:1518) (1396:1396:1396)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1190:1190:1190) (1114:1114:1114)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1198:1198:1198) (1122:1122:1122)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1182:1182:1182) (1124:1124:1124)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1228:1228:1228) (1144:1144:1144)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1209:1209:1209) (1133:1133:1133)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1275:1275:1275) (1193:1193:1193)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1264:1264:1264) (1181:1181:1181)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1263:1263:1263) (1182:1182:1182)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (443:443:443)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1238:1238:1238) (1166:1166:1166)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (433:433:433)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2071:2071:2071)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1570:1570:1570) (1467:1467:1467)) + (PORT clrn (1665:1665:1665) (1616:1616:1616)) + (PORT sload (1586:1586:1586) (1673:1673:1673)) + (PORT ena (2107:2107:2107) (2026:2026:2026)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (985:985:985) (967:967:967)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (813:813:813) (753:753:753)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1214:1214:1214) (1132:1132:1132)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2071:2071:2071)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1310:1310:1310) (1240:1240:1240)) + (PORT clrn (1665:1665:1665) (1616:1616:1616)) + (PORT sload (1586:1586:1586) (1673:1673:1673)) + (PORT ena (2107:2107:2107) (2026:2026:2026)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2071:2071:2071)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1272:1272:1272) (1216:1216:1216)) + (PORT clrn (1665:1665:1665) (1616:1616:1616)) + (PORT sload (1586:1586:1586) (1673:1673:1673)) + (PORT ena (2107:2107:2107) (2026:2026:2026)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (899:899:899) (913:913:913)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (786:786:786) (739:739:739)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1495:1495:1495) (1364:1364:1364)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (961:961:961)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (819:819:819) (766:766:766)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (914:914:914) (873:873:873)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2071:2071:2071)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1222:1222:1222) (1170:1170:1170)) + (PORT clrn (1665:1665:1665) (1616:1616:1616)) + (PORT sload (1586:1586:1586) (1673:1673:1673)) + (PORT ena (2107:2107:2107) (2026:2026:2026)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (954:954:954)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[17\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (789:789:789) (738:738:738)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1574:1574:1574) (1442:1442:1442)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (948:948:948) (938:938:938)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[18\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (832:832:832) (779:779:779)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1223:1223:1223) (1151:1151:1151)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (950:950:950) (954:954:954)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[19\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (862:862:862) (801:801:801)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (2055:2055:2055) (2059:2059:2059)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1523:1523:1523) (1389:1389:1389)) + (PORT clrn (1664:1664:1664) (1615:1615:1615)) + (PORT sload (1987:1987:1987) (2096:2096:2096)) + (PORT ena (2021:2021:2021) (1937:1937:1937)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kd_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kd_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1601:1601:1601) (1635:1635:1635)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1352:1352:1352) (1291:1291:1291)) + (PORT clrn (1665:1665:1665) (1616:1616:1616)) + (PORT sload (1586:1586:1586) (1673:1673:1673)) + (PORT ena (2047:2047:2047) (1958:1958:1958)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~20) + (DELAY + (ABSOLUTE + (PORT datac (528:528:528) (560:560:560)) + (PORT datad (1405:1405:1405) (1462:1462:1462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Ki\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult1\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT dataa[6] (568:568:568) (585:585:585)) + (PORT dataa[7] (589:589:589) (601:601:601)) + (PORT dataa[8] (818:818:818) (790:790:790)) + (PORT dataa[9] (594:594:594) (609:609:609)) + (PORT dataa[10] (859:859:859) (834:834:834)) + (PORT dataa[11] (586:586:586) (596:596:596)) + (PORT dataa[12] (561:561:561) (575:575:575)) + (PORT dataa[13] (832:832:832) (788:788:788)) + (PORT dataa[14] (571:571:571) (595:595:595)) + (PORT dataa[15] (561:561:561) (580:580:580)) + (PORT dataa[16] (835:835:835) (789:789:789)) + (PORT dataa[17] (582:582:582) (597:597:597)) + (PORT datab[10] (3710:3710:3710) (3872:3872:3872)) + (PORT datab[11] (4046:4046:4046) (4225:4225:4225)) + (PORT datab[12] (4136:4136:4136) (4399:4399:4399)) + (PORT datab[13] (4026:4026:4026) (4280:4280:4280)) + (PORT datab[14] (4065:4065:4065) (4204:4204:4204)) + (PORT datab[15] (4164:4164:4164) (4354:4354:4354)) + (PORT datab[16] (3738:3738:3738) (3906:3906:3906)) + (PORT datab[17] (3648:3648:3648) (3856:3856:3856)) + (IOPATH dataa dataout (3928:3928:3928) (3928:3928:3928)) + (IOPATH datab dataout (3863:3863:3863) (3863:3863:3863)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult1\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (139:139:139) (148:148:148)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1526:1526:1526) (1428:1428:1428)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1624:1624:1624) (1512:1512:1512)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1598:1598:1598) (1487:1487:1487)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1615:1615:1615) (1501:1501:1501)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1565:1565:1565) (1466:1466:1466)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1554:1554:1554) (1451:1451:1451)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1550:1550:1550) (1461:1461:1461)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1565:1565:1565) (1454:1454:1454)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1628:1628:1628) (1519:1519:1519)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (2069:2069:2069) (2089:2089:2089)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1658:1658:1658) (1540:1540:1540)) + (PORT clrn (1682:1682:1682) (1627:1627:1627)) + (PORT sload (2359:2359:2359) (2479:2479:2479)) + (PORT ena (2360:2360:2360) (2264:2264:2264)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1539:1539:1539) (1407:1407:1407)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (913:913:913) (872:872:872)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1177:1177:1177) (1105:1105:1105)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (911:911:911) (870:870:870)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1185:1185:1185) (1112:1112:1112)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (912:912:912) (871:871:871)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (914:914:914) (873:873:873)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1180:1180:1180) (1107:1107:1107)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1219:1219:1219) (1148:1148:1148)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (2061:2061:2061) (2074:2074:2074)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (911:911:911) (870:870:870)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2395:2395:2395) (2292:2292:2292)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Ki_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Ki_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1649:1649:1649)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (731:731:731) (748:748:748)) + (PORT clrn (1679:1679:1679) (1624:1624:1624)) + (PORT sload (2380:2380:2380) (2511:2511:2511)) + (PORT ena (2301:2301:2301) (2183:2183:2183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Kp\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_data_reg") + (INSTANCE Mult0\|auto_generated\|mac_mult1.dataa_reg) + (DELAY + (ABSOLUTE + (PORT data[0] (257:257:257) (271:271:271)) + (PORT data[1] (257:257:257) (271:271:271)) + (PORT data[2] (257:257:257) (271:271:271)) + (PORT data[3] (257:257:257) (271:271:271)) + (PORT data[4] (705:705:705) (692:692:692)) + (PORT data[5] (971:971:971) (913:913:913)) + (PORT data[6] (708:708:708) (697:697:697)) + (PORT data[7] (1039:1039:1039) (980:980:980)) + (PORT data[8] (699:699:699) (683:683:683)) + (PORT data[9] (741:741:741) (732:732:732)) + (PORT data[10] (974:974:974) (915:915:915)) + (PORT data[11] (697:697:697) (677:677:677)) + (PORT data[12] (738:738:738) (724:724:724)) + (PORT data[13] (698:698:698) (679:679:679)) + (PORT data[14] (698:698:698) (679:679:679)) + (PORT data[15] (738:738:738) (725:725:725)) + (PORT data[16] (976:976:976) (907:907:907)) + (PORT data[17] (704:704:704) (687:687:687)) + (PORT clk (1486:1486:1486) (1570:1570:1570)) + (PORT ena (2359:2359:2359) (2248:2248:2248)) + (PORT aclr (1662:1662:1662) (1680:1680:1680)) + (IOPATH (posedge aclr) dataout (275:275:275) (275:275:275)) + (IOPATH (posedge clk) dataout (355:355:355) (355:355:355)) + ) + ) + (TIMINGCHECK + (SETUP data (posedge clk) (228:228:228)) + (SETUP ena (posedge clk) (228:228:228)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_mult_internal") + (INSTANCE Mult0\|auto_generated\|mac_mult1.mac_multiply) + (DELAY + (ABSOLUTE + (PORT datab[10] (3773:3773:3773) (3943:3943:3943)) + (PORT datab[11] (4190:4190:4190) (4424:4424:4424)) + (PORT datab[12] (3728:3728:3728) (3987:3987:3987)) + (PORT datab[13] (3722:3722:3722) (3910:3910:3910)) + (PORT datab[14] (3519:3519:3519) (3730:3730:3730)) + (PORT datab[15] (3754:3754:3754) (3989:3989:3989)) + (PORT datab[16] (4007:4007:4007) (4201:4201:4201)) + (PORT datab[17] (3662:3662:3662) (3903:3903:3903)) + (IOPATH dataa dataout (3655:3655:3655) (3655:3655:3655)) + (IOPATH datab dataout (3863:3863:3863) (3863:3863:3863)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_mac_out") + (INSTANCE Mult0\|auto_generated\|mac_out2) + (DELAY + (ABSOLUTE + (IOPATH dataa dataout (139:139:139) (148:148:148)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1617:1617:1617) (1508:1508:1508)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[1\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1633:1633:1633) (1513:1513:1513)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[2\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1617:1617:1617) (1512:1512:1512)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[3\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1671:1671:1671) (1554:1554:1554)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[4\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1626:1626:1626) (1507:1507:1507)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[5\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1585:1585:1585) (1487:1487:1487)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[6\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1572:1572:1572) (1473:1473:1473)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[7\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1889:1889:1889) (1715:1715:1715)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[8\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1645:1645:1645) (1523:1523:1523)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[9\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1598:1598:1598) (1632:1632:1632)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1555:1555:1555) (1454:1454:1454)) + (PORT clrn (1662:1662:1662) (1613:1613:1613)) + (PORT sload (1945:1945:1945) (2061:2061:2061)) + (PORT ena (2448:2448:2448) (2342:2342:2342)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[10\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1569:1569:1569) (1468:1468:1468)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[11\]\~43) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1807:1807:1807) (1649:1649:1649)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[12\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1223:1223:1223) (1172:1172:1172)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[13\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1260:1260:1260) (1195:1195:1195)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[14\]\~49) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1540:1540:1540) (1447:1447:1447)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[15\]\~51) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1278:1278:1278) (1215:1215:1215)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[16\]\~53) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1596:1596:1596) (1474:1474:1474)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[17\]\~55) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1274:1274:1274) (1211:1211:1211)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[18\]\~57) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1916:1916:1916) (1796:1796:1796)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[19\]\~59) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1550:1550:1550) (1456:1456:1456)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Kp_Out\[20\]\~61) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Kp_Out\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1599:1599:1599) (1634:1634:1634)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1610:1610:1610) (1493:1493:1493)) + (PORT clrn (1664:1664:1664) (1614:1614:1614)) + (PORT sload (2003:2003:2003) (2114:2114:2114)) + (PORT ena (2365:2365:2365) (2270:2270:2270)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (940:940:940)) + (PORT datab (887:887:887) (874:874:874)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (947:947:947)) + (PORT datab (975:975:975) (955:955:955)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~4) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (940:940:940)) + (PORT datab (566:566:566) (596:596:596)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1328:1328:1328) (1270:1270:1270)) + (PORT datab (623:623:623) (631:631:631)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~8) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (607:607:607)) + (PORT datab (980:980:980) (966:966:966)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~10) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (881:881:881)) + (PORT datab (980:980:980) (966:966:966)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~12) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (882:882:882)) + (PORT datab (1350:1350:1350) (1283:1283:1283)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1241:1241:1241) (1208:1208:1208)) + (PORT datab (906:906:906) (889:889:889)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1244:1244:1244)) + (PORT datab (568:568:568) (598:598:598)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~27) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (647:647:647)) + (PORT datab (1299:1299:1299) (1222:1222:1222)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1529:1529:1529) (1452:1452:1452)) + (PORT datab (627:627:627) (631:631:631)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~33) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (612:612:612)) + (PORT datab (935:935:935) (939:939:939)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~36) + (DELAY + (ABSOLUTE + (PORT dataa (637:637:637) (642:642:642)) + (PORT datab (980:980:980) (962:962:962)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~39) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (614:614:614)) + (PORT datab (986:986:986) (969:969:969)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~42) + (DELAY + (ABSOLUTE + (PORT dataa (1612:1612:1612) (1593:1593:1593)) + (PORT datab (626:626:626) (630:630:630)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~45) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (957:957:957)) + (PORT datab (1246:1246:1246) (1209:1209:1209)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~48) + (DELAY + (ABSOLUTE + (PORT dataa (981:981:981) (951:951:951)) + (PORT datab (1346:1346:1346) (1309:1309:1309)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~51) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1251:1251:1251)) + (PORT datab (626:626:626) (629:629:629)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1347:1347:1347) (1297:1297:1297)) + (PORT datab (571:571:571) (602:602:602)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~57) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1306:1306:1306)) + (PORT datab (970:970:970) (932:932:932)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~60) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (609:609:609)) + (PORT datad (1225:1225:1225) (1155:1155:1155)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~62) + (DELAY + (ABSOLUTE + (PORT datac (635:635:635) (702:702:702)) + (PORT datad (879:879:879) (838:838:838)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~19) + (DELAY + (ABSOLUTE + (PORT datac (634:634:634) (701:701:701)) + (PORT datad (1370:1370:1370) (1346:1346:1346)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~18) + (DELAY + (ABSOLUTE + (PORT datac (633:633:633) (700:700:700)) + (PORT datad (1259:1259:1259) (1236:1236:1236)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~17) + (DELAY + (ABSOLUTE + (PORT datac (513:513:513) (549:549:549)) + (PORT datad (1395:1395:1395) (1451:1451:1451)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~16) + (DELAY + (ABSOLUTE + (PORT datac (578:578:578) (593:593:593)) + (PORT datad (1406:1406:1406) (1462:1462:1462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~15) + (DELAY + (ABSOLUTE + (PORT datac (631:631:631) (698:698:698)) + (PORT datad (1252:1252:1252) (1226:1226:1226)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~14) + (DELAY + (ABSOLUTE + (PORT datac (635:635:635) (702:702:702)) + (PORT datad (1277:1277:1277) (1251:1251:1251)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~13) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (614:614:614)) + (PORT datad (1408:1408:1408) (1464:1464:1464)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~12) + (DELAY + (ABSOLUTE + (PORT datab (1366:1366:1366) (1336:1336:1336)) + (PORT datac (633:633:633) (700:700:700)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~11) + (DELAY + (ABSOLUTE + (PORT datac (632:632:632) (699:699:699)) + (PORT datad (1262:1262:1262) (1233:1233:1233)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~10) + (DELAY + (ABSOLUTE + (PORT datac (580:580:580) (596:596:596)) + (PORT datad (1406:1406:1406) (1463:1463:1463)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE 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"cycloneive_lcell_comb") + (INSTANCE Add7\~6) + (DELAY + (ABSOLUTE + (PORT datac (1192:1192:1192) (1133:1133:1133)) + (PORT datad (1365:1365:1365) (1355:1355:1355)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~22) + (DELAY + (ABSOLUTE + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (1365:1365:1365) (1355:1355:1355)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~23) + (DELAY + (ABSOLUTE + (PORT datab (1371:1371:1371) (1357:1357:1357)) + (PORT datac (571:571:571) (571:571:571)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~7) + (DELAY + (ABSOLUTE + (PORT datac (580:580:580) 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dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (594:594:594)) + (PORT datab (819:819:819) (759:759:759)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (624:624:624)) + (PORT datab (277:277:277) (302:302:302)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (477:477:477) (466:466:466)) + (PORT datab (567:567:567) (577:577:577)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (950:950:950) (886:886:886)) + (PORT datab (625:625:625) (614:614:614)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[0\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1308:1308:1308) (1252:1252:1252)) + (PORT datab (277:277:277) (303:303:303)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[1\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (507:507:507)) + (PORT datab (278:278:278) (304:304:304)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[1\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1672:1672:1672)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1702:1702:1702) (1649:1649:1649)) + (PORT ena (2393:2393:2393) (2302:2302:2302)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~26) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (PORT datac (1327:1327:1327) (1318:1318:1318)) + (PORT datad (532:532:532) (534:534:534)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[2\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (1400:1400:1400) (1354:1354:1354)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[2\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1672:1672:1672)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1702:1702:1702) (1649:1649:1649)) + (PORT ena (2393:2393:2393) (2302:2302:2302)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~29) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datab (1371:1371:1371) (1357:1357:1357)) + (PORT datac (572:572:572) (570:570:570)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[3\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) 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(PORT datab (419:419:419) (517:517:517)) + (PORT datac (575:575:575) (576:576:576)) + (PORT datad (323:323:323) (393:393:393)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[4\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (621:621:621)) + (PORT datab (535:535:535) (500:500:500)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[4\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1632:1632:1632) (1669:1669:1669)) + (PORT d (99:99:99) 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(472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[6\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1280:1280:1280) (1289:1289:1289)) + (PORT datab (619:619:619) (605:605:605)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[6\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~41) + (DELAY + (ABSOLUTE + (PORT datab (769:769:769) (828:828:828)) + (PORT datac (591:591:591) (642:642:642)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[7\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (472:472:472) (452:452:452)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[7\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~44) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (439:439:439)) + (PORT datac (573:573:573) (573:573:573)) + (PORT datad (379:379:379) (474:474:474)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[8\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (504:504:504)) + (PORT datab (964:964:964) (908:908:908)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[8\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~47) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (729:729:729)) + (PORT datab (769:769:769) (828:828:828)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[9\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (1272:1272:1272) (1278:1278:1278)) + (PORT datab (276:276:276) (301:301:301)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[9\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~50) + (DELAY + (ABSOLUTE + (PORT datab (419:419:419) (517:517:517)) + (PORT datac (571:571:571) (572:572:572)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[10\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (1275:1275:1275) (1276:1276:1276)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[10\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~53) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (PORT datac (570:570:570) (569:569:569)) + (PORT datad (379:379:379) (474:474:474)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[11\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (507:507:507)) + (PORT datab (565:565:565) (572:572:572)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[11\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~56) + (DELAY + (ABSOLUTE + (PORT datab (769:769:769) (828:828:828)) + (PORT datac (602:602:602) (652:652:652)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[12\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (498:498:498)) + (PORT datab (619:619:619) (603:603:603)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[12\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add5\~59) + (DELAY + (ABSOLUTE + (PORT datab (622:622:622) (683:683:683)) + (PORT datac (933:933:933) (929:929:929)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Vout\[13\]\~54) + (DELAY + (ABSOLUTE + (PORT datab (1338:1338:1338) (1249:1249:1249)) + (PORT datad (468:468:468) (436:436:436)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[13\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2132:2132:2132) (2157:2157:2157)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1699:1699:1699) (1647:1647:1647)) + (PORT ena (2365:2365:2365) (2251:2251:2251)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add7\~0) + (DELAY + (ABSOLUTE + (PORT datac (1304:1304:1304) (1339:1339:1339)) + (PORT datad (564:564:564) (582:582:582)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE Vout\[0\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (2134:2134:2134) (2162:2162:2162)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1702:1702:1702) (1649:1649:1649)) + (PORT ena (2828:2828:2828) (2685:2685:2685)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) +) diff --git a/pid/simulation/modelsim/rtl_work/_info b/pid/simulation/modelsim/rtl_work/_info new file mode 100644 index 0000000..d23aa2d --- /dev/null +++ b/pid/simulation/modelsim/rtl_work/_info @@ -0,0 +1,54 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dF:/Code/FPGA/reserve/pid/simulation/modelsim +vpid +Z1 !s110 1544265853 +!i10b 1 +!s100 e[ZYR;P^31YZ7:N]4KUnz0 +I]3KglQ_eI`cFdYMTB 10000) + tmp = 10000; + else if (tmp < 100) + tmp = 100; + #40; + Sample = tmp*0.4 + {$random} % 20; + end + #100; + SetPoint = 100+{$random} % 3500; + end + + $stop; + end + +endmodule diff --git a/pid/testbench/pid_tb.v.bak b/pid/testbench/pid_tb.v.bak new file mode 100644 index 0000000..bdbb7a8 --- /dev/null +++ b/pid/testbench/pid_tb.v.bak @@ -0,0 +1,49 @@ +`timescale 1ns/1ns + +`define clk_period 20 + +module pid_tb; + +//source define + + + + + + + + +//probe define + + + + + +//instant user module + pid pid + ( + input clk,rst_n,//50Mhz + input [13:0]Sample, //要比AD数字量多一位 + input [13:0]Position, + input [7:0]Kp, + input [7:0]Ki, + input [7:0]Kd, + output reg [15:0]Out_Ctrl //DA/PWM占空比调节 + ); + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + integer i; + + initial begin + + + + + + $stop; + end + +endmodule diff --git a/spwm/.qsys_edit/filters.xml b/spwm/.qsys_edit/filters.xml new file mode 100644 index 0000000..7272345 --- /dev/null +++ b/spwm/.qsys_edit/filters.xml @@ -0,0 +1,2 @@ + + diff --git a/spwm/.qsys_edit/preferences.xml b/spwm/.qsys_edit/preferences.xml new file mode 100644 index 0000000..58d766f --- /dev/null +++ b/spwm/.qsys_edit/preferences.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/spwm/__Previews/spwm_nativelink_simulation.rptPreview b/spwm/__Previews/spwm_nativelink_simulation.rptPreview new file mode 100644 index 0000000..63b8689 --- /dev/null +++ b/spwm/__Previews/spwm_nativelink_simulation.rptPreview @@ -0,0 +1,14 @@ +[Preview] +LargeImageOriginalSize=710000 +LargeImageWidth=355 +LargeImageHeight=500 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1F5DDD7F2E2E2921E4FB837131E629723766848D816F0E73B1B03595B3AFD3755AE828F0D9D1D9C933F4BD1B3A8ADC8D7B112B02B611E343D54E60FC8C58708DD8E8CBA21DFDE86CE161E7C6AEA91C2BCF7DFDDD3088D6233FE258E7E4981DC5EE4F515C62D8E2B22C64BC6A751445D526B92B534013E7CAA4B98F81745D7917585BAC1A93588721E7ECDABF16D343FA33BC2B4A576F71F463778E8B0921BF0276EBB5F982B7B0A5A378B41DB06FC307C522DED25160FE03EF84386EC79C9729CC99BF5563A2BE441B971F6B4EF097F3C58410420821841042C8F74435115D581388F961D55E0C615E389ECBB0659AAE97DC1D45D04D74C339A94BBF5D379DCC6B639EE2ECFE4FF7B77582A9CC83FB79E4BA1F5C19C62F2684FCBB584D44ACBDB0FEB5AD32ADB3A36505ED9DB7A5B2B61A6BA9A3181ACF3E4F4208F9CA584D04F473AABDB85C2F8B18145B65C40F5757C9C98D7DA11B2EB24C625F0C5D33EB20D6728E6C81B8708803F7EC7E218490AFC2693C7FFAFAC0F470488E05F5C18410420821E473C0FA10C4887F763BFE065ECBF387EF3E4A534E08F91E20B603340D5559482C641FC3623DAE9A8DFFBE551EEBEE108F021A07E484C6BA41C4C6801D97781ADD729DB3EA30103703E5109359CB234708FED73CD612CF22ACE5AEDCB1514ED670B87D31671DB7794B8761EB845E23CBFC9A46AC2FC9AB46F41D12EB23B41973DBC87982FD34E749DD34728CD1B5ADAAEB107374487A5DDF18FAC16A4CE2BED335DC77FDBC12EF9F10F2F783D80EAA7DB0393E62D66C715C3E8E47D184756E3647C8E2984187E1FD75BDF8F5FEFBEFE5F67DB057AAC36882BEA230760CB6D0C74C7E6C9EDAD609BD86C4E30873DCDD68627D84366BCE141B83E37AB9F9162F61BD36CE6D11F743EAA936E37B6CDBE2ECE9F70421E4F3416C87AB1BB7D91C1F6BFEB72D5B3C9777E34D1B8F023A628C4B2586868C316BD14AD8B2AAC340DC0CE83090AF09E3499B2304FBA90EA32C4AD9867642631BA17C2D36FABC38B69C8F19171FC2B8D8D609BD06E27154EE1C3A676F4B37FED6581FDA668C85A7CBE4B57721E7C9D837C9E47E13341813BBB2751817DBB81FA8A7DA88EF01366DF1C6E78490BF1BC476503B86B51A5B393EA03B5B9B2FB6E563F212F312EF8B8101D672848067C790E8FA93D861BC37E2EFF00EA87E614F3127DC6F68A8EBBAE57C3121841042082184907F0ECC2F604E5662215FA695D812E5ABB125F0BF6A1A5006F3A9A5E41FA917B129B05DB8EDA36811EA45F9C5B1BBDE6B295EC9A14A08217F23F091214713FCFD58BFACFAAE2D5FDDE58A394DAC57F69A01EB6BCAF242FC58D3D02C6253E8B6D8ECA87C0C7D5784907F11680AA04F384FE7FBD812D87E25B6846A1A34960FF27CF832E7456C0AE41299DC5FE8D26CF9B5F6D0161342C80D892DF1C87E1B9A86F7C4A6E83AC4C2A42D2684104208213744A75AADAF9FFD5D18F3E0E380BF11F3ED718EBE8F4073F27D16589F627302C6E0BE79767F13F251689C8536E43146CC86B518108BBCF3652DEBB9BAAEB9CB8B81F514B2D66DF2F10F7C9C8641EAE8867135FF85C63C88F37220C7C6D8FBB519D0441C8B52341188339C1DF3BB18EF361E45ACA3A883BE02F523DF3372851EDDB90EA7538807E1F348D7452EED1CA3752472CE75959C4FFD5C3FEAC1B1D00FB5EB9BB62A37FB56DB22F125828E03EBFA06576799DFFAC6F62DCA9ECF6769A73DEEE93CC9B1F0F92471336E3E4ECCB11F1D9DACD1EEA4CDB146C49F5F2BF3E6384FDBB77EEDB43F4F7C3FD73F9DE5BAACDD43889BA1F50F835FEB87F9F758E3827B03E7DC75EDE23A6DE55F917B63C3676BEF1B42FE16AC7FAAD91887585B3CF6B767B2AA5BB1DD9A1743F7A9FBF35D1D3846B7727C8D79807CF4563B91BB670D6B82F11D341158370C4D849479201EC5424711DA051B5521CEC5E8E3C4174579778E728CEB4AEE676757349E906A3170ACD11D0BE586A6B93FB750AFB6A5947781EA38FC7BA6327D63FB56CB56519FF5EE1D855C24C72C0DFBF9EF918B04B12910B3A2ABF2A011A9EF3422DA4795F4E1B8E85B7B9EDAC75A7F857C27FDFDBA45C4CDD0EDC32193FDB156DB6A54B46FFD398F8BEBB4957FE5D5EBECDEBB8C9541BE3B73EE89B15FC45940CC03C44C588B01616D319E2F8C251B3C6367BF4E197931A049488D8E013AE1A3C45DE892D48DDDFC6FE77BDF9ADA1C9B97036354E4D8C85C79C48DC0FF12EB66F236FE115BAC3A0A8CED708E38BF416C4C2B7183BAD6DB1EB4333F665236DDEDA59DF1719BB6179B32B8311DCA1CF18E98463916E2A015EE78887BB1756EDA16F493EA38F2A38FED9639FBE563F60C8BBE459F952BF1E4BC8DAB66EDC7228685EBBF02B6D08D332586515DDE694446B9364719BF6ADBB46FE53CF11BC99D675E758BFAABEAFE5D034A197FFBFA7B19175752DE6A54BAB0CE1AE78C35EA7A9D702E5BF9575EBBCEB66F09F9AE68EE89E9E4EF731B6701BFE5D7624020E663EE7E5FFE6A5E775CD131F8B834DBB939DF1AF360B6852BDF696CA0F7F44BF74A5C86FB36A3EF5ED776D8F7DC7BF89DB2BF3ACF47FA288FE624AAF2E3F295D8EBB4A571C17DB3759DF5BEF913FD4308218410420821E46B8379C33CCB92BEEF167E7F7C077F0D74175EF7E6734F209E84CC0F16A5C4D8ADE1530FB92B6CBE09ABBD828E427379C4B92BA0D790F9D671903812D028348E385604E2FA427F806D9B8BC3FAEABD7EA0157D00745AAAC9C0DCAD9E5BACA3208490AF80F5DD59BF3FEC27FC439DA36EBD5DD4DC132F3F5FC4EF3E4EDE27263E9DBE5BE49B88EBB1B93C0A934FD9E6E240FDF0E9C4BE24D4F3F29226FB975D7239071F7D68F35A3C0AD50758FF50B5A1A3208490AF405E37CE16E7627B5F7EFE27FA8653D724E9B1128DECCBCB4BD28B56C0E7F6999C2D2C8F4572485319BB16452DBE1FD8E2B6ED655C9CA5FB451D3697C7344DC97E97CEB92B0AF7179FB76D93EC9CAD4DD32C39A6E9B28D652BEF84CA8DC1DBF228BEB3EC90DEF9EAA10FC036D637C30FB8DBFB7134C6C57A6E8FE648228490CF04F12CB13EE2D1FD61B35FD3246CE59B782D97C77B508D88F5D58B3EC0E808BC26E2F97D4C082184104208218490EF0BE21F607E1A6BBB30F76BB517889380F80FD06AA80E03F991651ED9ED17C73FC0DA82ACA89332AC2DB6E5A103C11C3774201A67A10AFE44C459C8CB728EB300BD898DB3D0446B90D1E6DD2E4D4E432FFFD7FD306B52EC36D6D7D8DCD18410F255B1F10FF0BFD55E204EC2D0F8FFAD0E23DE4F812D3E9F86A41D31AF3CCDE5631D88C659C05A69D5979C2E38C6B8D09B6CC559802DC6DC75BED2064208F98EC878B5446C06AFAFB3DA0BE825F2742F7112A0C3802D45FC33E825F6B0ADE5BD5EA272E3DDB6F56B6BB57C8BF2453DDBE2B67363F12293FC238DB3ABD097541DC6B8375B6CB51BA748AB3C9CA6A46911B3E1719F21E2FEB47539EB010921E46F067112D2F4F05BE5553FB2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+ diff --git a/spwm/db/.cmp.kpt b/spwm/db/.cmp.kpt new file mode 100644 index 0000000..9dd72dc Binary files /dev/null and b/spwm/db/.cmp.kpt differ diff --git a/spwm/db/add_sub_lgh.tdf b/spwm/db/add_sub_lgh.tdf new file mode 100644 index 0000000..8efc501 --- /dev/null +++ b/spwm/db/add_sub_lgh.tdf @@ -0,0 +1,31 @@ +--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=12 ONE_INPUT_IS_CONSTANT="YES" dataa datab result +--VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END + + +-- Copyright (C) 2018 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details. + + + +--synthesis_resources = lut 12 +SUBDESIGN add_sub_lgh +( + dataa[11..0] : input; + datab[11..0] : input; + result[11..0] : output; +) +BEGIN + result[] = dataa[] + datab[]; +END; +--VALID FILE diff --git a/spwm/db/add_sub_pgh.tdf b/spwm/db/add_sub_pgh.tdf new file mode 100644 index 0000000..d771676 --- /dev/null +++ b/spwm/db/add_sub_pgh.tdf @@ -0,0 +1,31 @@ +--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_PIPELINE=0 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=16 ONE_INPUT_IS_CONSTANT="YES" dataa datab result +--VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END + + +-- Copyright (C) 2018 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details. + + + +--synthesis_resources = lut 16 +SUBDESIGN add_sub_pgh +( + dataa[15..0] : input; + datab[15..0] : input; + result[15..0] : output; +) +BEGIN + result[] = dataa[] + datab[]; +END; +--VALID FILE diff --git a/spwm/db/altsyncram_sl91.tdf b/spwm/db/altsyncram_sl91.tdf new file mode 100644 index 0000000..785a0f6 --- /dev/null +++ b/spwm/db/altsyncram_sl91.tdf @@ -0,0 +1,241 @@ +--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="sin9bit_1024.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=9 WIDTH_BYTEENA_A=1 WIDTHAD_A=10 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END + + +-- Copyright (C) 2018 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_sl91 +( + address_a[9..0] : input; + clock0 : input; + q_a[8..0] : output; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin9bit_1024.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 9, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin9bit_1024.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 9, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin9bit_1024.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 9, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin9bit_1024.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 9, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin9bit_1024.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 9, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin9bit_1024.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 9, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin9bit_1024.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 9, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin9bit_1024.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 9, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin9bit_1024.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 9, + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[9..0] : WIRE; + +BEGIN + ram_block1a[8..0].clk0 = clock0; + ram_block1a[8..0].portaaddr[] = ( address_a_wire[9..0]); + ram_block1a[8..0].portare = B"111111111"; + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[8..0].portadataout[0..0]); +END; +--VALID FILE diff --git a/spwm/db/altsyncram_uo91.tdf b/spwm/db/altsyncram_uo91.tdf new file mode 100644 index 0000000..7c291fd --- /dev/null +++ b/spwm/db/altsyncram_uo91.tdf @@ -0,0 +1,285 @@ +--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="sin12bit_2048.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=11 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END + + +-- Copyright (C) 2018 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 3 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_uo91 +( + address_a[10..0] : input; + clock0 : input; + q_a[10..0] : output; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 11, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 11, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 11, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 11, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 11, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 11, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 11, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 11, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 11, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 11, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 11, + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[10..0] : WIRE; + +BEGIN + ram_block1a[10..0].clk0 = clock0; + ram_block1a[10..0].portaaddr[] = ( address_a_wire[10..0]); + ram_block1a[10..0].portare = B"11111111111"; + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[10..0].portadataout[0..0]); +END; +--VALID FILE diff --git a/spwm/db/altsyncram_vo91.tdf b/spwm/db/altsyncram_vo91.tdf new file mode 100644 index 0000000..361b64e --- /dev/null +++ b/spwm/db/altsyncram_vo91.tdf @@ -0,0 +1,307 @@ +--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="sin12bit_2048.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=12 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:24:SJ cbx_altsyncram 2018:09:12:13:04:24:SJ cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_lpm_mux 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_stratixiii 2018:09:12:13:04:24:SJ cbx_stratixv 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END + + +-- Copyright (C) 2018 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 3 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_vo91 +( + address_a[10..0] : input; + clock0 : input; + q_a[11..0] : output; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK0_OUTPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "sin12bit_2048.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_CLEAR = "none", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "clock0", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 12, + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[10..0] : WIRE; + +BEGIN + ram_block1a[11..0].clk0 = clock0; + ram_block1a[11..0].portaaddr[] = ( address_a_wire[10..0]); + ram_block1a[11..0].portare = B"111111111111"; + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[11..0].portadataout[0..0]); +END; +--VALID FILE diff --git a/spwm/db/cntr_qgg.tdf b/spwm/db/cntr_qgg.tdf new file mode 100644 index 0000000..a9f6206 --- /dev/null +++ b/spwm/db/cntr_qgg.tdf @@ -0,0 +1,114 @@ +--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" lpm_port_updown="PORT_USED" lpm_width=9 clock q updown CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END + + +-- Copyright (C) 2018 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 9 reg 9 +SUBDESIGN cntr_qgg +( + clock : input; + q[8..0] : output; + updown : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita6 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita7 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita8 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[8..0] : dffeas; + aclr_actual : WIRE; + clk_en : NODE; + cnt_en : NODE; + data[8..0] : NODE; + external_cin : WIRE; + s_val[8..0] : WIRE; + safe_q[8..0] : WIRE; + sclr : NODE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[8..0].cin = ( counter_comb_bita[7..0].cout, external_cin); + counter_comb_bita[8..0].dataa = ( counter_reg_bit[8..0].q); + counter_comb_bita[8..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[8..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[8..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = B"0"; + clk_en = VCC; + cnt_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"111111111"; + safe_q[] = counter_reg_bit[].q; + sclr = GND; + sload = GND; + sset = GND; + updown_dir = updown; +END; +--VALID FILE diff --git a/spwm/db/cntr_sug.tdf b/spwm/db/cntr_sug.tdf new file mode 100644 index 0000000..7e3f78e --- /dev/null +++ b/spwm/db/cntr_sug.tdf @@ -0,0 +1,115 @@ +--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" lpm_port_updown="PORT_USED" lpm_width=9 aclr clock q updown CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_compare 2018:09:12:13:04:24:SJ cbx_lpm_counter 2018:09:12:13:04:24:SJ cbx_lpm_decode 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END + + +-- Copyright (C) 2018 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 9 reg 9 +SUBDESIGN cntr_sug +( + aclr : input; + clock : input; + q[8..0] : output; + updown : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita6 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita7 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita8 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[8..0] : dffeas; + aclr_actual : WIRE; + clk_en : NODE; + cnt_en : NODE; + data[8..0] : NODE; + external_cin : WIRE; + s_val[8..0] : WIRE; + safe_q[8..0] : WIRE; + sclr : NODE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[8..0].cin = ( counter_comb_bita[7..0].cout, external_cin); + counter_comb_bita[8..0].dataa = ( counter_reg_bit[8..0].q); + counter_comb_bita[8..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[8..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[8..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = aclr; + clk_en = VCC; + cnt_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"111111111"; + safe_q[] = counter_reg_bit[].q; + sclr = GND; + sload = GND; + sset = GND; + updown_dir = updown; +END; +--VALID FILE diff --git a/spwm/db/prev_cmp_spwm.qmsg b/spwm/db/prev_cmp_spwm.qmsg new file mode 100644 index 0000000..0985f8e --- /dev/null +++ b/spwm/db/prev_cmp_spwm.qmsg @@ -0,0 +1,32 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544446441463 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544446441479 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 20:54:01 2018 " "Processing started: Mon Dec 10 20:54:01 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544446441479 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446441479 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spwm -c spwm " "Command: quartus_map --read_settings_files=on --write_settings_files=off spwm -c spwm" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446441479 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1544446442110 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1544446442110 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/spwm.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/spwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 spwm " "Found entity 1: spwm" { } { { "rtl/spwm.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/spwm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446455228 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446455228 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testbench/spwm_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file testbench/spwm_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 spwm_tb " "Found entity 1: spwm_tb" { } { { "testbench/spwm_tb.v" "" { Text "F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446455233 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446455233 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spwm_sin.v 1 1 " "Found 1 design units, including 1 entities, in source file spwm_sin.v" { { "Info" "ISGN_ENTITY_NAME" "1 spwm_sin " "Found entity 1: spwm_sin" { } { { "spwm_sin.v" "" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446455237 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446455237 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/modulation.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/modulation.v" { { "Info" "ISGN_ENTITY_NAME" "1 modulation " "Found entity 1: modulation" { } { { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446455240 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446455240 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spwm " "Elaborating entity \"spwm\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1544446455414 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spwm_sin spwm_sin:spwm_sin " "Elaborating entity \"spwm_sin\" for hierarchy \"spwm_sin:spwm_sin\"" { } { { "rtl/spwm.v" "spwm_sin" { Text "F:/Code/FPGA/reserve/spwm/rtl/spwm.v" 70 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446455425 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram spwm_sin:spwm_sin\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\"" { } { { "spwm_sin.v" "altsyncram_component" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446455499 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "spwm_sin:spwm_sin\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\"" { } { { "spwm_sin.v" "" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446455504 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "spwm_sin:spwm_sin\|altsyncram:altsyncram_component " "Instantiated megafunction \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file sin9bit_1024.mif " "Parameter \"init_file\" = \"sin9bit_1024.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 9 " "Parameter \"width_a\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455504 ""} } { { "spwm_sin.v" "" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1544446455504 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sl91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sl91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sl91 " "Found entity 1: altsyncram_sl91" { } { { "db/altsyncram_sl91.tdf" "" { Text "F:/Code/FPGA/reserve/spwm/db/altsyncram_sl91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446455577 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446455577 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sl91 spwm_sin:spwm_sin\|altsyncram:altsyncram_component\|altsyncram_sl91:auto_generated " "Elaborating entity \"altsyncram_sl91\" for hierarchy \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\|altsyncram_sl91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446455578 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "modulation modulation:modulation " "Elaborating entity \"modulation\" for hierarchy \"modulation:modulation\"" { } { { "rtl/spwm.v" "modulation" { Text "F:/Code/FPGA/reserve/spwm/rtl/spwm.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446455585 ""} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "modulation:modulation\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"modulation:modulation\|Mult0\"" { } { { "rtl/modulation.v" "Mult0" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1544446455862 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1544446455862 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446455933 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "modulation:modulation\|lpm_mult:Mult0 " "Instantiated megafunction \"modulation:modulation\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 9 " "Parameter \"LPM_WIDTHA\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455933 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 8 " "Parameter \"LPM_WIDTHB\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455933 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 17 " "Parameter \"LPM_WIDTHP\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455933 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 17 " "Parameter \"LPM_WIDTHR\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455933 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455933 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455933 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455933 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455933 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446455933 ""} } { { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1544446455933 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 308 5 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446456008 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "multcore.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446456057 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446456121 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lgh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_lgh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lgh " "Found entity 1: add_sub_lgh" { } { { "db/add_sub_lgh.tdf" "" { Text "F:/Code/FPGA/reserve/spwm/db/add_sub_lgh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446456189 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446456189 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446456198 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446456208 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_pgh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_pgh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_pgh " "Found entity 1: add_sub_pgh" { } { { "db/add_sub_pgh.tdf" "" { Text "F:/Code/FPGA/reserve/spwm/db/add_sub_pgh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446456277 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446456277 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|altshift:external_latency_ffs modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 351 4 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446456320 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1544446456756 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1544446457357 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446457357 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "148 " "Implemented 148 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1544446457426 ""} { "Info" "ICUT_CUT_TM_OPINS" "19 " "Implemented 19 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1544446457426 ""} { "Info" "ICUT_CUT_TM_LCELLS" "92 " "Implemented 92 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1544446457426 ""} { "Info" "ICUT_CUT_TM_RAMS" "9 " "Implemented 9 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1544446457426 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1544446457426 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4803 " "Peak virtual memory: 4803 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544446457444 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 20:54:17 2018 " "Processing ended: Mon Dec 10 20:54:17 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544446457444 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544446457444 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:33 " "Total CPU time (on all processors): 00:00:33" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544446457444 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446457444 ""} diff --git a/spwm/db/spwm.(0).cnf.cdb b/spwm/db/spwm.(0).cnf.cdb new file mode 100644 index 0000000..f10d79b Binary files /dev/null and b/spwm/db/spwm.(0).cnf.cdb differ diff --git a/spwm/db/spwm.(0).cnf.hdb b/spwm/db/spwm.(0).cnf.hdb new file mode 100644 index 0000000..c099783 Binary files /dev/null and b/spwm/db/spwm.(0).cnf.hdb differ diff --git a/spwm/db/spwm.(1).cnf.cdb b/spwm/db/spwm.(1).cnf.cdb new file mode 100644 index 0000000..2de503d Binary files /dev/null and b/spwm/db/spwm.(1).cnf.cdb differ diff --git a/spwm/db/spwm.(1).cnf.hdb b/spwm/db/spwm.(1).cnf.hdb new file mode 100644 index 0000000..a6a68e1 Binary files /dev/null and b/spwm/db/spwm.(1).cnf.hdb differ diff --git a/spwm/db/spwm.(10).cnf.cdb b/spwm/db/spwm.(10).cnf.cdb new file mode 100644 index 0000000..425821c Binary files /dev/null and b/spwm/db/spwm.(10).cnf.cdb differ diff --git a/spwm/db/spwm.(10).cnf.hdb b/spwm/db/spwm.(10).cnf.hdb new file mode 100644 index 0000000..dd13cfe Binary files /dev/null and b/spwm/db/spwm.(10).cnf.hdb differ diff --git a/spwm/db/spwm.(11).cnf.cdb b/spwm/db/spwm.(11).cnf.cdb new file mode 100644 index 0000000..8779413 Binary files /dev/null and b/spwm/db/spwm.(11).cnf.cdb differ diff --git a/spwm/db/spwm.(11).cnf.hdb b/spwm/db/spwm.(11).cnf.hdb new file mode 100644 index 0000000..1bfc31f Binary files /dev/null and b/spwm/db/spwm.(11).cnf.hdb differ diff --git a/spwm/db/spwm.(12).cnf.cdb b/spwm/db/spwm.(12).cnf.cdb new file mode 100644 index 0000000..295340f Binary files /dev/null and b/spwm/db/spwm.(12).cnf.cdb differ diff --git a/spwm/db/spwm.(12).cnf.hdb b/spwm/db/spwm.(12).cnf.hdb new file mode 100644 index 0000000..b6297f2 Binary files /dev/null and b/spwm/db/spwm.(12).cnf.hdb differ diff --git a/spwm/db/spwm.(13).cnf.cdb b/spwm/db/spwm.(13).cnf.cdb new file mode 100644 index 0000000..06ba6d3 Binary files /dev/null and b/spwm/db/spwm.(13).cnf.cdb differ diff --git a/spwm/db/spwm.(13).cnf.hdb b/spwm/db/spwm.(13).cnf.hdb new file mode 100644 index 0000000..679bc66 Binary files /dev/null and b/spwm/db/spwm.(13).cnf.hdb differ diff --git a/spwm/db/spwm.(14).cnf.cdb b/spwm/db/spwm.(14).cnf.cdb new file mode 100644 index 0000000..9d9236f Binary files /dev/null and b/spwm/db/spwm.(14).cnf.cdb differ diff --git a/spwm/db/spwm.(14).cnf.hdb b/spwm/db/spwm.(14).cnf.hdb new file mode 100644 index 0000000..53e48f9 Binary files /dev/null and b/spwm/db/spwm.(14).cnf.hdb differ diff --git a/spwm/db/spwm.(15).cnf.cdb b/spwm/db/spwm.(15).cnf.cdb new file mode 100644 index 0000000..768a03b Binary files /dev/null and b/spwm/db/spwm.(15).cnf.cdb differ diff --git a/spwm/db/spwm.(15).cnf.hdb b/spwm/db/spwm.(15).cnf.hdb new file mode 100644 index 0000000..906caea Binary files /dev/null and b/spwm/db/spwm.(15).cnf.hdb differ diff --git a/spwm/db/spwm.(16).cnf.cdb b/spwm/db/spwm.(16).cnf.cdb new file mode 100644 index 0000000..c9f148a Binary files /dev/null and b/spwm/db/spwm.(16).cnf.cdb differ diff --git a/spwm/db/spwm.(16).cnf.hdb b/spwm/db/spwm.(16).cnf.hdb new file mode 100644 index 0000000..70f8997 Binary files /dev/null and b/spwm/db/spwm.(16).cnf.hdb differ diff --git a/spwm/db/spwm.(17).cnf.cdb b/spwm/db/spwm.(17).cnf.cdb new file mode 100644 index 0000000..3370b77 Binary files /dev/null and b/spwm/db/spwm.(17).cnf.cdb differ diff --git a/spwm/db/spwm.(17).cnf.hdb b/spwm/db/spwm.(17).cnf.hdb new file mode 100644 index 0000000..e3c698f Binary files /dev/null and b/spwm/db/spwm.(17).cnf.hdb differ diff --git a/spwm/db/spwm.(18).cnf.cdb b/spwm/db/spwm.(18).cnf.cdb new file mode 100644 index 0000000..5e1d43a Binary files /dev/null and b/spwm/db/spwm.(18).cnf.cdb differ diff --git a/spwm/db/spwm.(18).cnf.hdb b/spwm/db/spwm.(18).cnf.hdb new file mode 100644 index 0000000..a8c4e9e Binary files /dev/null and b/spwm/db/spwm.(18).cnf.hdb differ diff --git a/spwm/db/spwm.(19).cnf.cdb b/spwm/db/spwm.(19).cnf.cdb new file mode 100644 index 0000000..24d81fa Binary files /dev/null and b/spwm/db/spwm.(19).cnf.cdb differ diff --git a/spwm/db/spwm.(19).cnf.hdb b/spwm/db/spwm.(19).cnf.hdb new file mode 100644 index 0000000..a9d8607 Binary files /dev/null and b/spwm/db/spwm.(19).cnf.hdb differ diff --git a/spwm/db/spwm.(2).cnf.cdb b/spwm/db/spwm.(2).cnf.cdb new file mode 100644 index 0000000..46367af Binary files /dev/null and b/spwm/db/spwm.(2).cnf.cdb differ diff --git a/spwm/db/spwm.(2).cnf.hdb b/spwm/db/spwm.(2).cnf.hdb new file mode 100644 index 0000000..2538820 Binary files /dev/null and b/spwm/db/spwm.(2).cnf.hdb differ diff --git a/spwm/db/spwm.(20).cnf.cdb b/spwm/db/spwm.(20).cnf.cdb new file mode 100644 index 0000000..94d1bb4 Binary files /dev/null and b/spwm/db/spwm.(20).cnf.cdb differ diff --git a/spwm/db/spwm.(20).cnf.hdb b/spwm/db/spwm.(20).cnf.hdb new file mode 100644 index 0000000..c8777e0 Binary files /dev/null and b/spwm/db/spwm.(20).cnf.hdb differ diff --git a/spwm/db/spwm.(21).cnf.cdb b/spwm/db/spwm.(21).cnf.cdb new file mode 100644 index 0000000..00f5f5d Binary files /dev/null and b/spwm/db/spwm.(21).cnf.cdb differ diff --git a/spwm/db/spwm.(21).cnf.hdb b/spwm/db/spwm.(21).cnf.hdb new file mode 100644 index 0000000..233b5ac Binary files /dev/null and b/spwm/db/spwm.(21).cnf.hdb differ diff --git a/spwm/db/spwm.(22).cnf.cdb b/spwm/db/spwm.(22).cnf.cdb new file mode 100644 index 0000000..a22331c Binary files /dev/null and b/spwm/db/spwm.(22).cnf.cdb differ diff --git a/spwm/db/spwm.(22).cnf.hdb b/spwm/db/spwm.(22).cnf.hdb new file mode 100644 index 0000000..c5a2e48 Binary files /dev/null and b/spwm/db/spwm.(22).cnf.hdb differ diff --git a/spwm/db/spwm.(23).cnf.cdb b/spwm/db/spwm.(23).cnf.cdb new file mode 100644 index 0000000..9d4377c Binary files /dev/null and b/spwm/db/spwm.(23).cnf.cdb differ diff --git a/spwm/db/spwm.(23).cnf.hdb b/spwm/db/spwm.(23).cnf.hdb new file mode 100644 index 0000000..1c6dea8 Binary files /dev/null and b/spwm/db/spwm.(23).cnf.hdb differ diff --git a/spwm/db/spwm.(24).cnf.cdb b/spwm/db/spwm.(24).cnf.cdb new file mode 100644 index 0000000..7ed3907 Binary files /dev/null and b/spwm/db/spwm.(24).cnf.cdb differ diff --git a/spwm/db/spwm.(24).cnf.hdb b/spwm/db/spwm.(24).cnf.hdb new file mode 100644 index 0000000..58ca4b9 Binary files /dev/null and b/spwm/db/spwm.(24).cnf.hdb differ diff --git a/spwm/db/spwm.(25).cnf.cdb b/spwm/db/spwm.(25).cnf.cdb new file mode 100644 index 0000000..ff03fbd Binary files /dev/null and b/spwm/db/spwm.(25).cnf.cdb differ diff --git a/spwm/db/spwm.(25).cnf.hdb b/spwm/db/spwm.(25).cnf.hdb new file mode 100644 index 0000000..6aa7b27 Binary files /dev/null and b/spwm/db/spwm.(25).cnf.hdb differ diff --git a/spwm/db/spwm.(26).cnf.cdb b/spwm/db/spwm.(26).cnf.cdb new file mode 100644 index 0000000..488d8ed Binary files /dev/null and b/spwm/db/spwm.(26).cnf.cdb differ diff --git a/spwm/db/spwm.(26).cnf.hdb b/spwm/db/spwm.(26).cnf.hdb new file mode 100644 index 0000000..f50dd2e Binary files /dev/null and b/spwm/db/spwm.(26).cnf.hdb differ diff --git a/spwm/db/spwm.(27).cnf.cdb b/spwm/db/spwm.(27).cnf.cdb new file mode 100644 index 0000000..1f77345 Binary files /dev/null and b/spwm/db/spwm.(27).cnf.cdb differ diff --git a/spwm/db/spwm.(27).cnf.hdb b/spwm/db/spwm.(27).cnf.hdb new file mode 100644 index 0000000..2d773c3 Binary files /dev/null and b/spwm/db/spwm.(27).cnf.hdb differ diff --git a/spwm/db/spwm.(3).cnf.cdb b/spwm/db/spwm.(3).cnf.cdb new file mode 100644 index 0000000..92a1de7 Binary files /dev/null and b/spwm/db/spwm.(3).cnf.cdb differ diff --git a/spwm/db/spwm.(3).cnf.hdb b/spwm/db/spwm.(3).cnf.hdb new file mode 100644 index 0000000..22a6757 Binary files /dev/null and b/spwm/db/spwm.(3).cnf.hdb differ diff --git a/spwm/db/spwm.(4).cnf.cdb b/spwm/db/spwm.(4).cnf.cdb new file mode 100644 index 0000000..92cd264 Binary files /dev/null and b/spwm/db/spwm.(4).cnf.cdb differ diff --git a/spwm/db/spwm.(4).cnf.hdb b/spwm/db/spwm.(4).cnf.hdb new file mode 100644 index 0000000..b8e408f Binary files /dev/null and b/spwm/db/spwm.(4).cnf.hdb differ diff --git a/spwm/db/spwm.(5).cnf.cdb b/spwm/db/spwm.(5).cnf.cdb new file mode 100644 index 0000000..0594aab Binary files /dev/null and b/spwm/db/spwm.(5).cnf.cdb differ diff --git a/spwm/db/spwm.(5).cnf.hdb b/spwm/db/spwm.(5).cnf.hdb new file mode 100644 index 0000000..87dc98b Binary files /dev/null and b/spwm/db/spwm.(5).cnf.hdb differ diff --git a/spwm/db/spwm.(6).cnf.cdb b/spwm/db/spwm.(6).cnf.cdb new file mode 100644 index 0000000..0b0b87c Binary files /dev/null and b/spwm/db/spwm.(6).cnf.cdb differ diff --git a/spwm/db/spwm.(6).cnf.hdb b/spwm/db/spwm.(6).cnf.hdb new file mode 100644 index 0000000..4cf2d78 Binary files /dev/null and b/spwm/db/spwm.(6).cnf.hdb differ diff --git a/spwm/db/spwm.(7).cnf.cdb b/spwm/db/spwm.(7).cnf.cdb new file mode 100644 index 0000000..41f9352 Binary files /dev/null and b/spwm/db/spwm.(7).cnf.cdb differ diff --git a/spwm/db/spwm.(7).cnf.hdb b/spwm/db/spwm.(7).cnf.hdb new file mode 100644 index 0000000..822c869 Binary files /dev/null and b/spwm/db/spwm.(7).cnf.hdb differ diff --git a/spwm/db/spwm.(8).cnf.cdb b/spwm/db/spwm.(8).cnf.cdb new file mode 100644 index 0000000..89c104f Binary files /dev/null and b/spwm/db/spwm.(8).cnf.cdb differ diff --git a/spwm/db/spwm.(8).cnf.hdb b/spwm/db/spwm.(8).cnf.hdb new file mode 100644 index 0000000..c9864cf Binary files /dev/null and b/spwm/db/spwm.(8).cnf.hdb differ diff --git a/spwm/db/spwm.(9).cnf.cdb b/spwm/db/spwm.(9).cnf.cdb new file mode 100644 index 0000000..170e7b0 Binary files /dev/null and b/spwm/db/spwm.(9).cnf.cdb differ diff --git a/spwm/db/spwm.(9).cnf.hdb b/spwm/db/spwm.(9).cnf.hdb new file mode 100644 index 0000000..be53ea3 Binary files /dev/null and b/spwm/db/spwm.(9).cnf.hdb differ diff --git a/spwm/db/spwm.ae.hdb b/spwm/db/spwm.ae.hdb new file mode 100644 index 0000000..5296f8c Binary files /dev/null and b/spwm/db/spwm.ae.hdb differ diff --git a/spwm/db/spwm.asm.qmsg b/spwm/db/spwm.asm.qmsg new file mode 100644 index 0000000..858cc62 --- /dev/null +++ b/spwm/db/spwm.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544446524588 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544446524603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 20:55:24 2018 " "Processing started: Mon Dec 10 20:55:24 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544446524603 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1544446524603 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spwm -c spwm " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spwm -c spwm" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1544446524603 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1544446525096 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1544446525455 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1544446525480 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4695 " "Peak virtual memory: 4695 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544446525648 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 20:55:25 2018 " "Processing ended: Mon Dec 10 20:55:25 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544446525648 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544446525648 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544446525648 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1544446525648 ""} diff --git a/spwm/db/spwm.asm.rdb b/spwm/db/spwm.asm.rdb new file mode 100644 index 0000000..76d17d1 Binary files /dev/null and b/spwm/db/spwm.asm.rdb differ diff --git a/spwm/db/spwm.asm_labs.ddb b/spwm/db/spwm.asm_labs.ddb new file mode 100644 index 0000000..c2016e4 Binary files /dev/null and b/spwm/db/spwm.asm_labs.ddb differ diff --git a/spwm/db/spwm.cbx.xml b/spwm/db/spwm.cbx.xml new file mode 100644 index 0000000..a3092a7 --- /dev/null +++ b/spwm/db/spwm.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/spwm/db/spwm.cmp.bpm b/spwm/db/spwm.cmp.bpm new file mode 100644 index 0000000..6522a57 Binary files /dev/null and b/spwm/db/spwm.cmp.bpm differ diff --git a/spwm/db/spwm.cmp.cdb b/spwm/db/spwm.cmp.cdb new file mode 100644 index 0000000..78cd98a Binary files /dev/null and b/spwm/db/spwm.cmp.cdb differ diff --git a/spwm/db/spwm.cmp.hdb b/spwm/db/spwm.cmp.hdb new file mode 100644 index 0000000..46d9873 Binary files /dev/null and b/spwm/db/spwm.cmp.hdb differ diff --git a/spwm/db/spwm.cmp.idb b/spwm/db/spwm.cmp.idb new file mode 100644 index 0000000..6c1bfc4 Binary files /dev/null and b/spwm/db/spwm.cmp.idb differ diff --git a/spwm/db/spwm.cmp.logdb b/spwm/db/spwm.cmp.logdb new file mode 100644 index 0000000..a9c77ac --- /dev/null +++ b/spwm/db/spwm.cmp.logdb @@ -0,0 +1,89 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;47;0;0;47;47;0;19;0;0;28;0;19;28;0;0;0;19;0;0;0;0;0;47;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,47;47;47;47;47;0;47;47;0;0;47;28;47;47;19;47;28;19;47;47;47;28;47;47;47;47;47;0;47;47, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,tri_out[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tri_out[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tri_out[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tri_out[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tri_out[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tri_out[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tri_out[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tri_out[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tri_out[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sin_out[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sin_out[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sin_out[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sin_out[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sin_out[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sin_out[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sin_out[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sin_out[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sin_out[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,spwm_out,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,clk_200m,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,rst_n,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Pword[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Pword[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Pword[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Pword[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Pword[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Pword[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Pword[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Pword[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Pword[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Pword[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Fword[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21, diff --git a/spwm/db/spwm.cmp.rdb b/spwm/db/spwm.cmp.rdb new file mode 100644 index 0000000..d65ccfe Binary files /dev/null and b/spwm/db/spwm.cmp.rdb differ diff --git a/spwm/db/spwm.cmp_merge.kpt b/spwm/db/spwm.cmp_merge.kpt new file mode 100644 index 0000000..3276a6f Binary files /dev/null and b/spwm/db/spwm.cmp_merge.kpt differ diff --git a/spwm/db/spwm.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/spwm/db/spwm.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd new file mode 100644 index 0000000..d24bd1b Binary files /dev/null and b/spwm/db/spwm.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd differ diff --git a/spwm/db/spwm.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd b/spwm/db/spwm.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd new file mode 100644 index 0000000..87b0f3a Binary files /dev/null and b/spwm/db/spwm.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd differ diff --git a/spwm/db/spwm.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd b/spwm/db/spwm.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd new file mode 100644 index 0000000..835548b Binary files /dev/null and b/spwm/db/spwm.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd differ diff --git a/spwm/db/spwm.db_info b/spwm/db/spwm.db_info new file mode 100644 index 0000000..af9f9b1 --- /dev/null +++ b/spwm/db/spwm.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Version_Index = 486699264 +Creation_Time = Sat Dec 08 18:55:20 2018 diff --git a/spwm/db/spwm.eda.qmsg b/spwm/db/spwm.eda.qmsg new file mode 100644 index 0000000..64e685d --- /dev/null +++ b/spwm/db/spwm.eda.qmsg @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544446530968 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544446530982 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 20:55:30 2018 " "Processing started: Mon Dec 10 20:55:30 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544446530982 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1544446530982 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spwm -c spwm " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spwm -c spwm" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1544446530983 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1544446531719 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spwm_8_1200mv_85c_slow.vo F:/Code/FPGA/reserve/spwm/simulation/modelsim/ simulation " "Generated file spwm_8_1200mv_85c_slow.vo in folder \"F:/Code/FPGA/reserve/spwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544446531933 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spwm_8_1200mv_0c_slow.vo F:/Code/FPGA/reserve/spwm/simulation/modelsim/ simulation " "Generated file spwm_8_1200mv_0c_slow.vo in folder \"F:/Code/FPGA/reserve/spwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544446531990 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spwm_min_1200mv_0c_fast.vo F:/Code/FPGA/reserve/spwm/simulation/modelsim/ simulation " "Generated file spwm_min_1200mv_0c_fast.vo in folder \"F:/Code/FPGA/reserve/spwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544446532051 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spwm.vo F:/Code/FPGA/reserve/spwm/simulation/modelsim/ simulation " "Generated file spwm.vo in folder \"F:/Code/FPGA/reserve/spwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544446532110 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spwm_8_1200mv_85c_v_slow.sdo F:/Code/FPGA/reserve/spwm/simulation/modelsim/ simulation " "Generated file spwm_8_1200mv_85c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/spwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544446532140 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spwm_8_1200mv_0c_v_slow.sdo F:/Code/FPGA/reserve/spwm/simulation/modelsim/ simulation " "Generated file spwm_8_1200mv_0c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/spwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544446532170 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spwm_min_1200mv_0c_v_fast.sdo F:/Code/FPGA/reserve/spwm/simulation/modelsim/ simulation " "Generated file spwm_min_1200mv_0c_v_fast.sdo in folder \"F:/Code/FPGA/reserve/spwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544446532198 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "spwm_v.sdo F:/Code/FPGA/reserve/spwm/simulation/modelsim/ simulation " "Generated file spwm_v.sdo in folder \"F:/Code/FPGA/reserve/spwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1544446532229 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544446532279 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 20:55:32 2018 " "Processing ended: Mon Dec 10 20:55:32 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544446532279 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544446532279 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544446532279 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1544446532279 ""} diff --git a/spwm/db/spwm.fit.qmsg b/spwm/db/spwm.fit.qmsg new file mode 100644 index 0000000..600a368 --- /dev/null +++ b/spwm/db/spwm.fit.qmsg @@ -0,0 +1,49 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1544446517127 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1544446517128 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "spwm EP4CE10F17C8 " "Selected device EP4CE10F17C8 for design \"spwm\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1544446517171 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1544446517251 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1544446517251 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1544446517387 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Device EP4CE6F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1544446517568 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1544446517568 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1544446517568 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1544446517568 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/spwm/" { { 0 { 0 ""} 0 484 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544446517570 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/spwm/" { { 0 { 0 ""} 0 486 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544446517570 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/spwm/" { { 0 { 0 ""} 0 488 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544446517570 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/spwm/" { { 0 { 0 ""} 0 490 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544446517570 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/spwm/" { { 0 { 0 ""} 0 492 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1544446517570 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1544446517570 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1544446517572 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1544446517575 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "47 47 " "No exact pin location assignment(s) for 47 pins of 47 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1544446517855 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spwm.sdc " "Synopsys Design Constraints File file not found: 'spwm.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1544446518199 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1544446518200 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1544446518204 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1544446518204 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1544446518204 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_200m~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk_200m~input (placed in PIN E1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1544446518231 ""} } { { "rtl/spwm.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/spwm.v" 11 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/spwm/" { { 0 { 0 ""} 0 452 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1544446518231 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1544446518231 ""} } { { "rtl/spwm.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/spwm.v" 12 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/spwm/" { { 0 { 0 ""} 0 453 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1544446518231 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1544446518451 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1544446518451 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1544446518451 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1544446518452 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1544446518453 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1544446518453 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1544446518453 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1544446518453 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1544446518467 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1544446518468 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1544446518468 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "45 unused 2.5V 26 19 0 " "Number of I/O pins in group: 45 (unused VREF, 2.5V VCCIO, 26 input, 19 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1544446518470 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1544446518470 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1544446518470 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 12 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544446518470 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 18 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544446518470 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 26 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544446518470 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 27 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544446518470 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 25 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544446518470 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 13 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544446518470 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 26 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544446518470 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 26 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1544446518470 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1544446518470 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1544446518470 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544446518507 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1544446518512 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1544446519048 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544446519097 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1544446519111 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1544446520612 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544446520612 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1544446520853 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X0_Y12 X10_Y24 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X0_Y12 to location X10_Y24" { } { { "loc" "" { Generic "F:/Code/FPGA/reserve/spwm/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X0_Y12 to location X10_Y24"} { { 12 { 0 ""} 0 12 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1544446521297 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1544446521297 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1544446521540 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1544446521540 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544446521543 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.19 " "Total time spent on timing analysis during the Fitter is 0.19 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1544446521685 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1544446521692 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1544446521853 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1544446521853 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1544446522015 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1544446522434 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/Code/FPGA/reserve/spwm/output_files/spwm.fit.smsg " "Generated suppressed messages file F:/Code/FPGA/reserve/spwm/output_files/spwm.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1544446522769 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5561 " "Peak virtual memory: 5561 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544446523168 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 20:55:23 2018 " "Processing ended: Mon Dec 10 20:55:23 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544446523168 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544446523168 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544446523168 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1544446523168 ""} diff --git a/spwm/db/spwm.hier_info b/spwm/db/spwm.hier_info new file mode 100644 index 0000000..52279dd --- /dev/null +++ b/spwm/db/spwm.hier_info @@ -0,0 +1,303 @@ +|spwm +clk_200m => clk_200m.IN2 +rst_n => F_acc[0].ACLR +rst_n => F_acc[1].ACLR +rst_n => F_acc[2].ACLR +rst_n => F_acc[3].ACLR +rst_n => F_acc[4].ACLR +rst_n => F_acc[5].ACLR +rst_n => F_acc[6].ACLR +rst_n => F_acc[7].ACLR +rst_n => F_acc[8].ACLR +rst_n => F_acc[9].ACLR +rst_n => F_acc[10].ACLR +rst_n => F_acc[11].ACLR +rst_n => F_acc[12].ACLR +rst_n => F_acc[13].ACLR +rst_n => F_acc[14].ACLR +rst_n => F_acc[15].ACLR +rst_n => F_acc[16].ACLR +rst_n => F_acc[17].ACLR +rst_n => F_acc[18].ACLR +rst_n => F_acc[19].ACLR +rst_n => F_acc[20].ACLR +rst_n => F_acc[21].ACLR +rst_n => F_acc[22].ACLR +rst_n => F_acc[23].ACLR +rst_n => F_acc[24].ACLR +rst_n => F_acc[25].ACLR +rst_n => updown.ACLR +rst_n => tri_out[0]~reg0.ACLR +rst_n => tri_out[1]~reg0.ACLR +rst_n => tri_out[2]~reg0.ACLR +rst_n => tri_out[3]~reg0.ACLR +rst_n => tri_out[4]~reg0.ACLR +rst_n => tri_out[5]~reg0.ACLR +rst_n => tri_out[6]~reg0.ACLR +rst_n => tri_out[7]~reg0.ACLR +rst_n => tri_out[8]~reg0.ACLR +tri_out[0] << tri_out[0].DB_MAX_OUTPUT_PORT_TYPE +tri_out[1] << tri_out[1].DB_MAX_OUTPUT_PORT_TYPE +tri_out[2] << tri_out[2].DB_MAX_OUTPUT_PORT_TYPE +tri_out[3] << tri_out[3].DB_MAX_OUTPUT_PORT_TYPE +tri_out[4] << tri_out[4].DB_MAX_OUTPUT_PORT_TYPE +tri_out[5] << tri_out[5].DB_MAX_OUTPUT_PORT_TYPE +tri_out[6] << tri_out[6].DB_MAX_OUTPUT_PORT_TYPE +tri_out[7] << tri_out[7].DB_MAX_OUTPUT_PORT_TYPE +tri_out[8] << tri_out[8].DB_MAX_OUTPUT_PORT_TYPE +sin_out[0] << sin_out[0].DB_MAX_OUTPUT_PORT_TYPE +sin_out[1] << sin_out[1].DB_MAX_OUTPUT_PORT_TYPE +sin_out[2] << sin_out[2].DB_MAX_OUTPUT_PORT_TYPE +sin_out[3] << sin_out[3].DB_MAX_OUTPUT_PORT_TYPE +sin_out[4] << sin_out[4].DB_MAX_OUTPUT_PORT_TYPE +sin_out[5] << sin_out[5].DB_MAX_OUTPUT_PORT_TYPE +sin_out[6] << sin_out[6].DB_MAX_OUTPUT_PORT_TYPE +sin_out[7] << sin_out[7].DB_MAX_OUTPUT_PORT_TYPE +sin_out[8] << sin_out[8].DB_MAX_OUTPUT_PORT_TYPE +Fword[0] => Add1.IN26 +Fword[1] => Add1.IN25 +Fword[2] => Add1.IN24 +Fword[3] => Add1.IN23 +Fword[4] => Add1.IN22 +Fword[5] => Add1.IN21 +Fword[6] => Add1.IN20 +Fword[7] => Add1.IN19 +Fword[8] => Add1.IN18 +Fword[9] => Add1.IN17 +Fword[10] => Add1.IN16 +Fword[11] => Add1.IN15 +Fword[12] => Add1.IN14 +Fword[13] => Add1.IN13 +Fword[14] => Add1.IN12 +Fword[15] => Add1.IN11 +Pword[0] => Add0.IN10 +Pword[1] => Add0.IN9 +Pword[2] => Add0.IN8 +Pword[3] => Add0.IN7 +Pword[4] => Add0.IN6 +Pword[5] => Add0.IN5 +Pword[6] => Add0.IN4 +Pword[7] => Add0.IN3 +Pword[8] => Add0.IN2 +Pword[9] => Add0.IN1 +spwm_out << modulation:modulation.out + + +|spwm|spwm_sin:spwm_sin +address[0] => address[0].IN1 +address[1] => address[1].IN1 +address[2] => address[2].IN1 +address[3] => address[3].IN1 +address[4] => address[4].IN1 +address[5] => address[5].IN1 +address[6] => address[6].IN1 +address[7] => address[7].IN1 +address[8] => address[8].IN1 +address[9] => address[9].IN1 +clock => clock.IN1 +q[0] <= altsyncram:altsyncram_component.q_a +q[1] <= altsyncram:altsyncram_component.q_a +q[2] <= altsyncram:altsyncram_component.q_a +q[3] <= altsyncram:altsyncram_component.q_a +q[4] <= altsyncram:altsyncram_component.q_a +q[5] <= altsyncram:altsyncram_component.q_a +q[6] <= altsyncram:altsyncram_component.q_a +q[7] <= altsyncram:altsyncram_component.q_a +q[8] <= altsyncram:altsyncram_component.q_a + + +|spwm|spwm_sin:spwm_sin|altsyncram:altsyncram_component +wren_a => ~NO_FANOUT~ +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => ~NO_FANOUT~ +data_a[1] => ~NO_FANOUT~ +data_a[2] => ~NO_FANOUT~ +data_a[3] => ~NO_FANOUT~ +data_a[4] => ~NO_FANOUT~ +data_a[5] => ~NO_FANOUT~ +data_a[6] => ~NO_FANOUT~ +data_a[7] => ~NO_FANOUT~ +data_a[8] => ~NO_FANOUT~ +data_b[0] => ~NO_FANOUT~ +address_a[0] => altsyncram_sl91:auto_generated.address_a[0] +address_a[1] => altsyncram_sl91:auto_generated.address_a[1] +address_a[2] => altsyncram_sl91:auto_generated.address_a[2] +address_a[3] => altsyncram_sl91:auto_generated.address_a[3] +address_a[4] => altsyncram_sl91:auto_generated.address_a[4] +address_a[5] => altsyncram_sl91:auto_generated.address_a[5] +address_a[6] => altsyncram_sl91:auto_generated.address_a[6] +address_a[7] => altsyncram_sl91:auto_generated.address_a[7] +address_a[8] => altsyncram_sl91:auto_generated.address_a[8] +address_a[9] => altsyncram_sl91:auto_generated.address_a[9] +address_b[0] => ~NO_FANOUT~ +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_sl91:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= altsyncram_sl91:auto_generated.q_a[0] +q_a[1] <= altsyncram_sl91:auto_generated.q_a[1] +q_a[2] <= altsyncram_sl91:auto_generated.q_a[2] +q_a[3] <= altsyncram_sl91:auto_generated.q_a[3] +q_a[4] <= altsyncram_sl91:auto_generated.q_a[4] +q_a[5] <= altsyncram_sl91:auto_generated.q_a[5] +q_a[6] <= altsyncram_sl91:auto_generated.q_a[6] +q_a[7] <= altsyncram_sl91:auto_generated.q_a[7] +q_a[8] <= altsyncram_sl91:auto_generated.q_a[8] +q_b[0] <= +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|spwm|spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[7] => ram_block1a0.PORTAADDR7 +address_a[7] => ram_block1a1.PORTAADDR7 +address_a[7] => ram_block1a2.PORTAADDR7 +address_a[7] => ram_block1a3.PORTAADDR7 +address_a[7] => ram_block1a4.PORTAADDR7 +address_a[7] => ram_block1a5.PORTAADDR7 +address_a[7] => ram_block1a6.PORTAADDR7 +address_a[7] => ram_block1a7.PORTAADDR7 +address_a[7] => ram_block1a8.PORTAADDR7 +address_a[8] => ram_block1a0.PORTAADDR8 +address_a[8] => ram_block1a1.PORTAADDR8 +address_a[8] => ram_block1a2.PORTAADDR8 +address_a[8] => ram_block1a3.PORTAADDR8 +address_a[8] => ram_block1a4.PORTAADDR8 +address_a[8] => ram_block1a5.PORTAADDR8 +address_a[8] => ram_block1a6.PORTAADDR8 +address_a[8] => ram_block1a7.PORTAADDR8 +address_a[8] => ram_block1a8.PORTAADDR8 +address_a[9] => ram_block1a0.PORTAADDR9 +address_a[9] => ram_block1a1.PORTAADDR9 +address_a[9] => ram_block1a2.PORTAADDR9 +address_a[9] => ram_block1a3.PORTAADDR9 +address_a[9] => ram_block1a4.PORTAADDR9 +address_a[9] => ram_block1a5.PORTAADDR9 +address_a[9] => ram_block1a6.PORTAADDR9 +address_a[9] => ram_block1a7.PORTAADDR9 +address_a[9] => ram_block1a8.PORTAADDR9 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +q_a[0] <= ram_block1a0.PORTADATAOUT +q_a[1] <= ram_block1a1.PORTADATAOUT +q_a[2] <= ram_block1a2.PORTADATAOUT +q_a[3] <= ram_block1a3.PORTADATAOUT +q_a[4] <= ram_block1a4.PORTADATAOUT +q_a[5] <= ram_block1a5.PORTADATAOUT +q_a[6] <= ram_block1a6.PORTADATAOUT +q_a[7] <= ram_block1a7.PORTADATAOUT +q_a[8] <= ram_block1a8.PORTADATAOUT + + +|spwm|modulation:modulation +clk_200m => out~reg0.CLK +tri_out[0] => LessThan0.IN17 +tri_out[1] => LessThan0.IN16 +tri_out[2] => LessThan0.IN15 +tri_out[3] => LessThan0.IN14 +tri_out[4] => LessThan0.IN13 +tri_out[5] => LessThan0.IN12 +tri_out[6] => LessThan0.IN11 +tri_out[7] => LessThan0.IN10 +tri_out[8] => LessThan0.IN9 +sin_out[0] => Mult0.IN8 +sin_out[1] => Mult0.IN7 +sin_out[2] => Mult0.IN6 +sin_out[3] => Mult0.IN5 +sin_out[4] => Mult0.IN4 +sin_out[5] => Mult0.IN3 +sin_out[6] => Mult0.IN2 +sin_out[7] => Mult0.IN1 +sin_out[8] => Mult0.IN0 +depth[0] => Mult0.IN16 +depth[1] => Mult0.IN15 +depth[2] => Mult0.IN14 +depth[3] => Mult0.IN13 +depth[4] => Mult0.IN12 +depth[5] => Mult0.IN11 +depth[6] => Mult0.IN10 +depth[7] => Mult0.IN9 +out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/spwm/db/spwm.hif b/spwm/db/spwm.hif new file mode 100644 index 0000000..123c2ab Binary files /dev/null and b/spwm/db/spwm.hif differ diff --git a/spwm/db/spwm.lpc.html b/spwm/db/spwm.lpc.html new file mode 100644 index 0000000..d7827c5 --- /dev/null +++ b/spwm/db/spwm.lpc.html @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
modulation27808188800000
spwm_sin|altsyncram_component|auto_generated11000900000000
spwm_sin11000900000000
diff --git a/spwm/db/spwm.lpc.rdb b/spwm/db/spwm.lpc.rdb new file mode 100644 index 0000000..480ce02 Binary files /dev/null and b/spwm/db/spwm.lpc.rdb differ diff --git a/spwm/db/spwm.lpc.txt b/spwm/db/spwm.lpc.txt new file mode 100644 index 0000000..a25a9b7 --- /dev/null +++ b/spwm/db/spwm.lpc.txt @@ -0,0 +1,9 @@ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; modulation ; 27 ; 8 ; 0 ; 8 ; 1 ; 8 ; 8 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; spwm_sin|altsyncram_component|auto_generated ; 11 ; 0 ; 0 ; 0 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; spwm_sin ; 11 ; 0 ; 0 ; 0 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/spwm/db/spwm.map.ammdb b/spwm/db/spwm.map.ammdb new file mode 100644 index 0000000..73f234e Binary files /dev/null and b/spwm/db/spwm.map.ammdb differ diff --git a/spwm/db/spwm.map.bpm b/spwm/db/spwm.map.bpm new file mode 100644 index 0000000..7e96d8f Binary files /dev/null and b/spwm/db/spwm.map.bpm differ diff --git a/spwm/db/spwm.map.cdb b/spwm/db/spwm.map.cdb new file mode 100644 index 0000000..8ff5dfe Binary files /dev/null and b/spwm/db/spwm.map.cdb differ diff --git a/spwm/db/spwm.map.hdb b/spwm/db/spwm.map.hdb new file mode 100644 index 0000000..29efac1 Binary files /dev/null and b/spwm/db/spwm.map.hdb differ diff --git a/spwm/db/spwm.map.kpt b/spwm/db/spwm.map.kpt new file mode 100644 index 0000000..878acc9 Binary files /dev/null and b/spwm/db/spwm.map.kpt differ diff --git a/spwm/db/spwm.map.logdb b/spwm/db/spwm.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/spwm/db/spwm.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/spwm/db/spwm.map.qmsg b/spwm/db/spwm.map.qmsg new file mode 100644 index 0000000..e8b76a6 --- /dev/null +++ b/spwm/db/spwm.map.qmsg @@ -0,0 +1,32 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544446499185 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544446499197 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 20:54:59 2018 " "Processing started: Mon Dec 10 20:54:59 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544446499197 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446499197 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spwm -c spwm " "Command: quartus_map --read_settings_files=on --write_settings_files=off spwm -c spwm" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446499198 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1544446499818 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1544446499818 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/spwm.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/spwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 spwm " "Found entity 1: spwm" { } { { "rtl/spwm.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/spwm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446512746 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446512746 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testbench/spwm_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file testbench/spwm_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 spwm_tb " "Found entity 1: spwm_tb" { } { { "testbench/spwm_tb.v" "" { Text "F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446512750 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446512750 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spwm_sin.v 1 1 " "Found 1 design units, including 1 entities, in source file spwm_sin.v" { { "Info" "ISGN_ENTITY_NAME" "1 spwm_sin " "Found entity 1: spwm_sin" { } { { "spwm_sin.v" "" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446512755 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446512755 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/modulation.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/modulation.v" { { "Info" "ISGN_ENTITY_NAME" "1 modulation " "Found entity 1: modulation" { } { { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446512758 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446512758 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "spwm " "Elaborating entity \"spwm\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1544446512939 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spwm_sin spwm_sin:spwm_sin " "Elaborating entity \"spwm_sin\" for hierarchy \"spwm_sin:spwm_sin\"" { } { { "rtl/spwm.v" "spwm_sin" { Text "F:/Code/FPGA/reserve/spwm/rtl/spwm.v" 70 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446512949 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram spwm_sin:spwm_sin\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\"" { } { { "spwm_sin.v" "altsyncram_component" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 81 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513024 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "spwm_sin:spwm_sin\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\"" { } { { "spwm_sin.v" "" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 81 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513030 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "spwm_sin:spwm_sin\|altsyncram:altsyncram_component " "Instantiated megafunction \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file sin9bit_1024.mif " "Parameter \"init_file\" = \"sin9bit_1024.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Parameter \"operation_mode\" = \"ROM\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Parameter \"outdata_reg_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 9 " "Parameter \"width_a\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513030 ""} } { { "spwm_sin.v" "" { Text "F:/Code/FPGA/reserve/spwm/spwm_sin.v" 81 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1544446513030 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sl91.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sl91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sl91 " "Found entity 1: altsyncram_sl91" { } { { "db/altsyncram_sl91.tdf" "" { Text "F:/Code/FPGA/reserve/spwm/db/altsyncram_sl91.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446513104 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446513104 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sl91 spwm_sin:spwm_sin\|altsyncram:altsyncram_component\|altsyncram_sl91:auto_generated " "Elaborating entity \"altsyncram_sl91\" for hierarchy \"spwm_sin:spwm_sin\|altsyncram:altsyncram_component\|altsyncram_sl91:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513104 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "modulation modulation:modulation " "Elaborating entity \"modulation\" for hierarchy \"modulation:modulation\"" { } { { "rtl/spwm.v" "modulation" { Text "F:/Code/FPGA/reserve/spwm/rtl/spwm.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513112 ""} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "modulation:modulation\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"modulation:modulation\|Mult0\"" { } { { "rtl/modulation.v" "Mult0" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1544446513379 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1544446513379 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513453 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "modulation:modulation\|lpm_mult:Mult0 " "Instantiated megafunction \"modulation:modulation\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 9 " "Parameter \"LPM_WIDTHA\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 8 " "Parameter \"LPM_WIDTHB\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 17 " "Parameter \"LPM_WIDTHP\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 17 " "Parameter \"LPM_WIDTHR\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT YES " "Parameter \"INPUT_B_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1544446513453 ""} } { { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1544446513453 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 308 5 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513524 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "multcore.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513569 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513632 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_lgh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_lgh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_lgh " "Found entity 1: add_sub_lgh" { } { { "db/add_sub_lgh.tdf" "" { Text "F:/Code/FPGA/reserve/spwm/db/add_sub_lgh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446513702 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446513702 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513708 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513721 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_pgh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_pgh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_pgh " "Found entity 1: add_sub_pgh" { } { { "db/add_sub_pgh.tdf" "" { Text "F:/Code/FPGA/reserve/spwm/db/add_sub_pgh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1544446513789 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446513789 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "modulation:modulation\|lpm_mult:Mult0\|altshift:external_latency_ffs modulation:modulation\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"modulation:modulation\|lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf" 351 4 0 } } { "rtl/modulation.v" "" { Text "F:/Code/FPGA/reserve/spwm/rtl/modulation.v" 22 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446513836 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1544446514266 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1544446514868 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1544446514868 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "148 " "Implemented 148 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "28 " "Implemented 28 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1544446514936 ""} { "Info" "ICUT_CUT_TM_OPINS" "19 " "Implemented 19 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1544446514936 ""} { "Info" "ICUT_CUT_TM_LCELLS" "92 " "Implemented 92 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1544446514936 ""} { "Info" "ICUT_CUT_TM_RAMS" "9 " "Implemented 9 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1544446514936 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1544446514936 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4804 " "Peak virtual memory: 4804 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544446514956 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 20:55:14 2018 " "Processing ended: Mon Dec 10 20:55:14 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544446514956 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:15 " "Elapsed time: 00:00:15" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544446514956 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544446514956 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1544446514956 ""} diff --git a/spwm/db/spwm.map.rdb b/spwm/db/spwm.map.rdb new file mode 100644 index 0000000..303f185 Binary files /dev/null and b/spwm/db/spwm.map.rdb differ diff --git a/spwm/db/spwm.map_bb.cdb b/spwm/db/spwm.map_bb.cdb new file mode 100644 index 0000000..0b76ad2 Binary files /dev/null and b/spwm/db/spwm.map_bb.cdb differ diff --git a/spwm/db/spwm.map_bb.hdb b/spwm/db/spwm.map_bb.hdb new file mode 100644 index 0000000..707f007 Binary files /dev/null and b/spwm/db/spwm.map_bb.hdb differ diff --git a/spwm/db/spwm.map_bb.logdb b/spwm/db/spwm.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/spwm/db/spwm.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/spwm/db/spwm.npp.qmsg b/spwm/db/spwm.npp.qmsg new file mode 100644 index 0000000..24e9cf0 --- /dev/null +++ b/spwm/db/spwm.npp.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544442759908 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544442759924 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 19:52:39 2018 " "Processing started: Mon Dec 10 19:52:39 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544442759924 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1544442759924 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp spwm -c spwm --netlist_type=sgate " "Command: quartus_npp spwm -c spwm --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1544442759924 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1544442760316 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4567 " "Peak virtual memory: 4567 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544442760337 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 19:52:40 2018 " "Processing ended: Mon Dec 10 19:52:40 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544442760337 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544442760337 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544442760337 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1544442760337 ""} diff --git a/spwm/db/spwm.pre_map.cdb b/spwm/db/spwm.pre_map.cdb new file mode 100644 index 0000000..83b6a70 Binary files /dev/null and b/spwm/db/spwm.pre_map.cdb differ diff --git a/spwm/db/spwm.pre_map.hdb b/spwm/db/spwm.pre_map.hdb new file mode 100644 index 0000000..6d200a7 Binary files /dev/null and b/spwm/db/spwm.pre_map.hdb differ diff --git a/spwm/db/spwm.root_partition.map.reg_db.cdb b/spwm/db/spwm.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..9d85189 Binary files /dev/null and b/spwm/db/spwm.root_partition.map.reg_db.cdb differ diff --git a/spwm/db/spwm.routing.rdb b/spwm/db/spwm.routing.rdb new file mode 100644 index 0000000..96e2fb3 Binary files /dev/null and b/spwm/db/spwm.routing.rdb differ diff --git a/spwm/db/spwm.rtlv.hdb b/spwm/db/spwm.rtlv.hdb new file mode 100644 index 0000000..40f10bf Binary files /dev/null and b/spwm/db/spwm.rtlv.hdb differ diff --git a/spwm/db/spwm.rtlv_sg.cdb b/spwm/db/spwm.rtlv_sg.cdb new file mode 100644 index 0000000..b716821 Binary files /dev/null and b/spwm/db/spwm.rtlv_sg.cdb differ diff --git a/spwm/db/spwm.rtlv_sg_swap.cdb b/spwm/db/spwm.rtlv_sg_swap.cdb new file mode 100644 index 0000000..46cf11f Binary files /dev/null and b/spwm/db/spwm.rtlv_sg_swap.cdb differ diff --git a/spwm/db/spwm.sgate.nvd b/spwm/db/spwm.sgate.nvd new file mode 100644 index 0000000..016eaab Binary files /dev/null and b/spwm/db/spwm.sgate.nvd differ diff --git a/spwm/db/spwm.sgate_sm.nvd b/spwm/db/spwm.sgate_sm.nvd new file mode 100644 index 0000000..9d46c8b Binary files /dev/null and b/spwm/db/spwm.sgate_sm.nvd differ diff --git a/spwm/db/spwm.sld_design_entry.sci b/spwm/db/spwm.sld_design_entry.sci new file mode 100644 index 0000000..0cf4f27 Binary files /dev/null and b/spwm/db/spwm.sld_design_entry.sci differ diff --git a/spwm/db/spwm.sld_design_entry_dsc.sci b/spwm/db/spwm.sld_design_entry_dsc.sci new file mode 100644 index 0000000..0cf4f27 Binary files /dev/null and b/spwm/db/spwm.sld_design_entry_dsc.sci differ diff --git a/spwm/db/spwm.smart_action.txt b/spwm/db/spwm.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/spwm/db/spwm.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/spwm/db/spwm.sta.qmsg b/spwm/db/spwm.sta.qmsg new file mode 100644 index 0000000..07c249b --- /dev/null +++ b/spwm/db/spwm.sta.qmsg @@ -0,0 +1,42 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1544446527458 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1544446527472 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 10 20:55:26 2018 " "Processing started: Mon Dec 10 20:55:26 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1544446527472 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1544446527472 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spwm -c spwm " "Command: quartus_sta spwm -c spwm" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1544446527472 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1544446527710 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1544446527970 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1544446527970 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446528047 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446528048 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "spwm.sdc " "Synopsys Design Constraints File file not found: 'spwm.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1544446528252 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446528252 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk_200m clk_200m " "create_clock -period 1.000 -name clk_200m clk_200m" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1544446528253 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544446528253 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1544446528254 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544446528254 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1544446528255 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1544446528264 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1544446528283 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1544446528283 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.406 " "Worst-case setup slack is -6.406" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528286 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528286 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.406 -106.964 clk_200m " " -6.406 -106.964 clk_200m " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528286 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446528286 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.452 " "Worst-case hold slack is 0.452" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528289 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528289 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 clk_200m " " 0.452 0.000 clk_200m " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528289 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446528289 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544446528294 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544446528298 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.201 " "Worst-case minimum pulse width slack is -3.201" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528300 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528300 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.201 -90.029 clk_200m " " -3.201 -90.029 clk_200m " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528300 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446528300 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1544446528340 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1544446528365 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1544446528724 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544446528807 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1544446528816 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1544446528816 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -5.774 " "Worst-case setup slack is -5.774" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528819 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528819 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.774 -92.754 clk_200m " " -5.774 -92.754 clk_200m " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528819 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446528819 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.400 " "Worst-case hold slack is 0.400" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528824 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.400 0.000 clk_200m " " 0.400 0.000 clk_200m " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528824 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446528824 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544446528830 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544446528834 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.201 " "Worst-case minimum pulse width slack is -3.201" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528838 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528838 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.201 -90.029 clk_200m " " -3.201 -90.029 clk_200m " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446528838 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446528838 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1544446528869 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1544446529002 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1544446529003 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1544446529003 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.286 " "Worst-case setup slack is -2.286" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446529006 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446529006 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.286 -19.805 clk_200m " " -2.286 -19.805 clk_200m " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446529006 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446529006 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.186 " "Worst-case hold slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446529011 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446529011 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 clk_200m " " 0.186 0.000 clk_200m " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446529011 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446529011 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544446529015 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1544446529019 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446529022 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446529022 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -53.627 clk_200m " " -3.000 -53.627 clk_200m " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1544446529022 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1544446529022 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1544446529476 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1544446529477 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4777 " "Peak virtual memory: 4777 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1544446529532 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 10 20:55:29 2018 " "Processing ended: Mon Dec 10 20:55:29 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1544446529532 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1544446529532 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1544446529532 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1544446529532 ""} diff --git a/spwm/db/spwm.sta.rdb b/spwm/db/spwm.sta.rdb new file mode 100644 index 0000000..cbd2557 Binary files /dev/null and b/spwm/db/spwm.sta.rdb differ diff --git a/spwm/db/spwm.sta_cmp.8_slow_1200mv_85c.tdb b/spwm/db/spwm.sta_cmp.8_slow_1200mv_85c.tdb new file mode 100644 index 0000000..a4b7571 Binary files /dev/null and b/spwm/db/spwm.sta_cmp.8_slow_1200mv_85c.tdb differ diff --git a/spwm/db/spwm.taw.rdb b/spwm/db/spwm.taw.rdb new file mode 100644 index 0000000..e9cca85 Binary files /dev/null and b/spwm/db/spwm.taw.rdb differ diff --git a/spwm/db/spwm.tis_db_list.ddb b/spwm/db/spwm.tis_db_list.ddb new file mode 100644 index 0000000..7dc5f0b Binary files /dev/null and b/spwm/db/spwm.tis_db_list.ddb differ diff --git a/spwm/db/spwm.tiscmp.fast_1200mv_0c.ddb b/spwm/db/spwm.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..8c9b381 Binary files /dev/null and b/spwm/db/spwm.tiscmp.fast_1200mv_0c.ddb differ diff --git a/spwm/db/spwm.tiscmp.fastest_slow_1200mv_0c.ddb b/spwm/db/spwm.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..9a3946b Binary files /dev/null and b/spwm/db/spwm.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/spwm/db/spwm.tiscmp.fastest_slow_1200mv_85c.ddb b/spwm/db/spwm.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..e8e7bcf Binary files /dev/null and b/spwm/db/spwm.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/spwm/db/spwm.tiscmp.slow_1200mv_0c.ddb b/spwm/db/spwm.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..4355f65 Binary files /dev/null and b/spwm/db/spwm.tiscmp.slow_1200mv_0c.ddb differ diff --git a/spwm/db/spwm.tiscmp.slow_1200mv_85c.ddb b/spwm/db/spwm.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..2af46c8 Binary files /dev/null and b/spwm/db/spwm.tiscmp.slow_1200mv_85c.ddb differ diff --git a/spwm/db/spwm.vpr.ammdb b/spwm/db/spwm.vpr.ammdb new file mode 100644 index 0000000..2d14536 Binary files /dev/null and b/spwm/db/spwm.vpr.ammdb differ diff --git a/spwm/db/spwm_partition_pins.json b/spwm/db/spwm_partition_pins.json new file mode 100644 index 0000000..f0a5856 --- /dev/null +++ b/spwm/db/spwm_partition_pins.json @@ -0,0 +1,197 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "tri_out[0]", + "strict" : false + }, + { + "name" : "tri_out[1]", + "strict" : false + }, + { + "name" : "tri_out[2]", + "strict" : false + }, + { + "name" : "tri_out[3]", + "strict" : false + }, + { + "name" : "tri_out[4]", + "strict" : false + }, + { + "name" : "tri_out[5]", + "strict" : false + }, + { + "name" : "tri_out[6]", + "strict" : false + }, + { + "name" : "tri_out[7]", + "strict" : false + }, + { + "name" : "tri_out[8]", + "strict" : false + }, + { + "name" : "sin_out[0]", + "strict" : false + }, + { + "name" : "sin_out[1]", + "strict" : false + }, + { + "name" : "sin_out[2]", + "strict" : false + }, + { + "name" : "sin_out[3]", + "strict" : false + }, + { + "name" : "sin_out[4]", + "strict" : false + }, + { + "name" : "sin_out[5]", + "strict" : false + }, + { + "name" : "sin_out[6]", + "strict" : false + }, + { + "name" : "sin_out[7]", + "strict" : false + }, + { + "name" : "sin_out[8]", + "strict" : false + }, + { + "name" : "spwm_out", + "strict" : false + }, + { + "name" : "clk_200m", + "strict" : false + }, + { + "name" : "rst_n", + "strict" : false + }, + { + "name" : "Pword[0]", + "strict" : false + }, + { + "name" : "Pword[1]", + "strict" : false + }, + { + "name" : "Pword[2]", + "strict" : false + }, + { + "name" : "Pword[3]", + "strict" : false + }, + { + "name" : "Pword[4]", + "strict" : false + }, + { + "name" : "Pword[5]", + "strict" : false + }, + { + "name" : "Pword[6]", + "strict" : false + }, + { + "name" : "Pword[7]", + "strict" : false + }, + { + "name" : "Pword[8]", + "strict" : false + }, + { + "name" : "Pword[9]", + "strict" : false + }, + { + "name" : "Fword[15]", + "strict" : false + }, + { + "name" : "Fword[14]", + "strict" : false + }, + { + "name" : "Fword[13]", + "strict" : false + }, + { + "name" : "Fword[12]", + "strict" : false + }, + { + "name" : "Fword[11]", + "strict" : false + }, + { + "name" : "Fword[10]", + "strict" : false + }, + { + "name" : "Fword[9]", + "strict" : false + }, + { + "name" : "Fword[8]", + "strict" : false + }, + { + "name" : "Fword[7]", + "strict" : false + }, + { + "name" : "Fword[6]", + "strict" : false + }, + { + "name" : "Fword[5]", + "strict" : false + }, + { + "name" : "Fword[4]", + "strict" : false + }, + { + "name" : "Fword[3]", + "strict" : false + }, + { + "name" : "Fword[2]", + "strict" : false + }, + { + "name" : "Fword[1]", + "strict" : false + }, + { + "name" : "Fword[0]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/spwm/greybox_tmp/cbx_args.txt b/spwm/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..210513b --- /dev/null +++ b/spwm/greybox_tmp/cbx_args.txt @@ -0,0 +1,16 @@ +ADDRESS_ACLR_A=NONE +CLOCK_ENABLE_INPUT_A=BYPASS +CLOCK_ENABLE_OUTPUT_A=BYPASS +INIT_FILE=sin9bit_1024.mif +INTENDED_DEVICE_FAMILY="Cyclone IV E" +NUMWORDS_A=1024 +OPERATION_MODE=ROM +OUTDATA_ACLR_A=NONE +OUTDATA_REG_A=CLOCK0 +WIDTHAD_A=10 +WIDTH_A=9 +WIDTH_BYTEENA_A=1 +DEVICE_FAMILY="Cyclone IV E" +address_a +clock0 +q_a diff --git a/spwm/incremental_db/README b/spwm/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/spwm/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/spwm/incremental_db/compiled_partitions/spwm.db_info b/spwm/incremental_db/compiled_partitions/spwm.db_info new file mode 100644 index 0000000..72a8a1b --- /dev/null +++ b/spwm/incremental_db/compiled_partitions/spwm.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Version_Index = 486699264 +Creation_Time = Sat Dec 08 19:09:57 2018 diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.ammdb b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.ammdb new file mode 100644 index 0000000..2818998 Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.ammdb differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.cdb b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.cdb new file mode 100644 index 0000000..b83ab9d Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.cdb differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.dfp b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.dfp differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.hdb b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.hdb new file mode 100644 index 0000000..14e99b4 Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.hdb differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.logdb b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.rcfdb b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.rcfdb new file mode 100644 index 0000000..0a1c649 Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.cmp.rcfdb differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.cdb b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.cdb new file mode 100644 index 0000000..4118bef Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.cdb differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.dpi b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.dpi new file mode 100644 index 0000000..a6a9aea Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.dpi differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.cdb b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..eec9f78 Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.cdb differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.hb_info b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.hb_info differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.hdb b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..e491cc4 Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.hdb differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.sig b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.sig new file mode 100644 index 0000000..6c0af65 --- /dev/null +++ b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +c5eb7f6cdd530884c3b884e0a3668ea4 \ No newline at end of file diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hdb b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hdb new file mode 100644 index 0000000..f505dcd Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.hdb differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.kpt b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.kpt new file mode 100644 index 0000000..8b1165b Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.root_partition.map.kpt differ diff --git a/spwm/incremental_db/compiled_partitions/spwm.rrp.hdb b/spwm/incremental_db/compiled_partitions/spwm.rrp.hdb new file mode 100644 index 0000000..86d862e Binary files /dev/null and b/spwm/incremental_db/compiled_partitions/spwm.rrp.hdb differ diff --git a/spwm/ip/spwm_pll.ppf b/spwm/ip/spwm_pll.ppf new file mode 100644 index 0000000..a490a83 --- /dev/null +++ b/spwm/ip/spwm_pll.ppf @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/spwm/ip/spwm_pll.qip b/spwm/ip/spwm_pll.qip new file mode 100644 index 0000000..8dadfcd --- /dev/null +++ b/spwm/ip/spwm_pll.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "spwm_pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "spwm_pll_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "spwm_pll.ppf"] diff --git a/spwm/ip/spwm_pll.v b/spwm/ip/spwm_pll.v new file mode 100644 index 0000000..5f35a01 --- /dev/null +++ b/spwm/ip/spwm_pll.v @@ -0,0 +1,301 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: spwm_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Standard Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module spwm_pll ( + inclk0, + c0); + + input inclk0; + output c0; + + wire [0:0] sub_wire2 = 1'h0; + wire [4:0] sub_wire3; + wire sub_wire0 = inclk0; + wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; + wire [0:0] sub_wire4 = sub_wire3[0:0]; + wire c0 = sub_wire4; + + altpll altpll_component ( + .inclk (sub_wire1), + .clk (sub_wire3), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 5, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=spwm_pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "spwm_pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/spwm/ip/spwm_pll_bb.v b/spwm/ip/spwm_pll_bb.v new file mode 100644 index 0000000..83a2e44 --- /dev/null +++ b/spwm/ip/spwm_pll_bb.v @@ -0,0 +1,194 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: spwm_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Standard Edition +// ************************************************************ + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module spwm_pll ( + inclk0, + c0); + + input inclk0; + output c0; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "80.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "80.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "spwm_pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_pll_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/spwm/ip/tri_counter.qip b/spwm/ip/tri_counter.qip new file mode 100644 index 0000000..037686c --- /dev/null +++ b/spwm/ip/tri_counter.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "tri_counter.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "tri_counter_bb.v"] diff --git a/spwm/ip/tri_counter.v b/spwm/ip/tri_counter.v new file mode 100644 index 0000000..df263d9 --- /dev/null +++ b/spwm/ip/tri_counter.v @@ -0,0 +1,115 @@ +// megafunction wizard: %LPM_COUNTER% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: LPM_COUNTER + +// ============================================================ +// File Name: tri_counter.v +// Megafunction Name(s): +// LPM_COUNTER +// +// Simulation Library Files(s): +// lpm +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Standard Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module tri_counter ( + clock, + updown, + q); + + input clock; + input updown; + output [8:0] q; + + wire [8:0] sub_wire0; + wire [8:0] q = sub_wire0[8:0]; + + lpm_counter LPM_COUNTER_component ( + .clock (clock), + .updown (updown), + .q (sub_wire0), + .aclr (1'b0), + .aload (1'b0), + .aset (1'b0), + .cin (1'b1), + .clk_en (1'b1), + .cnt_en (1'b1), + .cout (), + .data ({9{1'b0}}), + .eq (), + .sclr (1'b0), + .sload (1'b0), + .sset (1'b0)); + defparam + LPM_COUNTER_component.lpm_direction = "UNUSED", + LPM_COUNTER_component.lpm_port_updown = "PORT_USED", + LPM_COUNTER_component.lpm_type = "LPM_COUNTER", + LPM_COUNTER_component.lpm_width = 9; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACLR NUMERIC "0" +// Retrieval info: PRIVATE: ALOAD NUMERIC "0" +// Retrieval info: PRIVATE: ASET NUMERIC "0" +// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +// Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +// Retrieval info: PRIVATE: CNT_EN NUMERIC "0" +// Retrieval info: PRIVATE: CarryIn NUMERIC "0" +// Retrieval info: PRIVATE: CarryOut NUMERIC "0" +// Retrieval info: PRIVATE: Direction NUMERIC "2" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0" +// Retrieval info: PRIVATE: ModulusValue NUMERIC "0" +// Retrieval info: PRIVATE: SCLR NUMERIC "0" +// Retrieval info: PRIVATE: SLOAD NUMERIC "0" +// Retrieval info: PRIVATE: SSET NUMERIC "0" +// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: nBit NUMERIC "9" +// Retrieval info: PRIVATE: new_diagram STRING "1" +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all +// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_USED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]" +// Retrieval info: USED_PORT: updown 0 0 0 0 INPUT NODEFVAL "updown" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @updown 0 0 0 0 updown 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 9 0 @q 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter_bb.v TRUE +// Retrieval info: LIB_FILE: lpm diff --git a/spwm/ip/tri_counter_bb.v b/spwm/ip/tri_counter_bb.v new file mode 100644 index 0000000..960923a --- /dev/null +++ b/spwm/ip/tri_counter_bb.v @@ -0,0 +1,84 @@ +// megafunction wizard: %LPM_COUNTER%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: LPM_COUNTER + +// ============================================================ +// File Name: tri_counter.v +// Megafunction Name(s): +// LPM_COUNTER +// +// Simulation Library Files(s): +// lpm +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Standard Edition +// ************************************************************ + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module tri_counter ( + clock, + updown, + q); + + input clock; + input updown; + output [8:0] q; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACLR NUMERIC "0" +// Retrieval info: PRIVATE: ALOAD NUMERIC "0" +// Retrieval info: PRIVATE: ASET NUMERIC "0" +// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +// Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +// Retrieval info: PRIVATE: CNT_EN NUMERIC "0" +// Retrieval info: PRIVATE: CarryIn NUMERIC "0" +// Retrieval info: PRIVATE: CarryOut NUMERIC "0" +// Retrieval info: PRIVATE: Direction NUMERIC "2" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0" +// Retrieval info: PRIVATE: ModulusValue NUMERIC "0" +// Retrieval info: PRIVATE: SCLR NUMERIC "0" +// Retrieval info: PRIVATE: SLOAD NUMERIC "0" +// Retrieval info: PRIVATE: SSET NUMERIC "0" +// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: nBit NUMERIC "9" +// Retrieval info: PRIVATE: new_diagram STRING "1" +// Retrieval info: LIBRARY: lpm lpm.lpm_components.all +// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_USED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]" +// Retrieval info: USED_PORT: updown 0 0 0 0 INPUT NODEFVAL "updown" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @updown 0 0 0 0 updown 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 9 0 @q 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL tri_counter_bb.v TRUE +// Retrieval info: LIB_FILE: lpm diff --git a/spwm/output_files/spwm.asm.rpt b/spwm/output_files/spwm.asm.rpt new file mode 100644 index 0000000..9ab8a72 --- /dev/null +++ b/spwm/output_files/spwm.asm.rpt @@ -0,0 +1,91 @@ +Assembler report for spwm +Mon Dec 10 20:55:25 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: F:/Code/FPGA/reserve/spwm/output_files/spwm.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon Dec 10 20:55:25 2018 ; +; Revision Name ; spwm ; +; Top-level Entity Name ; spwm ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-------------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------------+ +; File Name ; ++-------------------------------------------------+ +; F:/Code/FPGA/reserve/spwm/output_files/spwm.sof ; ++-------------------------------------------------+ + + ++---------------------------------------------------------------------------+ +; Assembler Device Options: F:/Code/FPGA/reserve/spwm/output_files/spwm.sof ; ++----------------+----------------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------------+ +; JTAG usercode ; 0x000BA916 ; +; Checksum ; 0x000BA916 ; ++----------------+----------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Mon Dec 10 20:55:24 2018 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spwm -c spwm +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4695 megabytes + Info: Processing ended: Mon Dec 10 20:55:25 2018 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/spwm/output_files/spwm.done b/spwm/output_files/spwm.done new file mode 100644 index 0000000..6f4f7ca --- /dev/null +++ b/spwm/output_files/spwm.done @@ -0,0 +1 @@ +Mon Dec 10 20:55:32 2018 diff --git a/spwm/output_files/spwm.eda.rpt b/spwm/output_files/spwm.eda.rpt new file mode 100644 index 0000000..b0cf91f --- /dev/null +++ b/spwm/output_files/spwm.eda.rpt @@ -0,0 +1,108 @@ +EDA Netlist Writer report for spwm +Mon Dec 10 20:55:32 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Mon Dec 10 20:55:32 2018 ; +; Revision Name ; spwm ; +; Top-level Entity Name ; spwm ; +; Family ; Cyclone IV E ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------+ +; Simulation Generated Files ; ++-----------------------------------------------------------------------------+ +; Generated Files ; ++-----------------------------------------------------------------------------+ +; F:/Code/FPGA/reserve/spwm/simulation/modelsim/spwm_8_1200mv_85c_slow.vo ; +; F:/Code/FPGA/reserve/spwm/simulation/modelsim/spwm_8_1200mv_0c_slow.vo ; +; F:/Code/FPGA/reserve/spwm/simulation/modelsim/spwm_min_1200mv_0c_fast.vo ; +; F:/Code/FPGA/reserve/spwm/simulation/modelsim/spwm.vo ; +; F:/Code/FPGA/reserve/spwm/simulation/modelsim/spwm_8_1200mv_85c_v_slow.sdo ; +; F:/Code/FPGA/reserve/spwm/simulation/modelsim/spwm_8_1200mv_0c_v_slow.sdo ; +; F:/Code/FPGA/reserve/spwm/simulation/modelsim/spwm_min_1200mv_0c_v_fast.sdo ; +; F:/Code/FPGA/reserve/spwm/simulation/modelsim/spwm_v.sdo ; ++-----------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Mon Dec 10 20:55:30 2018 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spwm -c spwm +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file spwm_8_1200mv_85c_slow.vo in folder "F:/Code/FPGA/reserve/spwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spwm_8_1200mv_0c_slow.vo in folder "F:/Code/FPGA/reserve/spwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spwm_min_1200mv_0c_fast.vo in folder "F:/Code/FPGA/reserve/spwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spwm.vo in folder "F:/Code/FPGA/reserve/spwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spwm_8_1200mv_85c_v_slow.sdo in folder "F:/Code/FPGA/reserve/spwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spwm_8_1200mv_0c_v_slow.sdo in folder "F:/Code/FPGA/reserve/spwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spwm_min_1200mv_0c_v_fast.sdo in folder "F:/Code/FPGA/reserve/spwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file spwm_v.sdo in folder "F:/Code/FPGA/reserve/spwm/simulation/modelsim/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4663 megabytes + Info: Processing ended: Mon Dec 10 20:55:32 2018 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/spwm/output_files/spwm.fit.rpt b/spwm/output_files/spwm.fit.rpt new file mode 100644 index 0000000..7020634 --- /dev/null +++ b/spwm/output_files/spwm.fit.rpt @@ -0,0 +1,1478 @@ +Fitter report for spwm +Mon Dec 10 20:55:22 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Control Signals + 21. Global & Other Fast Signals + 22. Fitter RAM Summary + 23. |spwm|spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ALTSYNCRAM + 24. Routing Usage Summary + 25. LAB Logic Elements + 26. LAB-wide Signals + 27. LAB Signals Sourced + 28. LAB Signals Sourced Out + 29. LAB Distinct Inputs + 30. I/O Rules Summary + 31. I/O Rules Details + 32. I/O Rules Matrix + 33. Fitter Device Options + 34. Operating Settings and Conditions + 35. Fitter Messages + 36. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Mon Dec 10 20:55:22 2018 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; spwm ; +; Top-level Entity Name ; spwm ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Total logic elements ; 91 / 10,320 ( < 1 % ) ; +; Total combinational functions ; 91 / 10,320 ( < 1 % ) ; +; Dedicated logic registers ; 37 / 10,320 ( < 1 % ) ; +; Total registers ; 37 ; +; Total pins ; 47 / 180 ( 26 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 9,216 / 423,936 ( 2 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP4CE10F17C8 ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.02 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.5% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 244 ) ; 0.00 % ( 0 / 244 ) ; 0.00 % ( 0 / 244 ) ; +; -- Achieved ; 0.00 % ( 0 / 244 ) ; 0.00 % ( 0 / 244 ) ; 0.00 % ( 0 / 244 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 234 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in F:/Code/FPGA/reserve/spwm/output_files/spwm.pin. + + ++-----------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-------------------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------------------+ +; Total logic elements ; 91 / 10,320 ( < 1 % ) ; +; -- Combinational with no register ; 54 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 37 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 15 ; +; -- 3 input functions ; 53 ; +; -- <=2 input functions ; 23 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 25 ; +; -- arithmetic mode ; 66 ; +; ; ; +; Total registers* ; 37 / 11,172 ( < 1 % ) ; +; -- Dedicated logic registers ; 37 / 10,320 ( < 1 % ) ; +; -- I/O registers ; 0 / 852 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 8 / 645 ( 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 47 / 180 ( 26 % ) ; +; -- Clock pins ; 2 / 3 ( 67 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; M9Ks ; 1 / 46 ( 2 % ) ; +; Total block memory bits ; 9,216 / 423,936 ( 2 % ) ; +; Total block memory implementation bits ; 9,216 / 423,936 ( 2 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; PLLs ; 0 / 2 ( 0 % ) ; +; Global signals ; 2 ; +; -- Global clocks ; 2 / 10 ( 20 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.4% / 0.4% / 0.5% ; +; Peak interconnect usage (total/H/V) ; 1.1% / 1.4% / 1.0% ; +; Maximum fan-out ; 68 ; +; Highest non-global fan-out ; 9 ; +; Total fan-out ; 417 ; +; Average fan-out ; 1.77 ; ++---------------------------------------------+-------------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 91 / 10320 ( < 1 % ) ; 0 / 10320 ( 0 % ) ; +; -- Combinational with no register ; 54 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 37 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 15 ; 0 ; +; -- 3 input functions ; 53 ; 0 ; +; -- <=2 input functions ; 23 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 25 ; 0 ; +; -- arithmetic mode ; 66 ; 0 ; +; ; ; ; +; Total registers ; 37 ; 0 ; +; -- Dedicated logic registers ; 37 / 10320 ( < 1 % ) ; 0 / 10320 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 8 / 645 ( 1 % ) ; 0 / 645 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 47 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; 0 / 46 ( 0 % ) ; +; Total memory bits ; 9216 ; 0 ; +; Total RAM block bits ; 9216 ; 0 ; +; M9K ; 1 / 46 ( 2 % ) ; 0 / 46 ( 0 % ) ; +; Clock control block ; 2 / 12 ( 16 % ) ; 0 / 12 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 450 ; 5 ; +; -- Registered Connections ; 145 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 28 ; 0 ; +; -- Output Ports ; 19 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Fword[0] ; A4 ; 8 ; 5 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[10] ; B3 ; 8 ; 3 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[11] ; B5 ; 8 ; 5 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[12] ; A2 ; 8 ; 5 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[13] ; B1 ; 1 ; 0 ; 22 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[14] ; G2 ; 1 ; 0 ; 18 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[15] ; G5 ; 1 ; 0 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[1] ; D6 ; 8 ; 3 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[2] ; B7 ; 8 ; 11 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[3] ; D5 ; 8 ; 3 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[4] ; B6 ; 8 ; 9 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[5] ; A7 ; 8 ; 11 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[6] ; D3 ; 8 ; 1 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[7] ; B4 ; 8 ; 5 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[8] ; A3 ; 8 ; 3 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Fword[9] ; C6 ; 8 ; 9 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Pword[0] ; A6 ; 8 ; 9 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Pword[1] ; D1 ; 1 ; 0 ; 21 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Pword[2] ; E7 ; 8 ; 7 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Pword[3] ; F3 ; 1 ; 0 ; 21 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Pword[4] ; F1 ; 1 ; 0 ; 19 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Pword[5] ; A5 ; 8 ; 7 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Pword[6] ; G1 ; 1 ; 0 ; 18 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Pword[7] ; C2 ; 1 ; 0 ; 22 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Pword[8] ; F2 ; 1 ; 0 ; 19 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; Pword[9] ; E6 ; 8 ; 7 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; clk_200m ; E1 ; 1 ; 0 ; 11 ; 7 ; 38 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; rst_n ; M2 ; 2 ; 0 ; 11 ; 14 ; 36 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; sin_out[0] ; M8 ; 3 ; 13 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; sin_out[1] ; J6 ; 2 ; 0 ; 10 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; sin_out[2] ; L7 ; 3 ; 11 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; sin_out[3] ; R7 ; 3 ; 11 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; sin_out[4] ; F7 ; 8 ; 11 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; sin_out[5] ; J2 ; 2 ; 0 ; 10 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; sin_out[6] ; J1 ; 2 ; 0 ; 10 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; sin_out[7] ; P8 ; 3 ; 16 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; sin_out[8] ; R8 ; 3 ; 16 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; spwm_out ; L8 ; 3 ; 13 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tri_out[0] ; F8 ; 8 ; 13 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tri_out[1] ; A9 ; 7 ; 16 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tri_out[2] ; B8 ; 8 ; 16 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tri_out[3] ; E8 ; 8 ; 13 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tri_out[4] ; B9 ; 7 ; 16 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tri_out[5] ; A8 ; 8 ; 16 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tri_out[6] ; D8 ; 8 ; 13 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tri_out[7] ; F6 ; 8 ; 11 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tri_out[8] ; C8 ; 8 ; 13 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; ++------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; C1 ; DIFFIO_L1n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; D2 ; DIFFIO_L2p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; F4 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; H1 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; H2 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; H5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; J3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; H14 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; H13 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; H12 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; F16 ; DIFFIO_R3n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; +; E8 ; DIFFIO_T10n, DATA2 ; Use as regular IO ; tri_out[3] ; Dual Purpose Pin ; +; F8 ; DIFFIO_T10p, DATA3 ; Use as regular IO ; tri_out[0] ; Dual Purpose Pin ; +; B7 ; DIFFIO_T9p, DATA4 ; Use as regular IO ; Fword[2] ; Dual Purpose Pin ; +; E7 ; DATA5 ; Use as regular IO ; Pword[2] ; Dual Purpose Pin ; +; E6 ; DATA6 ; Use as regular IO ; Pword[9] ; Dual Purpose Pin ; +; A5 ; DIFFIO_T6n, DATA7 ; Use as regular IO ; Pword[5] ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 14 / 17 ( 82 % ) ; 2.5V ; -- ; +; 2 ; 4 / 19 ( 21 % ) ; 2.5V ; -- ; +; 3 ; 6 / 26 ( 23 % ) ; 2.5V ; -- ; +; 4 ; 0 / 27 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 25 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 1 / 14 ( 7 % ) ; 2.5V ; -- ; +; 7 ; 2 / 26 ( 8 % ) ; 2.5V ; -- ; +; 8 ; 25 / 26 ( 96 % ) ; 2.5V ; -- ; ++----------+------------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A2 ; 194 ; 8 ; Fword[12] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A3 ; 200 ; 8 ; Fword[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A4 ; 196 ; 8 ; Fword[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A5 ; 192 ; 8 ; Pword[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A6 ; 188 ; 8 ; Pword[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A7 ; 183 ; 8 ; Fword[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A8 ; 177 ; 8 ; tri_out[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A9 ; 175 ; 7 ; tri_out[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A10 ; 168 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 161 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A12 ; 159 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 153 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A14 ; 155 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 167 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B1 ; 3 ; 1 ; Fword[13] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 201 ; 8 ; Fword[10] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B4 ; 197 ; 8 ; Fword[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B5 ; 195 ; 8 ; Fword[11] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B6 ; 189 ; 8 ; Fword[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B7 ; 184 ; 8 ; Fword[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B8 ; 178 ; 8 ; tri_out[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B9 ; 176 ; 7 ; tri_out[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B10 ; 169 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 162 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 160 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; 154 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B14 ; 156 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B16 ; 141 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; C2 ; 4 ; 1 ; Pword[7] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; C3 ; 202 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 187 ; 8 ; Fword[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C7 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C8 ; 179 ; 8 ; tri_out[8] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C9 ; 172 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C10 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C11 ; 163 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C14 ; 149 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 147 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C16 ; 146 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 8 ; 1 ; Pword[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; D2 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; D3 ; 203 ; 8 ; Fword[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D4 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D5 ; 198 ; 8 ; Fword[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D6 ; 199 ; 8 ; Fword[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D8 ; 180 ; 8 ; tri_out[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D9 ; 173 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 151 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 152 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D13 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; D14 ; 150 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 144 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D16 ; 143 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 24 ; 1 ; clk_200m ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E5 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E6 ; 191 ; 8 ; Pword[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E7 ; 190 ; 8 ; Pword[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E8 ; 181 ; 8 ; tri_out[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E9 ; 174 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 158 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 157 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E12 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E15 ; 128 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; E16 ; 127 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; F1 ; 12 ; 1 ; Pword[4] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F2 ; 11 ; 1 ; Pword[8] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F3 ; 6 ; 1 ; Pword[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; F4 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; F5 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; 185 ; 8 ; tri_out[7] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F7 ; 186 ; 8 ; sin_out[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F8 ; 182 ; 8 ; tri_out[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F9 ; 165 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F10 ; 164 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F11 ; 166 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; F12 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; 138 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F14 ; 142 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; F15 ; 140 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F16 ; 139 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G1 ; 14 ; 1 ; Pword[6] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G2 ; 13 ; 1 ; Fword[14] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 10 ; 1 ; Fword[15] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G11 ; 145 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G12 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G12 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; 137 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G16 ; 136 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H2 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H3 ; 19 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; H4 ; 18 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; H5 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H12 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; H13 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; H14 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J1 ; 28 ; 2 ; sin_out[6] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J2 ; 27 ; 2 ; sin_out[5] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J3 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 21 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; J5 ; 20 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; J6 ; 29 ; 2 ; sin_out[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J11 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J12 ; 123 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J13 ; 124 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J14 ; 122 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 121 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; 120 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 33 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 32 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K5 ; 39 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 30 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K8 ; 60 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; 76 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K10 ; 87 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K11 ; 110 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K12 ; 105 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K15 ; 119 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; 118 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 35 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 34 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; 36 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; L4 ; 40 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L5 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L6 ; 31 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L7 ; 65 ; 3 ; sin_out[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; L8 ; 68 ; 3 ; spwm_out ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; L9 ; 77 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L10 ; 88 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L11 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L12 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L13 ; 114 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L14 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; L15 ; 116 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; 115 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 26 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M2 ; 25 ; 2 ; rst_n ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; 57 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M7 ; 59 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M8 ; 69 ; 3 ; sin_out[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; M9 ; 78 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M10 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M11 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M12 ; 103 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M15 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M16 ; 125 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 38 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 37 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 45 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N4 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N5 ; 55 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N6 ; 56 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N9 ; 79 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N12 ; 101 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N13 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N14 ; 106 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 112 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; 111 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P1 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P4 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; P7 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 71 ; 3 ; sin_out[7] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; P9 ; 89 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P11 ; 90 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P14 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P15 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 108 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; 47 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R4 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R5 ; 61 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R6 ; 63 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R7 ; 66 ; 3 ; sin_out[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R8 ; 72 ; 3 ; sin_out[8] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R9 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 80 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 85 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 91 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; 109 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; T1 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T2 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T3 ; 48 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T4 ; 54 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T5 ; 62 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T6 ; 64 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T7 ; 67 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T8 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 75 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T10 ; 81 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T11 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 86 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T13 ; 92 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T14 ; 95 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T15 ; 96 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++--------------------------------------------+ +; I/O Assignment Warnings ; ++------------+-------------------------------+ +; Pin Name ; Reason ; ++------------+-------------------------------+ +; tri_out[0] ; Incomplete set of assignments ; +; tri_out[1] ; Incomplete set of assignments ; +; tri_out[2] ; Incomplete set of assignments ; +; tri_out[3] ; Incomplete set of assignments ; +; tri_out[4] ; Incomplete set of assignments ; +; tri_out[5] ; Incomplete set of assignments ; +; tri_out[6] ; Incomplete set of assignments ; +; tri_out[7] ; Incomplete set of assignments ; +; tri_out[8] ; Incomplete set of assignments ; +; sin_out[0] ; Incomplete set of assignments ; +; sin_out[1] ; Incomplete set of assignments ; +; sin_out[2] ; Incomplete set of assignments ; +; sin_out[3] ; Incomplete set of assignments ; +; sin_out[4] ; Incomplete set of assignments ; +; sin_out[5] ; Incomplete set of assignments ; +; sin_out[6] ; Incomplete set of assignments ; +; sin_out[7] ; Incomplete set of assignments ; +; sin_out[8] ; Incomplete set of assignments ; +; spwm_out ; Incomplete set of assignments ; +; clk_200m ; Incomplete set of assignments ; +; rst_n ; Incomplete set of assignments ; +; Pword[0] ; Incomplete set of assignments ; +; Pword[1] ; Incomplete set of assignments ; +; Pword[2] ; Incomplete set of assignments ; +; Pword[3] ; Incomplete set of assignments ; +; Pword[4] ; Incomplete set of assignments ; +; Pword[5] ; Incomplete set of assignments ; +; Pword[6] ; Incomplete set of assignments ; +; Pword[7] ; Incomplete set of assignments ; +; Pword[8] ; Incomplete set of assignments ; +; Pword[9] ; Incomplete set of assignments ; +; Fword[15] ; Incomplete set of assignments ; +; Fword[14] ; Incomplete set of assignments ; +; Fword[13] ; Incomplete set of assignments ; +; Fword[12] ; Incomplete set of assignments ; +; Fword[11] ; Incomplete set of assignments ; +; Fword[10] ; Incomplete set of assignments ; +; Fword[9] ; Incomplete set of assignments ; +; Fword[8] ; Incomplete set of assignments ; +; Fword[7] ; Incomplete set of assignments ; +; Fword[6] ; Incomplete set of assignments ; +; Fword[5] ; Incomplete set of assignments ; +; Fword[4] ; Incomplete set of assignments ; +; Fword[3] ; Incomplete set of assignments ; +; Fword[2] ; Incomplete set of assignments ; +; Fword[1] ; Incomplete set of assignments ; +; Fword[0] ; Incomplete set of assignments ; +; tri_out[0] ; Missing location assignment ; +; tri_out[1] ; Missing location assignment ; +; tri_out[2] ; Missing location assignment ; +; tri_out[3] ; Missing location assignment ; +; tri_out[4] ; Missing location assignment ; +; tri_out[5] ; Missing location assignment ; +; tri_out[6] ; Missing location assignment ; +; tri_out[7] ; Missing location assignment ; +; tri_out[8] ; Missing location assignment ; +; sin_out[0] ; Missing location assignment ; +; sin_out[1] ; Missing location assignment ; +; sin_out[2] ; Missing location assignment ; +; sin_out[3] ; Missing location assignment ; +; sin_out[4] ; Missing location assignment ; +; sin_out[5] ; Missing location assignment ; +; sin_out[6] ; Missing location assignment ; +; sin_out[7] ; Missing location assignment ; +; sin_out[8] ; Missing location assignment ; +; spwm_out ; Missing location assignment ; +; clk_200m ; Missing location assignment ; +; rst_n ; Missing location assignment ; +; Pword[0] ; Missing location assignment ; +; Pword[1] ; Missing location assignment ; +; Pword[2] ; Missing location assignment ; +; Pword[3] ; Missing location assignment ; +; Pword[4] ; Missing location assignment ; +; Pword[5] ; Missing location assignment ; +; Pword[6] ; Missing location assignment ; +; Pword[7] ; Missing location assignment ; +; Pword[8] ; Missing location assignment ; +; Pword[9] ; Missing location assignment ; +; Fword[15] ; Missing location assignment ; +; Fword[14] ; Missing location assignment ; +; Fword[13] ; Missing location assignment ; +; Fword[12] ; Missing location assignment ; +; Fword[11] ; Missing location assignment ; +; Fword[10] ; Missing location assignment ; +; Fword[9] ; Missing location assignment ; +; Fword[8] ; Missing location assignment ; +; Fword[7] ; Missing location assignment ; +; Fword[6] ; Missing location assignment ; +; Fword[5] ; Missing location assignment ; +; Fword[4] ; Missing location assignment ; +; Fword[3] ; Missing location assignment ; +; Fword[2] ; Missing location assignment ; +; Fword[1] ; Missing location assignment ; +; Fword[0] ; Missing location assignment ; ++------------+-------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++---------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++---------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; |spwm ; 91 (49) ; 37 (36) ; 0 (0) ; 9216 ; 1 ; 0 ; 0 ; 0 ; 47 ; 0 ; 54 (13) ; 0 (0) ; 37 (36) ; |spwm ; spwm ; work ; +; |modulation:modulation| ; 42 (12) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 41 (11) ; 0 (0) ; 1 (1) ; |spwm|modulation:modulation ; modulation ; work ; +; |lpm_mult:Mult0| ; 30 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (0) ; 0 (0) ; 0 (0) ; |spwm|modulation:modulation|lpm_mult:Mult0 ; lpm_mult ; work ; +; |multcore:mult_core| ; 30 (13) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (13) ; 0 (0) ; 0 (0) ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core ; multcore ; work ; +; |mpar_add:padder| ; 17 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 (0) ; 0 (0) ; 0 (0) ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder ; mpar_add ; work ; +; |lpm_add_sub:adder[0]| ; 10 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 0 (0) ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; lpm_add_sub ; work ; +; |add_sub_lgh:auto_generated| ; 10 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 0 (0) ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_lgh:auto_generated ; add_sub_lgh ; work ; +; |mpar_add:sub_par_add| ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; mpar_add ; work ; +; |lpm_add_sub:adder[0]| ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 0 (0) ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; lpm_add_sub ; work ; +; |add_sub_pgh:auto_generated| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_pgh:auto_generated ; add_sub_pgh ; work ; +; |spwm_sin:spwm_sin| ; 0 (0) ; 0 (0) ; 0 (0) ; 9216 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |spwm|spwm_sin:spwm_sin ; spwm_sin ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 9216 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |spwm|spwm_sin:spwm_sin|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_sl91:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 9216 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |spwm|spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated ; altsyncram_sl91 ; work ; ++---------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------------+----------+---------------+---------------+-----------------------+-----+------+ +; tri_out[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tri_out[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tri_out[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tri_out[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tri_out[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tri_out[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tri_out[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tri_out[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tri_out[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; sin_out[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; sin_out[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; sin_out[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; sin_out[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; sin_out[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; sin_out[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; sin_out[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; sin_out[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; sin_out[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; spwm_out ; Output ; -- ; -- ; -- ; -- ; -- ; +; clk_200m ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; rst_n ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; Pword[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Pword[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Pword[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Pword[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Pword[4] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Pword[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Pword[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Pword[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Pword[8] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Pword[9] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[15] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Fword[14] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[13] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[12] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[11] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[10] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Fword[9] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[8] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[4] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Fword[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; Fword[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; Fword[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; ++------------+----------+---------------+---------------+-----------------------+-----+------+ + + ++--------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++--------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++--------------------------+-------------------+---------+ +; clk_200m ; ; ; +; rst_n ; ; ; +; Pword[0] ; ; ; +; - rom_address[0]~0 ; 0 ; 6 ; +; Pword[1] ; ; ; +; - rom_address[1]~2 ; 0 ; 6 ; +; Pword[2] ; ; ; +; - rom_address[2]~4 ; 0 ; 6 ; +; Pword[3] ; ; ; +; - rom_address[3]~6 ; 0 ; 6 ; +; Pword[4] ; ; ; +; - rom_address[4]~8 ; 1 ; 6 ; +; Pword[5] ; ; ; +; - rom_address[5]~10 ; 0 ; 6 ; +; Pword[6] ; ; ; +; - rom_address[6]~12 ; 0 ; 6 ; +; Pword[7] ; ; ; +; - rom_address[7]~14 ; 0 ; 6 ; +; Pword[8] ; ; ; +; - rom_address[8]~16 ; 1 ; 6 ; +; Pword[9] ; ; ; +; - rom_address[9]~18 ; 0 ; 6 ; +; Fword[15] ; ; ; +; - F_acc[15]~56 ; 1 ; 6 ; +; Fword[14] ; ; ; +; - F_acc[14]~54 ; 0 ; 6 ; +; Fword[13] ; ; ; +; - F_acc[13]~52 ; 0 ; 6 ; +; Fword[12] ; ; ; +; - F_acc[12]~50 ; 0 ; 6 ; +; Fword[11] ; ; ; +; - F_acc[11]~48 ; 0 ; 6 ; +; Fword[10] ; ; ; +; - F_acc[10]~46 ; 1 ; 6 ; +; Fword[9] ; ; ; +; - F_acc[9]~44 ; 0 ; 6 ; +; Fword[8] ; ; ; +; - F_acc[8]~42 ; 0 ; 6 ; +; Fword[7] ; ; ; +; - F_acc[7]~40 ; 0 ; 6 ; +; Fword[6] ; ; ; +; - F_acc[6]~38 ; 0 ; 6 ; +; Fword[5] ; ; ; +; - F_acc[5]~36 ; 0 ; 6 ; +; Fword[4] ; ; ; +; - F_acc[4]~34 ; 1 ; 6 ; +; Fword[3] ; ; ; +; - F_acc[3]~32 ; 1 ; 6 ; +; Fword[2] ; ; ; +; - F_acc[2]~30 ; 0 ; 6 ; +; Fword[1] ; ; ; +; - F_acc[1]~28 ; 0 ; 6 ; +; Fword[0] ; ; ; +; - F_acc[0]~26 ; 0 ; 6 ; ++--------------------------+-------------------+---------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++----------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; clk_200m ; PIN_E1 ; 38 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; +; rst_n ; PIN_M2 ; 36 ; Async. clear ; yes ; Global Clock ; GCLK4 ; -- ; ++----------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; clk_200m ; PIN_E1 ; 38 ; 1 ; Global Clock ; GCLK2 ; -- ; +; rst_n ; PIN_M2 ; 36 ; 0 ; Global Clock ; GCLK4 ; -- ; ++----------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++---------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------------------+----------------+----------------------+------------------------+------------------------+----------+------------------------+---------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ; ++---------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------------------+----------------+----------------------+------------------------+------------------------+----------+------------------------+---------------+ +; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; Single Clock ; 1024 ; 9 ; -- ; -- ; yes ; yes ; -- ; -- ; 9216 ; 1024 ; 9 ; -- ; -- ; 9216 ; 1 ; sin9bit_1024.mif ; M9K_X15_Y12_N0 ; Don't care ; New data with NBE Read ; New data with NBE Read ; Off ; No ; No - Unknown ; ++---------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------------------+----------------+----------------------+------------------------+------------------------+----------+------------------------+---------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + +RAM content values are presented in the following format: (Binary) (Octal) (Decimal) (Hexadecimal) ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; |spwm|spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ALTSYNCRAM ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Addr ; +0 ; +1 ; +2 ; +3 ; +4 ; +5 ; +6 ; +7 ; ++----------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+------------------------------+ +;0;(011111111) (377) (255) (FF) ;(100000000) (400) (256) (100) ;(100000010) (402) (258) (102) ;(100000011) (403) (259) (103) ;(100000101) (405) (261) (105) ;(100000110) (406) (262) (106) ;(100001000) (410) (264) (108) ;(100001001) (411) (265) (109) ; +;8;(100001011) (413) (267) (10B) ;(100001100) (414) (268) (10C) ;(100001110) (416) (270) (10E) ;(100001111) (417) (271) (10F) ;(100010001) (421) (273) (111) ;(100010010) (422) (274) (112) ;(100010100) (424) (276) (114) ;(100010101) (425) (277) (115) ; +;16;(100010111) (427) (279) (117) ;(100011000) (430) (280) (118) ;(100011001) (431) (281) (119) ;(100011011) (433) (283) (11B) ;(100011100) (434) (284) (11C) ;(100011110) (436) (286) (11E) ;(100011111) (437) (287) (11F) ;(100100001) (441) (289) (121) ; +;24;(100100010) (442) (290) (122) ;(100100100) (444) (292) (124) ;(100100101) (445) (293) (125) ;(100100111) (447) (295) (127) ;(100101000) (450) (296) (128) ;(100101001) (451) (297) (129) ;(100101011) (453) (299) (12B) ;(100101100) (454) (300) (12C) ; +;32;(100101110) (456) (302) (12E) ;(100101111) (457) (303) (12F) ;(100110001) (461) (305) (131) ;(100110010) (462) (306) (132) ;(100110100) (464) (308) (134) ;(100110101) (465) (309) (135) ;(100110110) (466) (310) (136) ;(100111000) (470) (312) (138) ; +;40;(100111001) (471) (313) (139) ;(100111011) (473) (315) (13B) ;(100111100) (474) (316) (13C) ;(100111110) (476) (318) (13E) ;(100111111) (477) (319) (13F) ;(101000000) (500) (320) (140) ;(101000010) (502) (322) (142) ;(101000011) (503) (323) (143) ; +;48;(101000101) (505) (325) (145) ;(101000110) (506) (326) (146) ;(101000111) (507) (327) (147) ;(101001001) (511) (329) (149) ;(101001010) (512) (330) (14A) ;(101001100) (514) (332) (14C) ;(101001101) (515) (333) (14D) ;(101001110) (516) (334) (14E) ; +;56;(101010000) (520) (336) (150) ;(101010001) (521) (337) (151) ;(101010011) (523) (339) (153) ;(101010100) (524) (340) (154) ;(101010101) (525) (341) (155) ;(101010111) (527) (343) (157) ;(101011000) (530) (344) (158) ;(101011001) (531) (345) (159) ; +;64;(101011011) (533) (347) (15B) ;(101011100) (534) (348) (15C) ;(101011110) (536) (350) (15E) ;(101011111) (537) (351) (15F) ;(101100000) (540) (352) (160) ;(101100010) (542) (354) (162) ;(101100011) (543) (355) (163) ;(101100100) (544) (356) (164) ; +;72;(101100110) (546) (358) (166) ;(101100111) (547) (359) (167) ;(101101000) (550) (360) (168) ;(101101010) (552) (362) (16A) ;(101101011) (553) (363) (16B) ;(101101100) (554) (364) (16C) ;(101101110) (556) (366) (16E) ;(101101111) (557) (367) (16F) ; +;80;(101110000) (560) (368) (170) ;(101110001) (561) (369) (171) ;(101110011) (563) (371) (173) ;(101110100) (564) (372) (174) ;(101110101) (565) (373) (175) ;(101110111) (567) (375) (177) ;(101111000) (570) (376) (178) ;(101111001) (571) (377) (179) ; +;88;(101111010) (572) (378) (17A) ;(101111100) (574) (380) (17C) ;(101111101) (575) (381) (17D) ;(101111110) (576) (382) (17E) ;(101111111) (577) (383) (17F) ;(110000001) (601) (385) (181) ;(110000010) (602) (386) (182) ;(110000011) (603) (387) (183) ; +;96;(110000100) (604) (388) (184) ;(110000110) (606) (390) (186) ;(110000111) (607) (391) (187) ;(110001000) (610) (392) (188) ;(110001001) (611) (393) (189) ;(110001010) (612) (394) (18A) ;(110001100) (614) (396) (18C) ;(110001101) (615) (397) (18D) ; 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+;960;(010100011) (243) (163) (A3) ;(010100101) (245) (165) (A5) ;(010100110) (246) (166) (A6) ;(010100111) (247) (167) (A7) ;(010101001) (251) (169) (A9) ;(010101010) (252) (170) (AA) ;(010101011) (253) (171) (AB) ;(010101101) (255) (173) (AD) ; +;968;(010101110) (256) (174) (AE) ;(010110000) (260) (176) (B0) ;(010110001) (261) (177) (B1) ;(010110010) (262) (178) (B2) ;(010110100) (264) (180) (B4) ;(010110101) (265) (181) (B5) ;(010110111) (267) (183) (B7) ;(010111000) (270) (184) (B8) ; +;976;(010111001) (271) (185) (B9) ;(010111011) (273) (187) (BB) ;(010111100) (274) (188) (BC) ;(010111110) (276) (190) (BE) ;(010111111) (277) (191) (BF) ;(011000000) (300) (192) (C0) ;(011000010) (302) (194) (C2) ;(011000011) (303) (195) (C3) ; +;984;(011000101) (305) (197) (C5) ;(011000110) (306) (198) (C6) ;(011001000) (310) (200) (C8) ;(011001001) (311) (201) (C9) ;(011001010) (312) (202) (CA) ;(011001100) (314) (204) (CC) ;(011001101) (315) (205) (CD) ;(011001111) (317) (207) (CF) ; +;992;(011010000) (320) (208) (D0) ;(011010010) (322) (210) (D2) ;(011010011) (323) (211) (D3) ;(011010101) (325) (213) (D5) ;(011010110) (326) (214) (D6) ;(011010111) (327) (215) (D7) ;(011011001) (331) (217) (D9) ;(011011010) (332) (218) (DA) ; +;1000;(011011100) (334) (220) (DC) ;(011011101) (335) (221) (DD) ;(011011111) (337) (223) (DF) ;(011100000) (340) (224) (E0) ;(011100010) (342) (226) (E2) ;(011100011) (343) (227) (E3) ;(011100101) (345) (229) (E5) ;(011100110) (346) (230) (E6) ; +;1008;(011100111) (347) (231) (E7) ;(011101001) (351) (233) (E9) ;(011101010) (352) (234) (EA) ;(011101100) (354) (236) (EC) ;(011101101) (355) (237) (ED) ;(011101111) (357) (239) (EF) ;(011110000) (360) (240) (F0) ;(011110010) (362) (242) (F2) ; +;1016;(011110011) (363) (243) (F3) ;(011110101) (365) (245) (F5) ;(011110110) (366) (246) (F6) ;(011111000) (370) (248) (F8) ;(011111001) (371) (249) (F9) ;(011111011) (373) (251) (FB) ;(011111100) (374) (252) (FC) ;(011111110) (376) (254) (FE) ; + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 128 / 32,401 ( < 1 % ) ; +; C16 interconnects ; 5 / 1,326 ( < 1 % ) ; +; C4 interconnects ; 102 / 21,816 ( < 1 % ) ; +; Direct links ; 26 / 32,401 ( < 1 % ) ; +; Global clocks ; 2 / 10 ( 20 % ) ; +; Local interconnects ; 45 / 10,320 ( < 1 % ) ; +; R24 interconnects ; 9 / 1,289 ( < 1 % ) ; +; R4 interconnects ; 89 / 28,186 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 11.38) ; Number of LABs (Total = 8) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 3 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 2 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 0.88) ; Number of LABs (Total = 8) ; ++------------------------------------+-----------------------------+ +; 1 Async. clear ; 3 ; +; 1 Clock ; 4 ; ++------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 14.88) ; Number of LABs (Total = 8) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 1 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 2 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 6.75) ; Number of LABs (Total = 8) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 1 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 3 ; ++-------------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 12.25) ; Number of LABs (Total = 8) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 2 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 1 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 0 ; +; 29 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 47 ; 0 ; 0 ; 47 ; 47 ; 0 ; 19 ; 0 ; 0 ; 28 ; 0 ; 19 ; 28 ; 0 ; 0 ; 0 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 47 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 47 ; 47 ; 47 ; 47 ; 47 ; 0 ; 47 ; 47 ; 0 ; 0 ; 47 ; 28 ; 47 ; 47 ; 19 ; 47 ; 28 ; 19 ; 47 ; 47 ; 47 ; 28 ; 47 ; 47 ; 47 ; 47 ; 47 ; 0 ; 47 ; 47 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; tri_out[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tri_out[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tri_out[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tri_out[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tri_out[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tri_out[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tri_out[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tri_out[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tri_out[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sin_out[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sin_out[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sin_out[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sin_out[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sin_out[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sin_out[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sin_out[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sin_out[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sin_out[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; spwm_out ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; clk_200m ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; rst_n ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Pword[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Pword[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Pword[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Pword[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Pword[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Pword[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Pword[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Pword[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Pword[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Pword[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; Fword[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 C ; +; High Junction Temperature ; 85 C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device EP4CE10F17C8 for design "spwm" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE6F17C8 is compatible + Info (176445): Device EP4CE15F17C8 is compatible + Info (176445): Device EP4CE22F17C8 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Critical Warning (169085): No exact pin location assignment(s) for 47 pins of 47 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Critical Warning (332012): Synopsys Design Constraints File file not found: 'spwm.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node clk_200m~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) File: F:/Code/FPGA/reserve/spwm/rtl/spwm.v Line: 11 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 +Info (176353): Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) File: F:/Code/FPGA/reserve/spwm/rtl/spwm.v Line: 12 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 45 (unused VREF, 2.5V VCCIO, 26 input, 19 output, 0 bidirectional) + Info (176212): I/O standards used: 2.5 V. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X0_Y12 to location X10_Y24 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.19 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (144001): Generated suppressed messages file F:/Code/FPGA/reserve/spwm/output_files/spwm.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 5561 megabytes + Info: Processing ended: Mon Dec 10 20:55:23 2018 + Info: Elapsed time: 00:00:07 + Info: Total CPU time (on all processors): 00:00:09 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in F:/Code/FPGA/reserve/spwm/output_files/spwm.fit.smsg. + + diff --git a/spwm/output_files/spwm.fit.smsg b/spwm/output_files/spwm.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/spwm/output_files/spwm.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/spwm/output_files/spwm.fit.summary b/spwm/output_files/spwm.fit.summary new file mode 100644 index 0000000..a13b1e9 --- /dev/null +++ b/spwm/output_files/spwm.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon Dec 10 20:55:22 2018 +Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Revision Name : spwm +Top-level Entity Name : spwm +Family : Cyclone IV E +Device : EP4CE10F17C8 +Timing Models : Final +Total logic elements : 91 / 10,320 ( < 1 % ) + Total combinational functions : 91 / 10,320 ( < 1 % ) + Dedicated logic registers : 37 / 10,320 ( < 1 % ) +Total registers : 37 +Total pins : 47 / 180 ( 26 % ) +Total virtual pins : 0 +Total memory bits : 9,216 / 423,936 ( 2 % ) +Embedded Multiplier 9-bit elements : 0 / 46 ( 0 % ) +Total PLLs : 0 / 2 ( 0 % ) diff --git a/spwm/output_files/spwm.flow.rpt b/spwm/output_files/spwm.flow.rpt new file mode 100644 index 0000000..0917292 --- /dev/null +++ b/spwm/output_files/spwm.flow.rpt @@ -0,0 +1,138 @@ +Flow report for spwm +Mon Dec 10 20:55:32 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Mon Dec 10 20:55:32 2018 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; spwm ; +; Top-level Entity Name ; spwm ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Total logic elements ; 91 / 10,320 ( < 1 % ) ; +; Total combinational functions ; 91 / 10,320 ( < 1 % ) ; +; Dedicated logic registers ; 37 / 10,320 ( < 1 % ) ; +; Total registers ; 37 ; +; Total pins ; 47 / 180 ( 26 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 9,216 / 423,936 ( 2 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/10/2018 20:54:59 ; +; Main task ; Compilation ; +; Revision Name ; spwm ; ++-------------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++--------------------------------------+----------------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++--------------------------------------+----------------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 93383153531551.154444649911872 ; -- ; -- ; -- ; +; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; spwm_tb ; +; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; spwm_tb ; -- ; -- ; eda_simulation ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; +; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ; +; EDA_TEST_BENCH_FILE ; testbench/spwm_tb.v ; -- ; -- ; spwm_tb ; +; EDA_TEST_BENCH_MODULE_NAME ; spwm_tb ; -- ; -- ; spwm_tb ; +; EDA_TEST_BENCH_NAME ; spwm_tb ; -- ; -- ; eda_simulation ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; spwm_sin_bb.v ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++--------------------------------------+----------------------------------------+---------------+-------------+----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:15 ; 1.0 ; 4804 MB ; 00:00:32 ; +; Fitter ; 00:00:06 ; 1.0 ; 5561 MB ; 00:00:08 ; +; Assembler ; 00:00:01 ; 1.0 ; 4694 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:03 ; 1.0 ; 4777 MB ; 00:00:03 ; +; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 4663 MB ; 00:00:02 ; +; Total ; 00:00:27 ; -- ; -- ; 00:00:46 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Timing Analyzer ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; ++----------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off spwm -c spwm +quartus_fit --read_settings_files=off --write_settings_files=off spwm -c spwm +quartus_asm --read_settings_files=off --write_settings_files=off spwm -c spwm +quartus_sta spwm -c spwm +quartus_eda --read_settings_files=off --write_settings_files=off spwm -c spwm + + + diff --git a/spwm/output_files/spwm.jdi b/spwm/output_files/spwm.jdi new file mode 100644 index 0000000..7e776bb --- /dev/null +++ b/spwm/output_files/spwm.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/spwm/output_files/spwm.map.rpt b/spwm/output_files/spwm.map.rpt new file mode 100644 index 0000000..c37a3c5 --- /dev/null +++ b/spwm/output_files/spwm.map.rpt @@ -0,0 +1,586 @@ +Analysis & Synthesis report for spwm +Mon Dec 10 20:55:14 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis RAM Summary + 9. Analysis & Synthesis IP Cores Summary + 10. General Register Statistics + 11. Source assignments for spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated + 12. Parameter Settings for User Entity Instance: Top-level Entity: |spwm + 13. Parameter Settings for User Entity Instance: spwm_sin:spwm_sin|altsyncram:altsyncram_component + 14. Parameter Settings for Inferred Entity Instance: modulation:modulation|lpm_mult:Mult0 + 15. altsyncram Parameter Settings by Entity Instance + 16. lpm_mult Parameter Settings by Entity Instance + 17. Port Connectivity Checks: "modulation:modulation" + 18. Post-Synthesis Netlist Statistics for Top Partition + 19. Elapsed Time Per Partition + 20. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Dec 10 20:55:14 2018 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; spwm ; +; Top-level Entity Name ; spwm ; +; Family ; Cyclone IV E ; +; Total logic elements ; 91 ; +; Total combinational functions ; 91 ; +; Dedicated logic registers ; 37 ; +; Total registers ; 37 ; +; Total pins ; 47 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 9,216 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+-------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP4CE10F17C8 ; ; +; Top-level entity name ; spwm ; spwm ; +; Family name ; Cyclone IV E ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.0% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------------+---------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------------+---------------------------------------------------------------------------+---------+ +; rtl/spwm.v ; yes ; User Verilog HDL File ; F:/Code/FPGA/reserve/spwm/rtl/spwm.v ; ; +; spwm_sin.v ; yes ; User Wizard-Generated File ; F:/Code/FPGA/reserve/spwm/spwm_sin.v ; ; +; rtl/modulation.v ; yes ; User Verilog HDL File ; F:/Code/FPGA/reserve/spwm/rtl/modulation.v ; ; +; altsyncram.tdf ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf ; ; +; stratix_ram_block.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; +; lpm_mux.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mux.inc ; ; +; lpm_decode.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_decode.inc ; ; +; aglobal181.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/aglobal181.inc ; ; +; a_rdenreg.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; +; altrom.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/altrom.inc ; ; +; altram.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/altram.inc ; ; +; altdpram.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/altdpram.inc ; ; +; db/altsyncram_sl91.tdf ; yes ; Auto-Generated Megafunction ; F:/Code/FPGA/reserve/spwm/db/altsyncram_sl91.tdf ; ; +; sin9bit_1024.mif ; yes ; Auto-Found Memory Initialization File ; F:/Code/FPGA/reserve/spwm/sin9bit_1024.mif ; ; +; lpm_mult.tdf ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf ; ; +; lpm_add_sub.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ; +; multcore.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/multcore.inc ; ; +; bypassff.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/bypassff.inc ; ; +; altshift.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/altshift.inc ; ; +; multcore.tdf ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/multcore.tdf ; ; +; csa_add.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/csa_add.inc ; ; +; mpar_add.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.inc ; ; +; muleabz.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/muleabz.inc ; ; +; mul_lfrg.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/mul_lfrg.inc ; ; +; mul_boothc.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/mul_boothc.inc ; ; +; alt_ded_mult.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/alt_ded_mult.inc ; ; +; alt_ded_mult_y.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/alt_ded_mult_y.inc ; ; +; dffpipe.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/dffpipe.inc ; ; +; mpar_add.tdf ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf ; ; +; lpm_add_sub.tdf ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ; +; addcore.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/addcore.inc ; ; +; look_add.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/look_add.inc ; ; +; alt_stratix_add_sub.inc ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ; +; db/add_sub_lgh.tdf ; yes ; Auto-Generated Megafunction ; F:/Code/FPGA/reserve/spwm/db/add_sub_lgh.tdf ; ; +; db/add_sub_pgh.tdf ; yes ; Auto-Generated Megafunction ; F:/Code/FPGA/reserve/spwm/db/add_sub_pgh.tdf ; ; +; altshift.tdf ; yes ; Megafunction ; d:/intelfpga/18.1/quartus/libraries/megafunctions/altshift.tdf ; ; ++----------------------------------+-----------------+----------------------------------------+---------------------------------------------------------------------------+---------+ + + ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; Estimated Total logic elements ; 91 ; +; ; ; +; Total combinational functions ; 91 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 15 ; +; -- 3 input functions ; 53 ; +; -- <=2 input functions ; 23 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 25 ; +; -- arithmetic mode ; 66 ; +; ; ; +; Total registers ; 37 ; +; -- Dedicated logic registers ; 37 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 47 ; +; Total memory bits ; 9216 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; clk_200m~input ; +; Maximum fan-out ; 46 ; +; Total fan-out ; 536 ; +; Average fan-out ; 2.32 ; ++---------------------------------------------+----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++---------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++---------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +; |spwm ; 91 (49) ; 37 (36) ; 9216 ; 0 ; 0 ; 0 ; 47 ; 0 ; |spwm ; spwm ; work ; +; |modulation:modulation| ; 42 (12) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|modulation:modulation ; modulation ; work ; +; |lpm_mult:Mult0| ; 30 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|modulation:modulation|lpm_mult:Mult0 ; lpm_mult ; work ; +; |multcore:mult_core| ; 30 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core ; multcore ; work ; +; |mpar_add:padder| ; 17 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder ; mpar_add ; work ; +; |lpm_add_sub:adder[0]| ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0] ; lpm_add_sub ; work ; +; |add_sub_lgh:auto_generated| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_lgh:auto_generated ; add_sub_lgh ; work ; +; |mpar_add:sub_par_add| ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add ; mpar_add ; work ; +; |lpm_add_sub:adder[0]| ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0] ; lpm_add_sub ; work ; +; |add_sub_pgh:auto_generated| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_pgh:auto_generated ; add_sub_pgh ; work ; +; |spwm_sin:spwm_sin| ; 0 (0) ; 0 (0) ; 9216 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|spwm_sin:spwm_sin ; spwm_sin ; work ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 9216 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|spwm_sin:spwm_sin|altsyncram:altsyncram_component ; altsyncram ; work ; +; |altsyncram_sl91:auto_generated| ; 0 (0) ; 0 (0) ; 9216 ; 0 ; 0 ; 0 ; 0 ; 0 ; |spwm|spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated ; altsyncram_sl91 ; work ; ++---------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++---------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++---------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------------+ +; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 1024 ; 9 ; -- ; -- ; 9216 ; sin9bit_1024.mif ; ++---------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+-------------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+-------------------------+-----------------+ +; Altera ; ROM: 1-PORT ; 18.1 ; N/A ; N/A ; |spwm|spwm_sin:spwm_sin ; spwm_sin.v ; ++--------+--------------+---------+--------------+--------------+-------------------------+-----------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 37 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 36 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Source assignments for spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated ; ++---------------------------------+--------------------+------+-------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------+ + + ++----------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Top-level Entity: |spwm ; ++----------------+----------+------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+----------+------------------------------------------+ +; depth ; 11100100 ; Unsigned Binary ; ++----------------+----------+------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: spwm_sin:spwm_sin|altsyncram:altsyncram_component ; ++------------------------------------+----------------------+------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+----------------------+------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; ROM ; Untyped ; +; WIDTH_A ; 9 ; Signed Integer ; +; WIDTHAD_A ; 10 ; Signed Integer ; +; NUMWORDS_A ; 1024 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 1 ; Untyped ; +; WIDTHAD_B ; 1 ; Untyped ; +; NUMWORDS_B ; 1 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; sin9bit_1024.mif ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ; +; WIDTH_ECCSTATUS ; 3 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; CBXI_PARAMETER ; altsyncram_sl91 ; Untyped ; ++------------------------------------+----------------------+------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: modulation:modulation|lpm_mult:Mult0 ; ++------------------------------------------------+--------------+-----------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------------------+--------------+-----------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTHA ; 9 ; Untyped ; +; LPM_WIDTHB ; 8 ; Untyped ; +; LPM_WIDTHP ; 17 ; Untyped ; +; LPM_WIDTHR ; 17 ; Untyped ; +; LPM_WIDTHS ; 1 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LATENCY ; 0 ; Untyped ; +; INPUT_A_IS_CONSTANT ; NO ; Untyped ; +; INPUT_B_IS_CONSTANT ; YES ; Untyped ; +; USE_EAB ; OFF ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; +; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; +; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; +; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; ++------------------------------------------------+--------------+-----------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------+ +; altsyncram Parameter Settings by Entity Instance ; ++-------------------------------------------+---------------------------------------------------+ +; Name ; Value ; ++-------------------------------------------+---------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; spwm_sin:spwm_sin|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; ROM ; +; -- WIDTH_A ; 9 ; +; -- NUMWORDS_A ; 1024 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 1 ; +; -- NUMWORDS_B ; 1 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ++-------------------------------------------+---------------------------------------------------+ + + ++------------------------------------------------------------------------------+ +; lpm_mult Parameter Settings by Entity Instance ; ++---------------------------------------+--------------------------------------+ +; Name ; Value ; ++---------------------------------------+--------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; modulation:modulation|lpm_mult:Mult0 ; +; -- LPM_WIDTHA ; 9 ; +; -- LPM_WIDTHB ; 8 ; +; -- LPM_WIDTHP ; 17 ; +; -- LPM_REPRESENTATION ; UNSIGNED ; +; -- INPUT_A_IS_CONSTANT ; NO ; +; -- INPUT_B_IS_CONSTANT ; YES ; +; -- USE_EAB ; OFF ; +; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; +; -- INPUT_A_FIXED_VALUE ; Bx ; +; -- INPUT_B_FIXED_VALUE ; Bx ; ++---------------------------------------+--------------------------------------+ + + ++---------------------------------------------------+ +; Port Connectivity Checks: "modulation:modulation" ; ++-------------+-------+----------+------------------+ +; Port ; Type ; Severity ; Details ; ++-------------+-------+----------+------------------+ +; depth[7..5] ; Input ; Info ; Stuck at VCC ; +; depth[4..3] ; Input ; Info ; Stuck at GND ; +; depth[1..0] ; Input ; Info ; Stuck at GND ; +; depth[2] ; Input ; Info ; Stuck at VCC ; ++-------------+-------+----------+------------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 47 ; +; cycloneiii_ff ; 37 ; +; CLR ; 36 ; +; plain ; 1 ; +; cycloneiii_lcell_comb ; 91 ; +; arith ; 66 ; +; 2 data inputs ; 16 ; +; 3 data inputs ; 50 ; +; normal ; 25 ; +; 0 data inputs ; 1 ; +; 1 data inputs ; 2 ; +; 2 data inputs ; 4 ; +; 3 data inputs ; 3 ; +; 4 data inputs ; 15 ; +; cycloneiii_ram_block ; 9 ; +; ; ; +; Max LUT depth ; 5.00 ; +; Average LUT depth ; 3.24 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:01 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Mon Dec 10 20:54:59 2018 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spwm -c spwm +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file rtl/spwm.v + Info (12023): Found entity 1: spwm File: F:/Code/FPGA/reserve/spwm/rtl/spwm.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file testbench/spwm_tb.v + Info (12023): Found entity 1: spwm_tb File: F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v Line: 5 +Info (12021): Found 1 design units, including 1 entities, in source file spwm_sin.v + Info (12023): Found entity 1: spwm_sin File: F:/Code/FPGA/reserve/spwm/spwm_sin.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file rtl/modulation.v + Info (12023): Found entity 1: modulation File: F:/Code/FPGA/reserve/spwm/rtl/modulation.v Line: 1 +Info (12127): Elaborating entity "spwm" for the top level hierarchy +Info (12128): Elaborating entity "spwm_sin" for hierarchy "spwm_sin:spwm_sin" File: F:/Code/FPGA/reserve/spwm/rtl/spwm.v Line: 70 +Info (12128): Elaborating entity "altsyncram" for hierarchy "spwm_sin:spwm_sin|altsyncram:altsyncram_component" File: F:/Code/FPGA/reserve/spwm/spwm_sin.v Line: 81 +Info (12130): Elaborated megafunction instantiation "spwm_sin:spwm_sin|altsyncram:altsyncram_component" File: F:/Code/FPGA/reserve/spwm/spwm_sin.v Line: 81 +Info (12133): Instantiated megafunction "spwm_sin:spwm_sin|altsyncram:altsyncram_component" with the following parameter: File: F:/Code/FPGA/reserve/spwm/spwm_sin.v Line: 81 + Info (12134): Parameter "address_aclr_a" = "NONE" + Info (12134): Parameter "clock_enable_input_a" = "BYPASS" + Info (12134): Parameter "clock_enable_output_a" = "BYPASS" + Info (12134): Parameter "init_file" = "sin9bit_1024.mif" + Info (12134): Parameter "intended_device_family" = "Cyclone IV E" + Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" + Info (12134): Parameter "lpm_type" = "altsyncram" + Info (12134): Parameter "numwords_a" = "1024" + Info (12134): Parameter "operation_mode" = "ROM" + Info (12134): Parameter "outdata_aclr_a" = "NONE" + Info (12134): Parameter "outdata_reg_a" = "CLOCK0" + Info (12134): Parameter "widthad_a" = "10" + Info (12134): Parameter "width_a" = "9" + Info (12134): Parameter "width_byteena_a" = "1" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_sl91.tdf + Info (12023): Found entity 1: altsyncram_sl91 File: F:/Code/FPGA/reserve/spwm/db/altsyncram_sl91.tdf Line: 27 +Info (12128): Elaborating entity "altsyncram_sl91" for hierarchy "spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated" File: d:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 791 +Info (12128): Elaborating entity "modulation" for hierarchy "modulation:modulation" File: F:/Code/FPGA/reserve/spwm/rtl/spwm.v Line: 78 +Info (278001): Inferred 1 megafunctions from design logic + Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "modulation:modulation|Mult0" File: F:/Code/FPGA/reserve/spwm/rtl/modulation.v Line: 22 +Info (12130): Elaborated megafunction instantiation "modulation:modulation|lpm_mult:Mult0" File: F:/Code/FPGA/reserve/spwm/rtl/modulation.v Line: 22 +Info (12133): Instantiated megafunction "modulation:modulation|lpm_mult:Mult0" with the following parameter: File: F:/Code/FPGA/reserve/spwm/rtl/modulation.v Line: 22 + Info (12134): Parameter "LPM_WIDTHA" = "9" + Info (12134): Parameter "LPM_WIDTHB" = "8" + Info (12134): Parameter "LPM_WIDTHP" = "17" + Info (12134): Parameter "LPM_WIDTHR" = "17" + Info (12134): Parameter "LPM_WIDTHS" = "1" + Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" + Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO" + Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "YES" + Info (12134): Parameter "MAXIMIZE_SPEED" = "5" +Info (12131): Elaborated megafunction instantiation "modulation:modulation|lpm_mult:Mult0|multcore:mult_core", which is child of megafunction instantiation "modulation:modulation|lpm_mult:Mult0" File: d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 308 +Info (12131): Elaborated megafunction instantiation "modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "modulation:modulation|lpm_mult:Mult0" File: d:/intelfpga/18.1/quartus/libraries/megafunctions/multcore.tdf Line: 228 +Info (12131): Elaborated megafunction instantiation "modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]", which is child of megafunction instantiation "modulation:modulation|lpm_mult:Mult0" File: d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78 +Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_lgh.tdf + Info (12023): Found entity 1: add_sub_lgh File: F:/Code/FPGA/reserve/spwm/db/add_sub_lgh.tdf Line: 22 +Info (12131): Elaborated megafunction instantiation "modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add", which is child of megafunction instantiation "modulation:modulation|lpm_mult:Mult0" File: d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 138 +Info (12131): Elaborated megafunction instantiation "modulation:modulation|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]", which is child of megafunction instantiation "modulation:modulation|lpm_mult:Mult0" File: d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf Line: 78 +Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_pgh.tdf + Info (12023): Found entity 1: add_sub_pgh File: F:/Code/FPGA/reserve/spwm/db/add_sub_pgh.tdf Line: 22 +Info (12131): Elaborated megafunction instantiation "modulation:modulation|lpm_mult:Mult0|altshift:external_latency_ffs", which is child of megafunction instantiation "modulation:modulation|lpm_mult:Mult0" File: d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf Line: 351 +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 148 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 28 input pins + Info (21059): Implemented 19 output pins + Info (21061): Implemented 92 logic cells + Info (21064): Implemented 9 RAM segments +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4804 megabytes + Info: Processing ended: Mon Dec 10 20:55:14 2018 + Info: Elapsed time: 00:00:15 + Info: Total CPU time (on all processors): 00:00:32 + + diff --git a/spwm/output_files/spwm.map.smsg b/spwm/output_files/spwm.map.smsg new file mode 100644 index 0000000..e4148de --- /dev/null +++ b/spwm/output_files/spwm.map.smsg @@ -0,0 +1 @@ +Warning (10268): Verilog HDL information at modulation.v(25): always construct contains both blocking and non-blocking assignments File: F:/Code/FPGA/reserve/spwm/rtl/modulation.v Line: 25 diff --git a/spwm/output_files/spwm.map.summary b/spwm/output_files/spwm.map.summary new file mode 100644 index 0000000..2950853 --- /dev/null +++ b/spwm/output_files/spwm.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon Dec 10 20:55:14 2018 +Quartus Prime Version : 18.1.0 Build 625 09/12/2018 SJ Standard Edition +Revision Name : spwm +Top-level Entity Name : spwm +Family : Cyclone IV E +Total logic elements : 91 + Total combinational functions : 91 + Dedicated logic registers : 37 +Total registers : 37 +Total pins : 47 +Total virtual pins : 0 +Total memory bits : 9,216 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/spwm/output_files/spwm.pin b/spwm/output_files/spwm.pin new file mode 100644 index 0000000..93b815d --- /dev/null +++ b/spwm/output_files/spwm.pin @@ -0,0 +1,326 @@ + -- Copyright (C) 2018 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +CHIP "spwm" ASSIGNED TO AN: EP4CE10F17C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +VCCIO8 : A1 : power : : 2.5V : 8 : +Fword[12] : A2 : input : 2.5 V : : 8 : N +Fword[8] : A3 : input : 2.5 V : : 8 : N +Fword[0] : A4 : input : 2.5 V : : 8 : N +Pword[5] : A5 : input : 2.5 V : : 8 : N +Pword[0] : A6 : input : 2.5 V : : 8 : N +Fword[5] : A7 : input : 2.5 V : : 8 : N +tri_out[5] : A8 : output : 2.5 V : : 8 : N +tri_out[1] : A9 : output : 2.5 V : : 7 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7 : +VCCIO7 : A16 : power : : 2.5V : 7 : +Fword[13] : B1 : input : 2.5 V : : 1 : N +GND : B2 : gnd : : : : +Fword[10] : B3 : input : 2.5 V : : 8 : N +Fword[7] : B4 : input : 2.5 V : : 8 : N +Fword[11] : B5 : input : 2.5 V : : 8 : N +Fword[4] : B6 : input : 2.5 V : : 8 : N +Fword[2] : B7 : input : 2.5 V : : 8 : N +tri_out[2] : B8 : output : 2.5 V : : 8 : N +tri_out[4] : B9 : output : 2.5 V : : 7 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +GND : B15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 2.5 V : : 1 : N +Pword[7] : C2 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +VCCIO8 : C4 : power : : 2.5V : 8 : +GND : C5 : gnd : : : : +Fword[9] : C6 : input : 2.5 V : : 8 : N +VCCIO8 : C7 : power : : 2.5V : 8 : +tri_out[8] : C8 : output : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 7 : +VCCIO7 : C10 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 7 : +GND : C12 : gnd : : : : +VCCIO7 : C13 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 : +Pword[1] : D1 : input : 2.5 V : : 1 : N +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 2.5 V : : 1 : N +Fword[6] : D3 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 1 : +Fword[3] : D5 : input : 2.5 V : : 8 : N +Fword[1] : D6 : input : 2.5 V : : 8 : N +GND : D7 : gnd : : : : +tri_out[6] : D8 : output : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 7 : +GND : D10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 7 : +VCCD_PLL2 : D13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 6 : +clk_200m : E1 : input : 2.5 V : : 1 : N +GND : E2 : gnd : : : : +VCCIO1 : E3 : power : : 2.5V : 1 : +GND : E4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 1 : +Pword[9] : E6 : input : 2.5 V : : 8 : N +Pword[2] : E7 : input : 2.5 V : : 8 : N +tri_out[3] : E8 : output : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 7 : +GNDA2 : E12 : gnd : : : : +GND : E13 : gnd : : : : +VCCIO6 : E14 : power : : 2.5V : 6 : +GND+ : E15 : : : : 6 : +GND+ : E16 : : : : 6 : +Pword[4] : F1 : input : 2.5 V : : 1 : N +Pword[8] : F2 : input : 2.5 V : : 1 : N +Pword[3] : F3 : input : 2.5 V : : 1 : N +nSTATUS : F4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 : +tri_out[7] : F6 : output : 2.5 V : : 8 : N +sin_out[4] : F7 : output : 2.5 V : : 8 : N +tri_out[0] : F8 : output : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 7 : +VCCA2 : F12 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 2.5 V : : 6 : N +Pword[6] : G1 : input : 2.5 V : : 1 : N +Fword[14] : G2 : input : 2.5 V : : 1 : N +VCCIO1 : G3 : power : : 2.5V : 1 : +GND : G4 : gnd : : : : +Fword[15] : G5 : input : 2.5 V : : 1 : N +VCCINT : G6 : power : : 1.2V : : +VCCINT : G7 : power : : 1.2V : : +VCCINT : G8 : power : : 1.2V : : +VCCINT : G9 : power : : 1.2V : : +VCCINT : G10 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 6 : +MSEL2 : G12 : : : : 6 : +GND : G13 : gnd : : : : +VCCIO6 : G14 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 6 : +~ALTERA_DCLK~ : H1 : output : 2.5 V : : 1 : N +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V : : 1 : N +TCK : H3 : input : : : 1 : +TDI : H4 : input : : : 1 : +nCONFIG : H5 : : : : 1 : +VCCINT : H6 : power : : 1.2V : : +GND : H7 : gnd : : : : +GND : H8 : gnd : : : : +GND : H9 : gnd : : : : +GND : H10 : gnd : : : : +VCCINT : H11 : power : : 1.2V : : +MSEL1 : H12 : : : : 6 : +MSEL0 : H13 : : : : 6 : +CONF_DONE : H14 : : : : 6 : +GND : H15 : gnd : : : : +GND : H16 : gnd : : : : +sin_out[6] : J1 : output : 2.5 V : : 2 : N +sin_out[5] : J2 : output : 2.5 V : : 2 : N +nCE : J3 : : : : 1 : +TDO : J4 : output : : : 1 : +TMS : J5 : input : : : 1 : +sin_out[1] : J6 : output : 2.5 V : : 2 : N +GND : J7 : gnd : : : : +GND : J8 : gnd : : : : +GND : J9 : gnd : : : : +GND : J10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 2 : +VCCIO2 : K3 : power : : 2.5V : 2 : +GND : K4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 2 : +VCCINT : K7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 5 : +GND : K13 : gnd : : : : +VCCIO5 : K14 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 2 : +VCCA1 : L5 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 2 : +sin_out[2] : L7 : output : 2.5 V : : 3 : N +spwm_out : L8 : output : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L12 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 5 : +GND+ : M1 : : : : 2 : +rst_n : M2 : input : 2.5 V : : 2 : N +VCCIO2 : M3 : power : : 2.5V : 2 : +GND : M4 : gnd : : : : +GNDA1 : M5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 3 : +sin_out[0] : M8 : output : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M12 : : : : 5 : +GND : M13 : gnd : : : : +VCCIO5 : M14 : power : : 2.5V : 5 : +GND+ : M15 : : : : 5 : +GND+ : M16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 3 : +VCCD_PLL1 : N4 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 3 : +GND : N7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N9 : : : : 4 : +GND : N10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3 : +VCCIO3 : P4 : power : : 2.5V : 3 : +GND : P5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P6 : : : : 3 : +VCCIO3 : P7 : power : : 2.5V : 3 : +sin_out[7] : P8 : output : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 4 : +VCCIO4 : P10 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P11 : : : : 4 : +GND : P12 : gnd : : : : +VCCIO4 : P13 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +GND : R2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 3 : +sin_out[3] : R7 : output : 2.5 V : : 3 : N +sin_out[8] : R8 : output : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : +GND : R15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 5 : +VCCIO3 : T1 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T12 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 : +VCCIO4 : T16 : power : : 2.5V : 4 : diff --git a/spwm/output_files/spwm.sld b/spwm/output_files/spwm.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/spwm/output_files/spwm.sld @@ -0,0 +1 @@ + diff --git a/spwm/output_files/spwm.sof b/spwm/output_files/spwm.sof new file mode 100644 index 0000000..547d4c6 Binary files /dev/null and b/spwm/output_files/spwm.sof differ diff --git a/spwm/output_files/spwm.sta.rpt b/spwm/output_files/spwm.sta.rpt new file mode 100644 index 0000000..a16879b --- /dev/null +++ b/spwm/output_files/spwm.sta.rpt @@ -0,0 +1,1358 @@ +Timing Analyzer report for spwm +Mon Dec 10 20:55:29 2018 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Slow 1200mV 85C Model Setup: 'clk_200m' + 13. Slow 1200mV 85C Model Hold: 'clk_200m' + 14. Slow 1200mV 85C Model Metastability Summary + 15. Slow 1200mV 0C Model Fmax Summary + 16. Slow 1200mV 0C Model Setup Summary + 17. Slow 1200mV 0C Model Hold Summary + 18. Slow 1200mV 0C Model Recovery Summary + 19. Slow 1200mV 0C Model Removal Summary + 20. Slow 1200mV 0C Model Minimum Pulse Width Summary + 21. Slow 1200mV 0C Model Setup: 'clk_200m' + 22. Slow 1200mV 0C Model Hold: 'clk_200m' + 23. Slow 1200mV 0C Model Metastability Summary + 24. Fast 1200mV 0C Model Setup Summary + 25. Fast 1200mV 0C Model Hold Summary + 26. Fast 1200mV 0C Model Recovery Summary + 27. Fast 1200mV 0C Model Removal Summary + 28. Fast 1200mV 0C Model Minimum Pulse Width Summary + 29. Fast 1200mV 0C Model Setup: 'clk_200m' + 30. Fast 1200mV 0C Model Hold: 'clk_200m' + 31. Fast 1200mV 0C Model Metastability Summary + 32. Multicorner Timing Analysis Summary + 33. Board Trace Model Assignments + 34. Input Transition Times + 35. Signal Integrity Metrics (Slow 1200mv 0c Model) + 36. Signal Integrity Metrics (Slow 1200mv 85c Model) + 37. Signal Integrity Metrics (Fast 1200mv 0c Model) + 38. Setup Transfers + 39. Hold Transfers + 40. Report TCCS + 41. Report RSKM + 42. Unconstrained Paths Summary + 43. Clock Status Summary + 44. Unconstrained Input Ports + 45. Unconstrained Output Ports + 46. Unconstrained Input Ports + 47. Unconstrained Output Ports + 48. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+---------------------------------------------------------+ +; Quartus Prime Version ; Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; spwm ; +; Device Family ; Cyclone IV E ; +; Device Name ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+---------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.04 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 2.4% ; +; Processors 3-4 ; 0.6% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ +; clk_200m ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk_200m } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+ + + ++--------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 135.03 MHz ; 135.03 MHz ; clk_200m ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++-------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++----------+--------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+-----------------+ +; clk_200m ; -6.406 ; -106.964 ; ++----------+--------+-----------------+ + + ++------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++----------+-------+-----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+-----------------+ +; clk_200m ; 0.452 ; 0.000 ; ++----------+-------+-----------------+ + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++---------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++----------+--------+-------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+-------------------------------+ +; clk_200m ; -3.201 ; -90.029 ; ++----------+--------+-------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'clk_200m' ; ++--------+------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -6.406 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[4] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.047 ; 7.454 ; +; -6.200 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[3] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.047 ; 7.248 ; +; -6.174 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[0] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.047 ; 7.222 ; +; -6.057 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[7] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.047 ; 7.105 ; +; -5.860 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[1] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.047 ; 6.908 ; +; -5.787 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[2] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.047 ; 6.835 ; +; -5.689 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[5] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.047 ; 6.737 ; +; -5.617 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[6] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.047 ; 6.665 ; +; -3.651 ; tri_out[8]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.570 ; +; -3.625 ; tri_out[5]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.544 ; +; -3.590 ; tri_out[8]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.509 ; +; -3.537 ; tri_out[5]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.456 ; +; -3.505 ; tri_out[8]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.424 ; +; -3.479 ; tri_out[5]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.398 ; +; -3.471 ; tri_out[2]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.390 ; +; -3.450 ; tri_out[4]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.369 ; +; -3.444 ; tri_out[8]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.363 ; +; -3.437 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[8] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.047 ; 4.485 ; +; -3.417 ; tri_out[6]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.336 ; +; -3.416 ; tri_out[6]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.335 ; +; -3.391 ; tri_out[5]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.310 ; +; -3.359 ; tri_out[8]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.278 ; +; -3.346 ; F_acc[16] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.302 ; 4.696 ; +; -3.333 ; tri_out[5]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.252 ; +; -3.325 ; tri_out[2]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.244 ; +; -3.324 ; tri_out[2]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.243 ; +; -3.319 ; tri_out[1]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.238 ; +; -3.317 ; F_acc[17] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.302 ; 4.667 ; +; -3.317 ; tri_out[4]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.236 ; +; -3.304 ; tri_out[4]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.223 ; +; -3.298 ; tri_out[8]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.217 ; +; -3.271 ; tri_out[6]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.190 ; +; -3.270 ; tri_out[6]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.189 ; +; -3.265 ; updown ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.184 ; +; -3.248 ; F_acc[18] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.302 ; 4.598 ; +; -3.245 ; tri_out[5]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.164 ; +; -3.213 ; tri_out[8]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.132 ; +; -3.207 ; F_acc[19] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.302 ; 4.557 ; +; -3.187 ; tri_out[5]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.106 ; +; -3.179 ; tri_out[1]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.098 ; +; -3.179 ; tri_out[2]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.098 ; +; -3.178 ; tri_out[2]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.097 ; +; -3.173 ; tri_out[1]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.092 ; +; -3.171 ; tri_out[4]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.090 ; +; -3.158 ; tri_out[4]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.077 ; +; -3.146 ; updown ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.065 ; +; -3.125 ; tri_out[6]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.044 ; +; -3.124 ; tri_out[6]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.043 ; +; -3.119 ; updown ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.038 ; +; -3.099 ; tri_out[7]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.018 ; +; -3.091 ; tri_out[3]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 4.010 ; +; -3.043 ; F_acc[20] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.302 ; 4.393 ; +; -3.033 ; tri_out[1]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.952 ; +; -3.033 ; tri_out[2]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.952 ; +; -3.032 ; tri_out[2]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.951 ; +; -3.029 ; F_acc[21] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.302 ; 4.379 ; +; -3.027 ; tri_out[1]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.946 ; +; -3.025 ; tri_out[4]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.944 ; +; -3.012 ; tri_out[4]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.931 ; +; -3.000 ; updown ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.919 ; +; -2.982 ; tri_out[7]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.901 ; +; -2.982 ; tri_out[3]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.901 ; +; -2.979 ; tri_out[6]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.898 ; +; -2.973 ; updown ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.892 ; +; -2.956 ; tri_out[0]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.875 ; +; -2.953 ; tri_out[7]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.872 ; +; -2.945 ; tri_out[3]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.864 ; +; -2.917 ; F_acc[23] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.302 ; 4.267 ; +; -2.901 ; F_acc[22] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.302 ; 4.251 ; +; -2.891 ; tri_out[0]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.810 ; +; -2.887 ; tri_out[1]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.806 ; +; -2.881 ; tri_out[1]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.800 ; +; -2.854 ; updown ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.773 ; +; -2.836 ; tri_out[7]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.755 ; +; -2.836 ; tri_out[3]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.755 ; +; -2.827 ; updown ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.746 ; +; -2.810 ; tri_out[0]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.729 ; +; -2.807 ; tri_out[7]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.726 ; +; -2.799 ; tri_out[3]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.718 ; +; -2.755 ; F_acc[24] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.302 ; 4.105 ; +; -2.745 ; tri_out[0]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.664 ; +; -2.690 ; tri_out[7]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.609 ; +; -2.690 ; tri_out[3]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.609 ; +; -2.671 ; tri_out[8]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.590 ; +; -2.664 ; tri_out[0]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.583 ; +; -2.661 ; tri_out[7]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.580 ; +; -2.656 ; F_acc[0] ; F_acc[25] ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.575 ; +; -2.653 ; tri_out[3]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.572 ; +; -2.627 ; F_acc[1] ; F_acc[24] ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.546 ; +; -2.618 ; tri_out[5]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.537 ; +; -2.602 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[8] ; clk_200m ; clk_200m ; 1.000 ; -0.090 ; 3.428 ; +; -2.602 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[7] ; clk_200m ; clk_200m ; 1.000 ; -0.090 ; 3.428 ; +; -2.602 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[6] ; clk_200m ; clk_200m ; 1.000 ; -0.090 ; 3.428 ; +; -2.602 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[5] ; clk_200m ; clk_200m ; 1.000 ; -0.090 ; 3.428 ; +; -2.602 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[4] ; clk_200m ; clk_200m ; 1.000 ; -0.090 ; 3.428 ; +; -2.602 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[3] ; clk_200m ; clk_200m ; 1.000 ; -0.090 ; 3.428 ; +; -2.602 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[2] ; clk_200m ; clk_200m ; 1.000 ; -0.090 ; 3.428 ; +; -2.602 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[1] ; clk_200m ; clk_200m ; 1.000 ; -0.090 ; 3.428 ; +; -2.602 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[0] ; clk_200m ; clk_200m ; 1.000 ; -0.090 ; 3.428 ; +; -2.599 ; tri_out[0]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.082 ; 3.518 ; ++--------+------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'clk_200m' ; ++-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+ +; 0.452 ; updown ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 0.746 ; +; 0.508 ; F_acc[25] ; F_acc[25] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 0.802 ; +; 0.735 ; F_acc[12] ; F_acc[12] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.028 ; +; 0.736 ; F_acc[14] ; F_acc[14] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.030 ; +; 0.736 ; F_acc[10] ; F_acc[10] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.029 ; +; 0.736 ; F_acc[8] ; F_acc[8] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.029 ; +; 0.736 ; F_acc[2] ; F_acc[2] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.029 ; +; 0.738 ; F_acc[15] ; F_acc[15] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.032 ; +; 0.738 ; F_acc[13] ; F_acc[13] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.032 ; +; 0.738 ; F_acc[6] ; F_acc[6] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.031 ; +; 0.738 ; F_acc[4] ; F_acc[4] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.031 ; +; 0.738 ; F_acc[3] ; F_acc[3] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.031 ; +; 0.739 ; F_acc[11] ; F_acc[11] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.032 ; +; 0.739 ; F_acc[9] ; F_acc[9] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.032 ; +; 0.739 ; F_acc[1] ; F_acc[1] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.032 ; +; 0.740 ; F_acc[7] ; F_acc[7] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.033 ; +; 0.740 ; F_acc[5] ; F_acc[5] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.033 ; +; 0.757 ; F_acc[0] ; F_acc[0] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.050 ; +; 0.761 ; F_acc[19] ; F_acc[19] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.055 ; +; 0.762 ; F_acc[17] ; F_acc[17] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.056 ; +; 0.763 ; F_acc[23] ; F_acc[23] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.057 ; +; 0.763 ; F_acc[21] ; F_acc[21] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.057 ; +; 0.763 ; F_acc[18] ; F_acc[18] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.057 ; +; 0.763 ; F_acc[16] ; F_acc[16] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.057 ; +; 0.764 ; F_acc[24] ; F_acc[24] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.058 ; +; 0.765 ; F_acc[22] ; F_acc[22] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.059 ; +; 0.765 ; F_acc[20] ; F_acc[20] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.059 ; +; 0.765 ; tri_out[5]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.059 ; +; 0.771 ; tri_out[1]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.065 ; +; 0.771 ; tri_out[4]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.065 ; +; 0.772 ; tri_out[7]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.066 ; +; 0.773 ; tri_out[3]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.067 ; +; 0.779 ; tri_out[2]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.073 ; +; 0.811 ; tri_out[0]~reg0 ; tri_out[0]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.105 ; +; 0.980 ; tri_out[6]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.274 ; +; 1.090 ; F_acc[13] ; F_acc[14] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.384 ; +; 1.090 ; F_acc[15] ; F_acc[16] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.384 ; +; 1.091 ; F_acc[11] ; F_acc[12] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.384 ; +; 1.091 ; F_acc[9] ; F_acc[10] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.384 ; +; 1.091 ; F_acc[1] ; F_acc[2] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.384 ; +; 1.091 ; F_acc[3] ; F_acc[4] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.384 ; +; 1.092 ; F_acc[7] ; F_acc[8] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.385 ; +; 1.092 ; F_acc[5] ; F_acc[6] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.385 ; +; 1.098 ; F_acc[12] ; F_acc[13] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.391 ; +; 1.099 ; F_acc[2] ; F_acc[3] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.392 ; +; 1.099 ; F_acc[14] ; F_acc[15] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.393 ; +; 1.099 ; F_acc[10] ; F_acc[11] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.392 ; +; 1.099 ; F_acc[8] ; F_acc[9] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.392 ; +; 1.099 ; F_acc[0] ; F_acc[1] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.392 ; +; 1.101 ; F_acc[6] ; F_acc[7] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.394 ; +; 1.101 ; F_acc[4] ; F_acc[5] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.394 ; +; 1.107 ; F_acc[12] ; F_acc[14] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.400 ; +; 1.108 ; F_acc[14] ; F_acc[16] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.402 ; +; 1.108 ; F_acc[10] ; F_acc[12] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.401 ; +; 1.108 ; F_acc[8] ; F_acc[10] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.401 ; +; 1.108 ; F_acc[0] ; F_acc[2] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.401 ; +; 1.108 ; F_acc[2] ; F_acc[4] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.401 ; +; 1.110 ; F_acc[6] ; F_acc[8] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.403 ; +; 1.110 ; F_acc[4] ; F_acc[6] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.403 ; +; 1.116 ; F_acc[17] ; F_acc[18] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.410 ; +; 1.116 ; F_acc[19] ; F_acc[20] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.410 ; +; 1.117 ; F_acc[23] ; F_acc[24] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.411 ; +; 1.117 ; F_acc[21] ; F_acc[22] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.411 ; +; 1.117 ; tri_out[5]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.411 ; +; 1.124 ; tri_out[7]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.418 ; +; 1.124 ; tri_out[1]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.418 ; +; 1.124 ; F_acc[18] ; F_acc[19] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.418 ; +; 1.124 ; F_acc[16] ; F_acc[17] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.418 ; +; 1.125 ; F_acc[24] ; F_acc[25] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.419 ; +; 1.125 ; tri_out[3]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.419 ; +; 1.126 ; F_acc[22] ; F_acc[23] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.420 ; +; 1.126 ; F_acc[20] ; F_acc[21] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.420 ; +; 1.132 ; tri_out[0]~reg0 ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.426 ; +; 1.133 ; F_acc[16] ; F_acc[18] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.427 ; +; 1.133 ; F_acc[18] ; F_acc[20] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.427 ; +; 1.134 ; tri_out[4]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.428 ; +; 1.135 ; F_acc[22] ; F_acc[24] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.429 ; +; 1.135 ; F_acc[20] ; F_acc[22] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.429 ; +; 1.142 ; tri_out[2]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.436 ; +; 1.143 ; tri_out[4]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.437 ; +; 1.151 ; tri_out[2]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.445 ; +; 1.155 ; tri_out[0]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.449 ; +; 1.164 ; tri_out[0]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.458 ; +; 1.168 ; tri_out[7]~reg0 ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.462 ; +; 1.172 ; tri_out[3]~reg0 ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.466 ; +; 1.198 ; tri_out[8]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.492 ; +; 1.221 ; F_acc[13] ; F_acc[15] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.515 ; +; 1.221 ; F_acc[15] ; F_acc[17] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.515 ; +; 1.222 ; F_acc[11] ; F_acc[13] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.515 ; +; 1.222 ; F_acc[1] ; F_acc[3] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.515 ; +; 1.222 ; F_acc[9] ; F_acc[11] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.515 ; +; 1.222 ; F_acc[3] ; F_acc[5] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.515 ; +; 1.223 ; F_acc[7] ; F_acc[9] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.516 ; +; 1.223 ; F_acc[5] ; F_acc[7] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.516 ; +; 1.230 ; F_acc[13] ; F_acc[16] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.524 ; +; 1.230 ; F_acc[15] ; F_acc[18] ; clk_200m ; clk_200m ; 0.000 ; 0.082 ; 1.524 ; +; 1.231 ; F_acc[11] ; F_acc[14] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.524 ; +; 1.231 ; F_acc[9] ; F_acc[12] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.524 ; +; 1.231 ; F_acc[1] ; F_acc[4] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.524 ; +; 1.231 ; F_acc[3] ; F_acc[6] ; clk_200m ; clk_200m ; 0.000 ; 0.081 ; 1.524 ; ++-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+ + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 147.62 MHz ; 147.62 MHz ; clk_200m ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++----------+--------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+----------------+ +; clk_200m ; -5.774 ; -92.754 ; ++----------+--------+----------------+ + + ++-----------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; clk_200m ; 0.400 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++----------+--------+------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+------------------------------+ +; clk_200m ; -3.201 ; -90.029 ; ++----------+--------+------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'clk_200m' ; ++--------+------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -5.774 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[4] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.070 ; 6.846 ; +; -5.653 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[0] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.070 ; 6.725 ; +; -5.611 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[3] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.070 ; 6.683 ; +; -5.447 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[7] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.070 ; 6.519 ; +; -5.365 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[1] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.070 ; 6.437 ; +; -5.287 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[2] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.070 ; 6.359 ; +; -5.222 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[5] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.070 ; 6.294 ; +; -5.097 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[6] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.070 ; 6.169 ; +; -3.294 ; tri_out[8]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 4.222 ; +; -3.255 ; tri_out[8]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 4.183 ; +; -3.226 ; tri_out[5]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 4.154 ; +; -3.187 ; tri_out[5]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 4.115 ; +; -3.168 ; tri_out[8]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 4.096 ; +; -3.129 ; tri_out[8]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 4.057 ; +; -3.100 ; tri_out[5]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 4.028 ; +; -3.087 ; F_acc[16] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.263 ; 4.389 ; +; -3.080 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[8] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.070 ; 4.152 ; +; -3.061 ; tri_out[6]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.989 ; +; -3.061 ; tri_out[5]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.989 ; +; -3.042 ; tri_out[8]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.970 ; +; -3.026 ; F_acc[17] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.263 ; 4.328 ; +; -3.022 ; tri_out[6]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.950 ; +; -3.013 ; tri_out[2]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.941 ; +; -3.013 ; F_acc[18] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.263 ; 4.315 ; +; -3.008 ; tri_out[4]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.936 ; +; -3.003 ; tri_out[8]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.931 ; +; -2.989 ; tri_out[2]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.917 ; +; -2.974 ; tri_out[5]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.902 ; +; -2.973 ; tri_out[4]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.901 ; +; -2.935 ; tri_out[6]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.863 ; +; -2.935 ; tri_out[5]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.863 ; +; -2.930 ; F_acc[19] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.263 ; 4.232 ; +; -2.896 ; tri_out[6]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.824 ; +; -2.892 ; tri_out[1]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.820 ; +; -2.887 ; tri_out[2]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.815 ; +; -2.882 ; tri_out[4]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.810 ; +; -2.870 ; updown ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.798 ; +; -2.863 ; tri_out[2]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.791 ; +; -2.853 ; tri_out[8]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.781 ; +; -2.853 ; tri_out[1]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.781 ; +; -2.847 ; tri_out[4]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.775 ; +; -2.831 ; updown ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.759 ; +; -2.825 ; F_acc[20] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.263 ; 4.127 ; +; -2.809 ; tri_out[6]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.737 ; +; -2.785 ; tri_out[5]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.713 ; +; -2.778 ; F_acc[21] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.263 ; 4.080 ; +; -2.770 ; tri_out[6]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.698 ; +; -2.766 ; tri_out[1]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.694 ; +; -2.761 ; tri_out[2]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.689 ; +; -2.756 ; tri_out[4]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.684 ; +; -2.744 ; updown ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.672 ; +; -2.737 ; tri_out[2]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.665 ; +; -2.727 ; tri_out[1]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.655 ; +; -2.721 ; tri_out[4]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.649 ; +; -2.705 ; updown ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.633 ; +; -2.704 ; F_acc[22] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.263 ; 4.006 ; +; -2.696 ; tri_out[3]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.624 ; +; -2.694 ; tri_out[7]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.622 ; +; -2.679 ; F_acc[23] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.263 ; 3.981 ; +; -2.657 ; tri_out[3]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.585 ; +; -2.655 ; tri_out[7]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.583 ; +; -2.640 ; tri_out[1]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.568 ; +; -2.631 ; tri_out[0]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.559 ; +; -2.620 ; tri_out[6]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.548 ; +; -2.618 ; updown ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.546 ; +; -2.611 ; tri_out[2]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.539 ; +; -2.601 ; tri_out[1]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.529 ; +; -2.595 ; tri_out[4]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.523 ; +; -2.592 ; tri_out[0]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.520 ; +; -2.579 ; updown ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.507 ; +; -2.578 ; F_acc[24] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.263 ; 3.880 ; +; -2.570 ; tri_out[3]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.498 ; +; -2.568 ; tri_out[7]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.496 ; +; -2.531 ; tri_out[3]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.459 ; +; -2.529 ; tri_out[7]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.457 ; +; -2.505 ; tri_out[0]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.433 ; +; -2.491 ; tri_out[8]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.419 ; +; -2.467 ; tri_out[1]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.395 ; +; -2.466 ; tri_out[0]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.394 ; +; -2.444 ; tri_out[3]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.372 ; +; -2.442 ; tri_out[7]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.370 ; +; -2.429 ; updown ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.357 ; +; -2.423 ; tri_out[5]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.351 ; +; -2.405 ; tri_out[3]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.333 ; +; -2.403 ; tri_out[7]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.331 ; +; -2.379 ; tri_out[0]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.307 ; +; -2.340 ; tri_out[0]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.268 ; +; -2.275 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[8] ; clk_200m ; clk_200m ; 1.000 ; -0.080 ; 3.119 ; +; -2.275 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[7] ; clk_200m ; clk_200m ; 1.000 ; -0.080 ; 3.119 ; +; -2.275 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[6] ; clk_200m ; clk_200m ; 1.000 ; -0.080 ; 3.119 ; +; -2.275 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[5] ; clk_200m ; clk_200m ; 1.000 ; -0.080 ; 3.119 ; +; -2.275 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[4] ; clk_200m ; clk_200m ; 1.000 ; -0.080 ; 3.119 ; +; -2.275 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[3] ; clk_200m ; clk_200m ; 1.000 ; -0.080 ; 3.119 ; +; -2.275 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[2] ; clk_200m ; clk_200m ; 1.000 ; -0.080 ; 3.119 ; +; -2.275 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[1] ; clk_200m ; clk_200m ; 1.000 ; -0.080 ; 3.119 ; +; -2.275 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[0] ; clk_200m ; clk_200m ; 1.000 ; -0.080 ; 3.119 ; +; -2.274 ; tri_out[7]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.202 ; +; -2.269 ; tri_out[3]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.197 ; +; -2.258 ; tri_out[6]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.186 ; +; -2.248 ; F_acc[0] ; F_acc[25] ; clk_200m ; clk_200m ; 1.000 ; -0.074 ; 3.176 ; ++--------+------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'clk_200m' ; ++-------+-----------------+---------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------------+---------------------------+--------------+-------------+--------------+------------+------------+ +; 0.400 ; updown ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.669 ; +; 0.469 ; F_acc[25] ; F_acc[25] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.737 ; +; 0.681 ; F_acc[12] ; F_acc[12] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.950 ; +; 0.682 ; F_acc[10] ; F_acc[10] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.951 ; +; 0.682 ; F_acc[2] ; F_acc[2] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.951 ; +; 0.683 ; F_acc[8] ; F_acc[8] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.952 ; +; 0.685 ; F_acc[14] ; F_acc[14] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.953 ; +; 0.685 ; F_acc[6] ; F_acc[6] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.954 ; +; 0.685 ; F_acc[4] ; F_acc[4] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.954 ; +; 0.685 ; F_acc[3] ; F_acc[3] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.954 ; +; 0.687 ; F_acc[11] ; F_acc[11] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.956 ; +; 0.688 ; F_acc[13] ; F_acc[13] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.956 ; +; 0.688 ; F_acc[9] ; F_acc[9] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.957 ; +; 0.688 ; F_acc[7] ; F_acc[7] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.957 ; +; 0.688 ; F_acc[1] ; F_acc[1] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.957 ; +; 0.689 ; F_acc[15] ; F_acc[15] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.957 ; +; 0.689 ; F_acc[5] ; F_acc[5] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.958 ; +; 0.706 ; F_acc[19] ; F_acc[19] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.974 ; +; 0.707 ; F_acc[18] ; F_acc[18] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.975 ; +; 0.707 ; F_acc[16] ; F_acc[16] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.975 ; +; 0.707 ; F_acc[0] ; F_acc[0] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.976 ; +; 0.708 ; F_acc[24] ; F_acc[24] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.976 ; +; 0.708 ; F_acc[17] ; F_acc[17] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.976 ; +; 0.709 ; F_acc[23] ; F_acc[23] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.977 ; +; 0.709 ; F_acc[21] ; F_acc[21] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.977 ; +; 0.711 ; tri_out[5]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.980 ; +; 0.712 ; F_acc[22] ; F_acc[22] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.980 ; +; 0.712 ; F_acc[20] ; F_acc[20] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 0.980 ; +; 0.715 ; tri_out[1]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.984 ; +; 0.716 ; tri_out[7]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.985 ; +; 0.716 ; tri_out[4]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.985 ; +; 0.718 ; tri_out[3]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.987 ; +; 0.724 ; tri_out[2]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 0.993 ; +; 0.756 ; tri_out[0]~reg0 ; tri_out[0]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.025 ; +; 0.896 ; tri_out[6]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.165 ; +; 1.003 ; F_acc[2] ; F_acc[3] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.272 ; +; 1.003 ; F_acc[10] ; F_acc[11] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.272 ; +; 1.003 ; F_acc[12] ; F_acc[13] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.271 ; +; 1.003 ; F_acc[0] ; F_acc[1] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.272 ; +; 1.004 ; F_acc[8] ; F_acc[9] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.273 ; +; 1.005 ; F_acc[3] ; F_acc[4] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.274 ; +; 1.005 ; F_acc[6] ; F_acc[7] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.274 ; +; 1.005 ; F_acc[14] ; F_acc[15] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.273 ; +; 1.006 ; F_acc[4] ; F_acc[5] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.275 ; +; 1.008 ; F_acc[11] ; F_acc[12] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.277 ; +; 1.009 ; tri_out[0]~reg0 ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.278 ; +; 1.009 ; F_acc[9] ; F_acc[10] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.278 ; +; 1.009 ; F_acc[1] ; F_acc[2] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.278 ; +; 1.009 ; F_acc[7] ; F_acc[8] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.278 ; +; 1.009 ; F_acc[13] ; F_acc[14] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.277 ; +; 1.010 ; F_acc[5] ; F_acc[6] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.279 ; +; 1.010 ; F_acc[15] ; F_acc[16] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.278 ; +; 1.018 ; F_acc[2] ; F_acc[4] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.287 ; +; 1.018 ; F_acc[10] ; F_acc[12] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.287 ; +; 1.018 ; F_acc[0] ; F_acc[2] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.287 ; +; 1.018 ; F_acc[12] ; F_acc[14] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.286 ; +; 1.019 ; F_acc[8] ; F_acc[10] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.288 ; +; 1.022 ; F_acc[6] ; F_acc[8] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.291 ; +; 1.022 ; F_acc[4] ; F_acc[6] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.291 ; +; 1.022 ; F_acc[14] ; F_acc[16] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.290 ; +; 1.026 ; F_acc[18] ; F_acc[19] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.294 ; +; 1.026 ; F_acc[16] ; F_acc[17] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.294 ; +; 1.027 ; F_acc[24] ; F_acc[25] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.295 ; +; 1.028 ; F_acc[19] ; F_acc[20] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.296 ; +; 1.030 ; F_acc[22] ; F_acc[23] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.298 ; +; 1.030 ; F_acc[20] ; F_acc[21] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.298 ; +; 1.032 ; F_acc[17] ; F_acc[18] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.300 ; +; 1.032 ; tri_out[5]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.301 ; +; 1.033 ; F_acc[23] ; F_acc[24] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.301 ; +; 1.033 ; F_acc[21] ; F_acc[22] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.301 ; +; 1.035 ; tri_out[1]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.304 ; +; 1.037 ; tri_out[7]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.306 ; +; 1.038 ; tri_out[4]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.307 ; +; 1.039 ; tri_out[3]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.308 ; +; 1.041 ; F_acc[18] ; F_acc[20] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.309 ; +; 1.041 ; F_acc[16] ; F_acc[18] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.309 ; +; 1.046 ; tri_out[2]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.315 ; +; 1.046 ; F_acc[22] ; F_acc[24] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.314 ; +; 1.046 ; F_acc[20] ; F_acc[22] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.314 ; +; 1.053 ; tri_out[4]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.322 ; +; 1.054 ; tri_out[0]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.323 ; +; 1.060 ; tri_out[8]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.329 ; +; 1.061 ; tri_out[2]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.330 ; +; 1.069 ; tri_out[0]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.338 ; +; 1.093 ; tri_out[7]~reg0 ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.362 ; +; 1.097 ; tri_out[3]~reg0 ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.366 ; +; 1.097 ; F_acc[3] ; F_acc[5] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.366 ; +; 1.102 ; tri_out[8]~reg0 ; modulation:modulation|out ; clk_200m ; clk_200m ; 0.000 ; 0.533 ; 1.830 ; +; 1.103 ; F_acc[13] ; F_acc[15] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.371 ; +; 1.103 ; F_acc[9] ; F_acc[11] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.372 ; +; 1.103 ; F_acc[1] ; F_acc[3] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.372 ; +; 1.103 ; F_acc[11] ; F_acc[13] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.371 ; +; 1.103 ; F_acc[7] ; F_acc[9] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.372 ; +; 1.104 ; F_acc[5] ; F_acc[7] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.373 ; +; 1.104 ; F_acc[15] ; F_acc[17] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.372 ; +; 1.121 ; F_acc[19] ; F_acc[21] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.389 ; +; 1.125 ; F_acc[2] ; F_acc[5] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.394 ; +; 1.125 ; F_acc[0] ; F_acc[3] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.394 ; +; 1.125 ; F_acc[12] ; F_acc[15] ; clk_200m ; clk_200m ; 0.000 ; 0.073 ; 1.393 ; +; 1.126 ; F_acc[8] ; F_acc[11] ; clk_200m ; clk_200m ; 0.000 ; 0.074 ; 1.395 ; ++-------+-----------------+---------------------------+--------------+-------------+--------------+------------+------------+ + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++----------+--------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+----------------+ +; clk_200m ; -2.286 ; -19.805 ; ++----------+--------+----------------+ + + ++-----------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++----------+-------+----------------+ +; Clock ; Slack ; End Point TNS ; ++----------+-------+----------------+ +; clk_200m ; 0.186 ; 0.000 ; ++----------+-------+----------------+ + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++--------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++----------+--------+------------------------------+ +; Clock ; Slack ; End Point TNS ; ++----------+--------+------------------------------+ +; clk_200m ; -3.000 ; -53.627 ; ++----------+--------+------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'clk_200m' ; ++--------+-----------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -2.286 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[4] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; -0.008 ; 3.265 ; +; -2.107 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[7] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; -0.008 ; 3.086 ; +; -2.104 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[3] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; -0.008 ; 3.083 ; +; -2.060 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[0] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; -0.008 ; 3.039 ; +; -1.968 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[2] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; -0.008 ; 2.947 ; +; -1.935 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[1] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; -0.008 ; 2.914 ; +; -1.884 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[5] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; -0.008 ; 2.863 ; +; -1.826 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[6] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; -0.008 ; 2.805 ; +; -1.071 ; tri_out[8]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 2.021 ; +; -1.051 ; tri_out[5]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 2.001 ; +; -1.007 ; tri_out[8]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.957 ; +; -1.003 ; tri_out[8]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.953 ; +; -0.987 ; tri_out[5]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.937 ; +; -0.983 ; tri_out[5]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.933 ; +; -0.975 ; tri_out[2]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.925 ; +; -0.966 ; tri_out[4]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.916 ; +; -0.961 ; F_acc[17] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.127 ; 2.097 ; +; -0.946 ; F_acc[16] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.127 ; 2.082 ; +; -0.939 ; tri_out[8]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.889 ; +; -0.935 ; tri_out[8]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.885 ; +; -0.935 ; tri_out[6]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.885 ; +; -0.920 ; tri_out[1]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.870 ; +; -0.919 ; tri_out[5]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.869 ; +; -0.915 ; tri_out[5]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.865 ; +; -0.911 ; tri_out[2]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.861 ; +; -0.909 ; F_acc[19] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.127 ; 2.045 ; +; -0.907 ; tri_out[2]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.857 ; +; -0.902 ; tri_out[4]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.852 ; +; -0.898 ; tri_out[4]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.848 ; +; -0.897 ; updown ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.847 ; +; -0.895 ; F_acc[18] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.127 ; 2.031 ; +; -0.880 ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|q_a[8] ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; -0.008 ; 1.859 ; +; -0.871 ; tri_out[8]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.821 ; +; -0.871 ; tri_out[6]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.821 ; +; -0.867 ; tri_out[8]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.817 ; +; -0.867 ; tri_out[6]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.817 ; +; -0.856 ; tri_out[1]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.806 ; +; -0.852 ; tri_out[1]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.802 ; +; -0.851 ; tri_out[5]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.801 ; +; -0.847 ; tri_out[5]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.797 ; +; -0.843 ; tri_out[2]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.793 ; +; -0.839 ; tri_out[2]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.789 ; +; -0.834 ; tri_out[4]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.784 ; +; -0.833 ; updown ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.783 ; +; -0.830 ; tri_out[4]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.780 ; +; -0.829 ; updown ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.779 ; +; -0.827 ; F_acc[21] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.127 ; 1.963 ; +; -0.817 ; tri_out[7]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.767 ; +; -0.812 ; tri_out[3]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.762 ; +; -0.811 ; F_acc[20] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.127 ; 1.947 ; +; -0.803 ; tri_out[6]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.753 ; +; -0.799 ; tri_out[6]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.749 ; +; -0.788 ; tri_out[1]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.738 ; +; -0.784 ; tri_out[1]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.734 ; +; -0.776 ; F_acc[23] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.127 ; 1.912 ; +; -0.775 ; tri_out[2]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.725 ; +; -0.771 ; tri_out[2]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.721 ; +; -0.766 ; tri_out[4]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.716 ; +; -0.765 ; updown ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.715 ; +; -0.763 ; tri_out[0]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.713 ; +; -0.762 ; tri_out[4]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.712 ; +; -0.761 ; updown ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.711 ; +; -0.753 ; tri_out[7]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.703 ; +; -0.749 ; tri_out[7]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.699 ; +; -0.748 ; tri_out[3]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.698 ; +; -0.744 ; tri_out[3]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.694 ; +; -0.742 ; F_acc[22] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.127 ; 1.878 ; +; -0.735 ; tri_out[6]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.685 ; +; -0.731 ; tri_out[6]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.681 ; +; -0.720 ; tri_out[1]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.670 ; +; -0.716 ; tri_out[1]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.666 ; +; -0.699 ; tri_out[0]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.649 ; +; -0.697 ; updown ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.647 ; +; -0.695 ; tri_out[0]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.645 ; +; -0.693 ; updown ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.643 ; +; -0.685 ; tri_out[7]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.635 ; +; -0.681 ; tri_out[7]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.631 ; +; -0.680 ; tri_out[3]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.630 ; +; -0.676 ; tri_out[3]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.626 ; +; -0.673 ; F_acc[24] ; spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ram_block1a0~porta_address_reg0 ; clk_200m ; clk_200m ; 1.000 ; 0.127 ; 1.809 ; +; -0.631 ; tri_out[0]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.581 ; +; -0.627 ; tri_out[0]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.577 ; +; -0.626 ; F_acc[1] ; F_acc[25] ; clk_200m ; clk_200m ; 1.000 ; -0.038 ; 1.575 ; +; -0.622 ; F_acc[1] ; F_acc[24] ; clk_200m ; clk_200m ; 1.000 ; -0.038 ; 1.571 ; +; -0.617 ; tri_out[7]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.567 ; +; -0.613 ; tri_out[7]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.563 ; +; -0.612 ; tri_out[3]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.562 ; +; -0.612 ; F_acc[0] ; F_acc[25] ; clk_200m ; clk_200m ; 1.000 ; -0.038 ; 1.561 ; +; -0.608 ; tri_out[3]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.558 ; +; -0.588 ; tri_out[1]~reg0 ; modulation:modulation|out ; clk_200m ; clk_200m ; 1.000 ; 0.151 ; 1.726 ; +; -0.582 ; tri_out[8]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.532 ; +; -0.574 ; F_acc[0] ; F_acc[24] ; clk_200m ; clk_200m ; 1.000 ; -0.038 ; 1.523 ; +; -0.563 ; tri_out[0]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.513 ; +; -0.562 ; tri_out[5]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.512 ; +; -0.559 ; tri_out[0]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 1.000 ; -0.037 ; 1.509 ; +; -0.558 ; F_acc[1] ; F_acc[23] ; clk_200m ; clk_200m ; 1.000 ; -0.038 ; 1.507 ; +; -0.554 ; F_acc[1] ; F_acc[22] ; clk_200m ; clk_200m ; 1.000 ; -0.038 ; 1.503 ; +; -0.554 ; F_acc[3] ; F_acc[25] ; clk_200m ; clk_200m ; 1.000 ; -0.038 ; 1.503 ; +; -0.550 ; F_acc[3] ; F_acc[24] ; clk_200m ; clk_200m ; 1.000 ; -0.038 ; 1.499 ; +; -0.544 ; F_acc[2] ; F_acc[25] ; clk_200m ; clk_200m ; 1.000 ; -0.038 ; 1.493 ; ++--------+-----------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'clk_200m' ; ++-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+ +; 0.186 ; updown ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.307 ; +; 0.204 ; F_acc[25] ; F_acc[25] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.325 ; +; 0.291 ; F_acc[12] ; F_acc[12] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.412 ; +; 0.292 ; F_acc[10] ; F_acc[10] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.413 ; +; 0.292 ; F_acc[8] ; F_acc[8] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.413 ; +; 0.292 ; F_acc[2] ; F_acc[2] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.413 ; +; 0.293 ; F_acc[14] ; F_acc[14] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.414 ; +; 0.293 ; F_acc[6] ; F_acc[6] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.414 ; +; 0.293 ; F_acc[4] ; F_acc[4] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.414 ; +; 0.293 ; F_acc[3] ; F_acc[3] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.414 ; +; 0.294 ; F_acc[15] ; F_acc[15] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.415 ; +; 0.294 ; F_acc[13] ; F_acc[13] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.415 ; +; 0.294 ; F_acc[11] ; F_acc[11] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.415 ; +; 0.294 ; F_acc[5] ; F_acc[5] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.415 ; +; 0.294 ; F_acc[1] ; F_acc[1] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.415 ; +; 0.295 ; F_acc[9] ; F_acc[9] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.416 ; +; 0.295 ; F_acc[7] ; F_acc[7] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.416 ; +; 0.299 ; F_acc[0] ; F_acc[0] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.420 ; +; 0.304 ; F_acc[19] ; F_acc[19] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.425 ; +; 0.305 ; F_acc[24] ; F_acc[24] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.426 ; +; 0.305 ; F_acc[21] ; F_acc[21] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.426 ; +; 0.305 ; F_acc[18] ; F_acc[18] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.426 ; +; 0.305 ; F_acc[17] ; F_acc[17] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.426 ; +; 0.305 ; F_acc[16] ; F_acc[16] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.426 ; +; 0.306 ; F_acc[23] ; F_acc[23] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.427 ; +; 0.306 ; F_acc[20] ; F_acc[20] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.427 ; +; 0.307 ; F_acc[22] ; F_acc[22] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.428 ; +; 0.307 ; tri_out[5]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.428 ; +; 0.310 ; tri_out[1]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.431 ; +; 0.310 ; tri_out[7]~reg0 ; tri_out[7]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.431 ; +; 0.310 ; tri_out[4]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.431 ; +; 0.310 ; tri_out[3]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.431 ; +; 0.314 ; tri_out[2]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.435 ; +; 0.329 ; tri_out[0]~reg0 ; tri_out[0]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.450 ; +; 0.386 ; tri_out[6]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.507 ; +; 0.441 ; F_acc[3] ; F_acc[4] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.562 ; +; 0.442 ; F_acc[11] ; F_acc[12] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.563 ; +; 0.442 ; F_acc[1] ; F_acc[2] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.563 ; +; 0.442 ; F_acc[13] ; F_acc[14] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.563 ; +; 0.442 ; F_acc[5] ; F_acc[6] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.563 ; +; 0.442 ; F_acc[15] ; F_acc[16] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.563 ; +; 0.443 ; tri_out[0]~reg0 ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.564 ; +; 0.443 ; F_acc[9] ; F_acc[10] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.564 ; +; 0.443 ; F_acc[7] ; F_acc[8] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.564 ; +; 0.451 ; F_acc[2] ; F_acc[3] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.572 ; +; 0.451 ; F_acc[12] ; F_acc[13] ; clk_200m ; clk_200m ; 0.000 ; 0.036 ; 0.571 ; +; 0.451 ; F_acc[10] ; F_acc[11] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.572 ; +; 0.451 ; F_acc[0] ; F_acc[1] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.572 ; +; 0.451 ; F_acc[8] ; F_acc[9] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.572 ; +; 0.452 ; F_acc[14] ; F_acc[15] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.573 ; +; 0.452 ; F_acc[4] ; F_acc[5] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.573 ; +; 0.452 ; F_acc[6] ; F_acc[7] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.573 ; +; 0.453 ; F_acc[19] ; F_acc[20] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.574 ; +; 0.454 ; F_acc[17] ; F_acc[18] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.575 ; +; 0.454 ; F_acc[21] ; F_acc[22] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.575 ; +; 0.454 ; F_acc[2] ; F_acc[4] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.575 ; +; 0.454 ; F_acc[10] ; F_acc[12] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.575 ; +; 0.454 ; F_acc[0] ; F_acc[2] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.575 ; +; 0.454 ; F_acc[12] ; F_acc[14] ; clk_200m ; clk_200m ; 0.000 ; 0.036 ; 0.574 ; +; 0.454 ; F_acc[8] ; F_acc[10] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.575 ; +; 0.455 ; F_acc[23] ; F_acc[24] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.576 ; +; 0.455 ; tri_out[5]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.576 ; +; 0.455 ; F_acc[4] ; F_acc[6] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.576 ; +; 0.455 ; F_acc[14] ; F_acc[16] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.576 ; +; 0.455 ; F_acc[6] ; F_acc[8] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.576 ; +; 0.458 ; tri_out[7]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.579 ; +; 0.458 ; tri_out[3]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.579 ; +; 0.458 ; tri_out[1]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.579 ; +; 0.463 ; F_acc[24] ; F_acc[25] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.584 ; +; 0.463 ; F_acc[18] ; F_acc[19] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.584 ; +; 0.463 ; F_acc[16] ; F_acc[17] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.584 ; +; 0.464 ; tri_out[7]~reg0 ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.585 ; +; 0.464 ; F_acc[20] ; F_acc[21] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.585 ; +; 0.464 ; tri_out[8]~reg0 ; tri_out[8]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.585 ; +; 0.465 ; F_acc[22] ; F_acc[23] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.586 ; +; 0.466 ; tri_out[3]~reg0 ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.587 ; +; 0.466 ; F_acc[18] ; F_acc[20] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.587 ; +; 0.466 ; F_acc[16] ; F_acc[18] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.587 ; +; 0.467 ; F_acc[20] ; F_acc[22] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.588 ; +; 0.468 ; F_acc[22] ; F_acc[24] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.589 ; +; 0.469 ; tri_out[4]~reg0 ; tri_out[5]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.590 ; +; 0.472 ; tri_out[4]~reg0 ; tri_out[6]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.593 ; +; 0.473 ; tri_out[2]~reg0 ; tri_out[3]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.594 ; +; 0.476 ; tri_out[2]~reg0 ; tri_out[4]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.597 ; +; 0.478 ; tri_out[0]~reg0 ; tri_out[1]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.599 ; +; 0.481 ; tri_out[0]~reg0 ; tri_out[2]~reg0 ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.602 ; +; 0.488 ; tri_out[6]~reg0 ; updown ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.609 ; +; 0.504 ; F_acc[3] ; F_acc[5] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.625 ; +; 0.505 ; F_acc[1] ; F_acc[3] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.626 ; +; 0.505 ; F_acc[13] ; F_acc[15] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.626 ; +; 0.505 ; F_acc[5] ; F_acc[7] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.626 ; +; 0.505 ; F_acc[15] ; F_acc[17] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.626 ; +; 0.506 ; F_acc[11] ; F_acc[13] ; clk_200m ; clk_200m ; 0.000 ; 0.036 ; 0.626 ; +; 0.506 ; F_acc[9] ; F_acc[11] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.627 ; +; 0.506 ; F_acc[7] ; F_acc[9] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.627 ; +; 0.507 ; F_acc[3] ; F_acc[6] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.628 ; +; 0.508 ; F_acc[1] ; F_acc[4] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.629 ; +; 0.508 ; F_acc[13] ; F_acc[16] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.629 ; +; 0.508 ; F_acc[5] ; F_acc[8] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.629 ; +; 0.508 ; F_acc[15] ; F_acc[18] ; clk_200m ; clk_200m ; 0.000 ; 0.037 ; 0.629 ; ++-------+-----------------+-----------------+--------------+-------------+--------------+------------+------------+ + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++--------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+----------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+----------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -6.406 ; 0.186 ; N/A ; N/A ; -3.201 ; +; clk_200m ; -6.406 ; 0.186 ; N/A ; N/A ; -3.201 ; +; Design-wide TNS ; -106.964 ; 0.0 ; 0.0 ; 0.0 ; -90.029 ; +; clk_200m ; -106.964 ; 0.000 ; N/A ; N/A ; -90.029 ; ++------------------+----------+-------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; tri_out[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tri_out[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tri_out[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tri_out[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tri_out[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tri_out[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tri_out[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tri_out[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tri_out[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sin_out[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sin_out[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sin_out[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sin_out[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sin_out[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sin_out[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sin_out[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sin_out[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sin_out[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; spwm_out ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; clk_200m ; 2.5 V ; 2000 ps ; 2000 ps ; +; rst_n ; 2.5 V ; 2000 ps ; 2000 ps ; +; Pword[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Pword[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Pword[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Pword[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Pword[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Pword[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Pword[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Pword[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Pword[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Pword[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[15] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[14] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; Fword[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; tri_out[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tri_out[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tri_out[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tri_out[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tri_out[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tri_out[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tri_out[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tri_out[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tri_out[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; sin_out[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; sin_out[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.38 V ; -0.0073 V ; 0.097 V ; 0.018 V ; 4.24e-10 s ; 3.65e-10 s ; No ; Yes ; 2.32 V ; 2.07e-09 V ; 2.38 V ; -0.0073 V ; 0.097 V ; 0.018 V ; 4.24e-10 s ; 3.65e-10 s ; No ; Yes ; +; sin_out[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; sin_out[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; sin_out[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; sin_out[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; sin_out[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; sin_out[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; sin_out[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; spwm_out ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; tri_out[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tri_out[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tri_out[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tri_out[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tri_out[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tri_out[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tri_out[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tri_out[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tri_out[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; sin_out[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; sin_out[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.35 V ; -0.00834 V ; 0.127 V ; 0.035 V ; 4.7e-10 s ; 4.64e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.35 V ; -0.00834 V ; 0.127 V ; 0.035 V ; 4.7e-10 s ; 4.64e-10 s ; Yes ; Yes ; +; sin_out[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; sin_out[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; sin_out[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; sin_out[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; sin_out[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; sin_out[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; sin_out[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; spwm_out ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; tri_out[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tri_out[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tri_out[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tri_out[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tri_out[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tri_out[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tri_out[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tri_out[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tri_out[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; sin_out[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; sin_out[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; sin_out[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; sin_out[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; sin_out[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; sin_out[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; sin_out[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; sin_out[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; sin_out[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; spwm_out ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk_200m ; clk_200m ; 2026 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk_200m ; clk_200m ; 2026 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 27 ; 27 ; +; Unconstrained Input Port Paths ; 342 ; 342 ; +; Unconstrained Output Ports ; 19 ; 19 ; +; Unconstrained Output Port Paths ; 19 ; 19 ; ++---------------------------------+-------+------+ + + ++------------------------------------------+ +; Clock Status Summary ; ++----------+----------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++----------+----------+------+-------------+ +; clk_200m ; clk_200m ; Base ; Constrained ; ++----------+----------+------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; Fword[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; sin_out[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; spwm_out ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; Fword[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Fword[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Pword[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; sin_out[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sin_out[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; spwm_out ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tri_out[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + Info: Processing started: Mon Dec 10 20:55:26 2018 +Info: Command: quartus_sta spwm -c spwm +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'spwm.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name clk_200m clk_200m +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -6.406 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -6.406 -106.964 clk_200m +Info (332146): Worst-case hold slack is 0.452 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.452 0.000 clk_200m +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -3.201 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -3.201 -90.029 clk_200m +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -5.774 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -5.774 -92.754 clk_200m +Info (332146): Worst-case hold slack is 0.400 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.400 0.000 clk_200m +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -3.201 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -3.201 -90.029 clk_200m +Info: Analyzing Fast 1200mV 0C Model +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Critical Warning (332148): Timing requirements not met + Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. +Info (332146): Worst-case setup slack is -2.286 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -2.286 -19.805 clk_200m +Info (332146): Worst-case hold slack is 0.186 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.186 0.000 clk_200m +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -3.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -3.000 -53.627 clk_200m +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 4777 megabytes + Info: Processing ended: Mon Dec 10 20:55:29 2018 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/spwm/output_files/spwm.sta.summary b/spwm/output_files/spwm.sta.summary new file mode 100644 index 0000000..f268385 --- /dev/null +++ b/spwm/output_files/spwm.sta.summary @@ -0,0 +1,41 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1200mV 85C Model Setup 'clk_200m' +Slack : -6.406 +TNS : -106.964 + +Type : Slow 1200mV 85C Model Hold 'clk_200m' +Slack : 0.452 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk_200m' +Slack : -3.201 +TNS : -90.029 + +Type : Slow 1200mV 0C Model Setup 'clk_200m' +Slack : -5.774 +TNS : -92.754 + +Type : Slow 1200mV 0C Model Hold 'clk_200m' +Slack : 0.400 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk_200m' +Slack : -3.201 +TNS : -90.029 + +Type : Fast 1200mV 0C Model Setup 'clk_200m' +Slack : -2.286 +TNS : -19.805 + +Type : Fast 1200mV 0C Model Hold 'clk_200m' +Slack : 0.186 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk_200m' +Slack : -3.000 +TNS : -53.627 + +------------------------------------------------------------ diff --git a/spwm/rtl/modulation.v b/spwm/rtl/modulation.v new file mode 100644 index 0000000..c3fec3c --- /dev/null +++ b/spwm/rtl/modulation.v @@ -0,0 +1,40 @@ +module modulation( + + clk_200m, + tri_out, + sin_out, + depth, + out +); + + input clk_200m; + input [9:0] tri_out; + input [8:0] sin_out; + input [7:0] depth;//调制深度 + output reg out; + + reg [16:0] triangle; + reg [16:0] sin; + + always @ (*) + begin + triangle = tri_out << 4'd7; + sin = sin_out*depth; + end + + always @ (posedge clk_200m ) + begin + if( sin > triangle) + out <= 1'b1; + else + out <= 1'b0; + end + + + + + + + +endmodule + diff --git a/spwm/rtl/modulation.v.bak b/spwm/rtl/modulation.v.bak new file mode 100644 index 0000000..b238451 --- /dev/null +++ b/spwm/rtl/modulation.v.bak @@ -0,0 +1,16 @@ +module modulation( + + input clk_200m; + input rst_n; + + +); + + + + + + + +endmodule + diff --git a/spwm/rtl/spwm.v b/spwm/rtl/spwm.v new file mode 100644 index 0000000..b1cf0f5 --- /dev/null +++ b/spwm/rtl/spwm.v @@ -0,0 +1,82 @@ +module spwm( + clk_200m, + rst_n, + tri_out, + sin_out, + Fword, + Pword, + depth, + spwm_out +); + input clk_200m; + input rst_n; + + input [15:0] Fword; + input [9:0] Pword; + input [7:0] depth; + + output reg [9:0] tri_out; + output [8:0] sin_out; + output spwm_out; + + reg updown; + + + reg [25:0] F_acc; + + + + wire [9:0] rom_address; + + assign rom_address = F_acc[25:16] + Pword; + + always @ (posedge clk_200m or negedge rst_n) + if(!rst_n) + F_acc <= 26'd0; + else + F_acc <= F_acc + Fword; + + always @ (posedge clk_200m or negedge rst_n) + if(!rst_n) + begin + tri_out <= 1'b0; + updown <= 1'b0; + end + else if(updown) + begin + if(tri_out == 1'b0) + begin + updown <= 1'b0; + tri_out <= tri_out + 1'd1; + end + else + tri_out <= tri_out - 1'd1; + end + else + begin + if(tri_out == 10'h3ff)//具体大小视最高频率定 + begin + updown <= 1'b1; + tri_out <= tri_out - 1'd1; + end + else + tri_out <= tri_out + 1'd1; + end + + + spwm_sin spwm_sin( + .address(rom_address), + .clock(clk_200m), + .q(sin_out) + ); + + modulation modulation( + .clk_200m(clk_200m), + .tri_out(tri_out), + .sin_out(sin_out), + .depth(depth), + .out(spwm_out) + ); + +endmodule + diff --git a/spwm/rtl/spwm.v.bak b/spwm/rtl/spwm.v.bak new file mode 100644 index 0000000..ce7c173 --- /dev/null +++ b/spwm/rtl/spwm.v.bak @@ -0,0 +1,6 @@ +module spwm( + + clk, + rst_n, + +) \ No newline at end of file diff --git a/spwm/simulation/modelsim/gate_work/_info b/spwm/simulation/modelsim/gate_work/_info new file mode 100644 index 0000000..ae611d5 --- /dev/null +++ b/spwm/simulation/modelsim/gate_work/_info @@ -0,0 +1,76 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dF:/Code/FPGA/reserve/spwm/simulation/modelsim +vhard_block +Z1 !s110 1544446556 +!i10b 1 +!s100 el3>jTN@1Am30h9T0 +IORAFj@DcZVm6Y4Y>l5PO;2 +Z2 VDg1SIo80bB@j0V0VzS_@n1 +R0 +Z3 w1544446531 +Z4 8spwm_8_1200mv_85c_slow.vo +Z5 Fspwm_8_1200mv_85c_slow.vo +L0 3365 +Z6 OV;L;10.5b;63 +r1 +!s85 0 +31 +Z7 !s108 1544446555.000000 +Z8 !s107 spwm_8_1200mv_85c_slow.vo| +Z9 !s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+.|spwm_8_1200mv_85c_slow.vo| +!i113 1 +Z10 o-vlog01compat -work work +Z11 !s92 -vlog01compat -work work +incdir+. +Z12 tCvgOpt 0 +vspwm +R1 +!i10b 1 +!s100 NULg@mohc[^9L51TBFO@92 +IQQ5h0jc]j;RiAjg<3 +R2 +R0 +w1544446409 +8F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v +FF:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v +L0 5 +R6 +r1 +!s85 0 +31 +!s108 1544446556.000000 +!s107 F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+F:/Code/FPGA/reserve/spwm/testbench|F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v| +!i113 1 +R10 +!s92 -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/testbench +R12 diff --git a/spwm/simulation/modelsim/gate_work/_lib.qdb b/spwm/simulation/modelsim/gate_work/_lib.qdb new file mode 100644 index 0000000..45e75e8 Binary files /dev/null and b/spwm/simulation/modelsim/gate_work/_lib.qdb differ diff --git a/spwm/simulation/modelsim/gate_work/_lib1_0.qdb b/spwm/simulation/modelsim/gate_work/_lib1_0.qdb new file mode 100644 index 0000000..63fd387 Binary files /dev/null and b/spwm/simulation/modelsim/gate_work/_lib1_0.qdb differ diff --git a/spwm/simulation/modelsim/gate_work/_lib1_0.qpg b/spwm/simulation/modelsim/gate_work/_lib1_0.qpg new file mode 100644 index 0000000..7d93e71 Binary files /dev/null and b/spwm/simulation/modelsim/gate_work/_lib1_0.qpg differ diff --git a/spwm/simulation/modelsim/gate_work/_lib1_0.qtl b/spwm/simulation/modelsim/gate_work/_lib1_0.qtl new file mode 100644 index 0000000..d09ab11 Binary files /dev/null and b/spwm/simulation/modelsim/gate_work/_lib1_0.qtl differ diff --git a/spwm/simulation/modelsim/gate_work/_vmake b/spwm/simulation/modelsim/gate_work/_vmake new file mode 100644 index 0000000..37aa36a --- /dev/null +++ b/spwm/simulation/modelsim/gate_work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/spwm/simulation/modelsim/modelsim.ini b/spwm/simulation/modelsim/modelsim.ini new file mode 100644 index 0000000..29480d4 --- /dev/null +++ b/spwm/simulation/modelsim/modelsim.ini @@ -0,0 +1,324 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +work = rtl_work +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/spwm/simulation/modelsim/msim_transcript b/spwm/simulation/modelsim/msim_transcript new file mode 100644 index 0000000..8ee773d --- /dev/null +++ b/spwm/simulation/modelsim/msim_transcript @@ -0,0 +1,190 @@ +# Reading D:/intelFPGA/modelsim_ase/tcl/vsim/pref.tcl +# do spwm_run_msim_rtl_verilog.do +# if {[file exists rtl_work]} { +# vdel -lib rtl_work -all +# } +# vlib rtl_work +# vmap work rtl_work +# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 +# vmap work rtl_work +# Copying D:/intelFPGA/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini +# Modifying modelsim.ini +# +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl {F:/Code/FPGA/reserve/spwm/rtl/spwm.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 14:58:50 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm/rtl" F:/Code/FPGA/reserve/spwm/rtl/spwm.v +# -- Compiling module spwm +# +# Top level modules: +# spwm +# End time: 14:58:50 on Dec 11,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm {F:/Code/FPGA/reserve/spwm/spwm_sin.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 14:58:50 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm" F:/Code/FPGA/reserve/spwm/spwm_sin.v +# -- Compiling module spwm_sin +# +# Top level modules: +# spwm_sin +# End time: 14:58:50 on Dec 11,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl {F:/Code/FPGA/reserve/spwm/rtl/modulation.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 14:58:50 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm/rtl" F:/Code/FPGA/reserve/spwm/rtl/modulation.v +# -- Compiling module modulation +# +# Top level modules: +# modulation +# End time: 14:58:51 on Dec 11,2018, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/testbench {F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 14:58:51 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm/testbench" F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v +# -- Compiling module spwm_tb +# +# Top level modules: +# spwm_tb +# End time: 14:58:51 on Dec 11,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# +# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" spwm_tb +# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=""+acc"" spwm_tb +# Start time: 14:58:51 on Dec 11,2018 +# Loading work.spwm_tb +# Loading work.spwm +# Loading work.spwm_sin +# Loading altera_mf_ver.altsyncram +# Loading work.modulation +# Loading altera_mf_ver.altsyncram_body +# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES +# Loading altera_mf_ver.ALTERA_MF_MEMORY_INITIALIZATION +# +# add wave * +# view structure +# .main_pane.structure.interior.cs.body.struct +# view signals +# .main_pane.objects.interior.cs.body.tree +# run -all +# ** Note: $stop : F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v(66) +# Time: 40000100 ns Iteration: 0 Instance: /spwm_tb +# Break in Module spwm_tb at F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v line 66 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl F:/Code/FPGA/reserve/spwm/rtl/modulation.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 15:13:21 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm/rtl" F:/Code/FPGA/reserve/spwm/rtl/modulation.v +# -- Compiling module modulation +# +# Top level modules: +# modulation +# End time: 15:13:21 on Dec 11,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl F:/Code/FPGA/reserve/spwm/rtl/spwm.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 15:13:21 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm/rtl" F:/Code/FPGA/reserve/spwm/rtl/spwm.v +# -- Compiling module spwm +# +# Top level modules: +# spwm +# End time: 15:13:21 on Dec 11,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm F:/Code/FPGA/reserve/spwm/spwm_sin.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 15:13:22 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm" F:/Code/FPGA/reserve/spwm/spwm_sin.v +# -- Compiling module spwm_sin +# +# Top level modules: +# spwm_sin +# End time: 15:13:22 on Dec 11,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/testbench F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 15:13:23 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm/testbench" F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v +# -- Compiling module spwm_tb +# +# Top level modules: +# spwm_tb +# End time: 15:13:23 on Dec 11,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +restart +# Loading work.spwm_tb +# Loading work.spwm +# Loading work.spwm_sin +# Loading work.modulation +run -all +# ** Note: $stop : F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v(66) +# Time: 25000100 ns Iteration: 0 Instance: /spwm_tb +# Break in Module spwm_tb at F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v line 66 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl F:/Code/FPGA/reserve/spwm/rtl/modulation.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 15:21:52 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm/rtl" F:/Code/FPGA/reserve/spwm/rtl/modulation.v +# -- Compiling module modulation +# +# Top level modules: +# modulation +# End time: 15:21:52 on Dec 11,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl F:/Code/FPGA/reserve/spwm/rtl/spwm.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 15:21:52 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm/rtl" F:/Code/FPGA/reserve/spwm/rtl/spwm.v +# -- Compiling module spwm +# +# Top level modules: +# spwm +# End time: 15:21:52 on Dec 11,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm F:/Code/FPGA/reserve/spwm/spwm_sin.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 15:21:52 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm" F:/Code/FPGA/reserve/spwm/spwm_sin.v +# -- Compiling module spwm_sin +# +# Top level modules: +# spwm_sin +# End time: 15:21:52 on Dec 11,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/testbench F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 15:21:52 on Dec 11,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/spwm/testbench" F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v +# -- Compiling module spwm_tb +# +# Top level modules: +# spwm_tb +# End time: 15:21:52 on Dec 11,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +restart +# Loading work.spwm_tb +# Loading work.spwm +# Loading work.spwm_sin +# Loading work.modulation +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v(66) +# Time: 25000100 ns Iteration: 0 Instance: /spwm_tb +# Break in Module spwm_tb at F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v line 66 +add wave -position insertpoint sim:/spwm_tb/spwm/* +restart +restart +add wave -position insertpoint sim:/spwm_tb/spwm/modulation/* +restart +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# ** Note: $stop : F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v(66) +# Time: 25000100 ns Iteration: 0 Instance: /spwm_tb +# Break in Module spwm_tb at F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v line 66 +# End time: 17:07:15 on Dec 11,2018, Elapsed time: 2:08:24 +# Errors: 0, Warnings: 0 diff --git a/spwm/simulation/modelsim/rtl_work/_info b/spwm/simulation/modelsim/rtl_work/_info new file mode 100644 index 0000000..e1ef29c --- /dev/null +++ b/spwm/simulation/modelsim/rtl_work/_info @@ -0,0 +1,98 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dF:/Code/FPGA/reserve/spwm/simulation/modelsim +vmodulation +Z1 !s110 1544512912 +!i10b 1 +!s100 5RY3Ze@:V3f3TRTVG4=MeSTVDE4IbaUPQO1V30 +Z2 VDg1SIo80bB@j0V0VzS_@n1 +R0 +w1544512892 +8F:/Code/FPGA/reserve/spwm/rtl/modulation.v +FF:/Code/FPGA/reserve/spwm/rtl/modulation.v +L0 1 +Z3 OV;L;10.5b;63 +r1 +!s85 0 +31 +Z4 !s108 1544512912.000000 +!s107 F:/Code/FPGA/reserve/spwm/rtl/modulation.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+F:/Code/FPGA/reserve/spwm/rtl|F:/Code/FPGA/reserve/spwm/rtl/modulation.v| +!i113 1 +Z5 o-vlog01compat -work work +Z6 !s92 -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl +Z7 tCvgOpt 0 +vspwm +R1 +!i10b 1 +!s100 8f@FbAE=b2idgAV=2MAT21 +IT8WYgFKVdH>3M=Tj7z?c:1 +R2 +R0 +w1544512886 +8F:/Code/FPGA/reserve/spwm/rtl/spwm.v +FF:/Code/FPGA/reserve/spwm/rtl/spwm.v +L0 1 +R3 +r1 +!s85 0 +31 +R4 +!s107 F:/Code/FPGA/reserve/spwm/rtl/spwm.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+F:/Code/FPGA/reserve/spwm/rtl|F:/Code/FPGA/reserve/spwm/rtl/spwm.v| +!i113 1 +R5 +R6 +R7 +vspwm_sin +R1 +!i10b 1 +!s100 NVQGTVZTH[KKP`a<`M8BB2 +IR4_eCB Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[1] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[2] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[3] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[4] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[5] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[6] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[7] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[8] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[0] => Location: PIN_M8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[1] => Location: PIN_J6, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[2] => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[3] => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[4] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[5] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[6] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[7] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[8] => Location: PIN_R8, I/O Standard: 2.5 V, Current Strength: Default +// spwm_out => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +// clk_200m => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[0] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// Pword[1] => Location: PIN_D1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[2] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// Pword[3] => Location: PIN_F3, I/O Standard: 2.5 V, Current Strength: Default +// Pword[4] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[5] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// Pword[6] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[7] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[8] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[9] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[15] => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[14] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// Fword[13] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +// Fword[12] => Location: PIN_A2, I/O Standard: 2.5 V, Current Strength: Default +// Fword[11] => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[10] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[9] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[8] => Location: PIN_A3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[7] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default +// Fword[6] => Location: PIN_D3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[5] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// Fword[4] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[3] => Location: PIN_D5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[2] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// Fword[1] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[0] => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("spwm_v.sdo"); +// synopsys translate_on + +wire \tri_out[0]~output_o ; +wire \tri_out[1]~output_o ; +wire \tri_out[2]~output_o ; +wire \tri_out[3]~output_o ; +wire \tri_out[4]~output_o ; +wire \tri_out[5]~output_o ; +wire \tri_out[6]~output_o ; +wire \tri_out[7]~output_o ; +wire \tri_out[8]~output_o ; +wire \sin_out[0]~output_o ; +wire \sin_out[1]~output_o ; +wire \sin_out[2]~output_o ; +wire \sin_out[3]~output_o ; +wire \sin_out[4]~output_o ; +wire \sin_out[5]~output_o ; +wire \sin_out[6]~output_o ; +wire \sin_out[7]~output_o ; +wire \sin_out[8]~output_o ; +wire \spwm_out~output_o ; +wire \clk_200m~input_o ; +wire \clk_200m~inputclkctrl_outclk ; +wire \tri_out[0]~9_combout ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \tri_out[0]~reg0_q ; +wire \tri_out[0]~10 ; +wire \tri_out[1]~16 ; +wire \tri_out[2]~17_combout ; +wire \tri_out[2]~reg0_q ; +wire \tri_out[2]~18 ; +wire \tri_out[3]~19_combout ; +wire \tri_out[3]~reg0_q ; +wire \tri_out[3]~20 ; +wire \tri_out[4]~21_combout ; +wire \tri_out[4]~reg0_q ; +wire \tri_out[4]~22 ; +wire \tri_out[5]~23_combout ; +wire \tri_out[5]~reg0_q ; +wire \tri_out[5]~24 ; +wire \tri_out[6]~25_combout ; +wire \tri_out[6]~reg0_q ; +wire \tri_out[6]~26 ; +wire \tri_out[7]~27_combout ; +wire \tri_out[7]~reg0_q ; +wire \tri_out[7]~28 ; +wire \tri_out[8]~29_combout ; +wire \tri_out[8]~reg0_q ; +wire \tri_out~12_combout ; +wire \tri_out~11_combout ; +wire \updown~q ; +wire \tri_out~13_combout ; +wire \tri_out~14_combout ; +wire \tri_out[1]~15_combout ; +wire \tri_out[1]~reg0_q ; +wire \Pword[0]~input_o ; +wire \Fword[15]~input_o ; +wire \Fword[14]~input_o ; +wire \Fword[13]~input_o ; +wire \Fword[12]~input_o ; +wire \Fword[11]~input_o ; +wire \Fword[10]~input_o ; +wire \Fword[9]~input_o ; +wire \Fword[8]~input_o ; +wire \Fword[7]~input_o ; +wire \Fword[6]~input_o ; +wire \Fword[5]~input_o ; +wire \Fword[4]~input_o ; +wire \Fword[3]~input_o ; +wire \Fword[2]~input_o ; +wire \Fword[1]~input_o ; +wire \Fword[0]~input_o ; +wire \F_acc[0]~26_combout ; +wire \F_acc[0]~27 ; +wire \F_acc[1]~28_combout ; +wire \F_acc[1]~29 ; +wire \F_acc[2]~30_combout ; +wire \F_acc[2]~31 ; +wire \F_acc[3]~32_combout ; +wire \F_acc[3]~33 ; +wire \F_acc[4]~34_combout ; +wire \F_acc[4]~35 ; +wire \F_acc[5]~36_combout ; +wire \F_acc[5]~37 ; +wire \F_acc[6]~38_combout ; +wire \F_acc[6]~39 ; +wire \F_acc[7]~40_combout ; +wire \F_acc[7]~41 ; +wire \F_acc[8]~42_combout ; +wire \F_acc[8]~43 ; +wire \F_acc[9]~44_combout ; +wire \F_acc[9]~45 ; +wire \F_acc[10]~46_combout ; +wire \F_acc[10]~47 ; +wire \F_acc[11]~48_combout ; +wire \F_acc[11]~49 ; +wire \F_acc[12]~50_combout ; +wire \F_acc[12]~51 ; +wire \F_acc[13]~52_combout ; +wire \F_acc[13]~53 ; +wire \F_acc[14]~54_combout ; +wire \F_acc[14]~55 ; +wire \F_acc[15]~56_combout ; +wire \F_acc[15]~57 ; +wire \F_acc[16]~58_combout ; +wire \rom_address[0]~0_combout ; +wire \F_acc[16]~59 ; +wire \F_acc[17]~60_combout ; +wire \Pword[1]~input_o ; +wire \rom_address[0]~1 ; +wire \rom_address[1]~2_combout ; +wire \F_acc[17]~61 ; +wire \F_acc[18]~62_combout ; +wire \Pword[2]~input_o ; +wire \rom_address[1]~3 ; +wire \rom_address[2]~4_combout ; +wire \F_acc[18]~63 ; +wire \F_acc[19]~64_combout ; +wire \Pword[3]~input_o ; +wire \rom_address[2]~5 ; +wire \rom_address[3]~6_combout ; +wire \F_acc[19]~65 ; +wire \F_acc[20]~66_combout ; +wire \Pword[4]~input_o ; +wire \rom_address[3]~7 ; +wire \rom_address[4]~8_combout ; +wire \F_acc[20]~67 ; +wire \F_acc[21]~68_combout ; +wire \Pword[5]~input_o ; +wire \rom_address[4]~9 ; +wire \rom_address[5]~10_combout ; +wire \Pword[6]~input_o ; +wire \F_acc[21]~69 ; +wire \F_acc[22]~70_combout ; +wire \rom_address[5]~11 ; +wire \rom_address[6]~12_combout ; +wire \Pword[7]~input_o ; +wire \F_acc[22]~71 ; +wire \F_acc[23]~72_combout ; +wire \rom_address[6]~13 ; +wire \rom_address[7]~14_combout ; +wire \Pword[8]~input_o ; +wire \F_acc[23]~73 ; +wire \F_acc[24]~74_combout ; +wire \rom_address[7]~15 ; +wire \rom_address[8]~16_combout ; +wire \Pword[9]~input_o ; +wire \F_acc[24]~75 ; +wire \F_acc[25]~76_combout ; +wire \rom_address[8]~17 ; +wire \rom_address[9]~18_combout ; +wire \modulation|Mult0|mult_core|romout[1][11]~0_combout ; +wire \modulation|Mult0|mult_core|romout[1][10]~combout ; +wire \modulation|Mult0|mult_core|romout[1][9]~combout ; +wire \modulation|Mult0|mult_core|romout[1][8]~1_combout ; +wire \modulation|Mult0|mult_core|romout[0][11]~2_combout ; +wire \modulation|Mult0|mult_core|romout[1][7]~combout ; +wire \modulation|Mult0|mult_core|romout[1][6]~combout ; +wire \modulation|Mult0|mult_core|romout[0][10]~3_combout ; +wire \modulation|Mult0|mult_core|romout[0][9]~5_combout ; +wire \modulation|Mult0|mult_core|romout[1][5]~4_combout ; +wire \modulation|Mult0|mult_core|romout[0][8]~6_combout ; +wire \modulation|Mult0|mult_core|romout[0][7]~7_combout ; +wire \modulation|Mult0|mult_core|romout[0][6]~8_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ; +wire \modulation|LessThan0~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ; +wire \modulation|LessThan0~1_combout ; +wire \modulation|LessThan0~3_cout ; +wire \modulation|LessThan0~5_cout ; +wire \modulation|LessThan0~7_cout ; +wire \modulation|LessThan0~9_cout ; +wire \modulation|LessThan0~11_cout ; +wire \modulation|LessThan0~13_cout ; +wire \modulation|LessThan0~15_cout ; +wire \modulation|LessThan0~17_cout ; +wire \modulation|LessThan0~19_cout ; +wire \modulation|LessThan0~20_combout ; +wire \modulation|out~q ; +wire [8:0] \spwm_sin|altsyncram_component|auto_generated|q_a ; +wire [25:0] F_acc; + +wire [8:0] \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; + +assign \spwm_sin|altsyncram_component|auto_generated|q_a [0] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [1] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [2] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [3] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [4] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [5] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [6] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [7] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [8] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [8]; + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: IOOBUF_X13_Y24_N23 +cycloneive_io_obuf \tri_out[0]~output ( + .i(\tri_out[0]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[0]~output .bus_hold = "false"; +defparam \tri_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N2 +cycloneive_io_obuf \tri_out[1]~output ( + .i(\tri_out[1]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[1]~output .bus_hold = "false"; +defparam \tri_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N23 +cycloneive_io_obuf \tri_out[2]~output ( + .i(\tri_out[2]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[2]~output .bus_hold = "false"; +defparam \tri_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N16 +cycloneive_io_obuf \tri_out[3]~output ( + .i(\tri_out[3]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[3]~output .bus_hold = "false"; +defparam \tri_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N9 +cycloneive_io_obuf \tri_out[4]~output ( + .i(\tri_out[4]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[4]~output .bus_hold = "false"; +defparam \tri_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N16 +cycloneive_io_obuf \tri_out[5]~output ( + .i(\tri_out[5]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[5]~output .bus_hold = "false"; +defparam \tri_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N9 +cycloneive_io_obuf \tri_out[6]~output ( + .i(\tri_out[6]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[6]~output .bus_hold = "false"; +defparam \tri_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N16 +cycloneive_io_obuf \tri_out[7]~output ( + .i(\tri_out[7]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[7]~output .bus_hold = "false"; +defparam \tri_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N2 +cycloneive_io_obuf \tri_out[8]~output ( + .i(\tri_out[8]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[8]~output .bus_hold = "false"; +defparam \tri_out[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y0_N2 +cycloneive_io_obuf \sin_out[0]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[0]~output .bus_hold = "false"; +defparam \sin_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N23 +cycloneive_io_obuf \sin_out[1]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[1]~output .bus_hold = "false"; +defparam \sin_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N9 +cycloneive_io_obuf \sin_out[2]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[2]~output .bus_hold = "false"; +defparam \sin_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N2 +cycloneive_io_obuf \sin_out[3]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[3]~output .bus_hold = "false"; +defparam \sin_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N23 +cycloneive_io_obuf \sin_out[4]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[4]~output .bus_hold = "false"; +defparam \sin_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N2 +cycloneive_io_obuf \sin_out[5]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[5]~output .bus_hold = "false"; +defparam \sin_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N16 +cycloneive_io_obuf \sin_out[6]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[6]~output .bus_hold = "false"; +defparam \sin_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N16 +cycloneive_io_obuf \sin_out[7]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[7]~output .bus_hold = "false"; +defparam \sin_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N9 +cycloneive_io_obuf \sin_out[8]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[8]~output .bus_hold = "false"; +defparam \sin_out[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y0_N16 +cycloneive_io_obuf \spwm_out~output ( + .i(\modulation|out~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\spwm_out~output_o ), + .obar()); +// synopsys translate_off +defparam \spwm_out~output .bus_hold = "false"; +defparam \spwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk_200m~input ( + .i(clk_200m), + .ibar(gnd), + .o(\clk_200m~input_o )); +// synopsys translate_off +defparam \clk_200m~input .bus_hold = "false"; +defparam \clk_200m~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk_200m~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_200m~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_200m~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk_200m~inputclkctrl .clock_type = "global clock"; +defparam \clk_200m~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N10 +cycloneive_lcell_comb \tri_out[0]~9 ( +// Equation(s): +// \tri_out[0]~9_combout = \tri_out[0]~reg0_q $ (VCC) +// \tri_out[0]~10 = CARRY(\tri_out[0]~reg0_q ) + + .dataa(\tri_out[0]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\tri_out[0]~9_combout ), + .cout(\tri_out[0]~10 )); +// synopsys translate_off +defparam \tri_out[0]~9 .lut_mask = 16'h55AA; +defparam \tri_out[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X14_Y19_N11 +dffeas \tri_out[0]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[0]~9_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[0]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[0]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[0]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N12 +cycloneive_lcell_comb \tri_out[1]~15 ( +// Equation(s): +// \tri_out[1]~15_combout = (\tri_out[1]~reg0_q & ((\tri_out~14_combout & (\tri_out[0]~10 & VCC)) # (!\tri_out~14_combout & (!\tri_out[0]~10 )))) # (!\tri_out[1]~reg0_q & ((\tri_out~14_combout & (!\tri_out[0]~10 )) # (!\tri_out~14_combout & +// ((\tri_out[0]~10 ) # (GND))))) +// \tri_out[1]~16 = CARRY((\tri_out[1]~reg0_q & (!\tri_out~14_combout & !\tri_out[0]~10 )) # (!\tri_out[1]~reg0_q & ((!\tri_out[0]~10 ) # (!\tri_out~14_combout )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\tri_out~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[0]~10 ), + .combout(\tri_out[1]~15_combout ), + .cout(\tri_out[1]~16 )); +// synopsys translate_off +defparam \tri_out[1]~15 .lut_mask = 16'h9617; +defparam \tri_out[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N14 +cycloneive_lcell_comb \tri_out[2]~17 ( +// Equation(s): +// \tri_out[2]~17_combout = ((\tri_out~14_combout $ (\tri_out[2]~reg0_q $ (!\tri_out[1]~16 )))) # (GND) +// \tri_out[2]~18 = CARRY((\tri_out~14_combout & ((\tri_out[2]~reg0_q ) # (!\tri_out[1]~16 ))) # (!\tri_out~14_combout & (\tri_out[2]~reg0_q & !\tri_out[1]~16 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[2]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[1]~16 ), + .combout(\tri_out[2]~17_combout ), + .cout(\tri_out[2]~18 )); +// synopsys translate_off +defparam \tri_out[2]~17 .lut_mask = 16'h698E; +defparam \tri_out[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N15 +dffeas \tri_out[2]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[2]~17_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[2]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[2]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[2]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N16 +cycloneive_lcell_comb \tri_out[3]~19 ( +// Equation(s): +// \tri_out[3]~19_combout = (\tri_out~14_combout & ((\tri_out[3]~reg0_q & (\tri_out[2]~18 & VCC)) # (!\tri_out[3]~reg0_q & (!\tri_out[2]~18 )))) # (!\tri_out~14_combout & ((\tri_out[3]~reg0_q & (!\tri_out[2]~18 )) # (!\tri_out[3]~reg0_q & +// ((\tri_out[2]~18 ) # (GND))))) +// \tri_out[3]~20 = CARRY((\tri_out~14_combout & (!\tri_out[3]~reg0_q & !\tri_out[2]~18 )) # (!\tri_out~14_combout & ((!\tri_out[2]~18 ) # (!\tri_out[3]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[3]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[2]~18 ), + .combout(\tri_out[3]~19_combout ), + .cout(\tri_out[3]~20 )); +// synopsys translate_off +defparam \tri_out[3]~19 .lut_mask = 16'h9617; +defparam \tri_out[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N17 +dffeas \tri_out[3]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[3]~19_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[3]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[3]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[3]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N18 +cycloneive_lcell_comb \tri_out[4]~21 ( +// Equation(s): +// \tri_out[4]~21_combout = ((\tri_out~14_combout $ (\tri_out[4]~reg0_q $ (!\tri_out[3]~20 )))) # (GND) +// \tri_out[4]~22 = CARRY((\tri_out~14_combout & ((\tri_out[4]~reg0_q ) # (!\tri_out[3]~20 ))) # (!\tri_out~14_combout & (\tri_out[4]~reg0_q & !\tri_out[3]~20 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[4]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[3]~20 ), + .combout(\tri_out[4]~21_combout ), + .cout(\tri_out[4]~22 )); +// synopsys translate_off +defparam \tri_out[4]~21 .lut_mask = 16'h698E; +defparam \tri_out[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N19 +dffeas \tri_out[4]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[4]~21_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[4]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[4]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[4]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N20 +cycloneive_lcell_comb \tri_out[5]~23 ( +// Equation(s): +// \tri_out[5]~23_combout = (\tri_out~14_combout & ((\tri_out[5]~reg0_q & (\tri_out[4]~22 & VCC)) # (!\tri_out[5]~reg0_q & (!\tri_out[4]~22 )))) # (!\tri_out~14_combout & ((\tri_out[5]~reg0_q & (!\tri_out[4]~22 )) # (!\tri_out[5]~reg0_q & +// ((\tri_out[4]~22 ) # (GND))))) +// \tri_out[5]~24 = CARRY((\tri_out~14_combout & (!\tri_out[5]~reg0_q & !\tri_out[4]~22 )) # (!\tri_out~14_combout & ((!\tri_out[4]~22 ) # (!\tri_out[5]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[5]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[4]~22 ), + .combout(\tri_out[5]~23_combout ), + .cout(\tri_out[5]~24 )); +// synopsys translate_off +defparam \tri_out[5]~23 .lut_mask = 16'h9617; +defparam \tri_out[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N21 +dffeas \tri_out[5]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[5]~23_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[5]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[5]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[5]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N22 +cycloneive_lcell_comb \tri_out[6]~25 ( +// Equation(s): +// \tri_out[6]~25_combout = ((\tri_out~14_combout $ (\tri_out[6]~reg0_q $ (!\tri_out[5]~24 )))) # (GND) +// \tri_out[6]~26 = CARRY((\tri_out~14_combout & ((\tri_out[6]~reg0_q ) # (!\tri_out[5]~24 ))) # (!\tri_out~14_combout & (\tri_out[6]~reg0_q & !\tri_out[5]~24 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[6]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[5]~24 ), + .combout(\tri_out[6]~25_combout ), + .cout(\tri_out[6]~26 )); +// synopsys translate_off +defparam \tri_out[6]~25 .lut_mask = 16'h698E; +defparam \tri_out[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N23 +dffeas \tri_out[6]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[6]~25_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[6]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[6]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[6]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N24 +cycloneive_lcell_comb \tri_out[7]~27 ( +// Equation(s): +// \tri_out[7]~27_combout = (\tri_out~14_combout & ((\tri_out[7]~reg0_q & (\tri_out[6]~26 & VCC)) # (!\tri_out[7]~reg0_q & (!\tri_out[6]~26 )))) # (!\tri_out~14_combout & ((\tri_out[7]~reg0_q & (!\tri_out[6]~26 )) # (!\tri_out[7]~reg0_q & +// ((\tri_out[6]~26 ) # (GND))))) +// \tri_out[7]~28 = CARRY((\tri_out~14_combout & (!\tri_out[7]~reg0_q & !\tri_out[6]~26 )) # (!\tri_out~14_combout & ((!\tri_out[6]~26 ) # (!\tri_out[7]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[7]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[6]~26 ), + .combout(\tri_out[7]~27_combout ), + .cout(\tri_out[7]~28 )); +// synopsys translate_off +defparam \tri_out[7]~27 .lut_mask = 16'h9617; +defparam \tri_out[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N25 +dffeas \tri_out[7]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[7]~27_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[7]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[7]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[7]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N26 +cycloneive_lcell_comb \tri_out[8]~29 ( +// Equation(s): +// \tri_out[8]~29_combout = \tri_out[8]~reg0_q $ (\tri_out[7]~28 $ (!\tri_out~14_combout )) + + .dataa(\tri_out[8]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\tri_out~14_combout ), + .cin(\tri_out[7]~28 ), + .combout(\tri_out[8]~29_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out[8]~29 .lut_mask = 16'h5AA5; +defparam \tri_out[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N27 +dffeas \tri_out[8]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[8]~29_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[8]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[8]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[8]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N6 +cycloneive_lcell_comb \tri_out~12 ( +// Equation(s): +// \tri_out~12_combout = (\tri_out[6]~reg0_q & (\tri_out[2]~reg0_q & (\tri_out[8]~reg0_q & \tri_out[7]~reg0_q ))) # (!\tri_out[6]~reg0_q & ((\tri_out[2]~reg0_q ) # ((\tri_out[8]~reg0_q ) # (\tri_out[7]~reg0_q )))) + + .dataa(\tri_out[6]~reg0_q ), + .datab(\tri_out[2]~reg0_q ), + .datac(\tri_out[8]~reg0_q ), + .datad(\tri_out[7]~reg0_q ), + .cin(gnd), + .combout(\tri_out~12_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~12 .lut_mask = 16'hD554; +defparam \tri_out~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N0 +cycloneive_lcell_comb \tri_out~11 ( +// Equation(s): +// \tri_out~11_combout = (\tri_out[5]~reg0_q & (((\tri_out[4]~reg0_q & \tri_out[3]~reg0_q )) # (!\tri_out[2]~reg0_q ))) # (!\tri_out[5]~reg0_q & (!\tri_out[2]~reg0_q & ((\tri_out[4]~reg0_q ) # (\tri_out[3]~reg0_q )))) + + .dataa(\tri_out[5]~reg0_q ), + .datab(\tri_out[4]~reg0_q ), + .datac(\tri_out[2]~reg0_q ), + .datad(\tri_out[3]~reg0_q ), + .cin(gnd), + .combout(\tri_out~11_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~11 .lut_mask = 16'h8F0E; +defparam \tri_out~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y19_N29 +dffeas updown( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out~14_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\updown~q ), + .prn(vcc)); +// synopsys translate_off +defparam updown.is_wysiwyg = "true"; +defparam updown.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N30 +cycloneive_lcell_comb \tri_out~13 ( +// Equation(s): +// \tri_out~13_combout = (\tri_out[1]~reg0_q & ((\updown~q ) # ((\tri_out[6]~reg0_q & \tri_out[0]~reg0_q )))) # (!\tri_out[1]~reg0_q & (\updown~q & ((\tri_out[6]~reg0_q ) # (\tri_out[0]~reg0_q )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\updown~q ), + .datac(\tri_out[6]~reg0_q ), + .datad(\tri_out[0]~reg0_q ), + .cin(gnd), + .combout(\tri_out~13_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~13 .lut_mask = 16'hECC8; +defparam \tri_out~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N28 +cycloneive_lcell_comb \tri_out~14 ( +// Equation(s): +// \tri_out~14_combout = (\tri_out~12_combout & ((\updown~q ) # ((\tri_out~11_combout & \tri_out~13_combout )))) # (!\tri_out~12_combout & (\updown~q & ((\tri_out~11_combout ) # (\tri_out~13_combout )))) + + .dataa(\tri_out~12_combout ), + .datab(\tri_out~11_combout ), + .datac(\updown~q ), + .datad(\tri_out~13_combout ), + .cin(gnd), + .combout(\tri_out~14_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~14 .lut_mask = 16'hF8E0; +defparam \tri_out~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y19_N13 +dffeas \tri_out[1]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[1]~15_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[1]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[1]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[1]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N15 +cycloneive_io_ibuf \Pword[0]~input ( + .i(Pword[0]), + .ibar(gnd), + .o(\Pword[0]~input_o )); +// synopsys translate_off +defparam \Pword[0]~input .bus_hold = "false"; +defparam \Pword[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N1 +cycloneive_io_ibuf \Fword[15]~input ( + .i(Fword[15]), + .ibar(gnd), + .o(\Fword[15]~input_o )); +// synopsys translate_off +defparam \Fword[15]~input .bus_hold = "false"; +defparam \Fword[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \Fword[14]~input ( + .i(Fword[14]), + .ibar(gnd), + .o(\Fword[14]~input_o )); +// synopsys translate_off +defparam \Fword[14]~input .bus_hold = "false"; +defparam \Fword[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y22_N1 +cycloneive_io_ibuf \Fword[13]~input ( + .i(Fword[13]), + .ibar(gnd), + .o(\Fword[13]~input_o )); +// synopsys translate_off +defparam \Fword[13]~input .bus_hold = "false"; +defparam \Fword[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N1 +cycloneive_io_ibuf \Fword[12]~input ( + .i(Fword[12]), + .ibar(gnd), + .o(\Fword[12]~input_o )); +// synopsys translate_off +defparam \Fword[12]~input .bus_hold = "false"; +defparam \Fword[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N8 +cycloneive_io_ibuf \Fword[11]~input ( + .i(Fword[11]), + .ibar(gnd), + .o(\Fword[11]~input_o )); +// synopsys translate_off +defparam \Fword[11]~input .bus_hold = "false"; +defparam \Fword[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N22 +cycloneive_io_ibuf \Fword[10]~input ( + .i(Fword[10]), + .ibar(gnd), + .o(\Fword[10]~input_o )); +// synopsys translate_off +defparam \Fword[10]~input .bus_hold = "false"; +defparam \Fword[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N8 +cycloneive_io_ibuf \Fword[9]~input ( + .i(Fword[9]), + .ibar(gnd), + .o(\Fword[9]~input_o )); +// synopsys translate_off +defparam \Fword[9]~input .bus_hold = "false"; +defparam \Fword[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N15 +cycloneive_io_ibuf \Fword[8]~input ( + .i(Fword[8]), + .ibar(gnd), + .o(\Fword[8]~input_o )); +// synopsys translate_off +defparam \Fword[8]~input .bus_hold = "false"; +defparam \Fword[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N22 +cycloneive_io_ibuf \Fword[7]~input ( + .i(Fword[7]), + .ibar(gnd), + .o(\Fword[7]~input_o )); +// synopsys translate_off +defparam \Fword[7]~input .bus_hold = "false"; +defparam \Fword[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y24_N8 +cycloneive_io_ibuf \Fword[6]~input ( + .i(Fword[6]), + .ibar(gnd), + .o(\Fword[6]~input_o )); +// synopsys translate_off +defparam \Fword[6]~input .bus_hold = "false"; +defparam \Fword[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N1 +cycloneive_io_ibuf \Fword[5]~input ( + .i(Fword[5]), + .ibar(gnd), + .o(\Fword[5]~input_o )); +// synopsys translate_off +defparam \Fword[5]~input .bus_hold = "false"; +defparam \Fword[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N22 +cycloneive_io_ibuf \Fword[4]~input ( + .i(Fword[4]), + .ibar(gnd), + .o(\Fword[4]~input_o )); +// synopsys translate_off +defparam \Fword[4]~input .bus_hold = "false"; +defparam \Fword[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N1 +cycloneive_io_ibuf \Fword[3]~input ( + .i(Fword[3]), + .ibar(gnd), + .o(\Fword[3]~input_o )); +// synopsys translate_off +defparam \Fword[3]~input .bus_hold = "false"; +defparam \Fword[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N8 +cycloneive_io_ibuf \Fword[2]~input ( + .i(Fword[2]), + .ibar(gnd), + .o(\Fword[2]~input_o )); +// synopsys translate_off +defparam \Fword[2]~input .bus_hold = "false"; +defparam \Fword[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N8 +cycloneive_io_ibuf \Fword[1]~input ( + .i(Fword[1]), + .ibar(gnd), + .o(\Fword[1]~input_o )); +// synopsys translate_off +defparam \Fword[1]~input .bus_hold = "false"; +defparam \Fword[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N15 +cycloneive_io_ibuf \Fword[0]~input ( + .i(Fword[0]), + .ibar(gnd), + .o(\Fword[0]~input_o )); +// synopsys translate_off +defparam \Fword[0]~input .bus_hold = "false"; +defparam \Fword[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N6 +cycloneive_lcell_comb \F_acc[0]~26 ( +// Equation(s): +// \F_acc[0]~26_combout = (F_acc[0] & (\Fword[0]~input_o $ (VCC))) # (!F_acc[0] & (\Fword[0]~input_o & VCC)) +// \F_acc[0]~27 = CARRY((F_acc[0] & \Fword[0]~input_o )) + + .dataa(F_acc[0]), + .datab(\Fword[0]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\F_acc[0]~26_combout ), + .cout(\F_acc[0]~27 )); +// synopsys translate_off +defparam \F_acc[0]~26 .lut_mask = 16'h6688; +defparam \F_acc[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X6_Y20_N7 +dffeas \F_acc[0] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[0]~26_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[0]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[0] .is_wysiwyg = "true"; +defparam \F_acc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N8 +cycloneive_lcell_comb \F_acc[1]~28 ( +// Equation(s): +// \F_acc[1]~28_combout = (\Fword[1]~input_o & ((F_acc[1] & (\F_acc[0]~27 & VCC)) # (!F_acc[1] & (!\F_acc[0]~27 )))) # (!\Fword[1]~input_o & ((F_acc[1] & (!\F_acc[0]~27 )) # (!F_acc[1] & ((\F_acc[0]~27 ) # (GND))))) +// \F_acc[1]~29 = CARRY((\Fword[1]~input_o & (!F_acc[1] & !\F_acc[0]~27 )) # (!\Fword[1]~input_o & ((!\F_acc[0]~27 ) # (!F_acc[1])))) + + .dataa(\Fword[1]~input_o ), + .datab(F_acc[1]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[0]~27 ), + .combout(\F_acc[1]~28_combout ), + .cout(\F_acc[1]~29 )); +// synopsys translate_off +defparam \F_acc[1]~28 .lut_mask = 16'h9617; +defparam \F_acc[1]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N9 +dffeas \F_acc[1] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[1]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[1]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[1] .is_wysiwyg = "true"; +defparam \F_acc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N10 +cycloneive_lcell_comb \F_acc[2]~30 ( +// Equation(s): +// \F_acc[2]~30_combout = ((F_acc[2] $ (\Fword[2]~input_o $ (!\F_acc[1]~29 )))) # (GND) +// \F_acc[2]~31 = CARRY((F_acc[2] & ((\Fword[2]~input_o ) # (!\F_acc[1]~29 ))) # (!F_acc[2] & (\Fword[2]~input_o & !\F_acc[1]~29 ))) + + .dataa(F_acc[2]), + .datab(\Fword[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[1]~29 ), + .combout(\F_acc[2]~30_combout ), + .cout(\F_acc[2]~31 )); +// synopsys translate_off +defparam \F_acc[2]~30 .lut_mask = 16'h698E; +defparam \F_acc[2]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N11 +dffeas \F_acc[2] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[2]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[2]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[2] .is_wysiwyg = "true"; +defparam \F_acc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N12 +cycloneive_lcell_comb \F_acc[3]~32 ( +// Equation(s): +// \F_acc[3]~32_combout = (F_acc[3] & ((\Fword[3]~input_o & (\F_acc[2]~31 & VCC)) # (!\Fword[3]~input_o & (!\F_acc[2]~31 )))) # (!F_acc[3] & ((\Fword[3]~input_o & (!\F_acc[2]~31 )) # (!\Fword[3]~input_o & ((\F_acc[2]~31 ) # (GND))))) +// \F_acc[3]~33 = CARRY((F_acc[3] & (!\Fword[3]~input_o & !\F_acc[2]~31 )) # (!F_acc[3] & ((!\F_acc[2]~31 ) # (!\Fword[3]~input_o )))) + + .dataa(F_acc[3]), + .datab(\Fword[3]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[2]~31 ), + .combout(\F_acc[3]~32_combout ), + .cout(\F_acc[3]~33 )); +// synopsys translate_off +defparam \F_acc[3]~32 .lut_mask = 16'h9617; +defparam \F_acc[3]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N13 +dffeas \F_acc[3] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[3]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[3]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[3] .is_wysiwyg = "true"; +defparam \F_acc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N14 +cycloneive_lcell_comb \F_acc[4]~34 ( +// Equation(s): +// \F_acc[4]~34_combout = ((\Fword[4]~input_o $ (F_acc[4] $ (!\F_acc[3]~33 )))) # (GND) +// \F_acc[4]~35 = CARRY((\Fword[4]~input_o & ((F_acc[4]) # (!\F_acc[3]~33 ))) # (!\Fword[4]~input_o & (F_acc[4] & !\F_acc[3]~33 ))) + + .dataa(\Fword[4]~input_o ), + .datab(F_acc[4]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[3]~33 ), + .combout(\F_acc[4]~34_combout ), + .cout(\F_acc[4]~35 )); +// synopsys translate_off +defparam \F_acc[4]~34 .lut_mask = 16'h698E; +defparam \F_acc[4]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N15 +dffeas \F_acc[4] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[4]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[4]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[4] .is_wysiwyg = "true"; +defparam \F_acc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N16 +cycloneive_lcell_comb \F_acc[5]~36 ( +// Equation(s): +// \F_acc[5]~36_combout = (\Fword[5]~input_o & ((F_acc[5] & (\F_acc[4]~35 & VCC)) # (!F_acc[5] & (!\F_acc[4]~35 )))) # (!\Fword[5]~input_o & ((F_acc[5] & (!\F_acc[4]~35 )) # (!F_acc[5] & ((\F_acc[4]~35 ) # (GND))))) +// \F_acc[5]~37 = CARRY((\Fword[5]~input_o & (!F_acc[5] & !\F_acc[4]~35 )) # (!\Fword[5]~input_o & ((!\F_acc[4]~35 ) # (!F_acc[5])))) + + .dataa(\Fword[5]~input_o ), + .datab(F_acc[5]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[4]~35 ), + .combout(\F_acc[5]~36_combout ), + .cout(\F_acc[5]~37 )); +// synopsys translate_off +defparam \F_acc[5]~36 .lut_mask = 16'h9617; +defparam \F_acc[5]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N17 +dffeas \F_acc[5] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[5]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[5]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[5] .is_wysiwyg = "true"; +defparam \F_acc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N18 +cycloneive_lcell_comb \F_acc[6]~38 ( +// Equation(s): +// \F_acc[6]~38_combout = ((\Fword[6]~input_o $ (F_acc[6] $ (!\F_acc[5]~37 )))) # (GND) +// \F_acc[6]~39 = CARRY((\Fword[6]~input_o & ((F_acc[6]) # (!\F_acc[5]~37 ))) # (!\Fword[6]~input_o & (F_acc[6] & !\F_acc[5]~37 ))) + + .dataa(\Fword[6]~input_o ), + .datab(F_acc[6]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[5]~37 ), + .combout(\F_acc[6]~38_combout ), + .cout(\F_acc[6]~39 )); +// synopsys translate_off +defparam \F_acc[6]~38 .lut_mask = 16'h698E; +defparam \F_acc[6]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N19 +dffeas \F_acc[6] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[6]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[6]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[6] .is_wysiwyg = "true"; +defparam \F_acc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N20 +cycloneive_lcell_comb \F_acc[7]~40 ( +// Equation(s): +// \F_acc[7]~40_combout = (\Fword[7]~input_o & ((F_acc[7] & (\F_acc[6]~39 & VCC)) # (!F_acc[7] & (!\F_acc[6]~39 )))) # (!\Fword[7]~input_o & ((F_acc[7] & (!\F_acc[6]~39 )) # (!F_acc[7] & ((\F_acc[6]~39 ) # (GND))))) +// \F_acc[7]~41 = CARRY((\Fword[7]~input_o & (!F_acc[7] & !\F_acc[6]~39 )) # (!\Fword[7]~input_o & ((!\F_acc[6]~39 ) # (!F_acc[7])))) + + .dataa(\Fword[7]~input_o ), + .datab(F_acc[7]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[6]~39 ), + .combout(\F_acc[7]~40_combout ), + .cout(\F_acc[7]~41 )); +// synopsys translate_off +defparam \F_acc[7]~40 .lut_mask = 16'h9617; +defparam \F_acc[7]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N21 +dffeas \F_acc[7] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[7]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[7]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[7] .is_wysiwyg = "true"; +defparam \F_acc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N22 +cycloneive_lcell_comb \F_acc[8]~42 ( +// Equation(s): +// \F_acc[8]~42_combout = ((F_acc[8] $ (\Fword[8]~input_o $ (!\F_acc[7]~41 )))) # (GND) +// \F_acc[8]~43 = CARRY((F_acc[8] & ((\Fword[8]~input_o ) # (!\F_acc[7]~41 ))) # (!F_acc[8] & (\Fword[8]~input_o & !\F_acc[7]~41 ))) + + .dataa(F_acc[8]), + .datab(\Fword[8]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[7]~41 ), + .combout(\F_acc[8]~42_combout ), + .cout(\F_acc[8]~43 )); +// synopsys translate_off +defparam \F_acc[8]~42 .lut_mask = 16'h698E; +defparam \F_acc[8]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N23 +dffeas \F_acc[8] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[8]~42_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[8]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[8] .is_wysiwyg = "true"; +defparam \F_acc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N24 +cycloneive_lcell_comb \F_acc[9]~44 ( +// Equation(s): +// \F_acc[9]~44_combout = (\Fword[9]~input_o & ((F_acc[9] & (\F_acc[8]~43 & VCC)) # (!F_acc[9] & (!\F_acc[8]~43 )))) # (!\Fword[9]~input_o & ((F_acc[9] & (!\F_acc[8]~43 )) # (!F_acc[9] & ((\F_acc[8]~43 ) # (GND))))) +// \F_acc[9]~45 = CARRY((\Fword[9]~input_o & (!F_acc[9] & !\F_acc[8]~43 )) # (!\Fword[9]~input_o & ((!\F_acc[8]~43 ) # (!F_acc[9])))) + + .dataa(\Fword[9]~input_o ), + .datab(F_acc[9]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[8]~43 ), + .combout(\F_acc[9]~44_combout ), + .cout(\F_acc[9]~45 )); +// synopsys translate_off +defparam \F_acc[9]~44 .lut_mask = 16'h9617; +defparam \F_acc[9]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N25 +dffeas \F_acc[9] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[9]~44_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[9]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[9] .is_wysiwyg = "true"; +defparam \F_acc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N26 +cycloneive_lcell_comb \F_acc[10]~46 ( +// Equation(s): +// \F_acc[10]~46_combout = ((F_acc[10] $ (\Fword[10]~input_o $ (!\F_acc[9]~45 )))) # (GND) +// \F_acc[10]~47 = CARRY((F_acc[10] & ((\Fword[10]~input_o ) # (!\F_acc[9]~45 ))) # (!F_acc[10] & (\Fword[10]~input_o & !\F_acc[9]~45 ))) + + .dataa(F_acc[10]), + .datab(\Fword[10]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[9]~45 ), + .combout(\F_acc[10]~46_combout ), + .cout(\F_acc[10]~47 )); +// synopsys translate_off +defparam \F_acc[10]~46 .lut_mask = 16'h698E; +defparam \F_acc[10]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N27 +dffeas \F_acc[10] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[10]~46_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[10]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[10] .is_wysiwyg = "true"; +defparam \F_acc[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N28 +cycloneive_lcell_comb \F_acc[11]~48 ( +// Equation(s): +// \F_acc[11]~48_combout = (\Fword[11]~input_o & ((F_acc[11] & (\F_acc[10]~47 & VCC)) # (!F_acc[11] & (!\F_acc[10]~47 )))) # (!\Fword[11]~input_o & ((F_acc[11] & (!\F_acc[10]~47 )) # (!F_acc[11] & ((\F_acc[10]~47 ) # (GND))))) +// \F_acc[11]~49 = CARRY((\Fword[11]~input_o & (!F_acc[11] & !\F_acc[10]~47 )) # (!\Fword[11]~input_o & ((!\F_acc[10]~47 ) # (!F_acc[11])))) + + .dataa(\Fword[11]~input_o ), + .datab(F_acc[11]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[10]~47 ), + .combout(\F_acc[11]~48_combout ), + .cout(\F_acc[11]~49 )); +// synopsys translate_off +defparam \F_acc[11]~48 .lut_mask = 16'h9617; +defparam \F_acc[11]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N29 +dffeas \F_acc[11] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[11]~48_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[11]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[11] .is_wysiwyg = "true"; +defparam \F_acc[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N30 +cycloneive_lcell_comb \F_acc[12]~50 ( +// Equation(s): +// \F_acc[12]~50_combout = ((F_acc[12] $ (\Fword[12]~input_o $ (!\F_acc[11]~49 )))) # (GND) +// \F_acc[12]~51 = CARRY((F_acc[12] & ((\Fword[12]~input_o ) # (!\F_acc[11]~49 ))) # (!F_acc[12] & (\Fword[12]~input_o & !\F_acc[11]~49 ))) + + .dataa(F_acc[12]), + .datab(\Fword[12]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[11]~49 ), + .combout(\F_acc[12]~50_combout ), + .cout(\F_acc[12]~51 )); +// synopsys translate_off +defparam \F_acc[12]~50 .lut_mask = 16'h698E; +defparam \F_acc[12]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N31 +dffeas \F_acc[12] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[12]~50_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[12]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[12] .is_wysiwyg = "true"; +defparam \F_acc[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N0 +cycloneive_lcell_comb \F_acc[13]~52 ( +// Equation(s): +// \F_acc[13]~52_combout = (\Fword[13]~input_o & ((F_acc[13] & (\F_acc[12]~51 & VCC)) # (!F_acc[13] & (!\F_acc[12]~51 )))) # (!\Fword[13]~input_o & ((F_acc[13] & (!\F_acc[12]~51 )) # (!F_acc[13] & ((\F_acc[12]~51 ) # (GND))))) +// \F_acc[13]~53 = CARRY((\Fword[13]~input_o & (!F_acc[13] & !\F_acc[12]~51 )) # (!\Fword[13]~input_o & ((!\F_acc[12]~51 ) # (!F_acc[13])))) + + .dataa(\Fword[13]~input_o ), + .datab(F_acc[13]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[12]~51 ), + .combout(\F_acc[13]~52_combout ), + .cout(\F_acc[13]~53 )); +// synopsys translate_off +defparam \F_acc[13]~52 .lut_mask = 16'h9617; +defparam \F_acc[13]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N1 +dffeas \F_acc[13] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[13]~52_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[13]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[13] .is_wysiwyg = "true"; +defparam \F_acc[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N2 +cycloneive_lcell_comb \F_acc[14]~54 ( +// Equation(s): +// \F_acc[14]~54_combout = ((\Fword[14]~input_o $ (F_acc[14] $ (!\F_acc[13]~53 )))) # (GND) +// \F_acc[14]~55 = CARRY((\Fword[14]~input_o & ((F_acc[14]) # (!\F_acc[13]~53 ))) # (!\Fword[14]~input_o & (F_acc[14] & !\F_acc[13]~53 ))) + + .dataa(\Fword[14]~input_o ), + .datab(F_acc[14]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[13]~53 ), + .combout(\F_acc[14]~54_combout ), + .cout(\F_acc[14]~55 )); +// synopsys translate_off +defparam \F_acc[14]~54 .lut_mask = 16'h698E; +defparam \F_acc[14]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N3 +dffeas \F_acc[14] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[14]~54_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[14]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[14] .is_wysiwyg = "true"; +defparam \F_acc[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N4 +cycloneive_lcell_comb \F_acc[15]~56 ( +// Equation(s): +// \F_acc[15]~56_combout = (\Fword[15]~input_o & ((F_acc[15] & (\F_acc[14]~55 & VCC)) # (!F_acc[15] & (!\F_acc[14]~55 )))) # (!\Fword[15]~input_o & ((F_acc[15] & (!\F_acc[14]~55 )) # (!F_acc[15] & ((\F_acc[14]~55 ) # (GND))))) +// \F_acc[15]~57 = CARRY((\Fword[15]~input_o & (!F_acc[15] & !\F_acc[14]~55 )) # (!\Fword[15]~input_o & ((!\F_acc[14]~55 ) # (!F_acc[15])))) + + .dataa(\Fword[15]~input_o ), + .datab(F_acc[15]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[14]~55 ), + .combout(\F_acc[15]~56_combout ), + .cout(\F_acc[15]~57 )); +// synopsys translate_off +defparam \F_acc[15]~56 .lut_mask = 16'h9617; +defparam \F_acc[15]~56 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N5 +dffeas \F_acc[15] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[15]~56_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[15]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[15] .is_wysiwyg = "true"; +defparam \F_acc[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N6 +cycloneive_lcell_comb \F_acc[16]~58 ( +// Equation(s): +// \F_acc[16]~58_combout = (F_acc[16] & (\F_acc[15]~57 $ (GND))) # (!F_acc[16] & (!\F_acc[15]~57 & VCC)) +// \F_acc[16]~59 = CARRY((F_acc[16] & !\F_acc[15]~57 )) + + .dataa(F_acc[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[15]~57 ), + .combout(\F_acc[16]~58_combout ), + .cout(\F_acc[16]~59 )); +// synopsys translate_off +defparam \F_acc[16]~58 .lut_mask = 16'hA50A; +defparam \F_acc[16]~58 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N7 +dffeas \F_acc[16] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[16]~58_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[16]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[16] .is_wysiwyg = "true"; +defparam \F_acc[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N10 +cycloneive_lcell_comb \rom_address[0]~0 ( +// Equation(s): +// \rom_address[0]~0_combout = (\Pword[0]~input_o & (F_acc[16] $ (VCC))) # (!\Pword[0]~input_o & (F_acc[16] & VCC)) +// \rom_address[0]~1 = CARRY((\Pword[0]~input_o & F_acc[16])) + + .dataa(\Pword[0]~input_o ), + .datab(F_acc[16]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\rom_address[0]~0_combout ), + .cout(\rom_address[0]~1 )); +// synopsys translate_off +defparam \rom_address[0]~0 .lut_mask = 16'h6688; +defparam \rom_address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N8 +cycloneive_lcell_comb \F_acc[17]~60 ( +// Equation(s): +// \F_acc[17]~60_combout = (F_acc[17] & (!\F_acc[16]~59 )) # (!F_acc[17] & ((\F_acc[16]~59 ) # (GND))) +// \F_acc[17]~61 = CARRY((!\F_acc[16]~59 ) # (!F_acc[17])) + + .dataa(gnd), + .datab(F_acc[17]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[16]~59 ), + .combout(\F_acc[17]~60_combout ), + .cout(\F_acc[17]~61 )); +// synopsys translate_off +defparam \F_acc[17]~60 .lut_mask = 16'h3C3F; +defparam \F_acc[17]~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N9 +dffeas \F_acc[17] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[17]~60_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[17]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[17] .is_wysiwyg = "true"; +defparam \F_acc[17] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N22 +cycloneive_io_ibuf \Pword[1]~input ( + .i(Pword[1]), + .ibar(gnd), + .o(\Pword[1]~input_o )); +// synopsys translate_off +defparam \Pword[1]~input .bus_hold = "false"; +defparam \Pword[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N12 +cycloneive_lcell_comb \rom_address[1]~2 ( +// Equation(s): +// \rom_address[1]~2_combout = (F_acc[17] & ((\Pword[1]~input_o & (\rom_address[0]~1 & VCC)) # (!\Pword[1]~input_o & (!\rom_address[0]~1 )))) # (!F_acc[17] & ((\Pword[1]~input_o & (!\rom_address[0]~1 )) # (!\Pword[1]~input_o & ((\rom_address[0]~1 ) # +// (GND))))) +// \rom_address[1]~3 = CARRY((F_acc[17] & (!\Pword[1]~input_o & !\rom_address[0]~1 )) # (!F_acc[17] & ((!\rom_address[0]~1 ) # (!\Pword[1]~input_o )))) + + .dataa(F_acc[17]), + .datab(\Pword[1]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[0]~1 ), + .combout(\rom_address[1]~2_combout ), + .cout(\rom_address[1]~3 )); +// synopsys translate_off +defparam \rom_address[1]~2 .lut_mask = 16'h9617; +defparam \rom_address[1]~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N10 +cycloneive_lcell_comb \F_acc[18]~62 ( +// Equation(s): +// \F_acc[18]~62_combout = (F_acc[18] & (\F_acc[17]~61 $ (GND))) # (!F_acc[18] & (!\F_acc[17]~61 & VCC)) +// \F_acc[18]~63 = CARRY((F_acc[18] & !\F_acc[17]~61 )) + + .dataa(F_acc[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[17]~61 ), + .combout(\F_acc[18]~62_combout ), + .cout(\F_acc[18]~63 )); +// synopsys translate_off +defparam \F_acc[18]~62 .lut_mask = 16'hA50A; +defparam \F_acc[18]~62 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N11 +dffeas \F_acc[18] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[18]~62_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[18]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[18] .is_wysiwyg = "true"; +defparam \F_acc[18] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N1 +cycloneive_io_ibuf \Pword[2]~input ( + .i(Pword[2]), + .ibar(gnd), + .o(\Pword[2]~input_o )); +// synopsys translate_off +defparam \Pword[2]~input .bus_hold = "false"; +defparam \Pword[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N14 +cycloneive_lcell_comb \rom_address[2]~4 ( +// Equation(s): +// \rom_address[2]~4_combout = ((F_acc[18] $ (\Pword[2]~input_o $ (!\rom_address[1]~3 )))) # (GND) +// \rom_address[2]~5 = CARRY((F_acc[18] & ((\Pword[2]~input_o ) # (!\rom_address[1]~3 ))) # (!F_acc[18] & (\Pword[2]~input_o & !\rom_address[1]~3 ))) + + .dataa(F_acc[18]), + .datab(\Pword[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[1]~3 ), + .combout(\rom_address[2]~4_combout ), + .cout(\rom_address[2]~5 )); +// synopsys translate_off +defparam \rom_address[2]~4 .lut_mask = 16'h698E; +defparam \rom_address[2]~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N12 +cycloneive_lcell_comb \F_acc[19]~64 ( +// Equation(s): +// \F_acc[19]~64_combout = (F_acc[19] & (!\F_acc[18]~63 )) # (!F_acc[19] & ((\F_acc[18]~63 ) # (GND))) +// \F_acc[19]~65 = CARRY((!\F_acc[18]~63 ) # (!F_acc[19])) + + .dataa(F_acc[19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[18]~63 ), + .combout(\F_acc[19]~64_combout ), + .cout(\F_acc[19]~65 )); +// synopsys translate_off +defparam \F_acc[19]~64 .lut_mask = 16'h5A5F; +defparam \F_acc[19]~64 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N13 +dffeas \F_acc[19] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[19]~64_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[19]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[19] .is_wysiwyg = "true"; +defparam \F_acc[19] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N8 +cycloneive_io_ibuf \Pword[3]~input ( + .i(Pword[3]), + .ibar(gnd), + .o(\Pword[3]~input_o )); +// synopsys translate_off +defparam \Pword[3]~input .bus_hold = "false"; +defparam \Pword[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N16 +cycloneive_lcell_comb \rom_address[3]~6 ( +// Equation(s): +// \rom_address[3]~6_combout = (F_acc[19] & ((\Pword[3]~input_o & (\rom_address[2]~5 & VCC)) # (!\Pword[3]~input_o & (!\rom_address[2]~5 )))) # (!F_acc[19] & ((\Pword[3]~input_o & (!\rom_address[2]~5 )) # (!\Pword[3]~input_o & ((\rom_address[2]~5 ) # +// (GND))))) +// \rom_address[3]~7 = CARRY((F_acc[19] & (!\Pword[3]~input_o & !\rom_address[2]~5 )) # (!F_acc[19] & ((!\rom_address[2]~5 ) # (!\Pword[3]~input_o )))) + + .dataa(F_acc[19]), + .datab(\Pword[3]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[2]~5 ), + .combout(\rom_address[3]~6_combout ), + .cout(\rom_address[3]~7 )); +// synopsys translate_off +defparam \rom_address[3]~6 .lut_mask = 16'h9617; +defparam \rom_address[3]~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N14 +cycloneive_lcell_comb \F_acc[20]~66 ( +// Equation(s): +// \F_acc[20]~66_combout = (F_acc[20] & (\F_acc[19]~65 $ (GND))) # (!F_acc[20] & (!\F_acc[19]~65 & VCC)) +// \F_acc[20]~67 = CARRY((F_acc[20] & !\F_acc[19]~65 )) + + .dataa(gnd), + .datab(F_acc[20]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[19]~65 ), + .combout(\F_acc[20]~66_combout ), + .cout(\F_acc[20]~67 )); +// synopsys translate_off +defparam \F_acc[20]~66 .lut_mask = 16'hC30C; +defparam \F_acc[20]~66 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N15 +dffeas \F_acc[20] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[20]~66_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[20]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[20] .is_wysiwyg = "true"; +defparam \F_acc[20] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N22 +cycloneive_io_ibuf \Pword[4]~input ( + .i(Pword[4]), + .ibar(gnd), + .o(\Pword[4]~input_o )); +// synopsys translate_off +defparam \Pword[4]~input .bus_hold = "false"; +defparam \Pword[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N18 +cycloneive_lcell_comb \rom_address[4]~8 ( +// Equation(s): +// \rom_address[4]~8_combout = ((F_acc[20] $ (\Pword[4]~input_o $ (!\rom_address[3]~7 )))) # (GND) +// \rom_address[4]~9 = CARRY((F_acc[20] & ((\Pword[4]~input_o ) # (!\rom_address[3]~7 ))) # (!F_acc[20] & (\Pword[4]~input_o & !\rom_address[3]~7 ))) + + .dataa(F_acc[20]), + .datab(\Pword[4]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[3]~7 ), + .combout(\rom_address[4]~8_combout ), + .cout(\rom_address[4]~9 )); +// synopsys translate_off +defparam \rom_address[4]~8 .lut_mask = 16'h698E; +defparam \rom_address[4]~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N16 +cycloneive_lcell_comb \F_acc[21]~68 ( +// Equation(s): +// \F_acc[21]~68_combout = (F_acc[21] & (!\F_acc[20]~67 )) # (!F_acc[21] & ((\F_acc[20]~67 ) # (GND))) +// \F_acc[21]~69 = CARRY((!\F_acc[20]~67 ) # (!F_acc[21])) + + .dataa(gnd), + .datab(F_acc[21]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[20]~67 ), + .combout(\F_acc[21]~68_combout ), + .cout(\F_acc[21]~69 )); +// synopsys translate_off +defparam \F_acc[21]~68 .lut_mask = 16'h3C3F; +defparam \F_acc[21]~68 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N17 +dffeas \F_acc[21] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[21]~68_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[21]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[21] .is_wysiwyg = "true"; +defparam \F_acc[21] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N15 +cycloneive_io_ibuf \Pword[5]~input ( + .i(Pword[5]), + .ibar(gnd), + .o(\Pword[5]~input_o )); +// synopsys translate_off +defparam \Pword[5]~input .bus_hold = "false"; +defparam \Pword[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N20 +cycloneive_lcell_comb \rom_address[5]~10 ( +// Equation(s): +// \rom_address[5]~10_combout = (F_acc[21] & ((\Pword[5]~input_o & (\rom_address[4]~9 & VCC)) # (!\Pword[5]~input_o & (!\rom_address[4]~9 )))) # (!F_acc[21] & ((\Pword[5]~input_o & (!\rom_address[4]~9 )) # (!\Pword[5]~input_o & ((\rom_address[4]~9 ) # +// (GND))))) +// \rom_address[5]~11 = CARRY((F_acc[21] & (!\Pword[5]~input_o & !\rom_address[4]~9 )) # (!F_acc[21] & ((!\rom_address[4]~9 ) # (!\Pword[5]~input_o )))) + + .dataa(F_acc[21]), + .datab(\Pword[5]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[4]~9 ), + .combout(\rom_address[5]~10_combout ), + .cout(\rom_address[5]~11 )); +// synopsys translate_off +defparam \rom_address[5]~10 .lut_mask = 16'h9617; +defparam \rom_address[5]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N22 +cycloneive_io_ibuf \Pword[6]~input ( + .i(Pword[6]), + .ibar(gnd), + .o(\Pword[6]~input_o )); +// synopsys translate_off +defparam \Pword[6]~input .bus_hold = "false"; +defparam \Pword[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N18 +cycloneive_lcell_comb \F_acc[22]~70 ( +// Equation(s): +// \F_acc[22]~70_combout = (F_acc[22] & (\F_acc[21]~69 $ (GND))) # (!F_acc[22] & (!\F_acc[21]~69 & VCC)) +// \F_acc[22]~71 = CARRY((F_acc[22] & !\F_acc[21]~69 )) + + .dataa(gnd), + .datab(F_acc[22]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[21]~69 ), + .combout(\F_acc[22]~70_combout ), + .cout(\F_acc[22]~71 )); +// synopsys translate_off +defparam \F_acc[22]~70 .lut_mask = 16'hC30C; +defparam \F_acc[22]~70 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N19 +dffeas \F_acc[22] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[22]~70_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[22]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[22] .is_wysiwyg = "true"; +defparam \F_acc[22] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N22 +cycloneive_lcell_comb \rom_address[6]~12 ( +// Equation(s): +// \rom_address[6]~12_combout = ((\Pword[6]~input_o $ (F_acc[22] $ (!\rom_address[5]~11 )))) # (GND) +// \rom_address[6]~13 = CARRY((\Pword[6]~input_o & ((F_acc[22]) # (!\rom_address[5]~11 ))) # (!\Pword[6]~input_o & (F_acc[22] & !\rom_address[5]~11 ))) + + .dataa(\Pword[6]~input_o ), + .datab(F_acc[22]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[5]~11 ), + .combout(\rom_address[6]~12_combout ), + .cout(\rom_address[6]~13 )); +// synopsys translate_off +defparam \rom_address[6]~12 .lut_mask = 16'h698E; +defparam \rom_address[6]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y22_N15 +cycloneive_io_ibuf \Pword[7]~input ( + .i(Pword[7]), + .ibar(gnd), + .o(\Pword[7]~input_o )); +// synopsys translate_off +defparam \Pword[7]~input .bus_hold = "false"; +defparam \Pword[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N20 +cycloneive_lcell_comb \F_acc[23]~72 ( +// Equation(s): +// \F_acc[23]~72_combout = (F_acc[23] & (!\F_acc[22]~71 )) # (!F_acc[23] & ((\F_acc[22]~71 ) # (GND))) +// \F_acc[23]~73 = CARRY((!\F_acc[22]~71 ) # (!F_acc[23])) + + .dataa(gnd), + .datab(F_acc[23]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[22]~71 ), + .combout(\F_acc[23]~72_combout ), + .cout(\F_acc[23]~73 )); +// synopsys translate_off +defparam \F_acc[23]~72 .lut_mask = 16'h3C3F; +defparam \F_acc[23]~72 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N21 +dffeas \F_acc[23] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[23]~72_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[23]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[23] .is_wysiwyg = "true"; +defparam \F_acc[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N24 +cycloneive_lcell_comb \rom_address[7]~14 ( +// Equation(s): +// \rom_address[7]~14_combout = (\Pword[7]~input_o & ((F_acc[23] & (\rom_address[6]~13 & VCC)) # (!F_acc[23] & (!\rom_address[6]~13 )))) # (!\Pword[7]~input_o & ((F_acc[23] & (!\rom_address[6]~13 )) # (!F_acc[23] & ((\rom_address[6]~13 ) # (GND))))) +// \rom_address[7]~15 = CARRY((\Pword[7]~input_o & (!F_acc[23] & !\rom_address[6]~13 )) # (!\Pword[7]~input_o & ((!\rom_address[6]~13 ) # (!F_acc[23])))) + + .dataa(\Pword[7]~input_o ), + .datab(F_acc[23]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[6]~13 ), + .combout(\rom_address[7]~14_combout ), + .cout(\rom_address[7]~15 )); +// synopsys translate_off +defparam \rom_address[7]~14 .lut_mask = 16'h9617; +defparam \rom_address[7]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N15 +cycloneive_io_ibuf \Pword[8]~input ( + .i(Pword[8]), + .ibar(gnd), + .o(\Pword[8]~input_o )); +// synopsys translate_off +defparam \Pword[8]~input .bus_hold = "false"; +defparam \Pword[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N22 +cycloneive_lcell_comb \F_acc[24]~74 ( +// Equation(s): +// \F_acc[24]~74_combout = (F_acc[24] & (\F_acc[23]~73 $ (GND))) # (!F_acc[24] & (!\F_acc[23]~73 & VCC)) +// \F_acc[24]~75 = CARRY((F_acc[24] & !\F_acc[23]~73 )) + + .dataa(F_acc[24]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[23]~73 ), + .combout(\F_acc[24]~74_combout ), + .cout(\F_acc[24]~75 )); +// synopsys translate_off +defparam \F_acc[24]~74 .lut_mask = 16'hA50A; +defparam \F_acc[24]~74 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N23 +dffeas \F_acc[24] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[24]~74_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[24]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[24] .is_wysiwyg = "true"; +defparam \F_acc[24] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N26 +cycloneive_lcell_comb \rom_address[8]~16 ( +// Equation(s): +// \rom_address[8]~16_combout = ((\Pword[8]~input_o $ (F_acc[24] $ (!\rom_address[7]~15 )))) # (GND) +// \rom_address[8]~17 = CARRY((\Pword[8]~input_o & ((F_acc[24]) # (!\rom_address[7]~15 ))) # (!\Pword[8]~input_o & (F_acc[24] & !\rom_address[7]~15 ))) + + .dataa(\Pword[8]~input_o ), + .datab(F_acc[24]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[7]~15 ), + .combout(\rom_address[8]~16_combout ), + .cout(\rom_address[8]~17 )); +// synopsys translate_off +defparam \rom_address[8]~16 .lut_mask = 16'h698E; +defparam \rom_address[8]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N8 +cycloneive_io_ibuf \Pword[9]~input ( + .i(Pword[9]), + .ibar(gnd), + .o(\Pword[9]~input_o )); +// synopsys translate_off +defparam \Pword[9]~input .bus_hold = "false"; +defparam \Pword[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N24 +cycloneive_lcell_comb \F_acc[25]~76 ( +// Equation(s): +// \F_acc[25]~76_combout = \F_acc[24]~75 $ (F_acc[25]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(F_acc[25]), + .cin(\F_acc[24]~75 ), + .combout(\F_acc[25]~76_combout ), + .cout()); +// synopsys translate_off +defparam \F_acc[25]~76 .lut_mask = 16'h0FF0; +defparam \F_acc[25]~76 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N25 +dffeas \F_acc[25] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[25]~76_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[25]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[25] .is_wysiwyg = "true"; +defparam \F_acc[25] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N28 +cycloneive_lcell_comb \rom_address[9]~18 ( +// Equation(s): +// \rom_address[9]~18_combout = \Pword[9]~input_o $ (\rom_address[8]~17 $ (F_acc[25])) + + .dataa(gnd), + .datab(\Pword[9]~input_o ), + .datac(gnd), + .datad(F_acc[25]), + .cin(\rom_address[8]~17 ), + .combout(\rom_address[9]~18_combout ), + .cout()); +// synopsys translate_off +defparam \rom_address[9]~18 .lut_mask = 16'hC33C; +defparam \rom_address[9]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: M9K_X15_Y12_N0 +cycloneive_ram_block \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\clk_200m~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(vcc), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(9'b000000000), + .portaaddr({\rom_address[9]~18_combout ,\rom_address[8]~16_combout ,\rom_address[7]~14_combout ,\rom_address[6]~12_combout ,\rom_address[5]~10_combout ,\rom_address[4]~8_combout ,\rom_address[3]~6_combout ,\rom_address[2]~4_combout ,\rom_address[1]~2_combout , +\rom_address[0]~0_combout }), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr(10'b0000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .init_file = "sin9bit_1024.mif"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ALTSYNCRAM"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 10; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 1023; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 1024; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 10; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init4 = 1024'h7F3F1F6F97C3D9EAF3793C1DEED763A9D2E773395C6E27037DBADC6D365AED66AB4DA4D067B3598CA64B218CC561B0980BF5F2F176B95C2DD6AB4592C560AE56AAD54A953A994AA3512813E9E4E26D34984BA592893492411E8E46A2D148943A190A8441205007F3E9F0F67A3C1DCEC753A1C8E270379B8DA6B351A4D0673319; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h0C66230980BE5E2E970B65A2C15CAC552A14CA4512813C9C4D2612C94492411C8C45229108642209007E3E1E8F0783B1D0E470371B8D86A34198CC6431180C05E2E168B4582B158A852291409C4E2612894482411888442110880401F0F8783C1D0E870381B0D86834190C86030180B85C2E160B0542A150A85028140984C26130904824120884422110884020100804020100803C1E0F0783C1E0F0783C1E0F0783C1E0F0783C1E0F0783C20100804020100804022110884422120904824130984C26140A0502A150A8542C160B85C2E180C06032190D068361B0E0703A1D0F0783E1F100804221110884624120944A261389C5029148A8562B160B45A2E178; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'hC06031190CC66341A8D86E371C0E4743B1E0F07A3E1F9008242219108A452311C90492512C984D2713CA0512914CA8552B15CB05A2D970BA5E2F980C26231990CC67341A4D46B369B8DE70389C8E8753B1DCF07A3D9F0FA7F40205048442A190E894522D1A8E47A4124934A2592E984D26D389E4FA8144A352A994EA9552AD5AAE582C564B45AADD70B95DAF17CBF6030986C56332192CA663359ED06934DAAD66BB65B4DC6EB7DC0E271B95CCE774BA9D8ED77BC1E4F37ABD9F0F97DBF1FCFF8040A070583422130B8643A1F11894522B178C466371C8F47E4322924964F2894CAE592E97CC665349ACDA71399DCF27D3FA050A8745A351E934AA65369D50A8; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'hD4EA955ABD62B35BAE57ABF60B158EC966B3DA2D56BB65BADF70B8DCEE975BBDE2F37ABE5F6FD7FC0E0B0784C361F1189C56331B8EC7E432393CA6572D97CC66B379CCEE7B3FA0D0E8B47A4D369F51A9D56AF59ADD76BF61B1D96CF69B5DB6DF71B9DCEEB77BCDEEFB7FC0E0F0B85C3E27178DC7E3F2393CAE5F2F99CDE773B9FD0E8F47A5D3E9F53ABD5EB75FAFD8ECF67B5DAEDF73B9DDEEF7BBDDFEFF83C1E1F0F8BC5E3F1F93C9E5F2F9BCDE6F3F9FCFE8F47A7D3E9F4FABD5EAF5FAFD7EBF67B3D9ECF6FB7DBEDF6FBBDDEEF77BBDDEEF77BFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDDEEF77BBDDEEF77BBDBEDF6FB7DBECF67B3D9EBF; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h5FAFD7EAF57ABD3E9F4FA7D1E8F3F9FCFE6F379BCBE5F2793C7E3F178BC3E1F0783BFDFEF77BBBDDEE773B7DAED767B3D8EBF5FADD5EAF53A7D3E9747A3D0E7F3B9DCDE672F97CAE4F238FC7E371789C3E170B83C0DFEFB7BBCDDEEB73B9DC6DF6DB5DA6CF65B1D86BF5DADD66AF55A9D469F4DA4D1E8B43A0CFE7B3B9CCDE6B3197CB6572993C8E431F8EC6E331589C461F0D84C1E0B037FBF5F6F97ABCDE2EF75BA5CEE370B7DBAD96BB55A2CF66B258EC560AFD7AB95BACD62AF55AA54EA350A7536994AA4D1E8D45A1D0A813F9F4F277399C4DA6B34994C65F2E964AE532893C96492290C7E3D1C8DC6631178AC52251187C3A190B84C220D0581C0A00FF; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N20 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][11]~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][11]~0_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [7] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [4]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [6]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [5])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][11]~0 .lut_mask = 16'hCCC8; +defparam \modulation|Mult0|mult_core|romout[1][11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][10] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][10]~combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [6] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [4] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [7])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [6] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [7]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][10]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][10] .lut_mask = 16'hC1C8; +defparam \modulation|Mult0|mult_core|romout[1][10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][9] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][9]~combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [4] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (\spwm_sin|altsyncram_component|auto_generated|q_a [6] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [5])) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [6]) # (\spwm_sin|altsyncram_component|auto_generated|q_a [7])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][9]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][9] .lut_mask = 16'h0AD4; +defparam \modulation|Mult0|mult_core|romout[1][9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][8]~1 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][8]~1_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (\spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (((!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [6]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [6])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][8]~1 .lut_mask = 16'hA856; +defparam \modulation|Mult0|mult_core|romout[1][8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N30 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][11]~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][11]~2_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][11]~2_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][11]~2 .lut_mask = 16'hCCC8; +defparam \modulation|Mult0|mult_core|romout[0][11]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N4 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][7] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][7]~combout = \spwm_sin|altsyncram_component|auto_generated|q_a [6] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # ((!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [4])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][7]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][7] .lut_mask = 16'h45BA; +defparam \modulation|Mult0|mult_core|romout[1][7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][6] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][6]~combout = \spwm_sin|altsyncram_component|auto_generated|q_a [5] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [4] & !\spwm_sin|altsyncram_component|auto_generated|q_a [7]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(gnd), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][6]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][6] .lut_mask = 16'hF50A; +defparam \modulation|Mult0|mult_core|romout[1][6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N28 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][10]~3 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][10]~3_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [2] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [0])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [2] & (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [0]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][10]~3 .lut_mask = 16'hA2A4; +defparam \modulation|Mult0|mult_core|romout[0][10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N26 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][9]~5 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][9]~5_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [1] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [0]))) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & (\spwm_sin|altsyncram_component|auto_generated|q_a [2] & !\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][9]~5_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][9]~5 .lut_mask = 16'h380E; +defparam \modulation|Mult0|mult_core|romout[0][9]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][5]~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][5]~4_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (\spwm_sin|altsyncram_component|auto_generated|q_a [7]) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(gnd), + .datac(gnd), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][5]~4_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][5]~4 .lut_mask = 16'h55AA; +defparam \modulation|Mult0|mult_core|romout[1][5]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][8]~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][8]~6_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (\spwm_sin|altsyncram_component|auto_generated|q_a [0] $ (((!\spwm_sin|altsyncram_component|auto_generated|q_a [2] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [1]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [0] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [1])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][8]~6_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][8]~6 .lut_mask = 16'hC836; +defparam \modulation|Mult0|mult_core|romout[0][8]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N2 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][7]~7 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][7]~7_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [2] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [0] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [3])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][7]~7 .lut_mask = 16'h0DF2; +defparam \modulation|Mult0|mult_core|romout[0][7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][6]~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][6]~8_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [1] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [0] & !\spwm_sin|altsyncram_component|auto_generated|q_a [3]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(gnd), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][6]~8 .lut_mask = 16'hDD22; +defparam \modulation|Mult0|mult_core|romout[0][6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N6 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout = (\modulation|Mult0|mult_core|romout[0][6]~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (VCC))) # (!\modulation|Mult0|mult_core|romout[0][6]~8_combout & +// (\spwm_sin|altsyncram_component|auto_generated|q_a [4] & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 = CARRY((\modulation|Mult0|mult_core|romout[0][6]~8_combout & \spwm_sin|altsyncram_component|auto_generated|q_a [4])) + + .dataa(\modulation|Mult0|mult_core|romout[0][6]~8_combout ), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\modulation|Mult0|mult_core|romout[0][7]~7_combout & +// (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 & VCC)) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )))) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\modulation|Mult0|mult_core|romout[0][7]~7_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & +// ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [5] & (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 +// )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datab(\modulation|Mult0|mult_core|romout[0][7]~7_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout = ((\spwm_sin|altsyncram_component|auto_generated|q_a [6] $ (\modulation|Mult0|mult_core|romout[0][8]~6_combout $ +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 )))) # (GND) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [6] & ((\modulation|Mult0|mult_core|romout[0][8]~6_combout ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [6] & (\modulation|Mult0|mult_core|romout[0][8]~6_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 +// ))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datab(\modulation|Mult0|mult_core|romout[0][8]~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N12 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout = (\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((\modulation|Mult0|mult_core|romout[1][5]~4_combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 +// & VCC)) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )))) # (!\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((\modulation|Mult0|mult_core|romout[1][5]~4_combout & +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 = CARRY((\modulation|Mult0|mult_core|romout[0][9]~5_combout & (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )) +// # (!\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout )))) + + .dataa(\modulation|Mult0|mult_core|romout[0][9]~5_combout ), + .datab(\modulation|Mult0|mult_core|romout[1][5]~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N14 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout = ((\modulation|Mult0|mult_core|romout[1][6]~combout $ (\modulation|Mult0|mult_core|romout[0][10]~3_combout $ (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 +// )))) # (GND) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 = CARRY((\modulation|Mult0|mult_core|romout[1][6]~combout & ((\modulation|Mult0|mult_core|romout[0][10]~3_combout ) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 +// ))) # (!\modulation|Mult0|mult_core|romout[1][6]~combout & (\modulation|Mult0|mult_core|romout[0][10]~3_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ))) + + .dataa(\modulation|Mult0|mult_core|romout[1][6]~combout ), + .datab(\modulation|Mult0|mult_core|romout[0][10]~3_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N16 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout = (\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((\modulation|Mult0|mult_core|romout[1][7]~combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 +// & VCC)) # (!\modulation|Mult0|mult_core|romout[1][7]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )))) # (!\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((\modulation|Mult0|mult_core|romout[1][7]~combout & +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )) # (!\modulation|Mult0|mult_core|romout[1][7]~combout & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 = CARRY((\modulation|Mult0|mult_core|romout[0][11]~2_combout & (!\modulation|Mult0|mult_core|romout[1][7]~combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )) +// # (!\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (!\modulation|Mult0|mult_core|romout[1][7]~combout )))) + + .dataa(\modulation|Mult0|mult_core|romout[0][11]~2_combout ), + .datab(\modulation|Mult0|mult_core|romout[1][7]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N18 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout = (\modulation|Mult0|mult_core|romout[1][8]~1_combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 $ (GND))) # +// (!\modulation|Mult0|mult_core|romout[1][8]~1_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 = CARRY((\modulation|Mult0|mult_core|romout[1][8]~1_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 )) + + .dataa(\modulation|Mult0|mult_core|romout[1][8]~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 .lut_mask = 16'hA50A; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N20 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout = (\modulation|Mult0|mult_core|romout[1][9]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 )) # (!\modulation|Mult0|mult_core|romout[1][9]~combout +// & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ) # (GND))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 = CARRY((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ) # (!\modulation|Mult0|mult_core|romout[1][9]~combout )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|romout[1][9]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 .lut_mask = 16'h3C3F; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N22 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout = (\modulation|Mult0|mult_core|romout[1][10]~combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 $ (GND))) # +// (!\modulation|Mult0|mult_core|romout[1][10]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 = CARRY((\modulation|Mult0|mult_core|romout[1][10]~combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|romout[1][10]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 .lut_mask = 16'hC30C; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N24 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout = \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 $ (\modulation|Mult0|mult_core|romout[1][11]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\modulation|Mult0|mult_core|romout[1][11]~0_combout ), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 .lut_mask = 16'h0FF0; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [8] $ (VCC))) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & VCC)) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & \spwm_sin|altsyncram_component|auto_generated|q_a [8])) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N2 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # (GND))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 = CARRY((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout )) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h5A5F; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N4 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 $ +// (GND))) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 & VCC)) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .lut_mask = 16'hC30C; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N6 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 & VCC)) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )))) +// # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout = ((\spwm_sin|altsyncram_component|auto_generated|q_a [8] $ (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout $ +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )))) # (GND) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 & VCC)) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )))) +// # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N12 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout = !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .lut_mask = 16'h0F0F; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \modulation|LessThan0~0 ( +// Equation(s): +// \modulation|LessThan0~0_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [0]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [3]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .cin(gnd), + .combout(\modulation|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~0 .lut_mask = 16'hFFFE; +defparam \modulation|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \modulation|LessThan0~1 ( +// Equation(s): +// \modulation|LessThan0~1_combout = (\modulation|LessThan0~0_combout ) # ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ) # (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout )) + + .dataa(gnd), + .datab(\modulation|LessThan0~0_combout ), + .datac(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ), + .datad(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ), + .cin(gnd), + .combout(\modulation|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~1 .lut_mask = 16'hFFFC; +defparam \modulation|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \modulation|LessThan0~3 ( +// Equation(s): +// \modulation|LessThan0~3_cout = CARRY(\modulation|LessThan0~1_combout ) + + .dataa(gnd), + .datab(\modulation|LessThan0~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\modulation|LessThan0~3_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~3 .lut_mask = 16'h00CC; +defparam \modulation|LessThan0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \modulation|LessThan0~5 ( +// Equation(s): +// \modulation|LessThan0~5_cout = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout & (\tri_out[0]~reg0_q & !\modulation|LessThan0~3_cout )) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout & +// ((\tri_out[0]~reg0_q ) # (!\modulation|LessThan0~3_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ), + .datab(\tri_out[0]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~3_cout ), + .combout(), + .cout(\modulation|LessThan0~5_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~5 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \modulation|LessThan0~7 ( +// Equation(s): +// \modulation|LessThan0~7_cout = CARRY((\tri_out[1]~reg0_q & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout & !\modulation|LessThan0~5_cout )) # (!\tri_out[1]~reg0_q & +// ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ) # (!\modulation|LessThan0~5_cout )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~5_cout ), + .combout(), + .cout(\modulation|LessThan0~7_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~7 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \modulation|LessThan0~9 ( +// Equation(s): +// \modulation|LessThan0~9_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout & (\tri_out[2]~reg0_q & !\modulation|LessThan0~7_cout )) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout & ((\tri_out[2]~reg0_q ) # (!\modulation|LessThan0~7_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ), + .datab(\tri_out[2]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~7_cout ), + .combout(), + .cout(\modulation|LessThan0~9_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~9 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \modulation|LessThan0~11 ( +// Equation(s): +// \modulation|LessThan0~11_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout & ((!\modulation|LessThan0~9_cout ) # (!\tri_out[3]~reg0_q ))) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout & (!\tri_out[3]~reg0_q & !\modulation|LessThan0~9_cout ))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ), + .datab(\tri_out[3]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~9_cout ), + .combout(), + .cout(\modulation|LessThan0~11_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~11 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \modulation|LessThan0~13 ( +// Equation(s): +// \modulation|LessThan0~13_cout = CARRY((\tri_out[4]~reg0_q & ((!\modulation|LessThan0~11_cout ) # (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ))) # (!\tri_out[4]~reg0_q & +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout & !\modulation|LessThan0~11_cout ))) + + .dataa(\tri_out[4]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~11_cout ), + .combout(), + .cout(\modulation|LessThan0~13_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~13 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \modulation|LessThan0~15 ( +// Equation(s): +// \modulation|LessThan0~15_cout = CARRY((\tri_out[5]~reg0_q & (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout & !\modulation|LessThan0~13_cout )) # (!\tri_out[5]~reg0_q & +// ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (!\modulation|LessThan0~13_cout )))) + + .dataa(\tri_out[5]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~13_cout ), + .combout(), + .cout(\modulation|LessThan0~15_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~15 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \modulation|LessThan0~17 ( +// Equation(s): +// \modulation|LessThan0~17_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout & (\tri_out[6]~reg0_q & !\modulation|LessThan0~15_cout )) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout & ((\tri_out[6]~reg0_q ) # (!\modulation|LessThan0~15_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ), + .datab(\tri_out[6]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~15_cout ), + .combout(), + .cout(\modulation|LessThan0~17_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~17 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \modulation|LessThan0~19 ( +// Equation(s): +// \modulation|LessThan0~19_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout & ((!\modulation|LessThan0~17_cout ) # (!\tri_out[7]~reg0_q ))) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout & (!\tri_out[7]~reg0_q & !\modulation|LessThan0~17_cout ))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ), + .datab(\tri_out[7]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~17_cout ), + .combout(), + .cout(\modulation|LessThan0~19_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~19 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \modulation|LessThan0~20 ( +// Equation(s): +// \modulation|LessThan0~20_combout = (\tri_out[8]~reg0_q & (\modulation|LessThan0~19_cout & \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout )) # (!\tri_out[8]~reg0_q & ((\modulation|LessThan0~19_cout ) # +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ))) + + .dataa(gnd), + .datab(\tri_out[8]~reg0_q ), + .datac(gnd), + .datad(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ), + .cin(\modulation|LessThan0~19_cout ), + .combout(\modulation|LessThan0~20_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~20 .lut_mask = 16'hF330; +defparam \modulation|LessThan0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y12_N23 +dffeas \modulation|out ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\modulation|LessThan0~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\modulation|out~q ), + .prn(vcc)); +// synopsys translate_off +defparam \modulation|out .is_wysiwyg = "true"; +defparam \modulation|out .power_up = "low"; +// synopsys translate_on + +assign tri_out[0] = \tri_out[0]~output_o ; + +assign tri_out[1] = \tri_out[1]~output_o ; + +assign tri_out[2] = \tri_out[2]~output_o ; + +assign tri_out[3] = \tri_out[3]~output_o ; + +assign tri_out[4] = \tri_out[4]~output_o ; + +assign tri_out[5] = \tri_out[5]~output_o ; + +assign tri_out[6] = \tri_out[6]~output_o ; + +assign tri_out[7] = \tri_out[7]~output_o ; + +assign tri_out[8] = \tri_out[8]~output_o ; + +assign sin_out[0] = \sin_out[0]~output_o ; + +assign sin_out[1] = \sin_out[1]~output_o ; + +assign sin_out[2] = \sin_out[2]~output_o ; + +assign sin_out[3] = \sin_out[3]~output_o ; + +assign sin_out[4] = \sin_out[4]~output_o ; + +assign sin_out[5] = \sin_out[5]~output_o ; + +assign sin_out[6] = \sin_out[6]~output_o ; + +assign sin_out[7] = \sin_out[7]~output_o ; + +assign sin_out[8] = \sin_out[8]~output_o ; + +assign spwm_out = \spwm_out~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_DATA0~~ibuf_o ; + + +endmodule diff --git a/spwm/simulation/modelsim/spwm_8_1200mv_0c_slow.vo b/spwm/simulation/modelsim/spwm_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..1589b86 --- /dev/null +++ b/spwm/simulation/modelsim/spwm_8_1200mv_0c_slow.vo @@ -0,0 +1,3398 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" + +// DATE "12/10/2018 20:55:31" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module spwm ( + clk_200m, + rst_n, + tri_out, + sin_out, + Fword, + Pword, + spwm_out); +input clk_200m; +input rst_n; +output [8:0] tri_out; +output [8:0] sin_out; +input [15:0] Fword; +input [9:0] Pword; +output spwm_out; + +// Design Ports Information +// tri_out[0] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[1] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[2] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[3] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[4] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[5] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[6] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[7] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[8] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[0] => Location: PIN_M8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[1] => Location: PIN_J6, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[2] => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[3] => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[4] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[5] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[6] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[7] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[8] => Location: PIN_R8, I/O Standard: 2.5 V, Current Strength: Default +// spwm_out => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +// clk_200m => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[0] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// Pword[1] => Location: PIN_D1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[2] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// Pword[3] => Location: PIN_F3, I/O Standard: 2.5 V, Current Strength: Default +// Pword[4] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[5] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// Pword[6] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[7] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[8] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[9] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[15] => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[14] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// Fword[13] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +// Fword[12] => Location: PIN_A2, I/O Standard: 2.5 V, Current Strength: Default +// Fword[11] => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[10] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[9] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[8] => Location: PIN_A3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[7] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default +// Fword[6] => Location: PIN_D3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[5] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// Fword[4] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[3] => Location: PIN_D5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[2] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// Fword[1] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[0] => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("spwm_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \tri_out[0]~output_o ; +wire \tri_out[1]~output_o ; +wire \tri_out[2]~output_o ; +wire \tri_out[3]~output_o ; +wire \tri_out[4]~output_o ; +wire \tri_out[5]~output_o ; +wire \tri_out[6]~output_o ; +wire \tri_out[7]~output_o ; +wire \tri_out[8]~output_o ; +wire \sin_out[0]~output_o ; +wire \sin_out[1]~output_o ; +wire \sin_out[2]~output_o ; +wire \sin_out[3]~output_o ; +wire \sin_out[4]~output_o ; +wire \sin_out[5]~output_o ; +wire \sin_out[6]~output_o ; +wire \sin_out[7]~output_o ; +wire \sin_out[8]~output_o ; +wire \spwm_out~output_o ; +wire \clk_200m~input_o ; +wire \clk_200m~inputclkctrl_outclk ; +wire \tri_out[0]~9_combout ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \tri_out[0]~reg0_q ; +wire \tri_out[0]~10 ; +wire \tri_out[1]~16 ; +wire \tri_out[2]~17_combout ; +wire \tri_out[2]~reg0_q ; +wire \tri_out[2]~18 ; +wire \tri_out[3]~19_combout ; +wire \tri_out[3]~reg0_q ; +wire \tri_out[3]~20 ; +wire \tri_out[4]~21_combout ; +wire \tri_out[4]~reg0_q ; +wire \tri_out[4]~22 ; +wire \tri_out[5]~23_combout ; +wire \tri_out[5]~reg0_q ; +wire \tri_out[5]~24 ; +wire \tri_out[6]~25_combout ; +wire \tri_out[6]~reg0_q ; +wire \tri_out[6]~26 ; +wire \tri_out[7]~27_combout ; +wire \tri_out[7]~reg0_q ; +wire \tri_out[7]~28 ; +wire \tri_out[8]~29_combout ; +wire \tri_out[8]~reg0_q ; +wire \tri_out~12_combout ; +wire \tri_out~11_combout ; +wire \updown~q ; +wire \tri_out~13_combout ; +wire \tri_out~14_combout ; +wire \tri_out[1]~15_combout ; +wire \tri_out[1]~reg0_q ; +wire \Pword[0]~input_o ; +wire \Fword[15]~input_o ; +wire \Fword[14]~input_o ; +wire \Fword[13]~input_o ; +wire \Fword[12]~input_o ; +wire \Fword[11]~input_o ; +wire \Fword[10]~input_o ; +wire \Fword[9]~input_o ; +wire \Fword[8]~input_o ; +wire \Fword[7]~input_o ; +wire \Fword[6]~input_o ; +wire \Fword[5]~input_o ; +wire \Fword[4]~input_o ; +wire \Fword[3]~input_o ; +wire \Fword[2]~input_o ; +wire \Fword[1]~input_o ; +wire \Fword[0]~input_o ; +wire \F_acc[0]~26_combout ; +wire \F_acc[0]~27 ; +wire \F_acc[1]~28_combout ; +wire \F_acc[1]~29 ; +wire \F_acc[2]~30_combout ; +wire \F_acc[2]~31 ; +wire \F_acc[3]~32_combout ; +wire \F_acc[3]~33 ; +wire \F_acc[4]~34_combout ; +wire \F_acc[4]~35 ; +wire \F_acc[5]~36_combout ; +wire \F_acc[5]~37 ; +wire \F_acc[6]~38_combout ; +wire \F_acc[6]~39 ; +wire \F_acc[7]~40_combout ; +wire \F_acc[7]~41 ; +wire \F_acc[8]~42_combout ; +wire \F_acc[8]~43 ; +wire \F_acc[9]~44_combout ; +wire \F_acc[9]~45 ; +wire \F_acc[10]~46_combout ; +wire \F_acc[10]~47 ; +wire \F_acc[11]~48_combout ; +wire \F_acc[11]~49 ; +wire \F_acc[12]~50_combout ; +wire \F_acc[12]~51 ; +wire \F_acc[13]~52_combout ; +wire \F_acc[13]~53 ; +wire \F_acc[14]~54_combout ; +wire \F_acc[14]~55 ; +wire \F_acc[15]~56_combout ; +wire \F_acc[15]~57 ; +wire \F_acc[16]~58_combout ; +wire \rom_address[0]~0_combout ; +wire \F_acc[16]~59 ; +wire \F_acc[17]~60_combout ; +wire \Pword[1]~input_o ; +wire \rom_address[0]~1 ; +wire \rom_address[1]~2_combout ; +wire \F_acc[17]~61 ; +wire \F_acc[18]~62_combout ; +wire \Pword[2]~input_o ; +wire \rom_address[1]~3 ; +wire \rom_address[2]~4_combout ; +wire \F_acc[18]~63 ; +wire \F_acc[19]~64_combout ; +wire \Pword[3]~input_o ; +wire \rom_address[2]~5 ; +wire \rom_address[3]~6_combout ; +wire \F_acc[19]~65 ; +wire \F_acc[20]~66_combout ; +wire \Pword[4]~input_o ; +wire \rom_address[3]~7 ; +wire \rom_address[4]~8_combout ; +wire \F_acc[20]~67 ; +wire \F_acc[21]~68_combout ; +wire \Pword[5]~input_o ; +wire \rom_address[4]~9 ; +wire \rom_address[5]~10_combout ; +wire \Pword[6]~input_o ; +wire \F_acc[21]~69 ; +wire \F_acc[22]~70_combout ; +wire \rom_address[5]~11 ; +wire \rom_address[6]~12_combout ; +wire \Pword[7]~input_o ; +wire \F_acc[22]~71 ; +wire \F_acc[23]~72_combout ; +wire \rom_address[6]~13 ; +wire \rom_address[7]~14_combout ; +wire \Pword[8]~input_o ; +wire \F_acc[23]~73 ; +wire \F_acc[24]~74_combout ; +wire \rom_address[7]~15 ; +wire \rom_address[8]~16_combout ; +wire \Pword[9]~input_o ; +wire \F_acc[24]~75 ; +wire \F_acc[25]~76_combout ; +wire \rom_address[8]~17 ; +wire \rom_address[9]~18_combout ; +wire \modulation|Mult0|mult_core|romout[1][11]~0_combout ; +wire \modulation|Mult0|mult_core|romout[1][10]~combout ; +wire \modulation|Mult0|mult_core|romout[1][9]~combout ; +wire \modulation|Mult0|mult_core|romout[1][8]~1_combout ; +wire \modulation|Mult0|mult_core|romout[0][11]~2_combout ; +wire \modulation|Mult0|mult_core|romout[1][7]~combout ; +wire \modulation|Mult0|mult_core|romout[1][6]~combout ; +wire \modulation|Mult0|mult_core|romout[0][10]~3_combout ; +wire \modulation|Mult0|mult_core|romout[0][9]~5_combout ; +wire \modulation|Mult0|mult_core|romout[1][5]~4_combout ; +wire \modulation|Mult0|mult_core|romout[0][8]~6_combout ; +wire \modulation|Mult0|mult_core|romout[0][7]~7_combout ; +wire \modulation|Mult0|mult_core|romout[0][6]~8_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ; +wire \modulation|LessThan0~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ; +wire \modulation|LessThan0~1_combout ; +wire \modulation|LessThan0~3_cout ; +wire \modulation|LessThan0~5_cout ; +wire \modulation|LessThan0~7_cout ; +wire \modulation|LessThan0~9_cout ; +wire \modulation|LessThan0~11_cout ; +wire \modulation|LessThan0~13_cout ; +wire \modulation|LessThan0~15_cout ; +wire \modulation|LessThan0~17_cout ; +wire \modulation|LessThan0~19_cout ; +wire \modulation|LessThan0~20_combout ; +wire \modulation|out~q ; +wire [8:0] \spwm_sin|altsyncram_component|auto_generated|q_a ; +wire [25:0] F_acc; + +wire [8:0] \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; + +assign \spwm_sin|altsyncram_component|auto_generated|q_a [0] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [1] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [2] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [3] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [4] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [5] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [6] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [7] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [8] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [8]; + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: IOOBUF_X13_Y24_N23 +cycloneive_io_obuf \tri_out[0]~output ( + .i(\tri_out[0]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[0]~output .bus_hold = "false"; +defparam \tri_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N2 +cycloneive_io_obuf \tri_out[1]~output ( + .i(\tri_out[1]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[1]~output .bus_hold = "false"; +defparam \tri_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N23 +cycloneive_io_obuf \tri_out[2]~output ( + .i(\tri_out[2]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[2]~output .bus_hold = "false"; +defparam \tri_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N16 +cycloneive_io_obuf \tri_out[3]~output ( + .i(\tri_out[3]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[3]~output .bus_hold = "false"; +defparam \tri_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N9 +cycloneive_io_obuf \tri_out[4]~output ( + .i(\tri_out[4]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[4]~output .bus_hold = "false"; +defparam \tri_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N16 +cycloneive_io_obuf \tri_out[5]~output ( + .i(\tri_out[5]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[5]~output .bus_hold = "false"; +defparam \tri_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N9 +cycloneive_io_obuf \tri_out[6]~output ( + .i(\tri_out[6]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[6]~output .bus_hold = "false"; +defparam \tri_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N16 +cycloneive_io_obuf \tri_out[7]~output ( + .i(\tri_out[7]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[7]~output .bus_hold = "false"; +defparam \tri_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N2 +cycloneive_io_obuf \tri_out[8]~output ( + .i(\tri_out[8]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[8]~output .bus_hold = "false"; +defparam \tri_out[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y0_N2 +cycloneive_io_obuf \sin_out[0]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[0]~output .bus_hold = "false"; +defparam \sin_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N23 +cycloneive_io_obuf \sin_out[1]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[1]~output .bus_hold = "false"; +defparam \sin_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N9 +cycloneive_io_obuf \sin_out[2]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[2]~output .bus_hold = "false"; +defparam \sin_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N2 +cycloneive_io_obuf \sin_out[3]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[3]~output .bus_hold = "false"; +defparam \sin_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N23 +cycloneive_io_obuf \sin_out[4]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[4]~output .bus_hold = "false"; +defparam \sin_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N2 +cycloneive_io_obuf \sin_out[5]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[5]~output .bus_hold = "false"; +defparam \sin_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N16 +cycloneive_io_obuf \sin_out[6]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[6]~output .bus_hold = "false"; +defparam \sin_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N16 +cycloneive_io_obuf \sin_out[7]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[7]~output .bus_hold = "false"; +defparam \sin_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N9 +cycloneive_io_obuf \sin_out[8]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[8]~output .bus_hold = "false"; +defparam \sin_out[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y0_N16 +cycloneive_io_obuf \spwm_out~output ( + .i(\modulation|out~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\spwm_out~output_o ), + .obar()); +// synopsys translate_off +defparam \spwm_out~output .bus_hold = "false"; +defparam \spwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk_200m~input ( + .i(clk_200m), + .ibar(gnd), + .o(\clk_200m~input_o )); +// synopsys translate_off +defparam \clk_200m~input .bus_hold = "false"; +defparam \clk_200m~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk_200m~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_200m~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_200m~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk_200m~inputclkctrl .clock_type = "global clock"; +defparam \clk_200m~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N10 +cycloneive_lcell_comb \tri_out[0]~9 ( +// Equation(s): +// \tri_out[0]~9_combout = \tri_out[0]~reg0_q $ (VCC) +// \tri_out[0]~10 = CARRY(\tri_out[0]~reg0_q ) + + .dataa(\tri_out[0]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\tri_out[0]~9_combout ), + .cout(\tri_out[0]~10 )); +// synopsys translate_off +defparam \tri_out[0]~9 .lut_mask = 16'h55AA; +defparam \tri_out[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X14_Y19_N11 +dffeas \tri_out[0]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[0]~9_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[0]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[0]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[0]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N12 +cycloneive_lcell_comb \tri_out[1]~15 ( +// Equation(s): +// \tri_out[1]~15_combout = (\tri_out[1]~reg0_q & ((\tri_out~14_combout & (\tri_out[0]~10 & VCC)) # (!\tri_out~14_combout & (!\tri_out[0]~10 )))) # (!\tri_out[1]~reg0_q & ((\tri_out~14_combout & (!\tri_out[0]~10 )) # (!\tri_out~14_combout & +// ((\tri_out[0]~10 ) # (GND))))) +// \tri_out[1]~16 = CARRY((\tri_out[1]~reg0_q & (!\tri_out~14_combout & !\tri_out[0]~10 )) # (!\tri_out[1]~reg0_q & ((!\tri_out[0]~10 ) # (!\tri_out~14_combout )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\tri_out~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[0]~10 ), + .combout(\tri_out[1]~15_combout ), + .cout(\tri_out[1]~16 )); +// synopsys translate_off +defparam \tri_out[1]~15 .lut_mask = 16'h9617; +defparam \tri_out[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N14 +cycloneive_lcell_comb \tri_out[2]~17 ( +// Equation(s): +// \tri_out[2]~17_combout = ((\tri_out~14_combout $ (\tri_out[2]~reg0_q $ (!\tri_out[1]~16 )))) # (GND) +// \tri_out[2]~18 = CARRY((\tri_out~14_combout & ((\tri_out[2]~reg0_q ) # (!\tri_out[1]~16 ))) # (!\tri_out~14_combout & (\tri_out[2]~reg0_q & !\tri_out[1]~16 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[2]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[1]~16 ), + .combout(\tri_out[2]~17_combout ), + .cout(\tri_out[2]~18 )); +// synopsys translate_off +defparam \tri_out[2]~17 .lut_mask = 16'h698E; +defparam \tri_out[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N15 +dffeas \tri_out[2]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[2]~17_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[2]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[2]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[2]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N16 +cycloneive_lcell_comb \tri_out[3]~19 ( +// Equation(s): +// \tri_out[3]~19_combout = (\tri_out~14_combout & ((\tri_out[3]~reg0_q & (\tri_out[2]~18 & VCC)) # (!\tri_out[3]~reg0_q & (!\tri_out[2]~18 )))) # (!\tri_out~14_combout & ((\tri_out[3]~reg0_q & (!\tri_out[2]~18 )) # (!\tri_out[3]~reg0_q & +// ((\tri_out[2]~18 ) # (GND))))) +// \tri_out[3]~20 = CARRY((\tri_out~14_combout & (!\tri_out[3]~reg0_q & !\tri_out[2]~18 )) # (!\tri_out~14_combout & ((!\tri_out[2]~18 ) # (!\tri_out[3]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[3]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[2]~18 ), + .combout(\tri_out[3]~19_combout ), + .cout(\tri_out[3]~20 )); +// synopsys translate_off +defparam \tri_out[3]~19 .lut_mask = 16'h9617; +defparam \tri_out[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N17 +dffeas \tri_out[3]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[3]~19_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[3]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[3]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[3]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N18 +cycloneive_lcell_comb \tri_out[4]~21 ( +// Equation(s): +// \tri_out[4]~21_combout = ((\tri_out~14_combout $ (\tri_out[4]~reg0_q $ (!\tri_out[3]~20 )))) # (GND) +// \tri_out[4]~22 = CARRY((\tri_out~14_combout & ((\tri_out[4]~reg0_q ) # (!\tri_out[3]~20 ))) # (!\tri_out~14_combout & (\tri_out[4]~reg0_q & !\tri_out[3]~20 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[4]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[3]~20 ), + .combout(\tri_out[4]~21_combout ), + .cout(\tri_out[4]~22 )); +// synopsys translate_off +defparam \tri_out[4]~21 .lut_mask = 16'h698E; +defparam \tri_out[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N19 +dffeas \tri_out[4]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[4]~21_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[4]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[4]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[4]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N20 +cycloneive_lcell_comb \tri_out[5]~23 ( +// Equation(s): +// \tri_out[5]~23_combout = (\tri_out~14_combout & ((\tri_out[5]~reg0_q & (\tri_out[4]~22 & VCC)) # (!\tri_out[5]~reg0_q & (!\tri_out[4]~22 )))) # (!\tri_out~14_combout & ((\tri_out[5]~reg0_q & (!\tri_out[4]~22 )) # (!\tri_out[5]~reg0_q & +// ((\tri_out[4]~22 ) # (GND))))) +// \tri_out[5]~24 = CARRY((\tri_out~14_combout & (!\tri_out[5]~reg0_q & !\tri_out[4]~22 )) # (!\tri_out~14_combout & ((!\tri_out[4]~22 ) # (!\tri_out[5]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[5]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[4]~22 ), + .combout(\tri_out[5]~23_combout ), + .cout(\tri_out[5]~24 )); +// synopsys translate_off +defparam \tri_out[5]~23 .lut_mask = 16'h9617; +defparam \tri_out[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N21 +dffeas \tri_out[5]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[5]~23_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[5]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[5]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[5]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N22 +cycloneive_lcell_comb \tri_out[6]~25 ( +// Equation(s): +// \tri_out[6]~25_combout = ((\tri_out~14_combout $ (\tri_out[6]~reg0_q $ (!\tri_out[5]~24 )))) # (GND) +// \tri_out[6]~26 = CARRY((\tri_out~14_combout & ((\tri_out[6]~reg0_q ) # (!\tri_out[5]~24 ))) # (!\tri_out~14_combout & (\tri_out[6]~reg0_q & !\tri_out[5]~24 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[6]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[5]~24 ), + .combout(\tri_out[6]~25_combout ), + .cout(\tri_out[6]~26 )); +// synopsys translate_off +defparam \tri_out[6]~25 .lut_mask = 16'h698E; +defparam \tri_out[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N23 +dffeas \tri_out[6]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[6]~25_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[6]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[6]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[6]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N24 +cycloneive_lcell_comb \tri_out[7]~27 ( +// Equation(s): +// \tri_out[7]~27_combout = (\tri_out~14_combout & ((\tri_out[7]~reg0_q & (\tri_out[6]~26 & VCC)) # (!\tri_out[7]~reg0_q & (!\tri_out[6]~26 )))) # (!\tri_out~14_combout & ((\tri_out[7]~reg0_q & (!\tri_out[6]~26 )) # (!\tri_out[7]~reg0_q & +// ((\tri_out[6]~26 ) # (GND))))) +// \tri_out[7]~28 = CARRY((\tri_out~14_combout & (!\tri_out[7]~reg0_q & !\tri_out[6]~26 )) # (!\tri_out~14_combout & ((!\tri_out[6]~26 ) # (!\tri_out[7]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[7]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[6]~26 ), + .combout(\tri_out[7]~27_combout ), + .cout(\tri_out[7]~28 )); +// synopsys translate_off +defparam \tri_out[7]~27 .lut_mask = 16'h9617; +defparam \tri_out[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N25 +dffeas \tri_out[7]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[7]~27_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[7]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[7]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[7]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N26 +cycloneive_lcell_comb \tri_out[8]~29 ( +// Equation(s): +// \tri_out[8]~29_combout = \tri_out[8]~reg0_q $ (\tri_out[7]~28 $ (!\tri_out~14_combout )) + + .dataa(\tri_out[8]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\tri_out~14_combout ), + .cin(\tri_out[7]~28 ), + .combout(\tri_out[8]~29_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out[8]~29 .lut_mask = 16'h5AA5; +defparam \tri_out[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N27 +dffeas \tri_out[8]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[8]~29_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[8]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[8]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[8]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N6 +cycloneive_lcell_comb \tri_out~12 ( +// Equation(s): +// \tri_out~12_combout = (\tri_out[6]~reg0_q & (\tri_out[2]~reg0_q & (\tri_out[8]~reg0_q & \tri_out[7]~reg0_q ))) # (!\tri_out[6]~reg0_q & ((\tri_out[2]~reg0_q ) # ((\tri_out[8]~reg0_q ) # (\tri_out[7]~reg0_q )))) + + .dataa(\tri_out[6]~reg0_q ), + .datab(\tri_out[2]~reg0_q ), + .datac(\tri_out[8]~reg0_q ), + .datad(\tri_out[7]~reg0_q ), + .cin(gnd), + .combout(\tri_out~12_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~12 .lut_mask = 16'hD554; +defparam \tri_out~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N0 +cycloneive_lcell_comb \tri_out~11 ( +// Equation(s): +// \tri_out~11_combout = (\tri_out[5]~reg0_q & (((\tri_out[4]~reg0_q & \tri_out[3]~reg0_q )) # (!\tri_out[2]~reg0_q ))) # (!\tri_out[5]~reg0_q & (!\tri_out[2]~reg0_q & ((\tri_out[4]~reg0_q ) # (\tri_out[3]~reg0_q )))) + + .dataa(\tri_out[5]~reg0_q ), + .datab(\tri_out[4]~reg0_q ), + .datac(\tri_out[2]~reg0_q ), + .datad(\tri_out[3]~reg0_q ), + .cin(gnd), + .combout(\tri_out~11_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~11 .lut_mask = 16'h8F0E; +defparam \tri_out~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y19_N29 +dffeas updown( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out~14_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\updown~q ), + .prn(vcc)); +// synopsys translate_off +defparam updown.is_wysiwyg = "true"; +defparam updown.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N30 +cycloneive_lcell_comb \tri_out~13 ( +// Equation(s): +// \tri_out~13_combout = (\tri_out[1]~reg0_q & ((\updown~q ) # ((\tri_out[6]~reg0_q & \tri_out[0]~reg0_q )))) # (!\tri_out[1]~reg0_q & (\updown~q & ((\tri_out[6]~reg0_q ) # (\tri_out[0]~reg0_q )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\updown~q ), + .datac(\tri_out[6]~reg0_q ), + .datad(\tri_out[0]~reg0_q ), + .cin(gnd), + .combout(\tri_out~13_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~13 .lut_mask = 16'hECC8; +defparam \tri_out~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N28 +cycloneive_lcell_comb \tri_out~14 ( +// Equation(s): +// \tri_out~14_combout = (\tri_out~12_combout & ((\updown~q ) # ((\tri_out~11_combout & \tri_out~13_combout )))) # (!\tri_out~12_combout & (\updown~q & ((\tri_out~11_combout ) # (\tri_out~13_combout )))) + + .dataa(\tri_out~12_combout ), + .datab(\tri_out~11_combout ), + .datac(\updown~q ), + .datad(\tri_out~13_combout ), + .cin(gnd), + .combout(\tri_out~14_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~14 .lut_mask = 16'hF8E0; +defparam \tri_out~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y19_N13 +dffeas \tri_out[1]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[1]~15_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[1]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[1]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[1]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N15 +cycloneive_io_ibuf \Pword[0]~input ( + .i(Pword[0]), + .ibar(gnd), + .o(\Pword[0]~input_o )); +// synopsys translate_off +defparam \Pword[0]~input .bus_hold = "false"; +defparam \Pword[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N1 +cycloneive_io_ibuf \Fword[15]~input ( + .i(Fword[15]), + .ibar(gnd), + .o(\Fword[15]~input_o )); +// synopsys translate_off +defparam \Fword[15]~input .bus_hold = "false"; +defparam \Fword[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \Fword[14]~input ( + .i(Fword[14]), + .ibar(gnd), + .o(\Fword[14]~input_o )); +// synopsys translate_off +defparam \Fword[14]~input .bus_hold = "false"; +defparam \Fword[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y22_N1 +cycloneive_io_ibuf \Fword[13]~input ( + .i(Fword[13]), + .ibar(gnd), + .o(\Fword[13]~input_o )); +// synopsys translate_off +defparam \Fword[13]~input .bus_hold = "false"; +defparam \Fword[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N1 +cycloneive_io_ibuf \Fword[12]~input ( + .i(Fword[12]), + .ibar(gnd), + .o(\Fword[12]~input_o )); +// synopsys translate_off +defparam \Fword[12]~input .bus_hold = "false"; +defparam \Fword[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N8 +cycloneive_io_ibuf \Fword[11]~input ( + .i(Fword[11]), + .ibar(gnd), + .o(\Fword[11]~input_o )); +// synopsys translate_off +defparam \Fword[11]~input .bus_hold = "false"; +defparam \Fword[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N22 +cycloneive_io_ibuf \Fword[10]~input ( + .i(Fword[10]), + .ibar(gnd), + .o(\Fword[10]~input_o )); +// synopsys translate_off +defparam \Fword[10]~input .bus_hold = "false"; +defparam \Fword[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N8 +cycloneive_io_ibuf \Fword[9]~input ( + .i(Fword[9]), + .ibar(gnd), + .o(\Fword[9]~input_o )); +// synopsys translate_off +defparam \Fword[9]~input .bus_hold = "false"; +defparam \Fword[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N15 +cycloneive_io_ibuf \Fword[8]~input ( + .i(Fword[8]), + .ibar(gnd), + .o(\Fword[8]~input_o )); +// synopsys translate_off +defparam \Fword[8]~input .bus_hold = "false"; +defparam \Fword[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N22 +cycloneive_io_ibuf \Fword[7]~input ( + .i(Fword[7]), + .ibar(gnd), + .o(\Fword[7]~input_o )); +// synopsys translate_off +defparam \Fword[7]~input .bus_hold = "false"; +defparam \Fword[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y24_N8 +cycloneive_io_ibuf \Fword[6]~input ( + .i(Fword[6]), + .ibar(gnd), + .o(\Fword[6]~input_o )); +// synopsys translate_off +defparam \Fword[6]~input .bus_hold = "false"; +defparam \Fword[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N1 +cycloneive_io_ibuf \Fword[5]~input ( + .i(Fword[5]), + .ibar(gnd), + .o(\Fword[5]~input_o )); +// synopsys translate_off +defparam \Fword[5]~input .bus_hold = "false"; +defparam \Fword[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N22 +cycloneive_io_ibuf \Fword[4]~input ( + .i(Fword[4]), + .ibar(gnd), + .o(\Fword[4]~input_o )); +// synopsys translate_off +defparam \Fword[4]~input .bus_hold = "false"; +defparam \Fword[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N1 +cycloneive_io_ibuf \Fword[3]~input ( + .i(Fword[3]), + .ibar(gnd), + .o(\Fword[3]~input_o )); +// synopsys translate_off +defparam \Fword[3]~input .bus_hold = "false"; +defparam \Fword[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N8 +cycloneive_io_ibuf \Fword[2]~input ( + .i(Fword[2]), + .ibar(gnd), + .o(\Fword[2]~input_o )); +// synopsys translate_off +defparam \Fword[2]~input .bus_hold = "false"; +defparam \Fword[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N8 +cycloneive_io_ibuf \Fword[1]~input ( + .i(Fword[1]), + .ibar(gnd), + .o(\Fword[1]~input_o )); +// synopsys translate_off +defparam \Fword[1]~input .bus_hold = "false"; +defparam \Fword[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N15 +cycloneive_io_ibuf \Fword[0]~input ( + .i(Fword[0]), + .ibar(gnd), + .o(\Fword[0]~input_o )); +// synopsys translate_off +defparam \Fword[0]~input .bus_hold = "false"; +defparam \Fword[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N6 +cycloneive_lcell_comb \F_acc[0]~26 ( +// Equation(s): +// \F_acc[0]~26_combout = (F_acc[0] & (\Fword[0]~input_o $ (VCC))) # (!F_acc[0] & (\Fword[0]~input_o & VCC)) +// \F_acc[0]~27 = CARRY((F_acc[0] & \Fword[0]~input_o )) + + .dataa(F_acc[0]), + .datab(\Fword[0]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\F_acc[0]~26_combout ), + .cout(\F_acc[0]~27 )); +// synopsys translate_off +defparam \F_acc[0]~26 .lut_mask = 16'h6688; +defparam \F_acc[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X6_Y20_N7 +dffeas \F_acc[0] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[0]~26_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[0]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[0] .is_wysiwyg = "true"; +defparam \F_acc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N8 +cycloneive_lcell_comb \F_acc[1]~28 ( +// Equation(s): +// \F_acc[1]~28_combout = (\Fword[1]~input_o & ((F_acc[1] & (\F_acc[0]~27 & VCC)) # (!F_acc[1] & (!\F_acc[0]~27 )))) # (!\Fword[1]~input_o & ((F_acc[1] & (!\F_acc[0]~27 )) # (!F_acc[1] & ((\F_acc[0]~27 ) # (GND))))) +// \F_acc[1]~29 = CARRY((\Fword[1]~input_o & (!F_acc[1] & !\F_acc[0]~27 )) # (!\Fword[1]~input_o & ((!\F_acc[0]~27 ) # (!F_acc[1])))) + + .dataa(\Fword[1]~input_o ), + .datab(F_acc[1]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[0]~27 ), + .combout(\F_acc[1]~28_combout ), + .cout(\F_acc[1]~29 )); +// synopsys translate_off +defparam \F_acc[1]~28 .lut_mask = 16'h9617; +defparam \F_acc[1]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N9 +dffeas \F_acc[1] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[1]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[1]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[1] .is_wysiwyg = "true"; +defparam \F_acc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N10 +cycloneive_lcell_comb \F_acc[2]~30 ( +// Equation(s): +// \F_acc[2]~30_combout = ((F_acc[2] $ (\Fword[2]~input_o $ (!\F_acc[1]~29 )))) # (GND) +// \F_acc[2]~31 = CARRY((F_acc[2] & ((\Fword[2]~input_o ) # (!\F_acc[1]~29 ))) # (!F_acc[2] & (\Fword[2]~input_o & !\F_acc[1]~29 ))) + + .dataa(F_acc[2]), + .datab(\Fword[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[1]~29 ), + .combout(\F_acc[2]~30_combout ), + .cout(\F_acc[2]~31 )); +// synopsys translate_off +defparam \F_acc[2]~30 .lut_mask = 16'h698E; +defparam \F_acc[2]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N11 +dffeas \F_acc[2] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[2]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[2]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[2] .is_wysiwyg = "true"; +defparam \F_acc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N12 +cycloneive_lcell_comb \F_acc[3]~32 ( +// Equation(s): +// \F_acc[3]~32_combout = (F_acc[3] & ((\Fword[3]~input_o & (\F_acc[2]~31 & VCC)) # (!\Fword[3]~input_o & (!\F_acc[2]~31 )))) # (!F_acc[3] & ((\Fword[3]~input_o & (!\F_acc[2]~31 )) # (!\Fword[3]~input_o & ((\F_acc[2]~31 ) # (GND))))) +// \F_acc[3]~33 = CARRY((F_acc[3] & (!\Fword[3]~input_o & !\F_acc[2]~31 )) # (!F_acc[3] & ((!\F_acc[2]~31 ) # (!\Fword[3]~input_o )))) + + .dataa(F_acc[3]), + .datab(\Fword[3]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[2]~31 ), + .combout(\F_acc[3]~32_combout ), + .cout(\F_acc[3]~33 )); +// synopsys translate_off +defparam \F_acc[3]~32 .lut_mask = 16'h9617; +defparam \F_acc[3]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N13 +dffeas \F_acc[3] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[3]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[3]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[3] .is_wysiwyg = "true"; +defparam \F_acc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N14 +cycloneive_lcell_comb \F_acc[4]~34 ( +// Equation(s): +// \F_acc[4]~34_combout = ((\Fword[4]~input_o $ (F_acc[4] $ (!\F_acc[3]~33 )))) # (GND) +// \F_acc[4]~35 = CARRY((\Fword[4]~input_o & ((F_acc[4]) # (!\F_acc[3]~33 ))) # (!\Fword[4]~input_o & (F_acc[4] & !\F_acc[3]~33 ))) + + .dataa(\Fword[4]~input_o ), + .datab(F_acc[4]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[3]~33 ), + .combout(\F_acc[4]~34_combout ), + .cout(\F_acc[4]~35 )); +// synopsys translate_off +defparam \F_acc[4]~34 .lut_mask = 16'h698E; +defparam \F_acc[4]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N15 +dffeas \F_acc[4] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[4]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[4]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[4] .is_wysiwyg = "true"; +defparam \F_acc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N16 +cycloneive_lcell_comb \F_acc[5]~36 ( +// Equation(s): +// \F_acc[5]~36_combout = (\Fword[5]~input_o & ((F_acc[5] & (\F_acc[4]~35 & VCC)) # (!F_acc[5] & (!\F_acc[4]~35 )))) # (!\Fword[5]~input_o & ((F_acc[5] & (!\F_acc[4]~35 )) # (!F_acc[5] & ((\F_acc[4]~35 ) # (GND))))) +// \F_acc[5]~37 = CARRY((\Fword[5]~input_o & (!F_acc[5] & !\F_acc[4]~35 )) # (!\Fword[5]~input_o & ((!\F_acc[4]~35 ) # (!F_acc[5])))) + + .dataa(\Fword[5]~input_o ), + .datab(F_acc[5]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[4]~35 ), + .combout(\F_acc[5]~36_combout ), + .cout(\F_acc[5]~37 )); +// synopsys translate_off +defparam \F_acc[5]~36 .lut_mask = 16'h9617; +defparam \F_acc[5]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N17 +dffeas \F_acc[5] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[5]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[5]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[5] .is_wysiwyg = "true"; +defparam \F_acc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N18 +cycloneive_lcell_comb \F_acc[6]~38 ( +// Equation(s): +// \F_acc[6]~38_combout = ((\Fword[6]~input_o $ (F_acc[6] $ (!\F_acc[5]~37 )))) # (GND) +// \F_acc[6]~39 = CARRY((\Fword[6]~input_o & ((F_acc[6]) # (!\F_acc[5]~37 ))) # (!\Fword[6]~input_o & (F_acc[6] & !\F_acc[5]~37 ))) + + .dataa(\Fword[6]~input_o ), + .datab(F_acc[6]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[5]~37 ), + .combout(\F_acc[6]~38_combout ), + .cout(\F_acc[6]~39 )); +// synopsys translate_off +defparam \F_acc[6]~38 .lut_mask = 16'h698E; +defparam \F_acc[6]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N19 +dffeas \F_acc[6] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[6]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[6]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[6] .is_wysiwyg = "true"; +defparam \F_acc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N20 +cycloneive_lcell_comb \F_acc[7]~40 ( +// Equation(s): +// \F_acc[7]~40_combout = (\Fword[7]~input_o & ((F_acc[7] & (\F_acc[6]~39 & VCC)) # (!F_acc[7] & (!\F_acc[6]~39 )))) # (!\Fword[7]~input_o & ((F_acc[7] & (!\F_acc[6]~39 )) # (!F_acc[7] & ((\F_acc[6]~39 ) # (GND))))) +// \F_acc[7]~41 = CARRY((\Fword[7]~input_o & (!F_acc[7] & !\F_acc[6]~39 )) # (!\Fword[7]~input_o & ((!\F_acc[6]~39 ) # (!F_acc[7])))) + + .dataa(\Fword[7]~input_o ), + .datab(F_acc[7]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[6]~39 ), + .combout(\F_acc[7]~40_combout ), + .cout(\F_acc[7]~41 )); +// synopsys translate_off +defparam \F_acc[7]~40 .lut_mask = 16'h9617; +defparam \F_acc[7]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N21 +dffeas \F_acc[7] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[7]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[7]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[7] .is_wysiwyg = "true"; +defparam \F_acc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N22 +cycloneive_lcell_comb \F_acc[8]~42 ( +// Equation(s): +// \F_acc[8]~42_combout = ((F_acc[8] $ (\Fword[8]~input_o $ (!\F_acc[7]~41 )))) # (GND) +// \F_acc[8]~43 = CARRY((F_acc[8] & ((\Fword[8]~input_o ) # (!\F_acc[7]~41 ))) # (!F_acc[8] & (\Fword[8]~input_o & !\F_acc[7]~41 ))) + + .dataa(F_acc[8]), + .datab(\Fword[8]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[7]~41 ), + .combout(\F_acc[8]~42_combout ), + .cout(\F_acc[8]~43 )); +// synopsys translate_off +defparam \F_acc[8]~42 .lut_mask = 16'h698E; +defparam \F_acc[8]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N23 +dffeas \F_acc[8] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[8]~42_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[8]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[8] .is_wysiwyg = "true"; +defparam \F_acc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N24 +cycloneive_lcell_comb \F_acc[9]~44 ( +// Equation(s): +// \F_acc[9]~44_combout = (\Fword[9]~input_o & ((F_acc[9] & (\F_acc[8]~43 & VCC)) # (!F_acc[9] & (!\F_acc[8]~43 )))) # (!\Fword[9]~input_o & ((F_acc[9] & (!\F_acc[8]~43 )) # (!F_acc[9] & ((\F_acc[8]~43 ) # (GND))))) +// \F_acc[9]~45 = CARRY((\Fword[9]~input_o & (!F_acc[9] & !\F_acc[8]~43 )) # (!\Fword[9]~input_o & ((!\F_acc[8]~43 ) # (!F_acc[9])))) + + .dataa(\Fword[9]~input_o ), + .datab(F_acc[9]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[8]~43 ), + .combout(\F_acc[9]~44_combout ), + .cout(\F_acc[9]~45 )); +// synopsys translate_off +defparam \F_acc[9]~44 .lut_mask = 16'h9617; +defparam \F_acc[9]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N25 +dffeas \F_acc[9] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[9]~44_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[9]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[9] .is_wysiwyg = "true"; +defparam \F_acc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N26 +cycloneive_lcell_comb \F_acc[10]~46 ( +// Equation(s): +// \F_acc[10]~46_combout = ((F_acc[10] $ (\Fword[10]~input_o $ (!\F_acc[9]~45 )))) # (GND) +// \F_acc[10]~47 = CARRY((F_acc[10] & ((\Fword[10]~input_o ) # (!\F_acc[9]~45 ))) # (!F_acc[10] & (\Fword[10]~input_o & !\F_acc[9]~45 ))) + + .dataa(F_acc[10]), + .datab(\Fword[10]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[9]~45 ), + .combout(\F_acc[10]~46_combout ), + .cout(\F_acc[10]~47 )); +// synopsys translate_off +defparam \F_acc[10]~46 .lut_mask = 16'h698E; +defparam \F_acc[10]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N27 +dffeas \F_acc[10] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[10]~46_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[10]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[10] .is_wysiwyg = "true"; +defparam \F_acc[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N28 +cycloneive_lcell_comb \F_acc[11]~48 ( +// Equation(s): +// \F_acc[11]~48_combout = (\Fword[11]~input_o & ((F_acc[11] & (\F_acc[10]~47 & VCC)) # (!F_acc[11] & (!\F_acc[10]~47 )))) # (!\Fword[11]~input_o & ((F_acc[11] & (!\F_acc[10]~47 )) # (!F_acc[11] & ((\F_acc[10]~47 ) # (GND))))) +// \F_acc[11]~49 = CARRY((\Fword[11]~input_o & (!F_acc[11] & !\F_acc[10]~47 )) # (!\Fword[11]~input_o & ((!\F_acc[10]~47 ) # (!F_acc[11])))) + + .dataa(\Fword[11]~input_o ), + .datab(F_acc[11]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[10]~47 ), + .combout(\F_acc[11]~48_combout ), + .cout(\F_acc[11]~49 )); +// synopsys translate_off +defparam \F_acc[11]~48 .lut_mask = 16'h9617; +defparam \F_acc[11]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N29 +dffeas \F_acc[11] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[11]~48_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[11]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[11] .is_wysiwyg = "true"; +defparam \F_acc[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N30 +cycloneive_lcell_comb \F_acc[12]~50 ( +// Equation(s): +// \F_acc[12]~50_combout = ((F_acc[12] $ (\Fword[12]~input_o $ (!\F_acc[11]~49 )))) # (GND) +// \F_acc[12]~51 = CARRY((F_acc[12] & ((\Fword[12]~input_o ) # (!\F_acc[11]~49 ))) # (!F_acc[12] & (\Fword[12]~input_o & !\F_acc[11]~49 ))) + + .dataa(F_acc[12]), + .datab(\Fword[12]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[11]~49 ), + .combout(\F_acc[12]~50_combout ), + .cout(\F_acc[12]~51 )); +// synopsys translate_off +defparam \F_acc[12]~50 .lut_mask = 16'h698E; +defparam \F_acc[12]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N31 +dffeas \F_acc[12] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[12]~50_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[12]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[12] .is_wysiwyg = "true"; +defparam \F_acc[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N0 +cycloneive_lcell_comb \F_acc[13]~52 ( +// Equation(s): +// \F_acc[13]~52_combout = (\Fword[13]~input_o & ((F_acc[13] & (\F_acc[12]~51 & VCC)) # (!F_acc[13] & (!\F_acc[12]~51 )))) # (!\Fword[13]~input_o & ((F_acc[13] & (!\F_acc[12]~51 )) # (!F_acc[13] & ((\F_acc[12]~51 ) # (GND))))) +// \F_acc[13]~53 = CARRY((\Fword[13]~input_o & (!F_acc[13] & !\F_acc[12]~51 )) # (!\Fword[13]~input_o & ((!\F_acc[12]~51 ) # (!F_acc[13])))) + + .dataa(\Fword[13]~input_o ), + .datab(F_acc[13]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[12]~51 ), + .combout(\F_acc[13]~52_combout ), + .cout(\F_acc[13]~53 )); +// synopsys translate_off +defparam \F_acc[13]~52 .lut_mask = 16'h9617; +defparam \F_acc[13]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N1 +dffeas \F_acc[13] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[13]~52_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[13]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[13] .is_wysiwyg = "true"; +defparam \F_acc[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N2 +cycloneive_lcell_comb \F_acc[14]~54 ( +// Equation(s): +// \F_acc[14]~54_combout = ((\Fword[14]~input_o $ (F_acc[14] $ (!\F_acc[13]~53 )))) # (GND) +// \F_acc[14]~55 = CARRY((\Fword[14]~input_o & ((F_acc[14]) # (!\F_acc[13]~53 ))) # (!\Fword[14]~input_o & (F_acc[14] & !\F_acc[13]~53 ))) + + .dataa(\Fword[14]~input_o ), + .datab(F_acc[14]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[13]~53 ), + .combout(\F_acc[14]~54_combout ), + .cout(\F_acc[14]~55 )); +// synopsys translate_off +defparam \F_acc[14]~54 .lut_mask = 16'h698E; +defparam \F_acc[14]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N3 +dffeas \F_acc[14] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[14]~54_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[14]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[14] .is_wysiwyg = "true"; +defparam \F_acc[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N4 +cycloneive_lcell_comb \F_acc[15]~56 ( +// Equation(s): +// \F_acc[15]~56_combout = (\Fword[15]~input_o & ((F_acc[15] & (\F_acc[14]~55 & VCC)) # (!F_acc[15] & (!\F_acc[14]~55 )))) # (!\Fword[15]~input_o & ((F_acc[15] & (!\F_acc[14]~55 )) # (!F_acc[15] & ((\F_acc[14]~55 ) # (GND))))) +// \F_acc[15]~57 = CARRY((\Fword[15]~input_o & (!F_acc[15] & !\F_acc[14]~55 )) # (!\Fword[15]~input_o & ((!\F_acc[14]~55 ) # (!F_acc[15])))) + + .dataa(\Fword[15]~input_o ), + .datab(F_acc[15]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[14]~55 ), + .combout(\F_acc[15]~56_combout ), + .cout(\F_acc[15]~57 )); +// synopsys translate_off +defparam \F_acc[15]~56 .lut_mask = 16'h9617; +defparam \F_acc[15]~56 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N5 +dffeas \F_acc[15] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[15]~56_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[15]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[15] .is_wysiwyg = "true"; +defparam \F_acc[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N6 +cycloneive_lcell_comb \F_acc[16]~58 ( +// Equation(s): +// \F_acc[16]~58_combout = (F_acc[16] & (\F_acc[15]~57 $ (GND))) # (!F_acc[16] & (!\F_acc[15]~57 & VCC)) +// \F_acc[16]~59 = CARRY((F_acc[16] & !\F_acc[15]~57 )) + + .dataa(F_acc[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[15]~57 ), + .combout(\F_acc[16]~58_combout ), + .cout(\F_acc[16]~59 )); +// synopsys translate_off +defparam \F_acc[16]~58 .lut_mask = 16'hA50A; +defparam \F_acc[16]~58 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N7 +dffeas \F_acc[16] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[16]~58_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[16]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[16] .is_wysiwyg = "true"; +defparam \F_acc[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N10 +cycloneive_lcell_comb \rom_address[0]~0 ( +// Equation(s): +// \rom_address[0]~0_combout = (\Pword[0]~input_o & (F_acc[16] $ (VCC))) # (!\Pword[0]~input_o & (F_acc[16] & VCC)) +// \rom_address[0]~1 = CARRY((\Pword[0]~input_o & F_acc[16])) + + .dataa(\Pword[0]~input_o ), + .datab(F_acc[16]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\rom_address[0]~0_combout ), + .cout(\rom_address[0]~1 )); +// synopsys translate_off +defparam \rom_address[0]~0 .lut_mask = 16'h6688; +defparam \rom_address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N8 +cycloneive_lcell_comb \F_acc[17]~60 ( +// Equation(s): +// \F_acc[17]~60_combout = (F_acc[17] & (!\F_acc[16]~59 )) # (!F_acc[17] & ((\F_acc[16]~59 ) # (GND))) +// \F_acc[17]~61 = CARRY((!\F_acc[16]~59 ) # (!F_acc[17])) + + .dataa(gnd), + .datab(F_acc[17]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[16]~59 ), + .combout(\F_acc[17]~60_combout ), + .cout(\F_acc[17]~61 )); +// synopsys translate_off +defparam \F_acc[17]~60 .lut_mask = 16'h3C3F; +defparam \F_acc[17]~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N9 +dffeas \F_acc[17] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[17]~60_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[17]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[17] .is_wysiwyg = "true"; +defparam \F_acc[17] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N22 +cycloneive_io_ibuf \Pword[1]~input ( + .i(Pword[1]), + .ibar(gnd), + .o(\Pword[1]~input_o )); +// synopsys translate_off +defparam \Pword[1]~input .bus_hold = "false"; +defparam \Pword[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N12 +cycloneive_lcell_comb \rom_address[1]~2 ( +// Equation(s): +// \rom_address[1]~2_combout = (F_acc[17] & ((\Pword[1]~input_o & (\rom_address[0]~1 & VCC)) # (!\Pword[1]~input_o & (!\rom_address[0]~1 )))) # (!F_acc[17] & ((\Pword[1]~input_o & (!\rom_address[0]~1 )) # (!\Pword[1]~input_o & ((\rom_address[0]~1 ) # +// (GND))))) +// \rom_address[1]~3 = CARRY((F_acc[17] & (!\Pword[1]~input_o & !\rom_address[0]~1 )) # (!F_acc[17] & ((!\rom_address[0]~1 ) # (!\Pword[1]~input_o )))) + + .dataa(F_acc[17]), + .datab(\Pword[1]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[0]~1 ), + .combout(\rom_address[1]~2_combout ), + .cout(\rom_address[1]~3 )); +// synopsys translate_off +defparam \rom_address[1]~2 .lut_mask = 16'h9617; +defparam \rom_address[1]~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N10 +cycloneive_lcell_comb \F_acc[18]~62 ( +// Equation(s): +// \F_acc[18]~62_combout = (F_acc[18] & (\F_acc[17]~61 $ (GND))) # (!F_acc[18] & (!\F_acc[17]~61 & VCC)) +// \F_acc[18]~63 = CARRY((F_acc[18] & !\F_acc[17]~61 )) + + .dataa(F_acc[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[17]~61 ), + .combout(\F_acc[18]~62_combout ), + .cout(\F_acc[18]~63 )); +// synopsys translate_off +defparam \F_acc[18]~62 .lut_mask = 16'hA50A; +defparam \F_acc[18]~62 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N11 +dffeas \F_acc[18] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[18]~62_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[18]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[18] .is_wysiwyg = "true"; +defparam \F_acc[18] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N1 +cycloneive_io_ibuf \Pword[2]~input ( + .i(Pword[2]), + .ibar(gnd), + .o(\Pword[2]~input_o )); +// synopsys translate_off +defparam \Pword[2]~input .bus_hold = "false"; +defparam \Pword[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N14 +cycloneive_lcell_comb \rom_address[2]~4 ( +// Equation(s): +// \rom_address[2]~4_combout = ((F_acc[18] $ (\Pword[2]~input_o $ (!\rom_address[1]~3 )))) # (GND) +// \rom_address[2]~5 = CARRY((F_acc[18] & ((\Pword[2]~input_o ) # (!\rom_address[1]~3 ))) # (!F_acc[18] & (\Pword[2]~input_o & !\rom_address[1]~3 ))) + + .dataa(F_acc[18]), + .datab(\Pword[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[1]~3 ), + .combout(\rom_address[2]~4_combout ), + .cout(\rom_address[2]~5 )); +// synopsys translate_off +defparam \rom_address[2]~4 .lut_mask = 16'h698E; +defparam \rom_address[2]~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N12 +cycloneive_lcell_comb \F_acc[19]~64 ( +// Equation(s): +// \F_acc[19]~64_combout = (F_acc[19] & (!\F_acc[18]~63 )) # (!F_acc[19] & ((\F_acc[18]~63 ) # (GND))) +// \F_acc[19]~65 = CARRY((!\F_acc[18]~63 ) # (!F_acc[19])) + + .dataa(F_acc[19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[18]~63 ), + .combout(\F_acc[19]~64_combout ), + .cout(\F_acc[19]~65 )); +// synopsys translate_off +defparam \F_acc[19]~64 .lut_mask = 16'h5A5F; +defparam \F_acc[19]~64 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N13 +dffeas \F_acc[19] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[19]~64_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[19]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[19] .is_wysiwyg = "true"; +defparam \F_acc[19] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N8 +cycloneive_io_ibuf \Pword[3]~input ( + .i(Pword[3]), + .ibar(gnd), + .o(\Pword[3]~input_o )); +// synopsys translate_off +defparam \Pword[3]~input .bus_hold = "false"; +defparam \Pword[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N16 +cycloneive_lcell_comb \rom_address[3]~6 ( +// Equation(s): +// \rom_address[3]~6_combout = (F_acc[19] & ((\Pword[3]~input_o & (\rom_address[2]~5 & VCC)) # (!\Pword[3]~input_o & (!\rom_address[2]~5 )))) # (!F_acc[19] & ((\Pword[3]~input_o & (!\rom_address[2]~5 )) # (!\Pword[3]~input_o & ((\rom_address[2]~5 ) # +// (GND))))) +// \rom_address[3]~7 = CARRY((F_acc[19] & (!\Pword[3]~input_o & !\rom_address[2]~5 )) # (!F_acc[19] & ((!\rom_address[2]~5 ) # (!\Pword[3]~input_o )))) + + .dataa(F_acc[19]), + .datab(\Pword[3]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[2]~5 ), + .combout(\rom_address[3]~6_combout ), + .cout(\rom_address[3]~7 )); +// synopsys translate_off +defparam \rom_address[3]~6 .lut_mask = 16'h9617; +defparam \rom_address[3]~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N14 +cycloneive_lcell_comb \F_acc[20]~66 ( +// Equation(s): +// \F_acc[20]~66_combout = (F_acc[20] & (\F_acc[19]~65 $ (GND))) # (!F_acc[20] & (!\F_acc[19]~65 & VCC)) +// \F_acc[20]~67 = CARRY((F_acc[20] & !\F_acc[19]~65 )) + + .dataa(gnd), + .datab(F_acc[20]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[19]~65 ), + .combout(\F_acc[20]~66_combout ), + .cout(\F_acc[20]~67 )); +// synopsys translate_off +defparam \F_acc[20]~66 .lut_mask = 16'hC30C; +defparam \F_acc[20]~66 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N15 +dffeas \F_acc[20] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[20]~66_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[20]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[20] .is_wysiwyg = "true"; +defparam \F_acc[20] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N22 +cycloneive_io_ibuf \Pword[4]~input ( + .i(Pword[4]), + .ibar(gnd), + .o(\Pword[4]~input_o )); +// synopsys translate_off +defparam \Pword[4]~input .bus_hold = "false"; +defparam \Pword[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N18 +cycloneive_lcell_comb \rom_address[4]~8 ( +// Equation(s): +// \rom_address[4]~8_combout = ((F_acc[20] $ (\Pword[4]~input_o $ (!\rom_address[3]~7 )))) # (GND) +// \rom_address[4]~9 = CARRY((F_acc[20] & ((\Pword[4]~input_o ) # (!\rom_address[3]~7 ))) # (!F_acc[20] & (\Pword[4]~input_o & !\rom_address[3]~7 ))) + + .dataa(F_acc[20]), + .datab(\Pword[4]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[3]~7 ), + .combout(\rom_address[4]~8_combout ), + .cout(\rom_address[4]~9 )); +// synopsys translate_off +defparam \rom_address[4]~8 .lut_mask = 16'h698E; +defparam \rom_address[4]~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N16 +cycloneive_lcell_comb \F_acc[21]~68 ( +// Equation(s): +// \F_acc[21]~68_combout = (F_acc[21] & (!\F_acc[20]~67 )) # (!F_acc[21] & ((\F_acc[20]~67 ) # (GND))) +// \F_acc[21]~69 = CARRY((!\F_acc[20]~67 ) # (!F_acc[21])) + + .dataa(gnd), + .datab(F_acc[21]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[20]~67 ), + .combout(\F_acc[21]~68_combout ), + .cout(\F_acc[21]~69 )); +// synopsys translate_off +defparam \F_acc[21]~68 .lut_mask = 16'h3C3F; +defparam \F_acc[21]~68 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N17 +dffeas \F_acc[21] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[21]~68_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[21]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[21] .is_wysiwyg = "true"; +defparam \F_acc[21] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N15 +cycloneive_io_ibuf \Pword[5]~input ( + .i(Pword[5]), + .ibar(gnd), + .o(\Pword[5]~input_o )); +// synopsys translate_off +defparam \Pword[5]~input .bus_hold = "false"; +defparam \Pword[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N20 +cycloneive_lcell_comb \rom_address[5]~10 ( +// Equation(s): +// \rom_address[5]~10_combout = (F_acc[21] & ((\Pword[5]~input_o & (\rom_address[4]~9 & VCC)) # (!\Pword[5]~input_o & (!\rom_address[4]~9 )))) # (!F_acc[21] & ((\Pword[5]~input_o & (!\rom_address[4]~9 )) # (!\Pword[5]~input_o & ((\rom_address[4]~9 ) # +// (GND))))) +// \rom_address[5]~11 = CARRY((F_acc[21] & (!\Pword[5]~input_o & !\rom_address[4]~9 )) # (!F_acc[21] & ((!\rom_address[4]~9 ) # (!\Pword[5]~input_o )))) + + .dataa(F_acc[21]), + .datab(\Pword[5]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[4]~9 ), + .combout(\rom_address[5]~10_combout ), + .cout(\rom_address[5]~11 )); +// synopsys translate_off +defparam \rom_address[5]~10 .lut_mask = 16'h9617; +defparam \rom_address[5]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N22 +cycloneive_io_ibuf \Pword[6]~input ( + .i(Pword[6]), + .ibar(gnd), + .o(\Pword[6]~input_o )); +// synopsys translate_off +defparam \Pword[6]~input .bus_hold = "false"; +defparam \Pword[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N18 +cycloneive_lcell_comb \F_acc[22]~70 ( +// Equation(s): +// \F_acc[22]~70_combout = (F_acc[22] & (\F_acc[21]~69 $ (GND))) # (!F_acc[22] & (!\F_acc[21]~69 & VCC)) +// \F_acc[22]~71 = CARRY((F_acc[22] & !\F_acc[21]~69 )) + + .dataa(gnd), + .datab(F_acc[22]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[21]~69 ), + .combout(\F_acc[22]~70_combout ), + .cout(\F_acc[22]~71 )); +// synopsys translate_off +defparam \F_acc[22]~70 .lut_mask = 16'hC30C; +defparam \F_acc[22]~70 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N19 +dffeas \F_acc[22] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[22]~70_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[22]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[22] .is_wysiwyg = "true"; +defparam \F_acc[22] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N22 +cycloneive_lcell_comb \rom_address[6]~12 ( +// Equation(s): +// \rom_address[6]~12_combout = ((\Pword[6]~input_o $ (F_acc[22] $ (!\rom_address[5]~11 )))) # (GND) +// \rom_address[6]~13 = CARRY((\Pword[6]~input_o & ((F_acc[22]) # (!\rom_address[5]~11 ))) # (!\Pword[6]~input_o & (F_acc[22] & !\rom_address[5]~11 ))) + + .dataa(\Pword[6]~input_o ), + .datab(F_acc[22]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[5]~11 ), + .combout(\rom_address[6]~12_combout ), + .cout(\rom_address[6]~13 )); +// synopsys translate_off +defparam \rom_address[6]~12 .lut_mask = 16'h698E; +defparam \rom_address[6]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y22_N15 +cycloneive_io_ibuf \Pword[7]~input ( + .i(Pword[7]), + .ibar(gnd), + .o(\Pword[7]~input_o )); +// synopsys translate_off +defparam \Pword[7]~input .bus_hold = "false"; +defparam \Pword[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N20 +cycloneive_lcell_comb \F_acc[23]~72 ( +// Equation(s): +// \F_acc[23]~72_combout = (F_acc[23] & (!\F_acc[22]~71 )) # (!F_acc[23] & ((\F_acc[22]~71 ) # (GND))) +// \F_acc[23]~73 = CARRY((!\F_acc[22]~71 ) # (!F_acc[23])) + + .dataa(gnd), + .datab(F_acc[23]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[22]~71 ), + .combout(\F_acc[23]~72_combout ), + .cout(\F_acc[23]~73 )); +// synopsys translate_off +defparam \F_acc[23]~72 .lut_mask = 16'h3C3F; +defparam \F_acc[23]~72 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N21 +dffeas \F_acc[23] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[23]~72_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[23]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[23] .is_wysiwyg = "true"; +defparam \F_acc[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N24 +cycloneive_lcell_comb \rom_address[7]~14 ( +// Equation(s): +// \rom_address[7]~14_combout = (\Pword[7]~input_o & ((F_acc[23] & (\rom_address[6]~13 & VCC)) # (!F_acc[23] & (!\rom_address[6]~13 )))) # (!\Pword[7]~input_o & ((F_acc[23] & (!\rom_address[6]~13 )) # (!F_acc[23] & ((\rom_address[6]~13 ) # (GND))))) +// \rom_address[7]~15 = CARRY((\Pword[7]~input_o & (!F_acc[23] & !\rom_address[6]~13 )) # (!\Pword[7]~input_o & ((!\rom_address[6]~13 ) # (!F_acc[23])))) + + .dataa(\Pword[7]~input_o ), + .datab(F_acc[23]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[6]~13 ), + .combout(\rom_address[7]~14_combout ), + .cout(\rom_address[7]~15 )); +// synopsys translate_off +defparam \rom_address[7]~14 .lut_mask = 16'h9617; +defparam \rom_address[7]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N15 +cycloneive_io_ibuf \Pword[8]~input ( + .i(Pword[8]), + .ibar(gnd), + .o(\Pword[8]~input_o )); +// synopsys translate_off +defparam \Pword[8]~input .bus_hold = "false"; +defparam \Pword[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N22 +cycloneive_lcell_comb \F_acc[24]~74 ( +// Equation(s): +// \F_acc[24]~74_combout = (F_acc[24] & (\F_acc[23]~73 $ (GND))) # (!F_acc[24] & (!\F_acc[23]~73 & VCC)) +// \F_acc[24]~75 = CARRY((F_acc[24] & !\F_acc[23]~73 )) + + .dataa(F_acc[24]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[23]~73 ), + .combout(\F_acc[24]~74_combout ), + .cout(\F_acc[24]~75 )); +// synopsys translate_off +defparam \F_acc[24]~74 .lut_mask = 16'hA50A; +defparam \F_acc[24]~74 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N23 +dffeas \F_acc[24] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[24]~74_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[24]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[24] .is_wysiwyg = "true"; +defparam \F_acc[24] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N26 +cycloneive_lcell_comb \rom_address[8]~16 ( +// Equation(s): +// \rom_address[8]~16_combout = ((\Pword[8]~input_o $ (F_acc[24] $ (!\rom_address[7]~15 )))) # (GND) +// \rom_address[8]~17 = CARRY((\Pword[8]~input_o & ((F_acc[24]) # (!\rom_address[7]~15 ))) # (!\Pword[8]~input_o & (F_acc[24] & !\rom_address[7]~15 ))) + + .dataa(\Pword[8]~input_o ), + .datab(F_acc[24]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[7]~15 ), + .combout(\rom_address[8]~16_combout ), + .cout(\rom_address[8]~17 )); +// synopsys translate_off +defparam \rom_address[8]~16 .lut_mask = 16'h698E; +defparam \rom_address[8]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N8 +cycloneive_io_ibuf \Pword[9]~input ( + .i(Pword[9]), + .ibar(gnd), + .o(\Pword[9]~input_o )); +// synopsys translate_off +defparam \Pword[9]~input .bus_hold = "false"; +defparam \Pword[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N24 +cycloneive_lcell_comb \F_acc[25]~76 ( +// Equation(s): +// \F_acc[25]~76_combout = \F_acc[24]~75 $ (F_acc[25]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(F_acc[25]), + .cin(\F_acc[24]~75 ), + .combout(\F_acc[25]~76_combout ), + .cout()); +// synopsys translate_off +defparam \F_acc[25]~76 .lut_mask = 16'h0FF0; +defparam \F_acc[25]~76 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N25 +dffeas \F_acc[25] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[25]~76_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[25]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[25] .is_wysiwyg = "true"; +defparam \F_acc[25] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N28 +cycloneive_lcell_comb \rom_address[9]~18 ( +// Equation(s): +// \rom_address[9]~18_combout = \Pword[9]~input_o $ (\rom_address[8]~17 $ (F_acc[25])) + + .dataa(gnd), + .datab(\Pword[9]~input_o ), + .datac(gnd), + .datad(F_acc[25]), + .cin(\rom_address[8]~17 ), + .combout(\rom_address[9]~18_combout ), + .cout()); +// synopsys translate_off +defparam \rom_address[9]~18 .lut_mask = 16'hC33C; +defparam \rom_address[9]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: M9K_X15_Y12_N0 +cycloneive_ram_block \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\clk_200m~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(vcc), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(9'b000000000), + .portaaddr({\rom_address[9]~18_combout ,\rom_address[8]~16_combout ,\rom_address[7]~14_combout ,\rom_address[6]~12_combout ,\rom_address[5]~10_combout ,\rom_address[4]~8_combout ,\rom_address[3]~6_combout ,\rom_address[2]~4_combout ,\rom_address[1]~2_combout , +\rom_address[0]~0_combout }), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr(10'b0000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .init_file = "sin9bit_1024.mif"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ALTSYNCRAM"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 10; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 1023; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 1024; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 10; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init4 = 1024'h7F3F1F6F97C3D9EAF3793C1DEED763A9D2E773395C6E27037DBADC6D365AED66AB4DA4D067B3598CA64B218CC561B0980BF5F2F176B95C2DD6AB4592C560AE56AAD54A953A994AA3512813E9E4E26D34984BA592893492411E8E46A2D148943A190A8441205007F3E9F0F67A3C1DCEC753A1C8E270379B8DA6B351A4D0673319; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h0C66230980BE5E2E970B65A2C15CAC552A14CA4512813C9C4D2612C94492411C8C45229108642209007E3E1E8F0783B1D0E470371B8D86A34198CC6431180C05E2E168B4582B158A852291409C4E2612894482411888442110880401F0F8783C1D0E870381B0D86834190C86030180B85C2E160B0542A150A85028140984C26130904824120884422110884020100804020100803C1E0F0783C1E0F0783C1E0F0783C1E0F0783C1E0F0783C20100804020100804022110884422120904824130984C26140A0502A150A8542C160B85C2E180C06032190D068361B0E0703A1D0F0783E1F100804221110884624120944A261389C5029148A8562B160B45A2E178; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'hC06031190CC66341A8D86E371C0E4743B1E0F07A3E1F9008242219108A452311C90492512C984D2713CA0512914CA8552B15CB05A2D970BA5E2F980C26231990CC67341A4D46B369B8DE70389C8E8753B1DCF07A3D9F0FA7F40205048442A190E894522D1A8E47A4124934A2592E984D26D389E4FA8144A352A994EA9552AD5AAE582C564B45AADD70B95DAF17CBF6030986C56332192CA663359ED06934DAAD66BB65B4DC6EB7DC0E271B95CCE774BA9D8ED77BC1E4F37ABD9F0F97DBF1FCFF8040A070583422130B8643A1F11894522B178C466371C8F47E4322924964F2894CAE592E97CC665349ACDA71399DCF27D3FA050A8745A351E934AA65369D50A8; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'hD4EA955ABD62B35BAE57ABF60B158EC966B3DA2D56BB65BADF70B8DCEE975BBDE2F37ABE5F6FD7FC0E0B0784C361F1189C56331B8EC7E432393CA6572D97CC66B379CCEE7B3FA0D0E8B47A4D369F51A9D56AF59ADD76BF61B1D96CF69B5DB6DF71B9DCEEB77BCDEEFB7FC0E0F0B85C3E27178DC7E3F2393CAE5F2F99CDE773B9FD0E8F47A5D3E9F53ABD5EB75FAFD8ECF67B5DAEDF73B9DDEEF7BBDDFEFF83C1E1F0F8BC5E3F1F93C9E5F2F9BCDE6F3F9FCFE8F47A7D3E9F4FABD5EAF5FAFD7EBF67B3D9ECF6FB7DBEDF6FBBDDEEF77BBDDEEF77BFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDDEEF77BBDDEEF77BBDBEDF6FB7DBECF67B3D9EBF; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h5FAFD7EAF57ABD3E9F4FA7D1E8F3F9FCFE6F379BCBE5F2793C7E3F178BC3E1F0783BFDFEF77BBBDDEE773B7DAED767B3D8EBF5FADD5EAF53A7D3E9747A3D0E7F3B9DCDE672F97CAE4F238FC7E371789C3E170B83C0DFEFB7BBCDDEEB73B9DC6DF6DB5DA6CF65B1D86BF5DADD66AF55A9D469F4DA4D1E8B43A0CFE7B3B9CCDE6B3197CB6572993C8E431F8EC6E331589C461F0D84C1E0B037FBF5F6F97ABCDE2EF75BA5CEE370B7DBAD96BB55A2CF66B258EC560AFD7AB95BACD62AF55AA54EA350A7536994AA4D1E8D45A1D0A813F9F4F277399C4DA6B34994C65F2E964AE532893C96492290C7E3D1C8DC6631178AC52251187C3A190B84C220D0581C0A00FF; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N20 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][11]~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][11]~0_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [7] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [4]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [6]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [5])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][11]~0 .lut_mask = 16'hCCC8; +defparam \modulation|Mult0|mult_core|romout[1][11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][10] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][10]~combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [6] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [4] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [7])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [6] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [7]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][10]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][10] .lut_mask = 16'hC1C8; +defparam \modulation|Mult0|mult_core|romout[1][10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][9] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][9]~combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [4] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (\spwm_sin|altsyncram_component|auto_generated|q_a [6] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [5])) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [6]) # (\spwm_sin|altsyncram_component|auto_generated|q_a [7])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][9]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][9] .lut_mask = 16'h0AD4; +defparam \modulation|Mult0|mult_core|romout[1][9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][8]~1 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][8]~1_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (\spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (((!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [6]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [6])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][8]~1 .lut_mask = 16'hA856; +defparam \modulation|Mult0|mult_core|romout[1][8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N30 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][11]~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][11]~2_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][11]~2_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][11]~2 .lut_mask = 16'hCCC8; +defparam \modulation|Mult0|mult_core|romout[0][11]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N4 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][7] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][7]~combout = \spwm_sin|altsyncram_component|auto_generated|q_a [6] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # ((!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [4])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][7]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][7] .lut_mask = 16'h45BA; +defparam \modulation|Mult0|mult_core|romout[1][7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][6] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][6]~combout = \spwm_sin|altsyncram_component|auto_generated|q_a [5] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [4] & !\spwm_sin|altsyncram_component|auto_generated|q_a [7]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(gnd), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][6]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][6] .lut_mask = 16'hF50A; +defparam \modulation|Mult0|mult_core|romout[1][6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N28 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][10]~3 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][10]~3_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [2] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [0])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [2] & (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [0]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][10]~3 .lut_mask = 16'hA2A4; +defparam \modulation|Mult0|mult_core|romout[0][10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N26 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][9]~5 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][9]~5_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [1] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [0]))) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & (\spwm_sin|altsyncram_component|auto_generated|q_a [2] & !\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][9]~5_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][9]~5 .lut_mask = 16'h380E; +defparam \modulation|Mult0|mult_core|romout[0][9]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][5]~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][5]~4_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (\spwm_sin|altsyncram_component|auto_generated|q_a [7]) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(gnd), + .datac(gnd), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][5]~4_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][5]~4 .lut_mask = 16'h55AA; +defparam \modulation|Mult0|mult_core|romout[1][5]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][8]~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][8]~6_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (\spwm_sin|altsyncram_component|auto_generated|q_a [0] $ (((!\spwm_sin|altsyncram_component|auto_generated|q_a [2] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [1]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [0] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [1])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][8]~6_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][8]~6 .lut_mask = 16'hC836; +defparam \modulation|Mult0|mult_core|romout[0][8]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N2 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][7]~7 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][7]~7_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [2] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [0] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [3])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][7]~7 .lut_mask = 16'h0DF2; +defparam \modulation|Mult0|mult_core|romout[0][7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][6]~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][6]~8_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [1] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [0] & !\spwm_sin|altsyncram_component|auto_generated|q_a [3]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(gnd), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][6]~8 .lut_mask = 16'hDD22; +defparam \modulation|Mult0|mult_core|romout[0][6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N6 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout = (\modulation|Mult0|mult_core|romout[0][6]~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (VCC))) # (!\modulation|Mult0|mult_core|romout[0][6]~8_combout & +// (\spwm_sin|altsyncram_component|auto_generated|q_a [4] & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 = CARRY((\modulation|Mult0|mult_core|romout[0][6]~8_combout & \spwm_sin|altsyncram_component|auto_generated|q_a [4])) + + .dataa(\modulation|Mult0|mult_core|romout[0][6]~8_combout ), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\modulation|Mult0|mult_core|romout[0][7]~7_combout & +// (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 & VCC)) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )))) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\modulation|Mult0|mult_core|romout[0][7]~7_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & +// ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [5] & (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 +// )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datab(\modulation|Mult0|mult_core|romout[0][7]~7_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout = ((\spwm_sin|altsyncram_component|auto_generated|q_a [6] $ (\modulation|Mult0|mult_core|romout[0][8]~6_combout $ +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 )))) # (GND) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [6] & ((\modulation|Mult0|mult_core|romout[0][8]~6_combout ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [6] & (\modulation|Mult0|mult_core|romout[0][8]~6_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 +// ))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datab(\modulation|Mult0|mult_core|romout[0][8]~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N12 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout = (\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((\modulation|Mult0|mult_core|romout[1][5]~4_combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 +// & VCC)) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )))) # (!\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((\modulation|Mult0|mult_core|romout[1][5]~4_combout & +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 = CARRY((\modulation|Mult0|mult_core|romout[0][9]~5_combout & (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )) +// # (!\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout )))) + + .dataa(\modulation|Mult0|mult_core|romout[0][9]~5_combout ), + .datab(\modulation|Mult0|mult_core|romout[1][5]~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N14 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout = ((\modulation|Mult0|mult_core|romout[1][6]~combout $ (\modulation|Mult0|mult_core|romout[0][10]~3_combout $ (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 +// )))) # (GND) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 = CARRY((\modulation|Mult0|mult_core|romout[1][6]~combout & ((\modulation|Mult0|mult_core|romout[0][10]~3_combout ) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 +// ))) # (!\modulation|Mult0|mult_core|romout[1][6]~combout & (\modulation|Mult0|mult_core|romout[0][10]~3_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ))) + + .dataa(\modulation|Mult0|mult_core|romout[1][6]~combout ), + .datab(\modulation|Mult0|mult_core|romout[0][10]~3_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N16 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout = (\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((\modulation|Mult0|mult_core|romout[1][7]~combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 +// & VCC)) # (!\modulation|Mult0|mult_core|romout[1][7]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )))) # (!\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((\modulation|Mult0|mult_core|romout[1][7]~combout & +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )) # (!\modulation|Mult0|mult_core|romout[1][7]~combout & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 = CARRY((\modulation|Mult0|mult_core|romout[0][11]~2_combout & (!\modulation|Mult0|mult_core|romout[1][7]~combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )) +// # (!\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (!\modulation|Mult0|mult_core|romout[1][7]~combout )))) + + .dataa(\modulation|Mult0|mult_core|romout[0][11]~2_combout ), + .datab(\modulation|Mult0|mult_core|romout[1][7]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N18 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout = (\modulation|Mult0|mult_core|romout[1][8]~1_combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 $ (GND))) # +// (!\modulation|Mult0|mult_core|romout[1][8]~1_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 = CARRY((\modulation|Mult0|mult_core|romout[1][8]~1_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 )) + + .dataa(\modulation|Mult0|mult_core|romout[1][8]~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 .lut_mask = 16'hA50A; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N20 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout = (\modulation|Mult0|mult_core|romout[1][9]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 )) # (!\modulation|Mult0|mult_core|romout[1][9]~combout +// & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ) # (GND))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 = CARRY((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ) # (!\modulation|Mult0|mult_core|romout[1][9]~combout )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|romout[1][9]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 .lut_mask = 16'h3C3F; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N22 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout = (\modulation|Mult0|mult_core|romout[1][10]~combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 $ (GND))) # +// (!\modulation|Mult0|mult_core|romout[1][10]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 = CARRY((\modulation|Mult0|mult_core|romout[1][10]~combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|romout[1][10]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 .lut_mask = 16'hC30C; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N24 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout = \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 $ (\modulation|Mult0|mult_core|romout[1][11]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\modulation|Mult0|mult_core|romout[1][11]~0_combout ), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 .lut_mask = 16'h0FF0; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [8] $ (VCC))) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & VCC)) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & \spwm_sin|altsyncram_component|auto_generated|q_a [8])) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N2 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # (GND))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 = CARRY((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout )) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h5A5F; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N4 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 $ +// (GND))) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 & VCC)) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .lut_mask = 16'hC30C; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N6 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 & VCC)) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )))) +// # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout = ((\spwm_sin|altsyncram_component|auto_generated|q_a [8] $ (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout $ +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )))) # (GND) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 & VCC)) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )))) +// # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N12 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout = !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .lut_mask = 16'h0F0F; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \modulation|LessThan0~0 ( +// Equation(s): +// \modulation|LessThan0~0_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [0]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [3]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .cin(gnd), + .combout(\modulation|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~0 .lut_mask = 16'hFFFE; +defparam \modulation|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \modulation|LessThan0~1 ( +// Equation(s): +// \modulation|LessThan0~1_combout = (\modulation|LessThan0~0_combout ) # ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ) # (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout )) + + .dataa(gnd), + .datab(\modulation|LessThan0~0_combout ), + .datac(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ), + .datad(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ), + .cin(gnd), + .combout(\modulation|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~1 .lut_mask = 16'hFFFC; +defparam \modulation|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \modulation|LessThan0~3 ( +// Equation(s): +// \modulation|LessThan0~3_cout = CARRY(\modulation|LessThan0~1_combout ) + + .dataa(gnd), + .datab(\modulation|LessThan0~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\modulation|LessThan0~3_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~3 .lut_mask = 16'h00CC; +defparam \modulation|LessThan0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \modulation|LessThan0~5 ( +// Equation(s): +// \modulation|LessThan0~5_cout = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout & (\tri_out[0]~reg0_q & !\modulation|LessThan0~3_cout )) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout & +// ((\tri_out[0]~reg0_q ) # (!\modulation|LessThan0~3_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ), + .datab(\tri_out[0]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~3_cout ), + .combout(), + .cout(\modulation|LessThan0~5_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~5 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \modulation|LessThan0~7 ( +// Equation(s): +// \modulation|LessThan0~7_cout = CARRY((\tri_out[1]~reg0_q & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout & !\modulation|LessThan0~5_cout )) # (!\tri_out[1]~reg0_q & +// ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ) # (!\modulation|LessThan0~5_cout )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~5_cout ), + .combout(), + .cout(\modulation|LessThan0~7_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~7 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \modulation|LessThan0~9 ( +// Equation(s): +// \modulation|LessThan0~9_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout & (\tri_out[2]~reg0_q & !\modulation|LessThan0~7_cout )) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout & ((\tri_out[2]~reg0_q ) # (!\modulation|LessThan0~7_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ), + .datab(\tri_out[2]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~7_cout ), + .combout(), + .cout(\modulation|LessThan0~9_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~9 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \modulation|LessThan0~11 ( +// Equation(s): +// \modulation|LessThan0~11_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout & ((!\modulation|LessThan0~9_cout ) # (!\tri_out[3]~reg0_q ))) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout & (!\tri_out[3]~reg0_q & !\modulation|LessThan0~9_cout ))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ), + .datab(\tri_out[3]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~9_cout ), + .combout(), + .cout(\modulation|LessThan0~11_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~11 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \modulation|LessThan0~13 ( +// Equation(s): +// \modulation|LessThan0~13_cout = CARRY((\tri_out[4]~reg0_q & ((!\modulation|LessThan0~11_cout ) # (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ))) # (!\tri_out[4]~reg0_q & +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout & !\modulation|LessThan0~11_cout ))) + + .dataa(\tri_out[4]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~11_cout ), + .combout(), + .cout(\modulation|LessThan0~13_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~13 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \modulation|LessThan0~15 ( +// Equation(s): +// \modulation|LessThan0~15_cout = CARRY((\tri_out[5]~reg0_q & (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout & !\modulation|LessThan0~13_cout )) # (!\tri_out[5]~reg0_q & +// ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (!\modulation|LessThan0~13_cout )))) + + .dataa(\tri_out[5]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~13_cout ), + .combout(), + .cout(\modulation|LessThan0~15_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~15 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \modulation|LessThan0~17 ( +// Equation(s): +// \modulation|LessThan0~17_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout & (\tri_out[6]~reg0_q & !\modulation|LessThan0~15_cout )) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout & ((\tri_out[6]~reg0_q ) # (!\modulation|LessThan0~15_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ), + .datab(\tri_out[6]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~15_cout ), + .combout(), + .cout(\modulation|LessThan0~17_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~17 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \modulation|LessThan0~19 ( +// Equation(s): +// \modulation|LessThan0~19_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout & ((!\modulation|LessThan0~17_cout ) # (!\tri_out[7]~reg0_q ))) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout & (!\tri_out[7]~reg0_q & !\modulation|LessThan0~17_cout ))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ), + .datab(\tri_out[7]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~17_cout ), + .combout(), + .cout(\modulation|LessThan0~19_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~19 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \modulation|LessThan0~20 ( +// Equation(s): +// \modulation|LessThan0~20_combout = (\tri_out[8]~reg0_q & (\modulation|LessThan0~19_cout & \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout )) # (!\tri_out[8]~reg0_q & ((\modulation|LessThan0~19_cout ) # +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ))) + + .dataa(gnd), + .datab(\tri_out[8]~reg0_q ), + .datac(gnd), + .datad(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ), + .cin(\modulation|LessThan0~19_cout ), + .combout(\modulation|LessThan0~20_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~20 .lut_mask = 16'hF330; +defparam \modulation|LessThan0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y12_N23 +dffeas \modulation|out ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\modulation|LessThan0~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\modulation|out~q ), + .prn(vcc)); +// synopsys translate_off +defparam \modulation|out .is_wysiwyg = "true"; +defparam \modulation|out .power_up = "low"; +// synopsys translate_on + +assign tri_out[0] = \tri_out[0]~output_o ; + +assign tri_out[1] = \tri_out[1]~output_o ; + +assign tri_out[2] = \tri_out[2]~output_o ; + +assign tri_out[3] = \tri_out[3]~output_o ; + +assign tri_out[4] = \tri_out[4]~output_o ; + +assign tri_out[5] = \tri_out[5]~output_o ; + +assign tri_out[6] = \tri_out[6]~output_o ; + +assign tri_out[7] = \tri_out[7]~output_o ; + +assign tri_out[8] = \tri_out[8]~output_o ; + +assign sin_out[0] = \sin_out[0]~output_o ; + +assign sin_out[1] = \sin_out[1]~output_o ; + +assign sin_out[2] = \sin_out[2]~output_o ; + +assign sin_out[3] = \sin_out[3]~output_o ; + +assign sin_out[4] = \sin_out[4]~output_o ; + +assign sin_out[5] = \sin_out[5]~output_o ; + +assign sin_out[6] = \sin_out[6]~output_o ; + +assign sin_out[7] = \sin_out[7]~output_o ; + +assign sin_out[8] = \sin_out[8]~output_o ; + +assign spwm_out = \spwm_out~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_DATA0~~ibuf_o ; + + +endmodule diff --git a/spwm/simulation/modelsim/spwm_8_1200mv_0c_v_slow.sdo b/spwm/simulation/modelsim/spwm_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..023c4ac --- /dev/null +++ b/spwm/simulation/modelsim/spwm_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,2573 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "spwm") + (DATE "12/10/2018 20:55:32") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1097:1097:1097) (951:951:951)) + (IOPATH i o (2793:2793:2793) (2757:2757:2757)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1399:1399:1399) (1219:1219:1219)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1434:1434:1434) (1241:1241:1241)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1063:1063:1063) (929:929:929)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1490:1490:1490) (1308:1308:1308)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1443:1443:1443) (1264:1264:1264)) + (IOPATH i o (2773:2773:2773) (2737:2737:2737)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1076:1076:1076) (951:951:951)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1411:1411:1411) (1184:1184:1184)) + (IOPATH i o (2793:2793:2793) (2757:2757:2757)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1078:1078:1078) (950:950:950)) + (IOPATH i o (2773:2773:2773) (2737:2737:2737)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1560:1560:1560) (1352:1352:1352)) + (IOPATH i o (2793:2793:2793) (2757:2757:2757)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1981:1981:1981) (1565:1565:1565)) + (IOPATH i o (2697:2697:2697) (2676:2676:2676)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1816:1816:1816) (1548:1548:1548)) + (IOPATH i o (2763:2763:2763) (2727:2727:2727)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1804:1804:1804) (1519:1519:1519)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1725:1725:1725) (1458:1458:1458)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1899:1899:1899) (1493:1493:1493)) + (IOPATH i o (2790:2790:2790) (2752:2752:2752)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1725:1725:1725) (1419:1419:1419)) + (IOPATH i o (2800:2800:2800) (2762:2762:2762)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2172:2172:2172) (1839:1839:1839)) + (IOPATH i o (2763:2763:2763) (2727:2727:2727)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1830:1830:1830) (1568:1568:1568)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE spwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (1560:1560:1560) (1394:1394:1394)) + (IOPATH i o (2783:2783:2783) (2747:2747:2747)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk_200m\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_200m\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (194:194:194) (190:190:190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (434:434:434)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (758:758:758) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (194:194:194) (190:190:190)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[0\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1466:1466:1466) (1506:1506:1506)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1529:1529:1529) (1458:1458:1458)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (416:416:416)) + (PORT datab (857:857:857) (684:684:684)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (748:748:748)) + (PORT datab (357:357:357) (418:418:418)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[2\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1466:1466:1466) (1506:1506:1506)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1529:1529:1529) (1458:1458:1458)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (747:747:747)) + (PORT datab (348:348:348) (405:405:405)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[3\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1466:1466:1466) (1506:1506:1506)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1529:1529:1529) (1458:1458:1458)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (747:747:747)) + (PORT datab (349:349:349) (407:407:407)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[4\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1466:1466:1466) (1506:1506:1506)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1529:1529:1529) (1458:1458:1458)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (746:746:746)) + (PORT datab (340:340:340) (396:396:396)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[5\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1466:1466:1466) (1506:1506:1506)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1529:1529:1529) (1458:1458:1458)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (746:746:746)) + (PORT datab (568:568:568) (566:566:566)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[6\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1466:1466:1466) (1506:1506:1506)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1529:1529:1529) (1458:1458:1458)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (746:746:746)) + (PORT datab (346:346:346) (404:404:404)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[7\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1466:1466:1466) (1506:1506:1506)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1529:1529:1529) (1458:1458:1458)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (730:730:730)) + (PORT datad (794:794:794) (640:640:640)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[8\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1466:1466:1466) (1506:1506:1506)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1529:1529:1529) (1458:1458:1458)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~12) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (413:413:413)) + (PORT datab (356:356:356) (417:417:417)) + (PORT datac (769:769:769) (693:693:693)) + (PORT datad (307:307:307) (366:366:366)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~11) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (558:558:558)) + (PORT datab (349:349:349) (407:407:407)) + (PORT datac (314:314:314) (384:384:384)) + (PORT datad (307:307:307) (367:367:367)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE updown) + (DELAY + (ABSOLUTE + (PORT clk (1466:1466:1466) (1506:1506:1506)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1529:1529:1529) (1458:1458:1458)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~13) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (416:416:416)) + (PORT datab (315:315:315) (369:369:369)) + (PORT datac (304:304:304) (372:372:372)) + (PORT datad (332:332:332) (392:392:392)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~14) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (285:285:285)) + (PORT datab (271:271:271) (278:278:278)) + (PORT datad (437:437:437) (373:373:373)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[1\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1466:1466:1466) (1506:1506:1506)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1529:1529:1529) (1458:1458:1458)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (718:718:718) (743:743:743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (757:757:757) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (747:747:747) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (747:747:747) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (707:707:707) (731:731:731)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (377:377:377)) + (PORT datab (2957:2957:2957) (3086:3086:3086)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (3238:3238:3238) (3286:3286:3286)) + (PORT datab (316:316:316) (370:370:370)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (378:378:378)) + (PORT datab (3292:3292:3292) (3333:3333:3333)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (378:378:378)) + (PORT datab (3582:3582:3582) (3521:3521:3521)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[4\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (3244:3244:3244) (3308:3308:3308)) + (PORT datab (317:317:317) (371:371:371)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[5\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (3350:3350:3350) (3369:3369:3369)) + (PORT datab (317:317:317) (371:371:371)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[6\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (3167:3167:3167) (3250:3250:3250)) + (PORT datab (317:317:317) (371:371:371)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[7\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (3013:3013:3013) (3115:3115:3115)) + (PORT datab (317:317:317) (371:371:371)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[8\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (378:378:378)) + (PORT datab (3205:3205:3205) (3255:3255:3255)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[9\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (3292:3292:3292) (3324:3324:3324)) + (PORT datab (317:317:317) (371:371:371)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[10\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (378:378:378)) + (PORT datab (3173:3173:3173) (3256:3256:3256)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[11\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (2924:2924:2924) (3073:3073:3073)) + (PORT datab (316:316:316) (370:370:370)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[12\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (377:377:377)) + (PORT datab (2977:2977:2977) (3093:3093:3093)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1473:1473:1473) (1512:1512:1512)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1535:1535:1535) (1465:1465:1465)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[13\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (3327:3327:3327) (3353:3353:3353)) + (PORT datab (316:316:316) (370:370:370)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[14\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (3291:3291:3291) (3346:3346:3346)) + (PORT datab (316:316:316) (370:370:370)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[15\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (3226:3226:3226) (3208:3208:3208)) + (PORT datab (317:317:317) (371:371:371)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[16\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3168:3168:3168) (3230:3230:3230)) + (PORT datab (547:547:547) (522:522:522)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[17\]\~60) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (738:738:738) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (528:528:528)) + (PORT datab (3587:3587:3587) (3538:3538:3538)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[18\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (557:557:557)) + (PORT datab (3198:3198:3198) (3248:3248:3248)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[19\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (708:708:708) (733:733:733)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (558:558:558)) + (PORT datab (3578:3578:3578) (3556:3556:3556)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[20\]\~66) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (532:532:532)) + (PORT datab (3180:3180:3180) (3188:3188:3188)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[21\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (532:532:532)) + (PORT datab (3265:3265:3265) (3343:3343:3343)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[22\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (3577:3577:3577) (3549:3549:3549)) + (PORT datab (542:542:542) (522:522:522)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[23\]\~72) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (3639:3639:3639) (3593:3593:3593)) + (PORT datab (598:598:598) (548:548:548)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (718:718:718) (743:743:743)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[24\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[8\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (3179:3179:3179) (3187:3187:3187)) + (PORT datab (542:542:542) (521:521:521)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (707:707:707) (731:731:731)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[25\]\~76) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (355:355:355)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[25\]) + (DELAY + (ABSOLUTE + (PORT clk (1472:1472:1472) (1510:1510:1510)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1533:1533:1533) (1464:1464:1464)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[9\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (3249:3249:3249) (3309:3309:3309)) + (PORT datad (537:537:537) (505:505:505)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1739:1739:1739) (1469:1469:1469)) + (PORT d[1] (1810:1810:1810) (1513:1513:1513)) + (PORT d[2] (2146:2146:2146) (1805:1805:1805)) + (PORT d[3] (2218:2218:2218) (1849:1849:1849)) + (PORT d[4] (2019:2019:2019) (1839:1839:1839)) + (PORT d[5] (2115:2115:2115) (1784:1784:1784)) + (PORT d[6] (2163:2163:2163) (1831:1831:1831)) + (PORT d[7] (2185:2185:2185) (1833:1833:1833)) + (PORT d[8] (2147:2147:2147) (1803:1803:1803)) + (PORT d[9] (2076:2076:2076) (1849:1849:1849)) + (PORT clk (1818:1818:1818) (1881:1881:1881)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1818:1818:1818) (1881:1881:1881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1819:1819:1819) (1882:1882:1882)) + (IOPATH (posedge clk) pulse (0:0:0) (2853:2853:2853)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1773:1773:1773) (1834:1834:1834)) + (IOPATH (posedge clk) q (355:355:355) (355:355:355)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (56:56:56)) + (HOLD d (posedge clk) (190:190:190)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (845:845:845) (868:868:868)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (846:846:846) (869:869:869)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (846:846:846) (869:869:869)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (846:846:846) (869:869:869)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (868:868:868)) + (PORT datab (965:965:965) (837:837:837)) + (PORT datac (954:954:954) (831:831:831)) + (PORT datad (870:870:870) (766:766:766)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[10\]) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (865:865:865)) + (PORT datab (1004:1004:1004) (863:863:863)) + (PORT datac (877:877:877) (764:764:764)) + (PORT datad (907:907:907) (799:799:799)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[9\]) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (481:481:481)) + (PORT datab (574:574:574) (484:484:484)) + (PORT datac (532:532:532) (461:461:461)) + (PORT datad (520:520:520) (451:451:451)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (501:501:501)) + (PORT datab (580:580:580) (491:491:491)) + (PORT datac (524:524:524) (453:453:453)) + (PORT datad (497:497:497) (439:439:439)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[11\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (732:732:732)) + (PORT datab (855:855:855) (702:702:702)) + (PORT datac (777:777:777) (654:654:654)) + (PORT datad (798:798:798) (664:664:664)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (689:689:689)) + (PORT datab (776:776:776) (644:644:644)) + (PORT datac (751:751:751) (624:624:624)) + (PORT datad (823:823:823) (673:673:673)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (474:474:474)) + (PORT datac (537:537:537) (467:467:467)) + (PORT datad (521:521:521) (452:452:452)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (731:731:731)) + (PORT datab (855:855:855) (702:702:702)) + (PORT datac (777:777:777) (654:654:654)) + (PORT datad (798:798:798) (664:664:664)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[9\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (730:730:730)) + (PORT datab (855:855:855) (702:702:702)) + (PORT datac (777:777:777) (654:654:654)) + (PORT datad (798:798:798) (663:663:663)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (864:864:864)) + (PORT datad (907:907:907) (799:799:799)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[8\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (720:720:720)) + (PORT datab (862:862:862) (710:710:710)) + (PORT datac (780:780:780) (657:657:657)) + (PORT datad (795:795:795) (659:659:659)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (709:709:709)) + (PORT datab (861:861:861) (709:709:709)) + (PORT datac (780:780:780) (657:657:657)) + (PORT datad (808:808:808) (672:672:672)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (474:474:474)) + (PORT datab (565:565:565) (473:473:473)) + (PORT datad (509:509:509) (435:435:435)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (677:677:677)) + (PORT datab (793:793:793) (657:657:657)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (688:688:688)) + (PORT datab (266:266:266) (272:272:272)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (722:722:722)) + (PORT datab (266:266:266) (273:273:273)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (281:281:281)) + (PORT datab (814:814:814) (688:688:688)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (639:639:639)) + (PORT datab (267:267:267) (274:274:274)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (280:280:280)) + (PORT datab (267:267:267) (274:274:274)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (753:753:753) (615:615:615)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT datab (803:803:803) (638:638:638)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT datab (824:824:824) (699:699:699)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~18) + (DELAY + (ABSOLUTE + (PORT datad (859:859:859) (720:720:720)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (411:411:411)) + (PORT datab (890:890:890) (757:757:757)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (417:417:417)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT datab (471:471:471) (406:406:406)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (793:793:793)) + (PORT datab (528:528:528) (432:432:432)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (793:793:793)) + (PORT datab (471:471:471) (406:406:406)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (794:794:794)) + (PORT datab (528:528:528) (432:432:432)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (476:476:476)) + (PORT datab (570:570:570) (477:477:477)) + (PORT datac (467:467:467) (410:410:410)) + (PORT datad (506:506:506) (433:433:433)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT datab (270:270:270) (278:278:278)) + (PORT datac (787:787:787) (649:649:649)) + (PORT datad (761:761:761) (632:632:632)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT datab (266:266:266) (272:272:272)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (659:659:659)) + (PORT datab (1345:1345:1345) (1214:1214:1214)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1867:1867:1867) (1625:1625:1625)) + (PORT datab (852:852:852) (710:710:710)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (434:434:434)) + (PORT datab (1645:1645:1645) (1491:1491:1491)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (433:433:433)) + (PORT datab (1672:1672:1672) (1459:1459:1459)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1347:1347:1347) (1249:1249:1249)) + (PORT datab (468:468:468) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1358:1358:1358) (1218:1218:1218)) + (PORT datab (476:476:476) (401:401:401)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (407:407:407)) + (PORT datab (1334:1334:1334) (1212:1212:1212)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (436:436:436)) + (PORT datab (1300:1300:1300) (1192:1192:1192)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~20) + (DELAY + (ABSOLUTE + (PORT datab (1337:1337:1337) (1235:1235:1235)) + (PORT datad (463:463:463) (384:384:384)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE modulation\|out) + (DELAY + (ABSOLUTE + (PORT clk (1925:1925:1925) (1920:1920:1920)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) +) diff --git a/spwm/simulation/modelsim/spwm_8_1200mv_85c_slow.vo b/spwm/simulation/modelsim/spwm_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..58abfd9 --- /dev/null +++ b/spwm/simulation/modelsim/spwm_8_1200mv_85c_slow.vo @@ -0,0 +1,3398 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" + +// DATE "12/10/2018 20:55:31" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module spwm ( + clk_200m, + rst_n, + tri_out, + sin_out, + Fword, + Pword, + spwm_out); +input clk_200m; +input rst_n; +output [8:0] tri_out; +output [8:0] sin_out; +input [15:0] Fword; +input [9:0] Pword; +output spwm_out; + +// Design Ports Information +// tri_out[0] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[1] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[2] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[3] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[4] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[5] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[6] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[7] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[8] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[0] => Location: PIN_M8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[1] => Location: PIN_J6, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[2] => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[3] => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[4] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[5] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[6] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[7] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[8] => Location: PIN_R8, I/O Standard: 2.5 V, Current Strength: Default +// spwm_out => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +// clk_200m => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[0] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// Pword[1] => Location: PIN_D1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[2] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// Pword[3] => Location: PIN_F3, I/O Standard: 2.5 V, Current Strength: Default +// Pword[4] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[5] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// Pword[6] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[7] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[8] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[9] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[15] => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[14] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// Fword[13] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +// Fword[12] => Location: PIN_A2, I/O Standard: 2.5 V, Current Strength: Default +// Fword[11] => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[10] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[9] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[8] => Location: PIN_A3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[7] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default +// Fword[6] => Location: PIN_D3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[5] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// Fword[4] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[3] => Location: PIN_D5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[2] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// Fword[1] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[0] => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("spwm_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \tri_out[0]~output_o ; +wire \tri_out[1]~output_o ; +wire \tri_out[2]~output_o ; +wire \tri_out[3]~output_o ; +wire \tri_out[4]~output_o ; +wire \tri_out[5]~output_o ; +wire \tri_out[6]~output_o ; +wire \tri_out[7]~output_o ; +wire \tri_out[8]~output_o ; +wire \sin_out[0]~output_o ; +wire \sin_out[1]~output_o ; +wire \sin_out[2]~output_o ; +wire \sin_out[3]~output_o ; +wire \sin_out[4]~output_o ; +wire \sin_out[5]~output_o ; +wire \sin_out[6]~output_o ; +wire \sin_out[7]~output_o ; +wire \sin_out[8]~output_o ; +wire \spwm_out~output_o ; +wire \clk_200m~input_o ; +wire \clk_200m~inputclkctrl_outclk ; +wire \tri_out[0]~9_combout ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \tri_out[0]~reg0_q ; +wire \tri_out[0]~10 ; +wire \tri_out[1]~16 ; +wire \tri_out[2]~17_combout ; +wire \tri_out[2]~reg0_q ; +wire \tri_out[2]~18 ; +wire \tri_out[3]~19_combout ; +wire \tri_out[3]~reg0_q ; +wire \tri_out[3]~20 ; +wire \tri_out[4]~21_combout ; +wire \tri_out[4]~reg0_q ; +wire \tri_out[4]~22 ; +wire \tri_out[5]~23_combout ; +wire \tri_out[5]~reg0_q ; +wire \tri_out[5]~24 ; +wire \tri_out[6]~25_combout ; +wire \tri_out[6]~reg0_q ; +wire \tri_out[6]~26 ; +wire \tri_out[7]~27_combout ; +wire \tri_out[7]~reg0_q ; +wire \tri_out[7]~28 ; +wire \tri_out[8]~29_combout ; +wire \tri_out[8]~reg0_q ; +wire \tri_out~12_combout ; +wire \tri_out~11_combout ; +wire \updown~q ; +wire \tri_out~13_combout ; +wire \tri_out~14_combout ; +wire \tri_out[1]~15_combout ; +wire \tri_out[1]~reg0_q ; +wire \Pword[0]~input_o ; +wire \Fword[15]~input_o ; +wire \Fword[14]~input_o ; +wire \Fword[13]~input_o ; +wire \Fword[12]~input_o ; +wire \Fword[11]~input_o ; +wire \Fword[10]~input_o ; +wire \Fword[9]~input_o ; +wire \Fword[8]~input_o ; +wire \Fword[7]~input_o ; +wire \Fword[6]~input_o ; +wire \Fword[5]~input_o ; +wire \Fword[4]~input_o ; +wire \Fword[3]~input_o ; +wire \Fword[2]~input_o ; +wire \Fword[1]~input_o ; +wire \Fword[0]~input_o ; +wire \F_acc[0]~26_combout ; +wire \F_acc[0]~27 ; +wire \F_acc[1]~28_combout ; +wire \F_acc[1]~29 ; +wire \F_acc[2]~30_combout ; +wire \F_acc[2]~31 ; +wire \F_acc[3]~32_combout ; +wire \F_acc[3]~33 ; +wire \F_acc[4]~34_combout ; +wire \F_acc[4]~35 ; +wire \F_acc[5]~36_combout ; +wire \F_acc[5]~37 ; +wire \F_acc[6]~38_combout ; +wire \F_acc[6]~39 ; +wire \F_acc[7]~40_combout ; +wire \F_acc[7]~41 ; +wire \F_acc[8]~42_combout ; +wire \F_acc[8]~43 ; +wire \F_acc[9]~44_combout ; +wire \F_acc[9]~45 ; +wire \F_acc[10]~46_combout ; +wire \F_acc[10]~47 ; +wire \F_acc[11]~48_combout ; +wire \F_acc[11]~49 ; +wire \F_acc[12]~50_combout ; +wire \F_acc[12]~51 ; +wire \F_acc[13]~52_combout ; +wire \F_acc[13]~53 ; +wire \F_acc[14]~54_combout ; +wire \F_acc[14]~55 ; +wire \F_acc[15]~56_combout ; +wire \F_acc[15]~57 ; +wire \F_acc[16]~58_combout ; +wire \rom_address[0]~0_combout ; +wire \F_acc[16]~59 ; +wire \F_acc[17]~60_combout ; +wire \Pword[1]~input_o ; +wire \rom_address[0]~1 ; +wire \rom_address[1]~2_combout ; +wire \F_acc[17]~61 ; +wire \F_acc[18]~62_combout ; +wire \Pword[2]~input_o ; +wire \rom_address[1]~3 ; +wire \rom_address[2]~4_combout ; +wire \F_acc[18]~63 ; +wire \F_acc[19]~64_combout ; +wire \Pword[3]~input_o ; +wire \rom_address[2]~5 ; +wire \rom_address[3]~6_combout ; +wire \F_acc[19]~65 ; +wire \F_acc[20]~66_combout ; +wire \Pword[4]~input_o ; +wire \rom_address[3]~7 ; +wire \rom_address[4]~8_combout ; +wire \F_acc[20]~67 ; +wire \F_acc[21]~68_combout ; +wire \Pword[5]~input_o ; +wire \rom_address[4]~9 ; +wire \rom_address[5]~10_combout ; +wire \Pword[6]~input_o ; +wire \F_acc[21]~69 ; +wire \F_acc[22]~70_combout ; +wire \rom_address[5]~11 ; +wire \rom_address[6]~12_combout ; +wire \Pword[7]~input_o ; +wire \F_acc[22]~71 ; +wire \F_acc[23]~72_combout ; +wire \rom_address[6]~13 ; +wire \rom_address[7]~14_combout ; +wire \Pword[8]~input_o ; +wire \F_acc[23]~73 ; +wire \F_acc[24]~74_combout ; +wire \rom_address[7]~15 ; +wire \rom_address[8]~16_combout ; +wire \Pword[9]~input_o ; +wire \F_acc[24]~75 ; +wire \F_acc[25]~76_combout ; +wire \rom_address[8]~17 ; +wire \rom_address[9]~18_combout ; +wire \modulation|Mult0|mult_core|romout[1][11]~0_combout ; +wire \modulation|Mult0|mult_core|romout[1][10]~combout ; +wire \modulation|Mult0|mult_core|romout[1][9]~combout ; +wire \modulation|Mult0|mult_core|romout[1][8]~1_combout ; +wire \modulation|Mult0|mult_core|romout[0][11]~2_combout ; +wire \modulation|Mult0|mult_core|romout[1][7]~combout ; +wire \modulation|Mult0|mult_core|romout[1][6]~combout ; +wire \modulation|Mult0|mult_core|romout[0][10]~3_combout ; +wire \modulation|Mult0|mult_core|romout[0][9]~5_combout ; +wire \modulation|Mult0|mult_core|romout[1][5]~4_combout ; +wire \modulation|Mult0|mult_core|romout[0][8]~6_combout ; +wire \modulation|Mult0|mult_core|romout[0][7]~7_combout ; +wire \modulation|Mult0|mult_core|romout[0][6]~8_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ; +wire \modulation|LessThan0~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ; +wire \modulation|LessThan0~1_combout ; +wire \modulation|LessThan0~3_cout ; +wire \modulation|LessThan0~5_cout ; +wire \modulation|LessThan0~7_cout ; +wire \modulation|LessThan0~9_cout ; +wire \modulation|LessThan0~11_cout ; +wire \modulation|LessThan0~13_cout ; +wire \modulation|LessThan0~15_cout ; +wire \modulation|LessThan0~17_cout ; +wire \modulation|LessThan0~19_cout ; +wire \modulation|LessThan0~20_combout ; +wire \modulation|out~q ; +wire [8:0] \spwm_sin|altsyncram_component|auto_generated|q_a ; +wire [25:0] F_acc; + +wire [8:0] \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; + +assign \spwm_sin|altsyncram_component|auto_generated|q_a [0] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [1] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [2] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [3] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [4] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [5] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [6] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [7] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [8] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [8]; + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: IOOBUF_X13_Y24_N23 +cycloneive_io_obuf \tri_out[0]~output ( + .i(\tri_out[0]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[0]~output .bus_hold = "false"; +defparam \tri_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N2 +cycloneive_io_obuf \tri_out[1]~output ( + .i(\tri_out[1]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[1]~output .bus_hold = "false"; +defparam \tri_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N23 +cycloneive_io_obuf \tri_out[2]~output ( + .i(\tri_out[2]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[2]~output .bus_hold = "false"; +defparam \tri_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N16 +cycloneive_io_obuf \tri_out[3]~output ( + .i(\tri_out[3]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[3]~output .bus_hold = "false"; +defparam \tri_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N9 +cycloneive_io_obuf \tri_out[4]~output ( + .i(\tri_out[4]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[4]~output .bus_hold = "false"; +defparam \tri_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N16 +cycloneive_io_obuf \tri_out[5]~output ( + .i(\tri_out[5]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[5]~output .bus_hold = "false"; +defparam \tri_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N9 +cycloneive_io_obuf \tri_out[6]~output ( + .i(\tri_out[6]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[6]~output .bus_hold = "false"; +defparam \tri_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N16 +cycloneive_io_obuf \tri_out[7]~output ( + .i(\tri_out[7]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[7]~output .bus_hold = "false"; +defparam \tri_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N2 +cycloneive_io_obuf \tri_out[8]~output ( + .i(\tri_out[8]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[8]~output .bus_hold = "false"; +defparam \tri_out[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y0_N2 +cycloneive_io_obuf \sin_out[0]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[0]~output .bus_hold = "false"; +defparam \sin_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N23 +cycloneive_io_obuf \sin_out[1]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[1]~output .bus_hold = "false"; +defparam \sin_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N9 +cycloneive_io_obuf \sin_out[2]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[2]~output .bus_hold = "false"; +defparam \sin_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N2 +cycloneive_io_obuf \sin_out[3]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[3]~output .bus_hold = "false"; +defparam \sin_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N23 +cycloneive_io_obuf \sin_out[4]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[4]~output .bus_hold = "false"; +defparam \sin_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N2 +cycloneive_io_obuf \sin_out[5]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[5]~output .bus_hold = "false"; +defparam \sin_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N16 +cycloneive_io_obuf \sin_out[6]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[6]~output .bus_hold = "false"; +defparam \sin_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N16 +cycloneive_io_obuf \sin_out[7]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[7]~output .bus_hold = "false"; +defparam \sin_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N9 +cycloneive_io_obuf \sin_out[8]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[8]~output .bus_hold = "false"; +defparam \sin_out[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y0_N16 +cycloneive_io_obuf \spwm_out~output ( + .i(\modulation|out~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\spwm_out~output_o ), + .obar()); +// synopsys translate_off +defparam \spwm_out~output .bus_hold = "false"; +defparam \spwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk_200m~input ( + .i(clk_200m), + .ibar(gnd), + .o(\clk_200m~input_o )); +// synopsys translate_off +defparam \clk_200m~input .bus_hold = "false"; +defparam \clk_200m~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk_200m~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_200m~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_200m~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk_200m~inputclkctrl .clock_type = "global clock"; +defparam \clk_200m~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N10 +cycloneive_lcell_comb \tri_out[0]~9 ( +// Equation(s): +// \tri_out[0]~9_combout = \tri_out[0]~reg0_q $ (VCC) +// \tri_out[0]~10 = CARRY(\tri_out[0]~reg0_q ) + + .dataa(\tri_out[0]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\tri_out[0]~9_combout ), + .cout(\tri_out[0]~10 )); +// synopsys translate_off +defparam \tri_out[0]~9 .lut_mask = 16'h55AA; +defparam \tri_out[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X14_Y19_N11 +dffeas \tri_out[0]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[0]~9_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[0]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[0]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[0]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N12 +cycloneive_lcell_comb \tri_out[1]~15 ( +// Equation(s): +// \tri_out[1]~15_combout = (\tri_out[1]~reg0_q & ((\tri_out~14_combout & (\tri_out[0]~10 & VCC)) # (!\tri_out~14_combout & (!\tri_out[0]~10 )))) # (!\tri_out[1]~reg0_q & ((\tri_out~14_combout & (!\tri_out[0]~10 )) # (!\tri_out~14_combout & +// ((\tri_out[0]~10 ) # (GND))))) +// \tri_out[1]~16 = CARRY((\tri_out[1]~reg0_q & (!\tri_out~14_combout & !\tri_out[0]~10 )) # (!\tri_out[1]~reg0_q & ((!\tri_out[0]~10 ) # (!\tri_out~14_combout )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\tri_out~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[0]~10 ), + .combout(\tri_out[1]~15_combout ), + .cout(\tri_out[1]~16 )); +// synopsys translate_off +defparam \tri_out[1]~15 .lut_mask = 16'h9617; +defparam \tri_out[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N14 +cycloneive_lcell_comb \tri_out[2]~17 ( +// Equation(s): +// \tri_out[2]~17_combout = ((\tri_out~14_combout $ (\tri_out[2]~reg0_q $ (!\tri_out[1]~16 )))) # (GND) +// \tri_out[2]~18 = CARRY((\tri_out~14_combout & ((\tri_out[2]~reg0_q ) # (!\tri_out[1]~16 ))) # (!\tri_out~14_combout & (\tri_out[2]~reg0_q & !\tri_out[1]~16 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[2]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[1]~16 ), + .combout(\tri_out[2]~17_combout ), + .cout(\tri_out[2]~18 )); +// synopsys translate_off +defparam \tri_out[2]~17 .lut_mask = 16'h698E; +defparam \tri_out[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N15 +dffeas \tri_out[2]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[2]~17_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[2]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[2]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[2]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N16 +cycloneive_lcell_comb \tri_out[3]~19 ( +// Equation(s): +// \tri_out[3]~19_combout = (\tri_out~14_combout & ((\tri_out[3]~reg0_q & (\tri_out[2]~18 & VCC)) # (!\tri_out[3]~reg0_q & (!\tri_out[2]~18 )))) # (!\tri_out~14_combout & ((\tri_out[3]~reg0_q & (!\tri_out[2]~18 )) # (!\tri_out[3]~reg0_q & +// ((\tri_out[2]~18 ) # (GND))))) +// \tri_out[3]~20 = CARRY((\tri_out~14_combout & (!\tri_out[3]~reg0_q & !\tri_out[2]~18 )) # (!\tri_out~14_combout & ((!\tri_out[2]~18 ) # (!\tri_out[3]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[3]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[2]~18 ), + .combout(\tri_out[3]~19_combout ), + .cout(\tri_out[3]~20 )); +// synopsys translate_off +defparam \tri_out[3]~19 .lut_mask = 16'h9617; +defparam \tri_out[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N17 +dffeas \tri_out[3]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[3]~19_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[3]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[3]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[3]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N18 +cycloneive_lcell_comb \tri_out[4]~21 ( +// Equation(s): +// \tri_out[4]~21_combout = ((\tri_out~14_combout $ (\tri_out[4]~reg0_q $ (!\tri_out[3]~20 )))) # (GND) +// \tri_out[4]~22 = CARRY((\tri_out~14_combout & ((\tri_out[4]~reg0_q ) # (!\tri_out[3]~20 ))) # (!\tri_out~14_combout & (\tri_out[4]~reg0_q & !\tri_out[3]~20 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[4]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[3]~20 ), + .combout(\tri_out[4]~21_combout ), + .cout(\tri_out[4]~22 )); +// synopsys translate_off +defparam \tri_out[4]~21 .lut_mask = 16'h698E; +defparam \tri_out[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N19 +dffeas \tri_out[4]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[4]~21_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[4]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[4]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[4]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N20 +cycloneive_lcell_comb \tri_out[5]~23 ( +// Equation(s): +// \tri_out[5]~23_combout = (\tri_out~14_combout & ((\tri_out[5]~reg0_q & (\tri_out[4]~22 & VCC)) # (!\tri_out[5]~reg0_q & (!\tri_out[4]~22 )))) # (!\tri_out~14_combout & ((\tri_out[5]~reg0_q & (!\tri_out[4]~22 )) # (!\tri_out[5]~reg0_q & +// ((\tri_out[4]~22 ) # (GND))))) +// \tri_out[5]~24 = CARRY((\tri_out~14_combout & (!\tri_out[5]~reg0_q & !\tri_out[4]~22 )) # (!\tri_out~14_combout & ((!\tri_out[4]~22 ) # (!\tri_out[5]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[5]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[4]~22 ), + .combout(\tri_out[5]~23_combout ), + .cout(\tri_out[5]~24 )); +// synopsys translate_off +defparam \tri_out[5]~23 .lut_mask = 16'h9617; +defparam \tri_out[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N21 +dffeas \tri_out[5]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[5]~23_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[5]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[5]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[5]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N22 +cycloneive_lcell_comb \tri_out[6]~25 ( +// Equation(s): +// \tri_out[6]~25_combout = ((\tri_out~14_combout $ (\tri_out[6]~reg0_q $ (!\tri_out[5]~24 )))) # (GND) +// \tri_out[6]~26 = CARRY((\tri_out~14_combout & ((\tri_out[6]~reg0_q ) # (!\tri_out[5]~24 ))) # (!\tri_out~14_combout & (\tri_out[6]~reg0_q & !\tri_out[5]~24 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[6]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[5]~24 ), + .combout(\tri_out[6]~25_combout ), + .cout(\tri_out[6]~26 )); +// synopsys translate_off +defparam \tri_out[6]~25 .lut_mask = 16'h698E; +defparam \tri_out[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N23 +dffeas \tri_out[6]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[6]~25_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[6]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[6]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[6]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N24 +cycloneive_lcell_comb \tri_out[7]~27 ( +// Equation(s): +// \tri_out[7]~27_combout = (\tri_out~14_combout & ((\tri_out[7]~reg0_q & (\tri_out[6]~26 & VCC)) # (!\tri_out[7]~reg0_q & (!\tri_out[6]~26 )))) # (!\tri_out~14_combout & ((\tri_out[7]~reg0_q & (!\tri_out[6]~26 )) # (!\tri_out[7]~reg0_q & +// ((\tri_out[6]~26 ) # (GND))))) +// \tri_out[7]~28 = CARRY((\tri_out~14_combout & (!\tri_out[7]~reg0_q & !\tri_out[6]~26 )) # (!\tri_out~14_combout & ((!\tri_out[6]~26 ) # (!\tri_out[7]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[7]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[6]~26 ), + .combout(\tri_out[7]~27_combout ), + .cout(\tri_out[7]~28 )); +// synopsys translate_off +defparam \tri_out[7]~27 .lut_mask = 16'h9617; +defparam \tri_out[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N25 +dffeas \tri_out[7]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[7]~27_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[7]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[7]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[7]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N26 +cycloneive_lcell_comb \tri_out[8]~29 ( +// Equation(s): +// \tri_out[8]~29_combout = \tri_out[8]~reg0_q $ (\tri_out[7]~28 $ (!\tri_out~14_combout )) + + .dataa(\tri_out[8]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\tri_out~14_combout ), + .cin(\tri_out[7]~28 ), + .combout(\tri_out[8]~29_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out[8]~29 .lut_mask = 16'h5AA5; +defparam \tri_out[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N27 +dffeas \tri_out[8]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[8]~29_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[8]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[8]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[8]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N6 +cycloneive_lcell_comb \tri_out~12 ( +// Equation(s): +// \tri_out~12_combout = (\tri_out[6]~reg0_q & (\tri_out[2]~reg0_q & (\tri_out[8]~reg0_q & \tri_out[7]~reg0_q ))) # (!\tri_out[6]~reg0_q & ((\tri_out[2]~reg0_q ) # ((\tri_out[8]~reg0_q ) # (\tri_out[7]~reg0_q )))) + + .dataa(\tri_out[6]~reg0_q ), + .datab(\tri_out[2]~reg0_q ), + .datac(\tri_out[8]~reg0_q ), + .datad(\tri_out[7]~reg0_q ), + .cin(gnd), + .combout(\tri_out~12_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~12 .lut_mask = 16'hD554; +defparam \tri_out~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N0 +cycloneive_lcell_comb \tri_out~11 ( +// Equation(s): +// \tri_out~11_combout = (\tri_out[5]~reg0_q & (((\tri_out[4]~reg0_q & \tri_out[3]~reg0_q )) # (!\tri_out[2]~reg0_q ))) # (!\tri_out[5]~reg0_q & (!\tri_out[2]~reg0_q & ((\tri_out[4]~reg0_q ) # (\tri_out[3]~reg0_q )))) + + .dataa(\tri_out[5]~reg0_q ), + .datab(\tri_out[4]~reg0_q ), + .datac(\tri_out[2]~reg0_q ), + .datad(\tri_out[3]~reg0_q ), + .cin(gnd), + .combout(\tri_out~11_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~11 .lut_mask = 16'h8F0E; +defparam \tri_out~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y19_N29 +dffeas updown( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out~14_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\updown~q ), + .prn(vcc)); +// synopsys translate_off +defparam updown.is_wysiwyg = "true"; +defparam updown.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N30 +cycloneive_lcell_comb \tri_out~13 ( +// Equation(s): +// \tri_out~13_combout = (\tri_out[1]~reg0_q & ((\updown~q ) # ((\tri_out[6]~reg0_q & \tri_out[0]~reg0_q )))) # (!\tri_out[1]~reg0_q & (\updown~q & ((\tri_out[6]~reg0_q ) # (\tri_out[0]~reg0_q )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\updown~q ), + .datac(\tri_out[6]~reg0_q ), + .datad(\tri_out[0]~reg0_q ), + .cin(gnd), + .combout(\tri_out~13_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~13 .lut_mask = 16'hECC8; +defparam \tri_out~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N28 +cycloneive_lcell_comb \tri_out~14 ( +// Equation(s): +// \tri_out~14_combout = (\tri_out~12_combout & ((\updown~q ) # ((\tri_out~11_combout & \tri_out~13_combout )))) # (!\tri_out~12_combout & (\updown~q & ((\tri_out~11_combout ) # (\tri_out~13_combout )))) + + .dataa(\tri_out~12_combout ), + .datab(\tri_out~11_combout ), + .datac(\updown~q ), + .datad(\tri_out~13_combout ), + .cin(gnd), + .combout(\tri_out~14_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~14 .lut_mask = 16'hF8E0; +defparam \tri_out~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y19_N13 +dffeas \tri_out[1]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[1]~15_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[1]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[1]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[1]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N15 +cycloneive_io_ibuf \Pword[0]~input ( + .i(Pword[0]), + .ibar(gnd), + .o(\Pword[0]~input_o )); +// synopsys translate_off +defparam \Pword[0]~input .bus_hold = "false"; +defparam \Pword[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N1 +cycloneive_io_ibuf \Fword[15]~input ( + .i(Fword[15]), + .ibar(gnd), + .o(\Fword[15]~input_o )); +// synopsys translate_off +defparam \Fword[15]~input .bus_hold = "false"; +defparam \Fword[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \Fword[14]~input ( + .i(Fword[14]), + .ibar(gnd), + .o(\Fword[14]~input_o )); +// synopsys translate_off +defparam \Fword[14]~input .bus_hold = "false"; +defparam \Fword[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y22_N1 +cycloneive_io_ibuf \Fword[13]~input ( + .i(Fword[13]), + .ibar(gnd), + .o(\Fword[13]~input_o )); +// synopsys translate_off +defparam \Fword[13]~input .bus_hold = "false"; +defparam \Fword[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N1 +cycloneive_io_ibuf \Fword[12]~input ( + .i(Fword[12]), + .ibar(gnd), + .o(\Fword[12]~input_o )); +// synopsys translate_off +defparam \Fword[12]~input .bus_hold = "false"; +defparam \Fword[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N8 +cycloneive_io_ibuf \Fword[11]~input ( + .i(Fword[11]), + .ibar(gnd), + .o(\Fword[11]~input_o )); +// synopsys translate_off +defparam \Fword[11]~input .bus_hold = "false"; +defparam \Fword[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N22 +cycloneive_io_ibuf \Fword[10]~input ( + .i(Fword[10]), + .ibar(gnd), + .o(\Fword[10]~input_o )); +// synopsys translate_off +defparam \Fword[10]~input .bus_hold = "false"; +defparam \Fword[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N8 +cycloneive_io_ibuf \Fword[9]~input ( + .i(Fword[9]), + .ibar(gnd), + .o(\Fword[9]~input_o )); +// synopsys translate_off +defparam \Fword[9]~input .bus_hold = "false"; +defparam \Fword[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N15 +cycloneive_io_ibuf \Fword[8]~input ( + .i(Fword[8]), + .ibar(gnd), + .o(\Fword[8]~input_o )); +// synopsys translate_off +defparam \Fword[8]~input .bus_hold = "false"; +defparam \Fword[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N22 +cycloneive_io_ibuf \Fword[7]~input ( + .i(Fword[7]), + .ibar(gnd), + .o(\Fword[7]~input_o )); +// synopsys translate_off +defparam \Fword[7]~input .bus_hold = "false"; +defparam \Fword[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y24_N8 +cycloneive_io_ibuf \Fword[6]~input ( + .i(Fword[6]), + .ibar(gnd), + .o(\Fword[6]~input_o )); +// synopsys translate_off +defparam \Fword[6]~input .bus_hold = "false"; +defparam \Fword[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N1 +cycloneive_io_ibuf \Fword[5]~input ( + .i(Fword[5]), + .ibar(gnd), + .o(\Fword[5]~input_o )); +// synopsys translate_off +defparam \Fword[5]~input .bus_hold = "false"; +defparam \Fword[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N22 +cycloneive_io_ibuf \Fword[4]~input ( + .i(Fword[4]), + .ibar(gnd), + .o(\Fword[4]~input_o )); +// synopsys translate_off +defparam \Fword[4]~input .bus_hold = "false"; +defparam \Fword[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N1 +cycloneive_io_ibuf \Fword[3]~input ( + .i(Fword[3]), + .ibar(gnd), + .o(\Fword[3]~input_o )); +// synopsys translate_off +defparam \Fword[3]~input .bus_hold = "false"; +defparam \Fword[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N8 +cycloneive_io_ibuf \Fword[2]~input ( + .i(Fword[2]), + .ibar(gnd), + .o(\Fword[2]~input_o )); +// synopsys translate_off +defparam \Fword[2]~input .bus_hold = "false"; +defparam \Fword[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N8 +cycloneive_io_ibuf \Fword[1]~input ( + .i(Fword[1]), + .ibar(gnd), + .o(\Fword[1]~input_o )); +// synopsys translate_off +defparam \Fword[1]~input .bus_hold = "false"; +defparam \Fword[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N15 +cycloneive_io_ibuf \Fword[0]~input ( + .i(Fword[0]), + .ibar(gnd), + .o(\Fword[0]~input_o )); +// synopsys translate_off +defparam \Fword[0]~input .bus_hold = "false"; +defparam \Fword[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N6 +cycloneive_lcell_comb \F_acc[0]~26 ( +// Equation(s): +// \F_acc[0]~26_combout = (F_acc[0] & (\Fword[0]~input_o $ (VCC))) # (!F_acc[0] & (\Fword[0]~input_o & VCC)) +// \F_acc[0]~27 = CARRY((F_acc[0] & \Fword[0]~input_o )) + + .dataa(F_acc[0]), + .datab(\Fword[0]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\F_acc[0]~26_combout ), + .cout(\F_acc[0]~27 )); +// synopsys translate_off +defparam \F_acc[0]~26 .lut_mask = 16'h6688; +defparam \F_acc[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X6_Y20_N7 +dffeas \F_acc[0] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[0]~26_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[0]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[0] .is_wysiwyg = "true"; +defparam \F_acc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N8 +cycloneive_lcell_comb \F_acc[1]~28 ( +// Equation(s): +// \F_acc[1]~28_combout = (\Fword[1]~input_o & ((F_acc[1] & (\F_acc[0]~27 & VCC)) # (!F_acc[1] & (!\F_acc[0]~27 )))) # (!\Fword[1]~input_o & ((F_acc[1] & (!\F_acc[0]~27 )) # (!F_acc[1] & ((\F_acc[0]~27 ) # (GND))))) +// \F_acc[1]~29 = CARRY((\Fword[1]~input_o & (!F_acc[1] & !\F_acc[0]~27 )) # (!\Fword[1]~input_o & ((!\F_acc[0]~27 ) # (!F_acc[1])))) + + .dataa(\Fword[1]~input_o ), + .datab(F_acc[1]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[0]~27 ), + .combout(\F_acc[1]~28_combout ), + .cout(\F_acc[1]~29 )); +// synopsys translate_off +defparam \F_acc[1]~28 .lut_mask = 16'h9617; +defparam \F_acc[1]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N9 +dffeas \F_acc[1] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[1]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[1]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[1] .is_wysiwyg = "true"; +defparam \F_acc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N10 +cycloneive_lcell_comb \F_acc[2]~30 ( +// Equation(s): +// \F_acc[2]~30_combout = ((F_acc[2] $ (\Fword[2]~input_o $ (!\F_acc[1]~29 )))) # (GND) +// \F_acc[2]~31 = CARRY((F_acc[2] & ((\Fword[2]~input_o ) # (!\F_acc[1]~29 ))) # (!F_acc[2] & (\Fword[2]~input_o & !\F_acc[1]~29 ))) + + .dataa(F_acc[2]), + .datab(\Fword[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[1]~29 ), + .combout(\F_acc[2]~30_combout ), + .cout(\F_acc[2]~31 )); +// synopsys translate_off +defparam \F_acc[2]~30 .lut_mask = 16'h698E; +defparam \F_acc[2]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N11 +dffeas \F_acc[2] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[2]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[2]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[2] .is_wysiwyg = "true"; +defparam \F_acc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N12 +cycloneive_lcell_comb \F_acc[3]~32 ( +// Equation(s): +// \F_acc[3]~32_combout = (F_acc[3] & ((\Fword[3]~input_o & (\F_acc[2]~31 & VCC)) # (!\Fword[3]~input_o & (!\F_acc[2]~31 )))) # (!F_acc[3] & ((\Fword[3]~input_o & (!\F_acc[2]~31 )) # (!\Fword[3]~input_o & ((\F_acc[2]~31 ) # (GND))))) +// \F_acc[3]~33 = CARRY((F_acc[3] & (!\Fword[3]~input_o & !\F_acc[2]~31 )) # (!F_acc[3] & ((!\F_acc[2]~31 ) # (!\Fword[3]~input_o )))) + + .dataa(F_acc[3]), + .datab(\Fword[3]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[2]~31 ), + .combout(\F_acc[3]~32_combout ), + .cout(\F_acc[3]~33 )); +// synopsys translate_off +defparam \F_acc[3]~32 .lut_mask = 16'h9617; +defparam \F_acc[3]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N13 +dffeas \F_acc[3] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[3]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[3]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[3] .is_wysiwyg = "true"; +defparam \F_acc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N14 +cycloneive_lcell_comb \F_acc[4]~34 ( +// Equation(s): +// \F_acc[4]~34_combout = ((\Fword[4]~input_o $ (F_acc[4] $ (!\F_acc[3]~33 )))) # (GND) +// \F_acc[4]~35 = CARRY((\Fword[4]~input_o & ((F_acc[4]) # (!\F_acc[3]~33 ))) # (!\Fword[4]~input_o & (F_acc[4] & !\F_acc[3]~33 ))) + + .dataa(\Fword[4]~input_o ), + .datab(F_acc[4]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[3]~33 ), + .combout(\F_acc[4]~34_combout ), + .cout(\F_acc[4]~35 )); +// synopsys translate_off +defparam \F_acc[4]~34 .lut_mask = 16'h698E; +defparam \F_acc[4]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N15 +dffeas \F_acc[4] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[4]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[4]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[4] .is_wysiwyg = "true"; +defparam \F_acc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N16 +cycloneive_lcell_comb \F_acc[5]~36 ( +// Equation(s): +// \F_acc[5]~36_combout = (\Fword[5]~input_o & ((F_acc[5] & (\F_acc[4]~35 & VCC)) # (!F_acc[5] & (!\F_acc[4]~35 )))) # (!\Fword[5]~input_o & ((F_acc[5] & (!\F_acc[4]~35 )) # (!F_acc[5] & ((\F_acc[4]~35 ) # (GND))))) +// \F_acc[5]~37 = CARRY((\Fword[5]~input_o & (!F_acc[5] & !\F_acc[4]~35 )) # (!\Fword[5]~input_o & ((!\F_acc[4]~35 ) # (!F_acc[5])))) + + .dataa(\Fword[5]~input_o ), + .datab(F_acc[5]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[4]~35 ), + .combout(\F_acc[5]~36_combout ), + .cout(\F_acc[5]~37 )); +// synopsys translate_off +defparam \F_acc[5]~36 .lut_mask = 16'h9617; +defparam \F_acc[5]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N17 +dffeas \F_acc[5] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[5]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[5]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[5] .is_wysiwyg = "true"; +defparam \F_acc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N18 +cycloneive_lcell_comb \F_acc[6]~38 ( +// Equation(s): +// \F_acc[6]~38_combout = ((\Fword[6]~input_o $ (F_acc[6] $ (!\F_acc[5]~37 )))) # (GND) +// \F_acc[6]~39 = CARRY((\Fword[6]~input_o & ((F_acc[6]) # (!\F_acc[5]~37 ))) # (!\Fword[6]~input_o & (F_acc[6] & !\F_acc[5]~37 ))) + + .dataa(\Fword[6]~input_o ), + .datab(F_acc[6]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[5]~37 ), + .combout(\F_acc[6]~38_combout ), + .cout(\F_acc[6]~39 )); +// synopsys translate_off +defparam \F_acc[6]~38 .lut_mask = 16'h698E; +defparam \F_acc[6]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N19 +dffeas \F_acc[6] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[6]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[6]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[6] .is_wysiwyg = "true"; +defparam \F_acc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N20 +cycloneive_lcell_comb \F_acc[7]~40 ( +// Equation(s): +// \F_acc[7]~40_combout = (\Fword[7]~input_o & ((F_acc[7] & (\F_acc[6]~39 & VCC)) # (!F_acc[7] & (!\F_acc[6]~39 )))) # (!\Fword[7]~input_o & ((F_acc[7] & (!\F_acc[6]~39 )) # (!F_acc[7] & ((\F_acc[6]~39 ) # (GND))))) +// \F_acc[7]~41 = CARRY((\Fword[7]~input_o & (!F_acc[7] & !\F_acc[6]~39 )) # (!\Fword[7]~input_o & ((!\F_acc[6]~39 ) # (!F_acc[7])))) + + .dataa(\Fword[7]~input_o ), + .datab(F_acc[7]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[6]~39 ), + .combout(\F_acc[7]~40_combout ), + .cout(\F_acc[7]~41 )); +// synopsys translate_off +defparam \F_acc[7]~40 .lut_mask = 16'h9617; +defparam \F_acc[7]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N21 +dffeas \F_acc[7] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[7]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[7]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[7] .is_wysiwyg = "true"; +defparam \F_acc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N22 +cycloneive_lcell_comb \F_acc[8]~42 ( +// Equation(s): +// \F_acc[8]~42_combout = ((F_acc[8] $ (\Fword[8]~input_o $ (!\F_acc[7]~41 )))) # (GND) +// \F_acc[8]~43 = CARRY((F_acc[8] & ((\Fword[8]~input_o ) # (!\F_acc[7]~41 ))) # (!F_acc[8] & (\Fword[8]~input_o & !\F_acc[7]~41 ))) + + .dataa(F_acc[8]), + .datab(\Fword[8]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[7]~41 ), + .combout(\F_acc[8]~42_combout ), + .cout(\F_acc[8]~43 )); +// synopsys translate_off +defparam \F_acc[8]~42 .lut_mask = 16'h698E; +defparam \F_acc[8]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N23 +dffeas \F_acc[8] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[8]~42_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[8]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[8] .is_wysiwyg = "true"; +defparam \F_acc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N24 +cycloneive_lcell_comb \F_acc[9]~44 ( +// Equation(s): +// \F_acc[9]~44_combout = (\Fword[9]~input_o & ((F_acc[9] & (\F_acc[8]~43 & VCC)) # (!F_acc[9] & (!\F_acc[8]~43 )))) # (!\Fword[9]~input_o & ((F_acc[9] & (!\F_acc[8]~43 )) # (!F_acc[9] & ((\F_acc[8]~43 ) # (GND))))) +// \F_acc[9]~45 = CARRY((\Fword[9]~input_o & (!F_acc[9] & !\F_acc[8]~43 )) # (!\Fword[9]~input_o & ((!\F_acc[8]~43 ) # (!F_acc[9])))) + + .dataa(\Fword[9]~input_o ), + .datab(F_acc[9]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[8]~43 ), + .combout(\F_acc[9]~44_combout ), + .cout(\F_acc[9]~45 )); +// synopsys translate_off +defparam \F_acc[9]~44 .lut_mask = 16'h9617; +defparam \F_acc[9]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N25 +dffeas \F_acc[9] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[9]~44_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[9]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[9] .is_wysiwyg = "true"; +defparam \F_acc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N26 +cycloneive_lcell_comb \F_acc[10]~46 ( +// Equation(s): +// \F_acc[10]~46_combout = ((F_acc[10] $ (\Fword[10]~input_o $ (!\F_acc[9]~45 )))) # (GND) +// \F_acc[10]~47 = CARRY((F_acc[10] & ((\Fword[10]~input_o ) # (!\F_acc[9]~45 ))) # (!F_acc[10] & (\Fword[10]~input_o & !\F_acc[9]~45 ))) + + .dataa(F_acc[10]), + .datab(\Fword[10]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[9]~45 ), + .combout(\F_acc[10]~46_combout ), + .cout(\F_acc[10]~47 )); +// synopsys translate_off +defparam \F_acc[10]~46 .lut_mask = 16'h698E; +defparam \F_acc[10]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N27 +dffeas \F_acc[10] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[10]~46_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[10]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[10] .is_wysiwyg = "true"; +defparam \F_acc[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N28 +cycloneive_lcell_comb \F_acc[11]~48 ( +// Equation(s): +// \F_acc[11]~48_combout = (\Fword[11]~input_o & ((F_acc[11] & (\F_acc[10]~47 & VCC)) # (!F_acc[11] & (!\F_acc[10]~47 )))) # (!\Fword[11]~input_o & ((F_acc[11] & (!\F_acc[10]~47 )) # (!F_acc[11] & ((\F_acc[10]~47 ) # (GND))))) +// \F_acc[11]~49 = CARRY((\Fword[11]~input_o & (!F_acc[11] & !\F_acc[10]~47 )) # (!\Fword[11]~input_o & ((!\F_acc[10]~47 ) # (!F_acc[11])))) + + .dataa(\Fword[11]~input_o ), + .datab(F_acc[11]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[10]~47 ), + .combout(\F_acc[11]~48_combout ), + .cout(\F_acc[11]~49 )); +// synopsys translate_off +defparam \F_acc[11]~48 .lut_mask = 16'h9617; +defparam \F_acc[11]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N29 +dffeas \F_acc[11] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[11]~48_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[11]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[11] .is_wysiwyg = "true"; +defparam \F_acc[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N30 +cycloneive_lcell_comb \F_acc[12]~50 ( +// Equation(s): +// \F_acc[12]~50_combout = ((F_acc[12] $ (\Fword[12]~input_o $ (!\F_acc[11]~49 )))) # (GND) +// \F_acc[12]~51 = CARRY((F_acc[12] & ((\Fword[12]~input_o ) # (!\F_acc[11]~49 ))) # (!F_acc[12] & (\Fword[12]~input_o & !\F_acc[11]~49 ))) + + .dataa(F_acc[12]), + .datab(\Fword[12]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[11]~49 ), + .combout(\F_acc[12]~50_combout ), + .cout(\F_acc[12]~51 )); +// synopsys translate_off +defparam \F_acc[12]~50 .lut_mask = 16'h698E; +defparam \F_acc[12]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N31 +dffeas \F_acc[12] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[12]~50_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[12]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[12] .is_wysiwyg = "true"; +defparam \F_acc[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N0 +cycloneive_lcell_comb \F_acc[13]~52 ( +// Equation(s): +// \F_acc[13]~52_combout = (\Fword[13]~input_o & ((F_acc[13] & (\F_acc[12]~51 & VCC)) # (!F_acc[13] & (!\F_acc[12]~51 )))) # (!\Fword[13]~input_o & ((F_acc[13] & (!\F_acc[12]~51 )) # (!F_acc[13] & ((\F_acc[12]~51 ) # (GND))))) +// \F_acc[13]~53 = CARRY((\Fword[13]~input_o & (!F_acc[13] & !\F_acc[12]~51 )) # (!\Fword[13]~input_o & ((!\F_acc[12]~51 ) # (!F_acc[13])))) + + .dataa(\Fword[13]~input_o ), + .datab(F_acc[13]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[12]~51 ), + .combout(\F_acc[13]~52_combout ), + .cout(\F_acc[13]~53 )); +// synopsys translate_off +defparam \F_acc[13]~52 .lut_mask = 16'h9617; +defparam \F_acc[13]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N1 +dffeas \F_acc[13] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[13]~52_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[13]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[13] .is_wysiwyg = "true"; +defparam \F_acc[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N2 +cycloneive_lcell_comb \F_acc[14]~54 ( +// Equation(s): +// \F_acc[14]~54_combout = ((\Fword[14]~input_o $ (F_acc[14] $ (!\F_acc[13]~53 )))) # (GND) +// \F_acc[14]~55 = CARRY((\Fword[14]~input_o & ((F_acc[14]) # (!\F_acc[13]~53 ))) # (!\Fword[14]~input_o & (F_acc[14] & !\F_acc[13]~53 ))) + + .dataa(\Fword[14]~input_o ), + .datab(F_acc[14]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[13]~53 ), + .combout(\F_acc[14]~54_combout ), + .cout(\F_acc[14]~55 )); +// synopsys translate_off +defparam \F_acc[14]~54 .lut_mask = 16'h698E; +defparam \F_acc[14]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N3 +dffeas \F_acc[14] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[14]~54_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[14]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[14] .is_wysiwyg = "true"; +defparam \F_acc[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N4 +cycloneive_lcell_comb \F_acc[15]~56 ( +// Equation(s): +// \F_acc[15]~56_combout = (\Fword[15]~input_o & ((F_acc[15] & (\F_acc[14]~55 & VCC)) # (!F_acc[15] & (!\F_acc[14]~55 )))) # (!\Fword[15]~input_o & ((F_acc[15] & (!\F_acc[14]~55 )) # (!F_acc[15] & ((\F_acc[14]~55 ) # (GND))))) +// \F_acc[15]~57 = CARRY((\Fword[15]~input_o & (!F_acc[15] & !\F_acc[14]~55 )) # (!\Fword[15]~input_o & ((!\F_acc[14]~55 ) # (!F_acc[15])))) + + .dataa(\Fword[15]~input_o ), + .datab(F_acc[15]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[14]~55 ), + .combout(\F_acc[15]~56_combout ), + .cout(\F_acc[15]~57 )); +// synopsys translate_off +defparam \F_acc[15]~56 .lut_mask = 16'h9617; +defparam \F_acc[15]~56 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N5 +dffeas \F_acc[15] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[15]~56_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[15]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[15] .is_wysiwyg = "true"; +defparam \F_acc[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N6 +cycloneive_lcell_comb \F_acc[16]~58 ( +// Equation(s): +// \F_acc[16]~58_combout = (F_acc[16] & (\F_acc[15]~57 $ (GND))) # (!F_acc[16] & (!\F_acc[15]~57 & VCC)) +// \F_acc[16]~59 = CARRY((F_acc[16] & !\F_acc[15]~57 )) + + .dataa(F_acc[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[15]~57 ), + .combout(\F_acc[16]~58_combout ), + .cout(\F_acc[16]~59 )); +// synopsys translate_off +defparam \F_acc[16]~58 .lut_mask = 16'hA50A; +defparam \F_acc[16]~58 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N7 +dffeas \F_acc[16] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[16]~58_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[16]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[16] .is_wysiwyg = "true"; +defparam \F_acc[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N10 +cycloneive_lcell_comb \rom_address[0]~0 ( +// Equation(s): +// \rom_address[0]~0_combout = (\Pword[0]~input_o & (F_acc[16] $ (VCC))) # (!\Pword[0]~input_o & (F_acc[16] & VCC)) +// \rom_address[0]~1 = CARRY((\Pword[0]~input_o & F_acc[16])) + + .dataa(\Pword[0]~input_o ), + .datab(F_acc[16]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\rom_address[0]~0_combout ), + .cout(\rom_address[0]~1 )); +// synopsys translate_off +defparam \rom_address[0]~0 .lut_mask = 16'h6688; +defparam \rom_address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N8 +cycloneive_lcell_comb \F_acc[17]~60 ( +// Equation(s): +// \F_acc[17]~60_combout = (F_acc[17] & (!\F_acc[16]~59 )) # (!F_acc[17] & ((\F_acc[16]~59 ) # (GND))) +// \F_acc[17]~61 = CARRY((!\F_acc[16]~59 ) # (!F_acc[17])) + + .dataa(gnd), + .datab(F_acc[17]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[16]~59 ), + .combout(\F_acc[17]~60_combout ), + .cout(\F_acc[17]~61 )); +// synopsys translate_off +defparam \F_acc[17]~60 .lut_mask = 16'h3C3F; +defparam \F_acc[17]~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N9 +dffeas \F_acc[17] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[17]~60_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[17]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[17] .is_wysiwyg = "true"; +defparam \F_acc[17] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N22 +cycloneive_io_ibuf \Pword[1]~input ( + .i(Pword[1]), + .ibar(gnd), + .o(\Pword[1]~input_o )); +// synopsys translate_off +defparam \Pword[1]~input .bus_hold = "false"; +defparam \Pword[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N12 +cycloneive_lcell_comb \rom_address[1]~2 ( +// Equation(s): +// \rom_address[1]~2_combout = (F_acc[17] & ((\Pword[1]~input_o & (\rom_address[0]~1 & VCC)) # (!\Pword[1]~input_o & (!\rom_address[0]~1 )))) # (!F_acc[17] & ((\Pword[1]~input_o & (!\rom_address[0]~1 )) # (!\Pword[1]~input_o & ((\rom_address[0]~1 ) # +// (GND))))) +// \rom_address[1]~3 = CARRY((F_acc[17] & (!\Pword[1]~input_o & !\rom_address[0]~1 )) # (!F_acc[17] & ((!\rom_address[0]~1 ) # (!\Pword[1]~input_o )))) + + .dataa(F_acc[17]), + .datab(\Pword[1]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[0]~1 ), + .combout(\rom_address[1]~2_combout ), + .cout(\rom_address[1]~3 )); +// synopsys translate_off +defparam \rom_address[1]~2 .lut_mask = 16'h9617; +defparam \rom_address[1]~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N10 +cycloneive_lcell_comb \F_acc[18]~62 ( +// Equation(s): +// \F_acc[18]~62_combout = (F_acc[18] & (\F_acc[17]~61 $ (GND))) # (!F_acc[18] & (!\F_acc[17]~61 & VCC)) +// \F_acc[18]~63 = CARRY((F_acc[18] & !\F_acc[17]~61 )) + + .dataa(F_acc[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[17]~61 ), + .combout(\F_acc[18]~62_combout ), + .cout(\F_acc[18]~63 )); +// synopsys translate_off +defparam \F_acc[18]~62 .lut_mask = 16'hA50A; +defparam \F_acc[18]~62 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N11 +dffeas \F_acc[18] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[18]~62_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[18]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[18] .is_wysiwyg = "true"; +defparam \F_acc[18] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N1 +cycloneive_io_ibuf \Pword[2]~input ( + .i(Pword[2]), + .ibar(gnd), + .o(\Pword[2]~input_o )); +// synopsys translate_off +defparam \Pword[2]~input .bus_hold = "false"; +defparam \Pword[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N14 +cycloneive_lcell_comb \rom_address[2]~4 ( +// Equation(s): +// \rom_address[2]~4_combout = ((F_acc[18] $ (\Pword[2]~input_o $ (!\rom_address[1]~3 )))) # (GND) +// \rom_address[2]~5 = CARRY((F_acc[18] & ((\Pword[2]~input_o ) # (!\rom_address[1]~3 ))) # (!F_acc[18] & (\Pword[2]~input_o & !\rom_address[1]~3 ))) + + .dataa(F_acc[18]), + .datab(\Pword[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[1]~3 ), + .combout(\rom_address[2]~4_combout ), + .cout(\rom_address[2]~5 )); +// synopsys translate_off +defparam \rom_address[2]~4 .lut_mask = 16'h698E; +defparam \rom_address[2]~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N12 +cycloneive_lcell_comb \F_acc[19]~64 ( +// Equation(s): +// \F_acc[19]~64_combout = (F_acc[19] & (!\F_acc[18]~63 )) # (!F_acc[19] & ((\F_acc[18]~63 ) # (GND))) +// \F_acc[19]~65 = CARRY((!\F_acc[18]~63 ) # (!F_acc[19])) + + .dataa(F_acc[19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[18]~63 ), + .combout(\F_acc[19]~64_combout ), + .cout(\F_acc[19]~65 )); +// synopsys translate_off +defparam \F_acc[19]~64 .lut_mask = 16'h5A5F; +defparam \F_acc[19]~64 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N13 +dffeas \F_acc[19] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[19]~64_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[19]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[19] .is_wysiwyg = "true"; +defparam \F_acc[19] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N8 +cycloneive_io_ibuf \Pword[3]~input ( + .i(Pword[3]), + .ibar(gnd), + .o(\Pword[3]~input_o )); +// synopsys translate_off +defparam \Pword[3]~input .bus_hold = "false"; +defparam \Pword[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N16 +cycloneive_lcell_comb \rom_address[3]~6 ( +// Equation(s): +// \rom_address[3]~6_combout = (F_acc[19] & ((\Pword[3]~input_o & (\rom_address[2]~5 & VCC)) # (!\Pword[3]~input_o & (!\rom_address[2]~5 )))) # (!F_acc[19] & ((\Pword[3]~input_o & (!\rom_address[2]~5 )) # (!\Pword[3]~input_o & ((\rom_address[2]~5 ) # +// (GND))))) +// \rom_address[3]~7 = CARRY((F_acc[19] & (!\Pword[3]~input_o & !\rom_address[2]~5 )) # (!F_acc[19] & ((!\rom_address[2]~5 ) # (!\Pword[3]~input_o )))) + + .dataa(F_acc[19]), + .datab(\Pword[3]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[2]~5 ), + .combout(\rom_address[3]~6_combout ), + .cout(\rom_address[3]~7 )); +// synopsys translate_off +defparam \rom_address[3]~6 .lut_mask = 16'h9617; +defparam \rom_address[3]~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N14 +cycloneive_lcell_comb \F_acc[20]~66 ( +// Equation(s): +// \F_acc[20]~66_combout = (F_acc[20] & (\F_acc[19]~65 $ (GND))) # (!F_acc[20] & (!\F_acc[19]~65 & VCC)) +// \F_acc[20]~67 = CARRY((F_acc[20] & !\F_acc[19]~65 )) + + .dataa(gnd), + .datab(F_acc[20]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[19]~65 ), + .combout(\F_acc[20]~66_combout ), + .cout(\F_acc[20]~67 )); +// synopsys translate_off +defparam \F_acc[20]~66 .lut_mask = 16'hC30C; +defparam \F_acc[20]~66 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N15 +dffeas \F_acc[20] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[20]~66_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[20]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[20] .is_wysiwyg = "true"; +defparam \F_acc[20] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N22 +cycloneive_io_ibuf \Pword[4]~input ( + .i(Pword[4]), + .ibar(gnd), + .o(\Pword[4]~input_o )); +// synopsys translate_off +defparam \Pword[4]~input .bus_hold = "false"; +defparam \Pword[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N18 +cycloneive_lcell_comb \rom_address[4]~8 ( +// Equation(s): +// \rom_address[4]~8_combout = ((F_acc[20] $ (\Pword[4]~input_o $ (!\rom_address[3]~7 )))) # (GND) +// \rom_address[4]~9 = CARRY((F_acc[20] & ((\Pword[4]~input_o ) # (!\rom_address[3]~7 ))) # (!F_acc[20] & (\Pword[4]~input_o & !\rom_address[3]~7 ))) + + .dataa(F_acc[20]), + .datab(\Pword[4]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[3]~7 ), + .combout(\rom_address[4]~8_combout ), + .cout(\rom_address[4]~9 )); +// synopsys translate_off +defparam \rom_address[4]~8 .lut_mask = 16'h698E; +defparam \rom_address[4]~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N16 +cycloneive_lcell_comb \F_acc[21]~68 ( +// Equation(s): +// \F_acc[21]~68_combout = (F_acc[21] & (!\F_acc[20]~67 )) # (!F_acc[21] & ((\F_acc[20]~67 ) # (GND))) +// \F_acc[21]~69 = CARRY((!\F_acc[20]~67 ) # (!F_acc[21])) + + .dataa(gnd), + .datab(F_acc[21]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[20]~67 ), + .combout(\F_acc[21]~68_combout ), + .cout(\F_acc[21]~69 )); +// synopsys translate_off +defparam \F_acc[21]~68 .lut_mask = 16'h3C3F; +defparam \F_acc[21]~68 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N17 +dffeas \F_acc[21] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[21]~68_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[21]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[21] .is_wysiwyg = "true"; +defparam \F_acc[21] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N15 +cycloneive_io_ibuf \Pword[5]~input ( + .i(Pword[5]), + .ibar(gnd), + .o(\Pword[5]~input_o )); +// synopsys translate_off +defparam \Pword[5]~input .bus_hold = "false"; +defparam \Pword[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N20 +cycloneive_lcell_comb \rom_address[5]~10 ( +// Equation(s): +// \rom_address[5]~10_combout = (F_acc[21] & ((\Pword[5]~input_o & (\rom_address[4]~9 & VCC)) # (!\Pword[5]~input_o & (!\rom_address[4]~9 )))) # (!F_acc[21] & ((\Pword[5]~input_o & (!\rom_address[4]~9 )) # (!\Pword[5]~input_o & ((\rom_address[4]~9 ) # +// (GND))))) +// \rom_address[5]~11 = CARRY((F_acc[21] & (!\Pword[5]~input_o & !\rom_address[4]~9 )) # (!F_acc[21] & ((!\rom_address[4]~9 ) # (!\Pword[5]~input_o )))) + + .dataa(F_acc[21]), + .datab(\Pword[5]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[4]~9 ), + .combout(\rom_address[5]~10_combout ), + .cout(\rom_address[5]~11 )); +// synopsys translate_off +defparam \rom_address[5]~10 .lut_mask = 16'h9617; +defparam \rom_address[5]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N22 +cycloneive_io_ibuf \Pword[6]~input ( + .i(Pword[6]), + .ibar(gnd), + .o(\Pword[6]~input_o )); +// synopsys translate_off +defparam \Pword[6]~input .bus_hold = "false"; +defparam \Pword[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N18 +cycloneive_lcell_comb \F_acc[22]~70 ( +// Equation(s): +// \F_acc[22]~70_combout = (F_acc[22] & (\F_acc[21]~69 $ (GND))) # (!F_acc[22] & (!\F_acc[21]~69 & VCC)) +// \F_acc[22]~71 = CARRY((F_acc[22] & !\F_acc[21]~69 )) + + .dataa(gnd), + .datab(F_acc[22]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[21]~69 ), + .combout(\F_acc[22]~70_combout ), + .cout(\F_acc[22]~71 )); +// synopsys translate_off +defparam \F_acc[22]~70 .lut_mask = 16'hC30C; +defparam \F_acc[22]~70 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N19 +dffeas \F_acc[22] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[22]~70_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[22]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[22] .is_wysiwyg = "true"; +defparam \F_acc[22] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N22 +cycloneive_lcell_comb \rom_address[6]~12 ( +// Equation(s): +// \rom_address[6]~12_combout = ((\Pword[6]~input_o $ (F_acc[22] $ (!\rom_address[5]~11 )))) # (GND) +// \rom_address[6]~13 = CARRY((\Pword[6]~input_o & ((F_acc[22]) # (!\rom_address[5]~11 ))) # (!\Pword[6]~input_o & (F_acc[22] & !\rom_address[5]~11 ))) + + .dataa(\Pword[6]~input_o ), + .datab(F_acc[22]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[5]~11 ), + .combout(\rom_address[6]~12_combout ), + .cout(\rom_address[6]~13 )); +// synopsys translate_off +defparam \rom_address[6]~12 .lut_mask = 16'h698E; +defparam \rom_address[6]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y22_N15 +cycloneive_io_ibuf \Pword[7]~input ( + .i(Pword[7]), + .ibar(gnd), + .o(\Pword[7]~input_o )); +// synopsys translate_off +defparam \Pword[7]~input .bus_hold = "false"; +defparam \Pword[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N20 +cycloneive_lcell_comb \F_acc[23]~72 ( +// Equation(s): +// \F_acc[23]~72_combout = (F_acc[23] & (!\F_acc[22]~71 )) # (!F_acc[23] & ((\F_acc[22]~71 ) # (GND))) +// \F_acc[23]~73 = CARRY((!\F_acc[22]~71 ) # (!F_acc[23])) + + .dataa(gnd), + .datab(F_acc[23]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[22]~71 ), + .combout(\F_acc[23]~72_combout ), + .cout(\F_acc[23]~73 )); +// synopsys translate_off +defparam \F_acc[23]~72 .lut_mask = 16'h3C3F; +defparam \F_acc[23]~72 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N21 +dffeas \F_acc[23] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[23]~72_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[23]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[23] .is_wysiwyg = "true"; +defparam \F_acc[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N24 +cycloneive_lcell_comb \rom_address[7]~14 ( +// Equation(s): +// \rom_address[7]~14_combout = (\Pword[7]~input_o & ((F_acc[23] & (\rom_address[6]~13 & VCC)) # (!F_acc[23] & (!\rom_address[6]~13 )))) # (!\Pword[7]~input_o & ((F_acc[23] & (!\rom_address[6]~13 )) # (!F_acc[23] & ((\rom_address[6]~13 ) # (GND))))) +// \rom_address[7]~15 = CARRY((\Pword[7]~input_o & (!F_acc[23] & !\rom_address[6]~13 )) # (!\Pword[7]~input_o & ((!\rom_address[6]~13 ) # (!F_acc[23])))) + + .dataa(\Pword[7]~input_o ), + .datab(F_acc[23]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[6]~13 ), + .combout(\rom_address[7]~14_combout ), + .cout(\rom_address[7]~15 )); +// synopsys translate_off +defparam \rom_address[7]~14 .lut_mask = 16'h9617; +defparam \rom_address[7]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N15 +cycloneive_io_ibuf \Pword[8]~input ( + .i(Pword[8]), + .ibar(gnd), + .o(\Pword[8]~input_o )); +// synopsys translate_off +defparam \Pword[8]~input .bus_hold = "false"; +defparam \Pword[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N22 +cycloneive_lcell_comb \F_acc[24]~74 ( +// Equation(s): +// \F_acc[24]~74_combout = (F_acc[24] & (\F_acc[23]~73 $ (GND))) # (!F_acc[24] & (!\F_acc[23]~73 & VCC)) +// \F_acc[24]~75 = CARRY((F_acc[24] & !\F_acc[23]~73 )) + + .dataa(F_acc[24]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[23]~73 ), + .combout(\F_acc[24]~74_combout ), + .cout(\F_acc[24]~75 )); +// synopsys translate_off +defparam \F_acc[24]~74 .lut_mask = 16'hA50A; +defparam \F_acc[24]~74 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N23 +dffeas \F_acc[24] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[24]~74_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[24]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[24] .is_wysiwyg = "true"; +defparam \F_acc[24] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N26 +cycloneive_lcell_comb \rom_address[8]~16 ( +// Equation(s): +// \rom_address[8]~16_combout = ((\Pword[8]~input_o $ (F_acc[24] $ (!\rom_address[7]~15 )))) # (GND) +// \rom_address[8]~17 = CARRY((\Pword[8]~input_o & ((F_acc[24]) # (!\rom_address[7]~15 ))) # (!\Pword[8]~input_o & (F_acc[24] & !\rom_address[7]~15 ))) + + .dataa(\Pword[8]~input_o ), + .datab(F_acc[24]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[7]~15 ), + .combout(\rom_address[8]~16_combout ), + .cout(\rom_address[8]~17 )); +// synopsys translate_off +defparam \rom_address[8]~16 .lut_mask = 16'h698E; +defparam \rom_address[8]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N8 +cycloneive_io_ibuf \Pword[9]~input ( + .i(Pword[9]), + .ibar(gnd), + .o(\Pword[9]~input_o )); +// synopsys translate_off +defparam \Pword[9]~input .bus_hold = "false"; +defparam \Pword[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N24 +cycloneive_lcell_comb \F_acc[25]~76 ( +// Equation(s): +// \F_acc[25]~76_combout = \F_acc[24]~75 $ (F_acc[25]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(F_acc[25]), + .cin(\F_acc[24]~75 ), + .combout(\F_acc[25]~76_combout ), + .cout()); +// synopsys translate_off +defparam \F_acc[25]~76 .lut_mask = 16'h0FF0; +defparam \F_acc[25]~76 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N25 +dffeas \F_acc[25] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[25]~76_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[25]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[25] .is_wysiwyg = "true"; +defparam \F_acc[25] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N28 +cycloneive_lcell_comb \rom_address[9]~18 ( +// Equation(s): +// \rom_address[9]~18_combout = \Pword[9]~input_o $ (\rom_address[8]~17 $ (F_acc[25])) + + .dataa(gnd), + .datab(\Pword[9]~input_o ), + .datac(gnd), + .datad(F_acc[25]), + .cin(\rom_address[8]~17 ), + .combout(\rom_address[9]~18_combout ), + .cout()); +// synopsys translate_off +defparam \rom_address[9]~18 .lut_mask = 16'hC33C; +defparam \rom_address[9]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: M9K_X15_Y12_N0 +cycloneive_ram_block \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\clk_200m~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(vcc), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(9'b000000000), + .portaaddr({\rom_address[9]~18_combout ,\rom_address[8]~16_combout ,\rom_address[7]~14_combout ,\rom_address[6]~12_combout ,\rom_address[5]~10_combout ,\rom_address[4]~8_combout ,\rom_address[3]~6_combout ,\rom_address[2]~4_combout ,\rom_address[1]~2_combout , +\rom_address[0]~0_combout }), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr(10'b0000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .init_file = "sin9bit_1024.mif"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ALTSYNCRAM"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 10; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 1023; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 1024; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 10; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init4 = 1024'h7F3F1F6F97C3D9EAF3793C1DEED763A9D2E773395C6E27037DBADC6D365AED66AB4DA4D067B3598CA64B218CC561B0980BF5F2F176B95C2DD6AB4592C560AE56AAD54A953A994AA3512813E9E4E26D34984BA592893492411E8E46A2D148943A190A8441205007F3E9F0F67A3C1DCEC753A1C8E270379B8DA6B351A4D0673319; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h0C66230980BE5E2E970B65A2C15CAC552A14CA4512813C9C4D2612C94492411C8C45229108642209007E3E1E8F0783B1D0E470371B8D86A34198CC6431180C05E2E168B4582B158A852291409C4E2612894482411888442110880401F0F8783C1D0E870381B0D86834190C86030180B85C2E160B0542A150A85028140984C26130904824120884422110884020100804020100803C1E0F0783C1E0F0783C1E0F0783C1E0F0783C1E0F0783C20100804020100804022110884422120904824130984C26140A0502A150A8542C160B85C2E180C06032190D068361B0E0703A1D0F0783E1F100804221110884624120944A261389C5029148A8562B160B45A2E178; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'hC06031190CC66341A8D86E371C0E4743B1E0F07A3E1F9008242219108A452311C90492512C984D2713CA0512914CA8552B15CB05A2D970BA5E2F980C26231990CC67341A4D46B369B8DE70389C8E8753B1DCF07A3D9F0FA7F40205048442A190E894522D1A8E47A4124934A2592E984D26D389E4FA8144A352A994EA9552AD5AAE582C564B45AADD70B95DAF17CBF6030986C56332192CA663359ED06934DAAD66BB65B4DC6EB7DC0E271B95CCE774BA9D8ED77BC1E4F37ABD9F0F97DBF1FCFF8040A070583422130B8643A1F11894522B178C466371C8F47E4322924964F2894CAE592E97CC665349ACDA71399DCF27D3FA050A8745A351E934AA65369D50A8; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'hD4EA955ABD62B35BAE57ABF60B158EC966B3DA2D56BB65BADF70B8DCEE975BBDE2F37ABE5F6FD7FC0E0B0784C361F1189C56331B8EC7E432393CA6572D97CC66B379CCEE7B3FA0D0E8B47A4D369F51A9D56AF59ADD76BF61B1D96CF69B5DB6DF71B9DCEEB77BCDEEFB7FC0E0F0B85C3E27178DC7E3F2393CAE5F2F99CDE773B9FD0E8F47A5D3E9F53ABD5EB75FAFD8ECF67B5DAEDF73B9DDEEF7BBDDFEFF83C1E1F0F8BC5E3F1F93C9E5F2F9BCDE6F3F9FCFE8F47A7D3E9F4FABD5EAF5FAFD7EBF67B3D9ECF6FB7DBEDF6FBBDDEEF77BBDDEEF77BFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDDEEF77BBDDEEF77BBDBEDF6FB7DBECF67B3D9EBF; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h5FAFD7EAF57ABD3E9F4FA7D1E8F3F9FCFE6F379BCBE5F2793C7E3F178BC3E1F0783BFDFEF77BBBDDEE773B7DAED767B3D8EBF5FADD5EAF53A7D3E9747A3D0E7F3B9DCDE672F97CAE4F238FC7E371789C3E170B83C0DFEFB7BBCDDEEB73B9DC6DF6DB5DA6CF65B1D86BF5DADD66AF55A9D469F4DA4D1E8B43A0CFE7B3B9CCDE6B3197CB6572993C8E431F8EC6E331589C461F0D84C1E0B037FBF5F6F97ABCDE2EF75BA5CEE370B7DBAD96BB55A2CF66B258EC560AFD7AB95BACD62AF55AA54EA350A7536994AA4D1E8D45A1D0A813F9F4F277399C4DA6B34994C65F2E964AE532893C96492290C7E3D1C8DC6631178AC52251187C3A190B84C220D0581C0A00FF; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N20 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][11]~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][11]~0_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [7] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [4]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [6]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [5])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][11]~0 .lut_mask = 16'hCCC8; +defparam \modulation|Mult0|mult_core|romout[1][11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][10] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][10]~combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [6] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [4] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [7])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [6] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [7]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][10]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][10] .lut_mask = 16'hC1C8; +defparam \modulation|Mult0|mult_core|romout[1][10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][9] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][9]~combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [4] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (\spwm_sin|altsyncram_component|auto_generated|q_a [6] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [5])) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [6]) # (\spwm_sin|altsyncram_component|auto_generated|q_a [7])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][9]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][9] .lut_mask = 16'h0AD4; +defparam \modulation|Mult0|mult_core|romout[1][9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][8]~1 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][8]~1_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (\spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (((!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [6]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [6])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][8]~1 .lut_mask = 16'hA856; +defparam \modulation|Mult0|mult_core|romout[1][8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N30 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][11]~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][11]~2_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][11]~2_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][11]~2 .lut_mask = 16'hCCC8; +defparam \modulation|Mult0|mult_core|romout[0][11]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N4 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][7] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][7]~combout = \spwm_sin|altsyncram_component|auto_generated|q_a [6] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # ((!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [4])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][7]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][7] .lut_mask = 16'h45BA; +defparam \modulation|Mult0|mult_core|romout[1][7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][6] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][6]~combout = \spwm_sin|altsyncram_component|auto_generated|q_a [5] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [4] & !\spwm_sin|altsyncram_component|auto_generated|q_a [7]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(gnd), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][6]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][6] .lut_mask = 16'hF50A; +defparam \modulation|Mult0|mult_core|romout[1][6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N28 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][10]~3 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][10]~3_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [2] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [0])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [2] & (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [0]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][10]~3 .lut_mask = 16'hA2A4; +defparam \modulation|Mult0|mult_core|romout[0][10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N26 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][9]~5 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][9]~5_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [1] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [0]))) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & (\spwm_sin|altsyncram_component|auto_generated|q_a [2] & !\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][9]~5_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][9]~5 .lut_mask = 16'h380E; +defparam \modulation|Mult0|mult_core|romout[0][9]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][5]~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][5]~4_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (\spwm_sin|altsyncram_component|auto_generated|q_a [7]) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(gnd), + .datac(gnd), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][5]~4_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][5]~4 .lut_mask = 16'h55AA; +defparam \modulation|Mult0|mult_core|romout[1][5]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][8]~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][8]~6_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (\spwm_sin|altsyncram_component|auto_generated|q_a [0] $ (((!\spwm_sin|altsyncram_component|auto_generated|q_a [2] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [1]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [0] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [1])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][8]~6_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][8]~6 .lut_mask = 16'hC836; +defparam \modulation|Mult0|mult_core|romout[0][8]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N2 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][7]~7 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][7]~7_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [2] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [0] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [3])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][7]~7 .lut_mask = 16'h0DF2; +defparam \modulation|Mult0|mult_core|romout[0][7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][6]~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][6]~8_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [1] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [0] & !\spwm_sin|altsyncram_component|auto_generated|q_a [3]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(gnd), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][6]~8 .lut_mask = 16'hDD22; +defparam \modulation|Mult0|mult_core|romout[0][6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N6 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout = (\modulation|Mult0|mult_core|romout[0][6]~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (VCC))) # (!\modulation|Mult0|mult_core|romout[0][6]~8_combout & +// (\spwm_sin|altsyncram_component|auto_generated|q_a [4] & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 = CARRY((\modulation|Mult0|mult_core|romout[0][6]~8_combout & \spwm_sin|altsyncram_component|auto_generated|q_a [4])) + + .dataa(\modulation|Mult0|mult_core|romout[0][6]~8_combout ), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\modulation|Mult0|mult_core|romout[0][7]~7_combout & +// (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 & VCC)) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )))) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\modulation|Mult0|mult_core|romout[0][7]~7_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & +// ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [5] & (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 +// )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datab(\modulation|Mult0|mult_core|romout[0][7]~7_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout = ((\spwm_sin|altsyncram_component|auto_generated|q_a [6] $ (\modulation|Mult0|mult_core|romout[0][8]~6_combout $ +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 )))) # (GND) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [6] & ((\modulation|Mult0|mult_core|romout[0][8]~6_combout ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [6] & (\modulation|Mult0|mult_core|romout[0][8]~6_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 +// ))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datab(\modulation|Mult0|mult_core|romout[0][8]~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N12 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout = (\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((\modulation|Mult0|mult_core|romout[1][5]~4_combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 +// & VCC)) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )))) # (!\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((\modulation|Mult0|mult_core|romout[1][5]~4_combout & +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 = CARRY((\modulation|Mult0|mult_core|romout[0][9]~5_combout & (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )) +// # (!\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout )))) + + .dataa(\modulation|Mult0|mult_core|romout[0][9]~5_combout ), + .datab(\modulation|Mult0|mult_core|romout[1][5]~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N14 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout = ((\modulation|Mult0|mult_core|romout[1][6]~combout $ (\modulation|Mult0|mult_core|romout[0][10]~3_combout $ (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 +// )))) # (GND) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 = CARRY((\modulation|Mult0|mult_core|romout[1][6]~combout & ((\modulation|Mult0|mult_core|romout[0][10]~3_combout ) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 +// ))) # (!\modulation|Mult0|mult_core|romout[1][6]~combout & (\modulation|Mult0|mult_core|romout[0][10]~3_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ))) + + .dataa(\modulation|Mult0|mult_core|romout[1][6]~combout ), + .datab(\modulation|Mult0|mult_core|romout[0][10]~3_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N16 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout = (\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((\modulation|Mult0|mult_core|romout[1][7]~combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 +// & VCC)) # (!\modulation|Mult0|mult_core|romout[1][7]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )))) # (!\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((\modulation|Mult0|mult_core|romout[1][7]~combout & +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )) # (!\modulation|Mult0|mult_core|romout[1][7]~combout & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 = CARRY((\modulation|Mult0|mult_core|romout[0][11]~2_combout & (!\modulation|Mult0|mult_core|romout[1][7]~combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )) +// # (!\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (!\modulation|Mult0|mult_core|romout[1][7]~combout )))) + + .dataa(\modulation|Mult0|mult_core|romout[0][11]~2_combout ), + .datab(\modulation|Mult0|mult_core|romout[1][7]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N18 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout = (\modulation|Mult0|mult_core|romout[1][8]~1_combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 $ (GND))) # +// (!\modulation|Mult0|mult_core|romout[1][8]~1_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 = CARRY((\modulation|Mult0|mult_core|romout[1][8]~1_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 )) + + .dataa(\modulation|Mult0|mult_core|romout[1][8]~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 .lut_mask = 16'hA50A; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N20 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout = (\modulation|Mult0|mult_core|romout[1][9]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 )) # (!\modulation|Mult0|mult_core|romout[1][9]~combout +// & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ) # (GND))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 = CARRY((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ) # (!\modulation|Mult0|mult_core|romout[1][9]~combout )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|romout[1][9]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 .lut_mask = 16'h3C3F; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N22 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout = (\modulation|Mult0|mult_core|romout[1][10]~combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 $ (GND))) # +// (!\modulation|Mult0|mult_core|romout[1][10]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 = CARRY((\modulation|Mult0|mult_core|romout[1][10]~combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|romout[1][10]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 .lut_mask = 16'hC30C; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N24 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout = \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 $ (\modulation|Mult0|mult_core|romout[1][11]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\modulation|Mult0|mult_core|romout[1][11]~0_combout ), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 .lut_mask = 16'h0FF0; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [8] $ (VCC))) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & VCC)) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & \spwm_sin|altsyncram_component|auto_generated|q_a [8])) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N2 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # (GND))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 = CARRY((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout )) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h5A5F; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N4 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 $ +// (GND))) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 & VCC)) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .lut_mask = 16'hC30C; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N6 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 & VCC)) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )))) +// # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout = ((\spwm_sin|altsyncram_component|auto_generated|q_a [8] $ (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout $ +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )))) # (GND) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 & VCC)) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )))) +// # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N12 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout = !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .lut_mask = 16'h0F0F; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \modulation|LessThan0~0 ( +// Equation(s): +// \modulation|LessThan0~0_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [0]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [3]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .cin(gnd), + .combout(\modulation|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~0 .lut_mask = 16'hFFFE; +defparam \modulation|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \modulation|LessThan0~1 ( +// Equation(s): +// \modulation|LessThan0~1_combout = (\modulation|LessThan0~0_combout ) # ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ) # (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout )) + + .dataa(gnd), + .datab(\modulation|LessThan0~0_combout ), + .datac(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ), + .datad(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ), + .cin(gnd), + .combout(\modulation|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~1 .lut_mask = 16'hFFFC; +defparam \modulation|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \modulation|LessThan0~3 ( +// Equation(s): +// \modulation|LessThan0~3_cout = CARRY(\modulation|LessThan0~1_combout ) + + .dataa(gnd), + .datab(\modulation|LessThan0~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\modulation|LessThan0~3_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~3 .lut_mask = 16'h00CC; +defparam \modulation|LessThan0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \modulation|LessThan0~5 ( +// Equation(s): +// \modulation|LessThan0~5_cout = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout & (\tri_out[0]~reg0_q & !\modulation|LessThan0~3_cout )) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout & +// ((\tri_out[0]~reg0_q ) # (!\modulation|LessThan0~3_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ), + .datab(\tri_out[0]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~3_cout ), + .combout(), + .cout(\modulation|LessThan0~5_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~5 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \modulation|LessThan0~7 ( +// Equation(s): +// \modulation|LessThan0~7_cout = CARRY((\tri_out[1]~reg0_q & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout & !\modulation|LessThan0~5_cout )) # (!\tri_out[1]~reg0_q & +// ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ) # (!\modulation|LessThan0~5_cout )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~5_cout ), + .combout(), + .cout(\modulation|LessThan0~7_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~7 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \modulation|LessThan0~9 ( +// Equation(s): +// \modulation|LessThan0~9_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout & (\tri_out[2]~reg0_q & !\modulation|LessThan0~7_cout )) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout & ((\tri_out[2]~reg0_q ) # (!\modulation|LessThan0~7_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ), + .datab(\tri_out[2]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~7_cout ), + .combout(), + .cout(\modulation|LessThan0~9_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~9 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \modulation|LessThan0~11 ( +// Equation(s): +// \modulation|LessThan0~11_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout & ((!\modulation|LessThan0~9_cout ) # (!\tri_out[3]~reg0_q ))) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout & (!\tri_out[3]~reg0_q & !\modulation|LessThan0~9_cout ))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ), + .datab(\tri_out[3]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~9_cout ), + .combout(), + .cout(\modulation|LessThan0~11_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~11 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \modulation|LessThan0~13 ( +// Equation(s): +// \modulation|LessThan0~13_cout = CARRY((\tri_out[4]~reg0_q & ((!\modulation|LessThan0~11_cout ) # (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ))) # (!\tri_out[4]~reg0_q & +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout & !\modulation|LessThan0~11_cout ))) + + .dataa(\tri_out[4]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~11_cout ), + .combout(), + .cout(\modulation|LessThan0~13_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~13 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \modulation|LessThan0~15 ( +// Equation(s): +// \modulation|LessThan0~15_cout = CARRY((\tri_out[5]~reg0_q & (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout & !\modulation|LessThan0~13_cout )) # (!\tri_out[5]~reg0_q & +// ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (!\modulation|LessThan0~13_cout )))) + + .dataa(\tri_out[5]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~13_cout ), + .combout(), + .cout(\modulation|LessThan0~15_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~15 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \modulation|LessThan0~17 ( +// Equation(s): +// \modulation|LessThan0~17_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout & (\tri_out[6]~reg0_q & !\modulation|LessThan0~15_cout )) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout & ((\tri_out[6]~reg0_q ) # (!\modulation|LessThan0~15_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ), + .datab(\tri_out[6]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~15_cout ), + .combout(), + .cout(\modulation|LessThan0~17_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~17 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \modulation|LessThan0~19 ( +// Equation(s): +// \modulation|LessThan0~19_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout & ((!\modulation|LessThan0~17_cout ) # (!\tri_out[7]~reg0_q ))) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout & (!\tri_out[7]~reg0_q & !\modulation|LessThan0~17_cout ))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ), + .datab(\tri_out[7]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~17_cout ), + .combout(), + .cout(\modulation|LessThan0~19_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~19 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \modulation|LessThan0~20 ( +// Equation(s): +// \modulation|LessThan0~20_combout = (\tri_out[8]~reg0_q & (\modulation|LessThan0~19_cout & \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout )) # (!\tri_out[8]~reg0_q & ((\modulation|LessThan0~19_cout ) # +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ))) + + .dataa(gnd), + .datab(\tri_out[8]~reg0_q ), + .datac(gnd), + .datad(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ), + .cin(\modulation|LessThan0~19_cout ), + .combout(\modulation|LessThan0~20_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~20 .lut_mask = 16'hF330; +defparam \modulation|LessThan0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y12_N23 +dffeas \modulation|out ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\modulation|LessThan0~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\modulation|out~q ), + .prn(vcc)); +// synopsys translate_off +defparam \modulation|out .is_wysiwyg = "true"; +defparam \modulation|out .power_up = "low"; +// synopsys translate_on + +assign tri_out[0] = \tri_out[0]~output_o ; + +assign tri_out[1] = \tri_out[1]~output_o ; + +assign tri_out[2] = \tri_out[2]~output_o ; + +assign tri_out[3] = \tri_out[3]~output_o ; + +assign tri_out[4] = \tri_out[4]~output_o ; + +assign tri_out[5] = \tri_out[5]~output_o ; + +assign tri_out[6] = \tri_out[6]~output_o ; + +assign tri_out[7] = \tri_out[7]~output_o ; + +assign tri_out[8] = \tri_out[8]~output_o ; + +assign sin_out[0] = \sin_out[0]~output_o ; + +assign sin_out[1] = \sin_out[1]~output_o ; + +assign sin_out[2] = \sin_out[2]~output_o ; + +assign sin_out[3] = \sin_out[3]~output_o ; + +assign sin_out[4] = \sin_out[4]~output_o ; + +assign sin_out[5] = \sin_out[5]~output_o ; + +assign sin_out[6] = \sin_out[6]~output_o ; + +assign sin_out[7] = \sin_out[7]~output_o ; + +assign sin_out[8] = \sin_out[8]~output_o ; + +assign spwm_out = \spwm_out~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_DATA0~~ibuf_o ; + + +endmodule diff --git a/spwm/simulation/modelsim/spwm_8_1200mv_85c_v_slow.sdo b/spwm/simulation/modelsim/spwm_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..afaa4ac --- /dev/null +++ b/spwm/simulation/modelsim/spwm_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,2573 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "spwm") + (DATE "12/10/2018 20:55:32") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1131:1131:1131) (1059:1059:1059)) + (IOPATH i o (3147:3147:3147) (3095:3095:3095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1455:1455:1455) (1357:1357:1357)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1494:1494:1494) (1382:1382:1382)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1099:1099:1099) (1037:1037:1037)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1556:1556:1556) (1453:1453:1453)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1503:1503:1503) (1406:1406:1406)) + (IOPATH i o (3127:3127:3127) (3075:3075:3075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1114:1114:1114) (1062:1062:1062)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1452:1452:1452) (1323:1323:1323)) + (IOPATH i o (3147:3147:3147) (3095:3095:3095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1119:1119:1119) (1061:1061:1061)) + (IOPATH i o (3127:3127:3127) (3075:3075:3075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1630:1630:1630) (1516:1516:1516)) + (IOPATH i o (3147:3147:3147) (3095:3095:3095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2014:2014:2014) (1771:1771:1771)) + (IOPATH i o (3048:3048:3048) (3009:3009:3009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1887:1887:1887) (1734:1734:1734)) + (IOPATH i o (3117:3117:3117) (3065:3065:3065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1866:1866:1866) (1705:1705:1705)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1790:1790:1790) (1635:1635:1635)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1935:1935:1935) (1695:1695:1695)) + (IOPATH i o (3128:3128:3128) (3105:3105:3105)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1766:1766:1766) (1601:1601:1601)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2263:2263:2263) (2058:2058:2058)) + (IOPATH i o (3117:3117:3117) (3065:3065:3065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1913:1913:1913) (1755:1755:1755)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE spwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (1617:1617:1617) (1548:1548:1548)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk_200m\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_200m\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (482:482:482)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[0\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (869:869:869) (777:777:777)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (841:841:841)) + (PORT datab (377:377:377) (465:465:465)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[2\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (840:840:840)) + (PORT datab (369:369:369) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[3\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (840:840:840)) + (PORT datab (368:368:368) (451:451:451)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[4\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (839:839:839)) + (PORT datab (360:360:360) (437:437:437)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[5\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (839:839:839)) + (PORT datab (587:587:587) (632:632:632)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[6\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (838:838:838)) + (PORT datab (368:368:368) (447:447:447)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[7\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (825:825:825)) + (PORT datad (808:808:808) (727:727:727)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[8\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~12) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (459:459:459)) + (PORT datab (376:376:376) (464:464:464)) + (PORT datac (787:787:787) (780:780:780)) + (PORT datad (329:329:329) (405:405:405)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~11) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (626:626:626)) + (PORT datab (369:369:369) (452:452:452)) + (PORT datac (335:335:335) (427:427:427)) + (PORT datad (329:329:329) (406:406:406)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE updown) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~13) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (462:462:462)) + (PORT datab (331:331:331) (407:407:407)) + (PORT datac (325:325:325) (410:410:410)) + (PORT datad (354:354:354) (432:432:432)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~14) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (280:280:280) (306:306:306)) + (PORT datad (442:442:442) (418:418:418)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[1\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (774:774:774) (821:821:821)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (418:418:418)) + (PORT datab (3363:3363:3363) (3595:3595:3595)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (3654:3654:3654) (3827:3827:3827)) + (PORT datab (332:332:332) (408:408:408)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (418:418:418)) + (PORT datab (3703:3703:3703) (3874:3874:3874)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (418:418:418)) + (PORT datab (3987:3987:3987) (4091:4091:4091)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[4\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (3655:3655:3655) (3847:3847:3847)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[5\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (3754:3754:3754) (3918:3918:3918)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[6\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (3583:3583:3583) (3781:3781:3781)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[7\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (3421:3421:3421) (3630:3630:3630)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[8\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (419:419:419)) + (PORT datab (3618:3618:3618) (3786:3786:3786)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[9\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (3696:3696:3696) (3868:3868:3868)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[10\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (418:418:418)) + (PORT datab (3591:3591:3591) (3784:3784:3784)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[11\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (3335:3335:3335) (3582:3582:3582)) + (PORT datab (332:332:332) (408:408:408)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[12\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (417:417:417)) + (PORT datab (3386:3386:3386) (3605:3605:3605)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[13\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (3731:3731:3731) (3898:3898:3898)) + (PORT datab (332:332:332) (407:407:407)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[14\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (3702:3702:3702) (3890:3890:3890)) + (PORT datab (332:332:332) (408:408:408)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[15\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (3614:3614:3614) (3744:3744:3744)) + (PORT datab (333:333:333) (408:408:408)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[16\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3565:3565:3565) (3764:3764:3764)) + (PORT datab (565:565:565) (585:585:585)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[17\]\~60) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (593:593:593)) + (PORT datab (3993:3993:3993) (4104:4104:4104)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[18\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (629:629:629)) + (PORT datab (3600:3600:3600) (3783:3783:3783)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[19\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (726:726:726) (772:772:772)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (629:629:629)) + (PORT datab (3994:3994:3994) (4125:4125:4125)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[20\]\~66) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (598:598:598)) + (PORT datab (3578:3578:3578) (3713:3713:3713)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[21\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (597:597:597)) + (PORT datab (3674:3674:3674) (3888:3888:3888)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[22\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (3983:3983:3983) (4122:4122:4122)) + (PORT datab (558:558:558) (584:584:584)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[23\]\~72) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (4049:4049:4049) (4173:4173:4173)) + (PORT datab (613:613:613) (618:618:618)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[24\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[8\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (3571:3571:3571) (3711:3711:3711)) + (PORT datab (558:558:558) (584:584:584)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[25\]\~76) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (392:392:392)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[25\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[9\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (3657:3657:3657) (3851:3851:3851)) + (PORT datad (554:554:554) (568:568:568)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1796:1796:1796) (1630:1630:1630)) + (PORT d[1] (1875:1875:1875) (1676:1676:1676)) + (PORT d[2] (2226:2226:2226) (2004:2004:2004)) + (PORT d[3] (2287:2287:2287) (2057:2057:2057)) + (PORT d[4] (2093:2093:2093) (2053:2053:2053)) + (PORT d[5] (2187:2187:2187) (1984:1984:1984)) + (PORT d[6] (2236:2236:2236) (2029:2029:2029)) + (PORT d[7] (2257:2257:2257) (2031:2031:2031)) + (PORT d[8] (2216:2216:2216) (2005:2005:2005)) + (PORT d[9] (2152:2152:2152) (2050:2050:2050)) + (PORT clk (2036:2036:2036) (2082:2082:2082)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2036:2036:2036) (2082:2082:2082)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2037:2037:2037) (2083:2083:2083)) + (IOPATH (posedge clk) pulse (0:0:0) (3134:3134:3134)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1988:1988:1988) (2035:2035:2035)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (976:976:976)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (960:960:960) (977:977:977)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (960:960:960) (977:977:977)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (960:960:960) (977:977:977)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (979:979:979)) + (PORT datab (1006:1006:1006) (946:946:946)) + (PORT datac (992:992:992) (940:940:940)) + (PORT datad (913:913:913) (861:861:861)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[10\]) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (976:976:976)) + (PORT datab (1042:1042:1042) (976:976:976)) + (PORT datac (920:920:920) (858:858:858)) + (PORT datad (949:949:949) (901:901:901)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[9\]) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (549:549:549)) + (PORT datab (590:590:590) (553:553:553)) + (PORT datac (545:545:545) (525:525:525)) + (PORT datad (538:538:538) (516:516:516)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (571:571:571)) + (PORT datab (597:597:597) (563:563:563)) + (PORT datac (539:539:539) (516:516:516)) + (PORT datad (513:513:513) (500:500:500)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[11\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (834:834:834)) + (PORT datab (868:868:868) (804:804:804)) + (PORT datac (798:798:798) (747:747:747)) + (PORT datad (816:816:816) (762:762:762)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (784:784:784)) + (PORT datab (789:789:789) (734:734:734)) + (PORT datac (773:773:773) (714:714:714)) + (PORT datad (840:840:840) (766:766:766)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (543:543:543)) + (PORT datac (550:550:550) (531:531:531)) + (PORT datad (539:539:539) (517:517:517)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (833:833:833)) + (PORT datab (868:868:868) (804:804:804)) + (PORT datac (798:798:798) (747:747:747)) + (PORT datad (816:816:816) (761:761:761)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[9\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (833:833:833)) + (PORT datab (868:868:868) (805:805:805)) + (PORT datac (799:799:799) (747:747:747)) + (PORT datad (815:815:815) (761:761:761)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (976:976:976)) + (PORT datad (949:949:949) (901:901:901)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[8\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (823:823:823)) + (PORT datab (874:874:874) (812:812:812)) + (PORT datac (801:801:801) (751:751:751)) + (PORT datad (812:812:812) (757:757:757)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (815:815:815)) + (PORT datab (874:874:874) (811:811:811)) + (PORT datac (801:801:801) (750:750:750)) + (PORT datad (812:812:812) (766:766:766)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (541:541:541)) + (PORT datab (581:581:581) (542:542:542)) + (PORT datad (524:524:524) (497:497:497)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (771:771:771)) + (PORT datab (813:813:813) (751:751:751)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (784:784:784)) + (PORT datab (275:275:275) (299:299:299)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (824:824:824)) + (PORT datab (275:275:275) (300:300:300)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (823:823:823) (772:772:772)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (727:727:727)) + (PORT datab (276:276:276) (301:301:301)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (276:276:276) (301:301:301)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (759:759:759) (695:695:695)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT datab (803:803:803) (724:724:724)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT datab (834:834:834) (784:784:784)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~18) + (DELAY + (ABSOLUTE + (PORT datad (869:869:869) (809:809:809)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (464:464:464)) + (PORT datab (909:909:909) (850:850:850)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (472:472:472)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT datab (475:475:475) (459:459:459)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (895:895:895)) + (PORT datab (530:530:530) (493:493:493)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (896:896:896)) + (PORT datab (475:475:475) (459:459:459)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (897:897:897)) + (PORT datab (530:530:530) (493:493:493)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (542:542:542)) + (PORT datab (584:584:584) (546:546:546)) + (PORT datac (482:482:482) (465:465:465)) + (PORT datad (523:523:523) (495:495:495)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (809:809:809) (730:730:730)) + (PORT datad (784:784:784) (710:710:710)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT datab (274:274:274) (299:299:299)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (745:745:745)) + (PORT datab (1394:1394:1394) (1354:1354:1354)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1937:1937:1937) (1823:1823:1823)) + (PORT datab (871:871:871) (796:796:796)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (495:495:495)) + (PORT datab (1709:1709:1709) (1659:1659:1659)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (493:493:493)) + (PORT datab (1738:1738:1738) (1632:1632:1632)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1402:1402:1402) (1394:1394:1394)) + (PORT datab (471:471:471) (451:451:451)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1404:1404:1404) (1360:1360:1360)) + (PORT datab (483:483:483) (452:452:452)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (461:461:461)) + (PORT datab (1380:1380:1380) (1355:1355:1355)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (496:496:496)) + (PORT datab (1349:1349:1349) (1329:1329:1329)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~20) + (DELAY + (ABSOLUTE + (PORT datab (1388:1388:1388) (1381:1381:1381)) + (PORT datad (468:468:468) (436:436:436)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE modulation\|out) + (DELAY + (ABSOLUTE + (PORT clk (2121:2121:2121) (2132:2132:2132)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) +) diff --git a/spwm/simulation/modelsim/spwm_8_1200mv_85c_v_slow.sdo_typ.csd b/spwm/simulation/modelsim/spwm_8_1200mv_85c_v_slow.sdo_typ.csd new file mode 100644 index 0000000..635e797 Binary files /dev/null and b/spwm/simulation/modelsim/spwm_8_1200mv_85c_v_slow.sdo_typ.csd differ diff --git a/spwm/simulation/modelsim/spwm_min_1200mv_0c_fast.vo b/spwm/simulation/modelsim/spwm_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..25cae97 --- /dev/null +++ b/spwm/simulation/modelsim/spwm_min_1200mv_0c_fast.vo @@ -0,0 +1,3398 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" + +// DATE "12/10/2018 20:55:32" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module spwm ( + clk_200m, + rst_n, + tri_out, + sin_out, + Fword, + Pword, + spwm_out); +input clk_200m; +input rst_n; +output [8:0] tri_out; +output [8:0] sin_out; +input [15:0] Fword; +input [9:0] Pword; +output spwm_out; + +// Design Ports Information +// tri_out[0] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[1] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[2] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[3] => Location: PIN_E8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[4] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[5] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[6] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[7] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// tri_out[8] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[0] => Location: PIN_M8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[1] => Location: PIN_J6, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[2] => Location: PIN_L7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[3] => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[4] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[5] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[6] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[7] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default +// sin_out[8] => Location: PIN_R8, I/O Standard: 2.5 V, Current Strength: Default +// spwm_out => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +// clk_200m => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[0] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// Pword[1] => Location: PIN_D1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[2] => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// Pword[3] => Location: PIN_F3, I/O Standard: 2.5 V, Current Strength: Default +// Pword[4] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[5] => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// Pword[6] => Location: PIN_G1, I/O Standard: 2.5 V, Current Strength: Default +// Pword[7] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[8] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// Pword[9] => Location: PIN_E6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[15] => Location: PIN_G5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[14] => Location: PIN_G2, I/O Standard: 2.5 V, Current Strength: Default +// Fword[13] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +// Fword[12] => Location: PIN_A2, I/O Standard: 2.5 V, Current Strength: Default +// Fword[11] => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[10] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[9] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[8] => Location: PIN_A3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[7] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default +// Fword[6] => Location: PIN_D3, I/O Standard: 2.5 V, Current Strength: Default +// Fword[5] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// Fword[4] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[3] => Location: PIN_D5, I/O Standard: 2.5 V, Current Strength: Default +// Fword[2] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// Fword[1] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// Fword[0] => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("spwm_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \tri_out[0]~output_o ; +wire \tri_out[1]~output_o ; +wire \tri_out[2]~output_o ; +wire \tri_out[3]~output_o ; +wire \tri_out[4]~output_o ; +wire \tri_out[5]~output_o ; +wire \tri_out[6]~output_o ; +wire \tri_out[7]~output_o ; +wire \tri_out[8]~output_o ; +wire \sin_out[0]~output_o ; +wire \sin_out[1]~output_o ; +wire \sin_out[2]~output_o ; +wire \sin_out[3]~output_o ; +wire \sin_out[4]~output_o ; +wire \sin_out[5]~output_o ; +wire \sin_out[6]~output_o ; +wire \sin_out[7]~output_o ; +wire \sin_out[8]~output_o ; +wire \spwm_out~output_o ; +wire \clk_200m~input_o ; +wire \clk_200m~inputclkctrl_outclk ; +wire \tri_out[0]~9_combout ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \tri_out[0]~reg0_q ; +wire \tri_out[0]~10 ; +wire \tri_out[1]~16 ; +wire \tri_out[2]~17_combout ; +wire \tri_out[2]~reg0_q ; +wire \tri_out[2]~18 ; +wire \tri_out[3]~19_combout ; +wire \tri_out[3]~reg0_q ; +wire \tri_out[3]~20 ; +wire \tri_out[4]~21_combout ; +wire \tri_out[4]~reg0_q ; +wire \tri_out[4]~22 ; +wire \tri_out[5]~23_combout ; +wire \tri_out[5]~reg0_q ; +wire \tri_out[5]~24 ; +wire \tri_out[6]~25_combout ; +wire \tri_out[6]~reg0_q ; +wire \tri_out[6]~26 ; +wire \tri_out[7]~27_combout ; +wire \tri_out[7]~reg0_q ; +wire \tri_out[7]~28 ; +wire \tri_out[8]~29_combout ; +wire \tri_out[8]~reg0_q ; +wire \tri_out~12_combout ; +wire \tri_out~11_combout ; +wire \updown~q ; +wire \tri_out~13_combout ; +wire \tri_out~14_combout ; +wire \tri_out[1]~15_combout ; +wire \tri_out[1]~reg0_q ; +wire \Pword[0]~input_o ; +wire \Fword[15]~input_o ; +wire \Fword[14]~input_o ; +wire \Fword[13]~input_o ; +wire \Fword[12]~input_o ; +wire \Fword[11]~input_o ; +wire \Fword[10]~input_o ; +wire \Fword[9]~input_o ; +wire \Fword[8]~input_o ; +wire \Fword[7]~input_o ; +wire \Fword[6]~input_o ; +wire \Fword[5]~input_o ; +wire \Fword[4]~input_o ; +wire \Fword[3]~input_o ; +wire \Fword[2]~input_o ; +wire \Fword[1]~input_o ; +wire \Fword[0]~input_o ; +wire \F_acc[0]~26_combout ; +wire \F_acc[0]~27 ; +wire \F_acc[1]~28_combout ; +wire \F_acc[1]~29 ; +wire \F_acc[2]~30_combout ; +wire \F_acc[2]~31 ; +wire \F_acc[3]~32_combout ; +wire \F_acc[3]~33 ; +wire \F_acc[4]~34_combout ; +wire \F_acc[4]~35 ; +wire \F_acc[5]~36_combout ; +wire \F_acc[5]~37 ; +wire \F_acc[6]~38_combout ; +wire \F_acc[6]~39 ; +wire \F_acc[7]~40_combout ; +wire \F_acc[7]~41 ; +wire \F_acc[8]~42_combout ; +wire \F_acc[8]~43 ; +wire \F_acc[9]~44_combout ; +wire \F_acc[9]~45 ; +wire \F_acc[10]~46_combout ; +wire \F_acc[10]~47 ; +wire \F_acc[11]~48_combout ; +wire \F_acc[11]~49 ; +wire \F_acc[12]~50_combout ; +wire \F_acc[12]~51 ; +wire \F_acc[13]~52_combout ; +wire \F_acc[13]~53 ; +wire \F_acc[14]~54_combout ; +wire \F_acc[14]~55 ; +wire \F_acc[15]~56_combout ; +wire \F_acc[15]~57 ; +wire \F_acc[16]~58_combout ; +wire \rom_address[0]~0_combout ; +wire \F_acc[16]~59 ; +wire \F_acc[17]~60_combout ; +wire \Pword[1]~input_o ; +wire \rom_address[0]~1 ; +wire \rom_address[1]~2_combout ; +wire \F_acc[17]~61 ; +wire \F_acc[18]~62_combout ; +wire \Pword[2]~input_o ; +wire \rom_address[1]~3 ; +wire \rom_address[2]~4_combout ; +wire \F_acc[18]~63 ; +wire \F_acc[19]~64_combout ; +wire \Pword[3]~input_o ; +wire \rom_address[2]~5 ; +wire \rom_address[3]~6_combout ; +wire \F_acc[19]~65 ; +wire \F_acc[20]~66_combout ; +wire \Pword[4]~input_o ; +wire \rom_address[3]~7 ; +wire \rom_address[4]~8_combout ; +wire \F_acc[20]~67 ; +wire \F_acc[21]~68_combout ; +wire \Pword[5]~input_o ; +wire \rom_address[4]~9 ; +wire \rom_address[5]~10_combout ; +wire \Pword[6]~input_o ; +wire \F_acc[21]~69 ; +wire \F_acc[22]~70_combout ; +wire \rom_address[5]~11 ; +wire \rom_address[6]~12_combout ; +wire \Pword[7]~input_o ; +wire \F_acc[22]~71 ; +wire \F_acc[23]~72_combout ; +wire \rom_address[6]~13 ; +wire \rom_address[7]~14_combout ; +wire \Pword[8]~input_o ; +wire \F_acc[23]~73 ; +wire \F_acc[24]~74_combout ; +wire \rom_address[7]~15 ; +wire \rom_address[8]~16_combout ; +wire \Pword[9]~input_o ; +wire \F_acc[24]~75 ; +wire \F_acc[25]~76_combout ; +wire \rom_address[8]~17 ; +wire \rom_address[9]~18_combout ; +wire \modulation|Mult0|mult_core|romout[1][11]~0_combout ; +wire \modulation|Mult0|mult_core|romout[1][10]~combout ; +wire \modulation|Mult0|mult_core|romout[1][9]~combout ; +wire \modulation|Mult0|mult_core|romout[1][8]~1_combout ; +wire \modulation|Mult0|mult_core|romout[0][11]~2_combout ; +wire \modulation|Mult0|mult_core|romout[1][7]~combout ; +wire \modulation|Mult0|mult_core|romout[1][6]~combout ; +wire \modulation|Mult0|mult_core|romout[0][10]~3_combout ; +wire \modulation|Mult0|mult_core|romout[0][9]~5_combout ; +wire \modulation|Mult0|mult_core|romout[1][5]~4_combout ; +wire \modulation|Mult0|mult_core|romout[0][8]~6_combout ; +wire \modulation|Mult0|mult_core|romout[0][7]~7_combout ; +wire \modulation|Mult0|mult_core|romout[0][6]~8_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ; +wire \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ; +wire \modulation|LessThan0~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ; +wire \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ; +wire \modulation|LessThan0~1_combout ; +wire \modulation|LessThan0~3_cout ; +wire \modulation|LessThan0~5_cout ; +wire \modulation|LessThan0~7_cout ; +wire \modulation|LessThan0~9_cout ; +wire \modulation|LessThan0~11_cout ; +wire \modulation|LessThan0~13_cout ; +wire \modulation|LessThan0~15_cout ; +wire \modulation|LessThan0~17_cout ; +wire \modulation|LessThan0~19_cout ; +wire \modulation|LessThan0~20_combout ; +wire \modulation|out~q ; +wire [8:0] \spwm_sin|altsyncram_component|auto_generated|q_a ; +wire [25:0] F_acc; + +wire [8:0] \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ; + +assign \spwm_sin|altsyncram_component|auto_generated|q_a [0] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [1] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [2] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [3] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [4] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [5] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [6] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [7] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]; +assign \spwm_sin|altsyncram_component|auto_generated|q_a [8] = \spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [8]; + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: IOOBUF_X13_Y24_N23 +cycloneive_io_obuf \tri_out[0]~output ( + .i(\tri_out[0]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[0]~output .bus_hold = "false"; +defparam \tri_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N2 +cycloneive_io_obuf \tri_out[1]~output ( + .i(\tri_out[1]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[1]~output .bus_hold = "false"; +defparam \tri_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N23 +cycloneive_io_obuf \tri_out[2]~output ( + .i(\tri_out[2]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[2]~output .bus_hold = "false"; +defparam \tri_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N16 +cycloneive_io_obuf \tri_out[3]~output ( + .i(\tri_out[3]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[3]~output .bus_hold = "false"; +defparam \tri_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N9 +cycloneive_io_obuf \tri_out[4]~output ( + .i(\tri_out[4]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[4]~output .bus_hold = "false"; +defparam \tri_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y24_N16 +cycloneive_io_obuf \tri_out[5]~output ( + .i(\tri_out[5]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[5]~output .bus_hold = "false"; +defparam \tri_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N9 +cycloneive_io_obuf \tri_out[6]~output ( + .i(\tri_out[6]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[6]~output .bus_hold = "false"; +defparam \tri_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N16 +cycloneive_io_obuf \tri_out[7]~output ( + .i(\tri_out[7]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[7]~output .bus_hold = "false"; +defparam \tri_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y24_N2 +cycloneive_io_obuf \tri_out[8]~output ( + .i(\tri_out[8]~reg0_q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tri_out[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \tri_out[8]~output .bus_hold = "false"; +defparam \tri_out[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y0_N2 +cycloneive_io_obuf \sin_out[0]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[0]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[0]~output .bus_hold = "false"; +defparam \sin_out[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N23 +cycloneive_io_obuf \sin_out[1]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[1]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[1]~output .bus_hold = "false"; +defparam \sin_out[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N9 +cycloneive_io_obuf \sin_out[2]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[2]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[2]~output .bus_hold = "false"; +defparam \sin_out[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y0_N2 +cycloneive_io_obuf \sin_out[3]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[3]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[3]~output .bus_hold = "false"; +defparam \sin_out[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y24_N23 +cycloneive_io_obuf \sin_out[4]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[4]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[4]~output .bus_hold = "false"; +defparam \sin_out[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N2 +cycloneive_io_obuf \sin_out[5]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[5]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[5]~output .bus_hold = "false"; +defparam \sin_out[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y10_N16 +cycloneive_io_obuf \sin_out[6]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[6]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[6]~output .bus_hold = "false"; +defparam \sin_out[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N16 +cycloneive_io_obuf \sin_out[7]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[7]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[7]~output .bus_hold = "false"; +defparam \sin_out[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X16_Y0_N9 +cycloneive_io_obuf \sin_out[8]~output ( + .i(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\sin_out[8]~output_o ), + .obar()); +// synopsys translate_off +defparam \sin_out[8]~output .bus_hold = "false"; +defparam \sin_out[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X13_Y0_N16 +cycloneive_io_obuf \spwm_out~output ( + .i(\modulation|out~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\spwm_out~output_o ), + .obar()); +// synopsys translate_off +defparam \spwm_out~output .bus_hold = "false"; +defparam \spwm_out~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk_200m~input ( + .i(clk_200m), + .ibar(gnd), + .o(\clk_200m~input_o )); +// synopsys translate_off +defparam \clk_200m~input .bus_hold = "false"; +defparam \clk_200m~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G2 +cycloneive_clkctrl \clk_200m~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_200m~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_200m~inputclkctrl_outclk )); +// synopsys translate_off +defparam \clk_200m~inputclkctrl .clock_type = "global clock"; +defparam \clk_200m~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N10 +cycloneive_lcell_comb \tri_out[0]~9 ( +// Equation(s): +// \tri_out[0]~9_combout = \tri_out[0]~reg0_q $ (VCC) +// \tri_out[0]~10 = CARRY(\tri_out[0]~reg0_q ) + + .dataa(\tri_out[0]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\tri_out[0]~9_combout ), + .cout(\tri_out[0]~10 )); +// synopsys translate_off +defparam \tri_out[0]~9 .lut_mask = 16'h55AA; +defparam \tri_out[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X14_Y19_N11 +dffeas \tri_out[0]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[0]~9_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[0]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[0]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[0]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N12 +cycloneive_lcell_comb \tri_out[1]~15 ( +// Equation(s): +// \tri_out[1]~15_combout = (\tri_out[1]~reg0_q & ((\tri_out~14_combout & (\tri_out[0]~10 & VCC)) # (!\tri_out~14_combout & (!\tri_out[0]~10 )))) # (!\tri_out[1]~reg0_q & ((\tri_out~14_combout & (!\tri_out[0]~10 )) # (!\tri_out~14_combout & +// ((\tri_out[0]~10 ) # (GND))))) +// \tri_out[1]~16 = CARRY((\tri_out[1]~reg0_q & (!\tri_out~14_combout & !\tri_out[0]~10 )) # (!\tri_out[1]~reg0_q & ((!\tri_out[0]~10 ) # (!\tri_out~14_combout )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\tri_out~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[0]~10 ), + .combout(\tri_out[1]~15_combout ), + .cout(\tri_out[1]~16 )); +// synopsys translate_off +defparam \tri_out[1]~15 .lut_mask = 16'h9617; +defparam \tri_out[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N14 +cycloneive_lcell_comb \tri_out[2]~17 ( +// Equation(s): +// \tri_out[2]~17_combout = ((\tri_out~14_combout $ (\tri_out[2]~reg0_q $ (!\tri_out[1]~16 )))) # (GND) +// \tri_out[2]~18 = CARRY((\tri_out~14_combout & ((\tri_out[2]~reg0_q ) # (!\tri_out[1]~16 ))) # (!\tri_out~14_combout & (\tri_out[2]~reg0_q & !\tri_out[1]~16 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[2]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[1]~16 ), + .combout(\tri_out[2]~17_combout ), + .cout(\tri_out[2]~18 )); +// synopsys translate_off +defparam \tri_out[2]~17 .lut_mask = 16'h698E; +defparam \tri_out[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N15 +dffeas \tri_out[2]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[2]~17_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[2]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[2]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[2]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N16 +cycloneive_lcell_comb \tri_out[3]~19 ( +// Equation(s): +// \tri_out[3]~19_combout = (\tri_out~14_combout & ((\tri_out[3]~reg0_q & (\tri_out[2]~18 & VCC)) # (!\tri_out[3]~reg0_q & (!\tri_out[2]~18 )))) # (!\tri_out~14_combout & ((\tri_out[3]~reg0_q & (!\tri_out[2]~18 )) # (!\tri_out[3]~reg0_q & +// ((\tri_out[2]~18 ) # (GND))))) +// \tri_out[3]~20 = CARRY((\tri_out~14_combout & (!\tri_out[3]~reg0_q & !\tri_out[2]~18 )) # (!\tri_out~14_combout & ((!\tri_out[2]~18 ) # (!\tri_out[3]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[3]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[2]~18 ), + .combout(\tri_out[3]~19_combout ), + .cout(\tri_out[3]~20 )); +// synopsys translate_off +defparam \tri_out[3]~19 .lut_mask = 16'h9617; +defparam \tri_out[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N17 +dffeas \tri_out[3]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[3]~19_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[3]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[3]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[3]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N18 +cycloneive_lcell_comb \tri_out[4]~21 ( +// Equation(s): +// \tri_out[4]~21_combout = ((\tri_out~14_combout $ (\tri_out[4]~reg0_q $ (!\tri_out[3]~20 )))) # (GND) +// \tri_out[4]~22 = CARRY((\tri_out~14_combout & ((\tri_out[4]~reg0_q ) # (!\tri_out[3]~20 ))) # (!\tri_out~14_combout & (\tri_out[4]~reg0_q & !\tri_out[3]~20 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[4]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[3]~20 ), + .combout(\tri_out[4]~21_combout ), + .cout(\tri_out[4]~22 )); +// synopsys translate_off +defparam \tri_out[4]~21 .lut_mask = 16'h698E; +defparam \tri_out[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N19 +dffeas \tri_out[4]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[4]~21_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[4]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[4]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[4]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N20 +cycloneive_lcell_comb \tri_out[5]~23 ( +// Equation(s): +// \tri_out[5]~23_combout = (\tri_out~14_combout & ((\tri_out[5]~reg0_q & (\tri_out[4]~22 & VCC)) # (!\tri_out[5]~reg0_q & (!\tri_out[4]~22 )))) # (!\tri_out~14_combout & ((\tri_out[5]~reg0_q & (!\tri_out[4]~22 )) # (!\tri_out[5]~reg0_q & +// ((\tri_out[4]~22 ) # (GND))))) +// \tri_out[5]~24 = CARRY((\tri_out~14_combout & (!\tri_out[5]~reg0_q & !\tri_out[4]~22 )) # (!\tri_out~14_combout & ((!\tri_out[4]~22 ) # (!\tri_out[5]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[5]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[4]~22 ), + .combout(\tri_out[5]~23_combout ), + .cout(\tri_out[5]~24 )); +// synopsys translate_off +defparam \tri_out[5]~23 .lut_mask = 16'h9617; +defparam \tri_out[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N21 +dffeas \tri_out[5]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[5]~23_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[5]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[5]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[5]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N22 +cycloneive_lcell_comb \tri_out[6]~25 ( +// Equation(s): +// \tri_out[6]~25_combout = ((\tri_out~14_combout $ (\tri_out[6]~reg0_q $ (!\tri_out[5]~24 )))) # (GND) +// \tri_out[6]~26 = CARRY((\tri_out~14_combout & ((\tri_out[6]~reg0_q ) # (!\tri_out[5]~24 ))) # (!\tri_out~14_combout & (\tri_out[6]~reg0_q & !\tri_out[5]~24 ))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[6]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[5]~24 ), + .combout(\tri_out[6]~25_combout ), + .cout(\tri_out[6]~26 )); +// synopsys translate_off +defparam \tri_out[6]~25 .lut_mask = 16'h698E; +defparam \tri_out[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N23 +dffeas \tri_out[6]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[6]~25_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[6]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[6]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[6]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N24 +cycloneive_lcell_comb \tri_out[7]~27 ( +// Equation(s): +// \tri_out[7]~27_combout = (\tri_out~14_combout & ((\tri_out[7]~reg0_q & (\tri_out[6]~26 & VCC)) # (!\tri_out[7]~reg0_q & (!\tri_out[6]~26 )))) # (!\tri_out~14_combout & ((\tri_out[7]~reg0_q & (!\tri_out[6]~26 )) # (!\tri_out[7]~reg0_q & +// ((\tri_out[6]~26 ) # (GND))))) +// \tri_out[7]~28 = CARRY((\tri_out~14_combout & (!\tri_out[7]~reg0_q & !\tri_out[6]~26 )) # (!\tri_out~14_combout & ((!\tri_out[6]~26 ) # (!\tri_out[7]~reg0_q )))) + + .dataa(\tri_out~14_combout ), + .datab(\tri_out[7]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\tri_out[6]~26 ), + .combout(\tri_out[7]~27_combout ), + .cout(\tri_out[7]~28 )); +// synopsys translate_off +defparam \tri_out[7]~27 .lut_mask = 16'h9617; +defparam \tri_out[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N25 +dffeas \tri_out[7]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[7]~27_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[7]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[7]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[7]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N26 +cycloneive_lcell_comb \tri_out[8]~29 ( +// Equation(s): +// \tri_out[8]~29_combout = \tri_out[8]~reg0_q $ (\tri_out[7]~28 $ (!\tri_out~14_combout )) + + .dataa(\tri_out[8]~reg0_q ), + .datab(gnd), + .datac(gnd), + .datad(\tri_out~14_combout ), + .cin(\tri_out[7]~28 ), + .combout(\tri_out[8]~29_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out[8]~29 .lut_mask = 16'h5AA5; +defparam \tri_out[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y19_N27 +dffeas \tri_out[8]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[8]~29_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[8]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[8]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[8]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N6 +cycloneive_lcell_comb \tri_out~12 ( +// Equation(s): +// \tri_out~12_combout = (\tri_out[6]~reg0_q & (\tri_out[2]~reg0_q & (\tri_out[8]~reg0_q & \tri_out[7]~reg0_q ))) # (!\tri_out[6]~reg0_q & ((\tri_out[2]~reg0_q ) # ((\tri_out[8]~reg0_q ) # (\tri_out[7]~reg0_q )))) + + .dataa(\tri_out[6]~reg0_q ), + .datab(\tri_out[2]~reg0_q ), + .datac(\tri_out[8]~reg0_q ), + .datad(\tri_out[7]~reg0_q ), + .cin(gnd), + .combout(\tri_out~12_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~12 .lut_mask = 16'hD554; +defparam \tri_out~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N0 +cycloneive_lcell_comb \tri_out~11 ( +// Equation(s): +// \tri_out~11_combout = (\tri_out[5]~reg0_q & (((\tri_out[4]~reg0_q & \tri_out[3]~reg0_q )) # (!\tri_out[2]~reg0_q ))) # (!\tri_out[5]~reg0_q & (!\tri_out[2]~reg0_q & ((\tri_out[4]~reg0_q ) # (\tri_out[3]~reg0_q )))) + + .dataa(\tri_out[5]~reg0_q ), + .datab(\tri_out[4]~reg0_q ), + .datac(\tri_out[2]~reg0_q ), + .datad(\tri_out[3]~reg0_q ), + .cin(gnd), + .combout(\tri_out~11_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~11 .lut_mask = 16'h8F0E; +defparam \tri_out~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y19_N29 +dffeas updown( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out~14_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\updown~q ), + .prn(vcc)); +// synopsys translate_off +defparam updown.is_wysiwyg = "true"; +defparam updown.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N30 +cycloneive_lcell_comb \tri_out~13 ( +// Equation(s): +// \tri_out~13_combout = (\tri_out[1]~reg0_q & ((\updown~q ) # ((\tri_out[6]~reg0_q & \tri_out[0]~reg0_q )))) # (!\tri_out[1]~reg0_q & (\updown~q & ((\tri_out[6]~reg0_q ) # (\tri_out[0]~reg0_q )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\updown~q ), + .datac(\tri_out[6]~reg0_q ), + .datad(\tri_out[0]~reg0_q ), + .cin(gnd), + .combout(\tri_out~13_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~13 .lut_mask = 16'hECC8; +defparam \tri_out~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y19_N28 +cycloneive_lcell_comb \tri_out~14 ( +// Equation(s): +// \tri_out~14_combout = (\tri_out~12_combout & ((\updown~q ) # ((\tri_out~11_combout & \tri_out~13_combout )))) # (!\tri_out~12_combout & (\updown~q & ((\tri_out~11_combout ) # (\tri_out~13_combout )))) + + .dataa(\tri_out~12_combout ), + .datab(\tri_out~11_combout ), + .datac(\updown~q ), + .datad(\tri_out~13_combout ), + .cin(gnd), + .combout(\tri_out~14_combout ), + .cout()); +// synopsys translate_off +defparam \tri_out~14 .lut_mask = 16'hF8E0; +defparam \tri_out~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y19_N13 +dffeas \tri_out[1]~reg0 ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\tri_out[1]~15_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\tri_out[1]~reg0_q ), + .prn(vcc)); +// synopsys translate_off +defparam \tri_out[1]~reg0 .is_wysiwyg = "true"; +defparam \tri_out[1]~reg0 .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N15 +cycloneive_io_ibuf \Pword[0]~input ( + .i(Pword[0]), + .ibar(gnd), + .o(\Pword[0]~input_o )); +// synopsys translate_off +defparam \Pword[0]~input .bus_hold = "false"; +defparam \Pword[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N1 +cycloneive_io_ibuf \Fword[15]~input ( + .i(Fword[15]), + .ibar(gnd), + .o(\Fword[15]~input_o )); +// synopsys translate_off +defparam \Fword[15]~input .bus_hold = "false"; +defparam \Fword[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N15 +cycloneive_io_ibuf \Fword[14]~input ( + .i(Fword[14]), + .ibar(gnd), + .o(\Fword[14]~input_o )); +// synopsys translate_off +defparam \Fword[14]~input .bus_hold = "false"; +defparam \Fword[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y22_N1 +cycloneive_io_ibuf \Fword[13]~input ( + .i(Fword[13]), + .ibar(gnd), + .o(\Fword[13]~input_o )); +// synopsys translate_off +defparam \Fword[13]~input .bus_hold = "false"; +defparam \Fword[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N1 +cycloneive_io_ibuf \Fword[12]~input ( + .i(Fword[12]), + .ibar(gnd), + .o(\Fword[12]~input_o )); +// synopsys translate_off +defparam \Fword[12]~input .bus_hold = "false"; +defparam \Fword[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N8 +cycloneive_io_ibuf \Fword[11]~input ( + .i(Fword[11]), + .ibar(gnd), + .o(\Fword[11]~input_o )); +// synopsys translate_off +defparam \Fword[11]~input .bus_hold = "false"; +defparam \Fword[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N22 +cycloneive_io_ibuf \Fword[10]~input ( + .i(Fword[10]), + .ibar(gnd), + .o(\Fword[10]~input_o )); +// synopsys translate_off +defparam \Fword[10]~input .bus_hold = "false"; +defparam \Fword[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N8 +cycloneive_io_ibuf \Fword[9]~input ( + .i(Fword[9]), + .ibar(gnd), + .o(\Fword[9]~input_o )); +// synopsys translate_off +defparam \Fword[9]~input .bus_hold = "false"; +defparam \Fword[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N15 +cycloneive_io_ibuf \Fword[8]~input ( + .i(Fword[8]), + .ibar(gnd), + .o(\Fword[8]~input_o )); +// synopsys translate_off +defparam \Fword[8]~input .bus_hold = "false"; +defparam \Fword[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N22 +cycloneive_io_ibuf \Fword[7]~input ( + .i(Fword[7]), + .ibar(gnd), + .o(\Fword[7]~input_o )); +// synopsys translate_off +defparam \Fword[7]~input .bus_hold = "false"; +defparam \Fword[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X1_Y24_N8 +cycloneive_io_ibuf \Fword[6]~input ( + .i(Fword[6]), + .ibar(gnd), + .o(\Fword[6]~input_o )); +// synopsys translate_off +defparam \Fword[6]~input .bus_hold = "false"; +defparam \Fword[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N1 +cycloneive_io_ibuf \Fword[5]~input ( + .i(Fword[5]), + .ibar(gnd), + .o(\Fword[5]~input_o )); +// synopsys translate_off +defparam \Fword[5]~input .bus_hold = "false"; +defparam \Fword[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y24_N22 +cycloneive_io_ibuf \Fword[4]~input ( + .i(Fword[4]), + .ibar(gnd), + .o(\Fword[4]~input_o )); +// synopsys translate_off +defparam \Fword[4]~input .bus_hold = "false"; +defparam \Fword[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N1 +cycloneive_io_ibuf \Fword[3]~input ( + .i(Fword[3]), + .ibar(gnd), + .o(\Fword[3]~input_o )); +// synopsys translate_off +defparam \Fword[3]~input .bus_hold = "false"; +defparam \Fword[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N8 +cycloneive_io_ibuf \Fword[2]~input ( + .i(Fword[2]), + .ibar(gnd), + .o(\Fword[2]~input_o )); +// synopsys translate_off +defparam \Fword[2]~input .bus_hold = "false"; +defparam \Fword[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N8 +cycloneive_io_ibuf \Fword[1]~input ( + .i(Fword[1]), + .ibar(gnd), + .o(\Fword[1]~input_o )); +// synopsys translate_off +defparam \Fword[1]~input .bus_hold = "false"; +defparam \Fword[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N15 +cycloneive_io_ibuf \Fword[0]~input ( + .i(Fword[0]), + .ibar(gnd), + .o(\Fword[0]~input_o )); +// synopsys translate_off +defparam \Fword[0]~input .bus_hold = "false"; +defparam \Fword[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N6 +cycloneive_lcell_comb \F_acc[0]~26 ( +// Equation(s): +// \F_acc[0]~26_combout = (F_acc[0] & (\Fword[0]~input_o $ (VCC))) # (!F_acc[0] & (\Fword[0]~input_o & VCC)) +// \F_acc[0]~27 = CARRY((F_acc[0] & \Fword[0]~input_o )) + + .dataa(F_acc[0]), + .datab(\Fword[0]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\F_acc[0]~26_combout ), + .cout(\F_acc[0]~27 )); +// synopsys translate_off +defparam \F_acc[0]~26 .lut_mask = 16'h6688; +defparam \F_acc[0]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X6_Y20_N7 +dffeas \F_acc[0] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[0]~26_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[0]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[0] .is_wysiwyg = "true"; +defparam \F_acc[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N8 +cycloneive_lcell_comb \F_acc[1]~28 ( +// Equation(s): +// \F_acc[1]~28_combout = (\Fword[1]~input_o & ((F_acc[1] & (\F_acc[0]~27 & VCC)) # (!F_acc[1] & (!\F_acc[0]~27 )))) # (!\Fword[1]~input_o & ((F_acc[1] & (!\F_acc[0]~27 )) # (!F_acc[1] & ((\F_acc[0]~27 ) # (GND))))) +// \F_acc[1]~29 = CARRY((\Fword[1]~input_o & (!F_acc[1] & !\F_acc[0]~27 )) # (!\Fword[1]~input_o & ((!\F_acc[0]~27 ) # (!F_acc[1])))) + + .dataa(\Fword[1]~input_o ), + .datab(F_acc[1]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[0]~27 ), + .combout(\F_acc[1]~28_combout ), + .cout(\F_acc[1]~29 )); +// synopsys translate_off +defparam \F_acc[1]~28 .lut_mask = 16'h9617; +defparam \F_acc[1]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N9 +dffeas \F_acc[1] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[1]~28_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[1]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[1] .is_wysiwyg = "true"; +defparam \F_acc[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N10 +cycloneive_lcell_comb \F_acc[2]~30 ( +// Equation(s): +// \F_acc[2]~30_combout = ((F_acc[2] $ (\Fword[2]~input_o $ (!\F_acc[1]~29 )))) # (GND) +// \F_acc[2]~31 = CARRY((F_acc[2] & ((\Fword[2]~input_o ) # (!\F_acc[1]~29 ))) # (!F_acc[2] & (\Fword[2]~input_o & !\F_acc[1]~29 ))) + + .dataa(F_acc[2]), + .datab(\Fword[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[1]~29 ), + .combout(\F_acc[2]~30_combout ), + .cout(\F_acc[2]~31 )); +// synopsys translate_off +defparam \F_acc[2]~30 .lut_mask = 16'h698E; +defparam \F_acc[2]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N11 +dffeas \F_acc[2] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[2]~30_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[2]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[2] .is_wysiwyg = "true"; +defparam \F_acc[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N12 +cycloneive_lcell_comb \F_acc[3]~32 ( +// Equation(s): +// \F_acc[3]~32_combout = (F_acc[3] & ((\Fword[3]~input_o & (\F_acc[2]~31 & VCC)) # (!\Fword[3]~input_o & (!\F_acc[2]~31 )))) # (!F_acc[3] & ((\Fword[3]~input_o & (!\F_acc[2]~31 )) # (!\Fword[3]~input_o & ((\F_acc[2]~31 ) # (GND))))) +// \F_acc[3]~33 = CARRY((F_acc[3] & (!\Fword[3]~input_o & !\F_acc[2]~31 )) # (!F_acc[3] & ((!\F_acc[2]~31 ) # (!\Fword[3]~input_o )))) + + .dataa(F_acc[3]), + .datab(\Fword[3]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[2]~31 ), + .combout(\F_acc[3]~32_combout ), + .cout(\F_acc[3]~33 )); +// synopsys translate_off +defparam \F_acc[3]~32 .lut_mask = 16'h9617; +defparam \F_acc[3]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N13 +dffeas \F_acc[3] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[3]~32_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[3]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[3] .is_wysiwyg = "true"; +defparam \F_acc[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N14 +cycloneive_lcell_comb \F_acc[4]~34 ( +// Equation(s): +// \F_acc[4]~34_combout = ((\Fword[4]~input_o $ (F_acc[4] $ (!\F_acc[3]~33 )))) # (GND) +// \F_acc[4]~35 = CARRY((\Fword[4]~input_o & ((F_acc[4]) # (!\F_acc[3]~33 ))) # (!\Fword[4]~input_o & (F_acc[4] & !\F_acc[3]~33 ))) + + .dataa(\Fword[4]~input_o ), + .datab(F_acc[4]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[3]~33 ), + .combout(\F_acc[4]~34_combout ), + .cout(\F_acc[4]~35 )); +// synopsys translate_off +defparam \F_acc[4]~34 .lut_mask = 16'h698E; +defparam \F_acc[4]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N15 +dffeas \F_acc[4] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[4]~34_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[4]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[4] .is_wysiwyg = "true"; +defparam \F_acc[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N16 +cycloneive_lcell_comb \F_acc[5]~36 ( +// Equation(s): +// \F_acc[5]~36_combout = (\Fword[5]~input_o & ((F_acc[5] & (\F_acc[4]~35 & VCC)) # (!F_acc[5] & (!\F_acc[4]~35 )))) # (!\Fword[5]~input_o & ((F_acc[5] & (!\F_acc[4]~35 )) # (!F_acc[5] & ((\F_acc[4]~35 ) # (GND))))) +// \F_acc[5]~37 = CARRY((\Fword[5]~input_o & (!F_acc[5] & !\F_acc[4]~35 )) # (!\Fword[5]~input_o & ((!\F_acc[4]~35 ) # (!F_acc[5])))) + + .dataa(\Fword[5]~input_o ), + .datab(F_acc[5]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[4]~35 ), + .combout(\F_acc[5]~36_combout ), + .cout(\F_acc[5]~37 )); +// synopsys translate_off +defparam \F_acc[5]~36 .lut_mask = 16'h9617; +defparam \F_acc[5]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N17 +dffeas \F_acc[5] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[5]~36_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[5]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[5] .is_wysiwyg = "true"; +defparam \F_acc[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N18 +cycloneive_lcell_comb \F_acc[6]~38 ( +// Equation(s): +// \F_acc[6]~38_combout = ((\Fword[6]~input_o $ (F_acc[6] $ (!\F_acc[5]~37 )))) # (GND) +// \F_acc[6]~39 = CARRY((\Fword[6]~input_o & ((F_acc[6]) # (!\F_acc[5]~37 ))) # (!\Fword[6]~input_o & (F_acc[6] & !\F_acc[5]~37 ))) + + .dataa(\Fword[6]~input_o ), + .datab(F_acc[6]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[5]~37 ), + .combout(\F_acc[6]~38_combout ), + .cout(\F_acc[6]~39 )); +// synopsys translate_off +defparam \F_acc[6]~38 .lut_mask = 16'h698E; +defparam \F_acc[6]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N19 +dffeas \F_acc[6] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[6]~38_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[6]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[6] .is_wysiwyg = "true"; +defparam \F_acc[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N20 +cycloneive_lcell_comb \F_acc[7]~40 ( +// Equation(s): +// \F_acc[7]~40_combout = (\Fword[7]~input_o & ((F_acc[7] & (\F_acc[6]~39 & VCC)) # (!F_acc[7] & (!\F_acc[6]~39 )))) # (!\Fword[7]~input_o & ((F_acc[7] & (!\F_acc[6]~39 )) # (!F_acc[7] & ((\F_acc[6]~39 ) # (GND))))) +// \F_acc[7]~41 = CARRY((\Fword[7]~input_o & (!F_acc[7] & !\F_acc[6]~39 )) # (!\Fword[7]~input_o & ((!\F_acc[6]~39 ) # (!F_acc[7])))) + + .dataa(\Fword[7]~input_o ), + .datab(F_acc[7]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[6]~39 ), + .combout(\F_acc[7]~40_combout ), + .cout(\F_acc[7]~41 )); +// synopsys translate_off +defparam \F_acc[7]~40 .lut_mask = 16'h9617; +defparam \F_acc[7]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N21 +dffeas \F_acc[7] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[7]~40_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[7]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[7] .is_wysiwyg = "true"; +defparam \F_acc[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N22 +cycloneive_lcell_comb \F_acc[8]~42 ( +// Equation(s): +// \F_acc[8]~42_combout = ((F_acc[8] $ (\Fword[8]~input_o $ (!\F_acc[7]~41 )))) # (GND) +// \F_acc[8]~43 = CARRY((F_acc[8] & ((\Fword[8]~input_o ) # (!\F_acc[7]~41 ))) # (!F_acc[8] & (\Fword[8]~input_o & !\F_acc[7]~41 ))) + + .dataa(F_acc[8]), + .datab(\Fword[8]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[7]~41 ), + .combout(\F_acc[8]~42_combout ), + .cout(\F_acc[8]~43 )); +// synopsys translate_off +defparam \F_acc[8]~42 .lut_mask = 16'h698E; +defparam \F_acc[8]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N23 +dffeas \F_acc[8] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[8]~42_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[8]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[8] .is_wysiwyg = "true"; +defparam \F_acc[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N24 +cycloneive_lcell_comb \F_acc[9]~44 ( +// Equation(s): +// \F_acc[9]~44_combout = (\Fword[9]~input_o & ((F_acc[9] & (\F_acc[8]~43 & VCC)) # (!F_acc[9] & (!\F_acc[8]~43 )))) # (!\Fword[9]~input_o & ((F_acc[9] & (!\F_acc[8]~43 )) # (!F_acc[9] & ((\F_acc[8]~43 ) # (GND))))) +// \F_acc[9]~45 = CARRY((\Fword[9]~input_o & (!F_acc[9] & !\F_acc[8]~43 )) # (!\Fword[9]~input_o & ((!\F_acc[8]~43 ) # (!F_acc[9])))) + + .dataa(\Fword[9]~input_o ), + .datab(F_acc[9]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[8]~43 ), + .combout(\F_acc[9]~44_combout ), + .cout(\F_acc[9]~45 )); +// synopsys translate_off +defparam \F_acc[9]~44 .lut_mask = 16'h9617; +defparam \F_acc[9]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N25 +dffeas \F_acc[9] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[9]~44_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[9]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[9] .is_wysiwyg = "true"; +defparam \F_acc[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N26 +cycloneive_lcell_comb \F_acc[10]~46 ( +// Equation(s): +// \F_acc[10]~46_combout = ((F_acc[10] $ (\Fword[10]~input_o $ (!\F_acc[9]~45 )))) # (GND) +// \F_acc[10]~47 = CARRY((F_acc[10] & ((\Fword[10]~input_o ) # (!\F_acc[9]~45 ))) # (!F_acc[10] & (\Fword[10]~input_o & !\F_acc[9]~45 ))) + + .dataa(F_acc[10]), + .datab(\Fword[10]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[9]~45 ), + .combout(\F_acc[10]~46_combout ), + .cout(\F_acc[10]~47 )); +// synopsys translate_off +defparam \F_acc[10]~46 .lut_mask = 16'h698E; +defparam \F_acc[10]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N27 +dffeas \F_acc[10] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[10]~46_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[10]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[10] .is_wysiwyg = "true"; +defparam \F_acc[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N28 +cycloneive_lcell_comb \F_acc[11]~48 ( +// Equation(s): +// \F_acc[11]~48_combout = (\Fword[11]~input_o & ((F_acc[11] & (\F_acc[10]~47 & VCC)) # (!F_acc[11] & (!\F_acc[10]~47 )))) # (!\Fword[11]~input_o & ((F_acc[11] & (!\F_acc[10]~47 )) # (!F_acc[11] & ((\F_acc[10]~47 ) # (GND))))) +// \F_acc[11]~49 = CARRY((\Fword[11]~input_o & (!F_acc[11] & !\F_acc[10]~47 )) # (!\Fword[11]~input_o & ((!\F_acc[10]~47 ) # (!F_acc[11])))) + + .dataa(\Fword[11]~input_o ), + .datab(F_acc[11]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[10]~47 ), + .combout(\F_acc[11]~48_combout ), + .cout(\F_acc[11]~49 )); +// synopsys translate_off +defparam \F_acc[11]~48 .lut_mask = 16'h9617; +defparam \F_acc[11]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N29 +dffeas \F_acc[11] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[11]~48_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[11]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[11] .is_wysiwyg = "true"; +defparam \F_acc[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y20_N30 +cycloneive_lcell_comb \F_acc[12]~50 ( +// Equation(s): +// \F_acc[12]~50_combout = ((F_acc[12] $ (\Fword[12]~input_o $ (!\F_acc[11]~49 )))) # (GND) +// \F_acc[12]~51 = CARRY((F_acc[12] & ((\Fword[12]~input_o ) # (!\F_acc[11]~49 ))) # (!F_acc[12] & (\Fword[12]~input_o & !\F_acc[11]~49 ))) + + .dataa(F_acc[12]), + .datab(\Fword[12]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[11]~49 ), + .combout(\F_acc[12]~50_combout ), + .cout(\F_acc[12]~51 )); +// synopsys translate_off +defparam \F_acc[12]~50 .lut_mask = 16'h698E; +defparam \F_acc[12]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y20_N31 +dffeas \F_acc[12] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[12]~50_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[12]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[12] .is_wysiwyg = "true"; +defparam \F_acc[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N0 +cycloneive_lcell_comb \F_acc[13]~52 ( +// Equation(s): +// \F_acc[13]~52_combout = (\Fword[13]~input_o & ((F_acc[13] & (\F_acc[12]~51 & VCC)) # (!F_acc[13] & (!\F_acc[12]~51 )))) # (!\Fword[13]~input_o & ((F_acc[13] & (!\F_acc[12]~51 )) # (!F_acc[13] & ((\F_acc[12]~51 ) # (GND))))) +// \F_acc[13]~53 = CARRY((\Fword[13]~input_o & (!F_acc[13] & !\F_acc[12]~51 )) # (!\Fword[13]~input_o & ((!\F_acc[12]~51 ) # (!F_acc[13])))) + + .dataa(\Fword[13]~input_o ), + .datab(F_acc[13]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[12]~51 ), + .combout(\F_acc[13]~52_combout ), + .cout(\F_acc[13]~53 )); +// synopsys translate_off +defparam \F_acc[13]~52 .lut_mask = 16'h9617; +defparam \F_acc[13]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N1 +dffeas \F_acc[13] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[13]~52_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[13]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[13] .is_wysiwyg = "true"; +defparam \F_acc[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N2 +cycloneive_lcell_comb \F_acc[14]~54 ( +// Equation(s): +// \F_acc[14]~54_combout = ((\Fword[14]~input_o $ (F_acc[14] $ (!\F_acc[13]~53 )))) # (GND) +// \F_acc[14]~55 = CARRY((\Fword[14]~input_o & ((F_acc[14]) # (!\F_acc[13]~53 ))) # (!\Fword[14]~input_o & (F_acc[14] & !\F_acc[13]~53 ))) + + .dataa(\Fword[14]~input_o ), + .datab(F_acc[14]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[13]~53 ), + .combout(\F_acc[14]~54_combout ), + .cout(\F_acc[14]~55 )); +// synopsys translate_off +defparam \F_acc[14]~54 .lut_mask = 16'h698E; +defparam \F_acc[14]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N3 +dffeas \F_acc[14] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[14]~54_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[14]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[14] .is_wysiwyg = "true"; +defparam \F_acc[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N4 +cycloneive_lcell_comb \F_acc[15]~56 ( +// Equation(s): +// \F_acc[15]~56_combout = (\Fword[15]~input_o & ((F_acc[15] & (\F_acc[14]~55 & VCC)) # (!F_acc[15] & (!\F_acc[14]~55 )))) # (!\Fword[15]~input_o & ((F_acc[15] & (!\F_acc[14]~55 )) # (!F_acc[15] & ((\F_acc[14]~55 ) # (GND))))) +// \F_acc[15]~57 = CARRY((\Fword[15]~input_o & (!F_acc[15] & !\F_acc[14]~55 )) # (!\Fword[15]~input_o & ((!\F_acc[14]~55 ) # (!F_acc[15])))) + + .dataa(\Fword[15]~input_o ), + .datab(F_acc[15]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[14]~55 ), + .combout(\F_acc[15]~56_combout ), + .cout(\F_acc[15]~57 )); +// synopsys translate_off +defparam \F_acc[15]~56 .lut_mask = 16'h9617; +defparam \F_acc[15]~56 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N5 +dffeas \F_acc[15] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[15]~56_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[15]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[15] .is_wysiwyg = "true"; +defparam \F_acc[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N6 +cycloneive_lcell_comb \F_acc[16]~58 ( +// Equation(s): +// \F_acc[16]~58_combout = (F_acc[16] & (\F_acc[15]~57 $ (GND))) # (!F_acc[16] & (!\F_acc[15]~57 & VCC)) +// \F_acc[16]~59 = CARRY((F_acc[16] & !\F_acc[15]~57 )) + + .dataa(F_acc[16]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[15]~57 ), + .combout(\F_acc[16]~58_combout ), + .cout(\F_acc[16]~59 )); +// synopsys translate_off +defparam \F_acc[16]~58 .lut_mask = 16'hA50A; +defparam \F_acc[16]~58 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N7 +dffeas \F_acc[16] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[16]~58_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[16]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[16] .is_wysiwyg = "true"; +defparam \F_acc[16] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N10 +cycloneive_lcell_comb \rom_address[0]~0 ( +// Equation(s): +// \rom_address[0]~0_combout = (\Pword[0]~input_o & (F_acc[16] $ (VCC))) # (!\Pword[0]~input_o & (F_acc[16] & VCC)) +// \rom_address[0]~1 = CARRY((\Pword[0]~input_o & F_acc[16])) + + .dataa(\Pword[0]~input_o ), + .datab(F_acc[16]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\rom_address[0]~0_combout ), + .cout(\rom_address[0]~1 )); +// synopsys translate_off +defparam \rom_address[0]~0 .lut_mask = 16'h6688; +defparam \rom_address[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N8 +cycloneive_lcell_comb \F_acc[17]~60 ( +// Equation(s): +// \F_acc[17]~60_combout = (F_acc[17] & (!\F_acc[16]~59 )) # (!F_acc[17] & ((\F_acc[16]~59 ) # (GND))) +// \F_acc[17]~61 = CARRY((!\F_acc[16]~59 ) # (!F_acc[17])) + + .dataa(gnd), + .datab(F_acc[17]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[16]~59 ), + .combout(\F_acc[17]~60_combout ), + .cout(\F_acc[17]~61 )); +// synopsys translate_off +defparam \F_acc[17]~60 .lut_mask = 16'h3C3F; +defparam \F_acc[17]~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N9 +dffeas \F_acc[17] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[17]~60_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[17]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[17] .is_wysiwyg = "true"; +defparam \F_acc[17] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N22 +cycloneive_io_ibuf \Pword[1]~input ( + .i(Pword[1]), + .ibar(gnd), + .o(\Pword[1]~input_o )); +// synopsys translate_off +defparam \Pword[1]~input .bus_hold = "false"; +defparam \Pword[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N12 +cycloneive_lcell_comb \rom_address[1]~2 ( +// Equation(s): +// \rom_address[1]~2_combout = (F_acc[17] & ((\Pword[1]~input_o & (\rom_address[0]~1 & VCC)) # (!\Pword[1]~input_o & (!\rom_address[0]~1 )))) # (!F_acc[17] & ((\Pword[1]~input_o & (!\rom_address[0]~1 )) # (!\Pword[1]~input_o & ((\rom_address[0]~1 ) # +// (GND))))) +// \rom_address[1]~3 = CARRY((F_acc[17] & (!\Pword[1]~input_o & !\rom_address[0]~1 )) # (!F_acc[17] & ((!\rom_address[0]~1 ) # (!\Pword[1]~input_o )))) + + .dataa(F_acc[17]), + .datab(\Pword[1]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[0]~1 ), + .combout(\rom_address[1]~2_combout ), + .cout(\rom_address[1]~3 )); +// synopsys translate_off +defparam \rom_address[1]~2 .lut_mask = 16'h9617; +defparam \rom_address[1]~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N10 +cycloneive_lcell_comb \F_acc[18]~62 ( +// Equation(s): +// \F_acc[18]~62_combout = (F_acc[18] & (\F_acc[17]~61 $ (GND))) # (!F_acc[18] & (!\F_acc[17]~61 & VCC)) +// \F_acc[18]~63 = CARRY((F_acc[18] & !\F_acc[17]~61 )) + + .dataa(F_acc[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[17]~61 ), + .combout(\F_acc[18]~62_combout ), + .cout(\F_acc[18]~63 )); +// synopsys translate_off +defparam \F_acc[18]~62 .lut_mask = 16'hA50A; +defparam \F_acc[18]~62 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N11 +dffeas \F_acc[18] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[18]~62_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[18]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[18] .is_wysiwyg = "true"; +defparam \F_acc[18] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N1 +cycloneive_io_ibuf \Pword[2]~input ( + .i(Pword[2]), + .ibar(gnd), + .o(\Pword[2]~input_o )); +// synopsys translate_off +defparam \Pword[2]~input .bus_hold = "false"; +defparam \Pword[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N14 +cycloneive_lcell_comb \rom_address[2]~4 ( +// Equation(s): +// \rom_address[2]~4_combout = ((F_acc[18] $ (\Pword[2]~input_o $ (!\rom_address[1]~3 )))) # (GND) +// \rom_address[2]~5 = CARRY((F_acc[18] & ((\Pword[2]~input_o ) # (!\rom_address[1]~3 ))) # (!F_acc[18] & (\Pword[2]~input_o & !\rom_address[1]~3 ))) + + .dataa(F_acc[18]), + .datab(\Pword[2]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[1]~3 ), + .combout(\rom_address[2]~4_combout ), + .cout(\rom_address[2]~5 )); +// synopsys translate_off +defparam \rom_address[2]~4 .lut_mask = 16'h698E; +defparam \rom_address[2]~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N12 +cycloneive_lcell_comb \F_acc[19]~64 ( +// Equation(s): +// \F_acc[19]~64_combout = (F_acc[19] & (!\F_acc[18]~63 )) # (!F_acc[19] & ((\F_acc[18]~63 ) # (GND))) +// \F_acc[19]~65 = CARRY((!\F_acc[18]~63 ) # (!F_acc[19])) + + .dataa(F_acc[19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[18]~63 ), + .combout(\F_acc[19]~64_combout ), + .cout(\F_acc[19]~65 )); +// synopsys translate_off +defparam \F_acc[19]~64 .lut_mask = 16'h5A5F; +defparam \F_acc[19]~64 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N13 +dffeas \F_acc[19] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[19]~64_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[19]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[19] .is_wysiwyg = "true"; +defparam \F_acc[19] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N8 +cycloneive_io_ibuf \Pword[3]~input ( + .i(Pword[3]), + .ibar(gnd), + .o(\Pword[3]~input_o )); +// synopsys translate_off +defparam \Pword[3]~input .bus_hold = "false"; +defparam \Pword[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N16 +cycloneive_lcell_comb \rom_address[3]~6 ( +// Equation(s): +// \rom_address[3]~6_combout = (F_acc[19] & ((\Pword[3]~input_o & (\rom_address[2]~5 & VCC)) # (!\Pword[3]~input_o & (!\rom_address[2]~5 )))) # (!F_acc[19] & ((\Pword[3]~input_o & (!\rom_address[2]~5 )) # (!\Pword[3]~input_o & ((\rom_address[2]~5 ) # +// (GND))))) +// \rom_address[3]~7 = CARRY((F_acc[19] & (!\Pword[3]~input_o & !\rom_address[2]~5 )) # (!F_acc[19] & ((!\rom_address[2]~5 ) # (!\Pword[3]~input_o )))) + + .dataa(F_acc[19]), + .datab(\Pword[3]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[2]~5 ), + .combout(\rom_address[3]~6_combout ), + .cout(\rom_address[3]~7 )); +// synopsys translate_off +defparam \rom_address[3]~6 .lut_mask = 16'h9617; +defparam \rom_address[3]~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N14 +cycloneive_lcell_comb \F_acc[20]~66 ( +// Equation(s): +// \F_acc[20]~66_combout = (F_acc[20] & (\F_acc[19]~65 $ (GND))) # (!F_acc[20] & (!\F_acc[19]~65 & VCC)) +// \F_acc[20]~67 = CARRY((F_acc[20] & !\F_acc[19]~65 )) + + .dataa(gnd), + .datab(F_acc[20]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[19]~65 ), + .combout(\F_acc[20]~66_combout ), + .cout(\F_acc[20]~67 )); +// synopsys translate_off +defparam \F_acc[20]~66 .lut_mask = 16'hC30C; +defparam \F_acc[20]~66 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N15 +dffeas \F_acc[20] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[20]~66_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[20]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[20] .is_wysiwyg = "true"; +defparam \F_acc[20] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N22 +cycloneive_io_ibuf \Pword[4]~input ( + .i(Pword[4]), + .ibar(gnd), + .o(\Pword[4]~input_o )); +// synopsys translate_off +defparam \Pword[4]~input .bus_hold = "false"; +defparam \Pword[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N18 +cycloneive_lcell_comb \rom_address[4]~8 ( +// Equation(s): +// \rom_address[4]~8_combout = ((F_acc[20] $ (\Pword[4]~input_o $ (!\rom_address[3]~7 )))) # (GND) +// \rom_address[4]~9 = CARRY((F_acc[20] & ((\Pword[4]~input_o ) # (!\rom_address[3]~7 ))) # (!F_acc[20] & (\Pword[4]~input_o & !\rom_address[3]~7 ))) + + .dataa(F_acc[20]), + .datab(\Pword[4]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[3]~7 ), + .combout(\rom_address[4]~8_combout ), + .cout(\rom_address[4]~9 )); +// synopsys translate_off +defparam \rom_address[4]~8 .lut_mask = 16'h698E; +defparam \rom_address[4]~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N16 +cycloneive_lcell_comb \F_acc[21]~68 ( +// Equation(s): +// \F_acc[21]~68_combout = (F_acc[21] & (!\F_acc[20]~67 )) # (!F_acc[21] & ((\F_acc[20]~67 ) # (GND))) +// \F_acc[21]~69 = CARRY((!\F_acc[20]~67 ) # (!F_acc[21])) + + .dataa(gnd), + .datab(F_acc[21]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[20]~67 ), + .combout(\F_acc[21]~68_combout ), + .cout(\F_acc[21]~69 )); +// synopsys translate_off +defparam \F_acc[21]~68 .lut_mask = 16'h3C3F; +defparam \F_acc[21]~68 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N17 +dffeas \F_acc[21] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[21]~68_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[21]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[21] .is_wysiwyg = "true"; +defparam \F_acc[21] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N15 +cycloneive_io_ibuf \Pword[5]~input ( + .i(Pword[5]), + .ibar(gnd), + .o(\Pword[5]~input_o )); +// synopsys translate_off +defparam \Pword[5]~input .bus_hold = "false"; +defparam \Pword[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N20 +cycloneive_lcell_comb \rom_address[5]~10 ( +// Equation(s): +// \rom_address[5]~10_combout = (F_acc[21] & ((\Pword[5]~input_o & (\rom_address[4]~9 & VCC)) # (!\Pword[5]~input_o & (!\rom_address[4]~9 )))) # (!F_acc[21] & ((\Pword[5]~input_o & (!\rom_address[4]~9 )) # (!\Pword[5]~input_o & ((\rom_address[4]~9 ) # +// (GND))))) +// \rom_address[5]~11 = CARRY((F_acc[21] & (!\Pword[5]~input_o & !\rom_address[4]~9 )) # (!F_acc[21] & ((!\rom_address[4]~9 ) # (!\Pword[5]~input_o )))) + + .dataa(F_acc[21]), + .datab(\Pword[5]~input_o ), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[4]~9 ), + .combout(\rom_address[5]~10_combout ), + .cout(\rom_address[5]~11 )); +// synopsys translate_off +defparam \rom_address[5]~10 .lut_mask = 16'h9617; +defparam \rom_address[5]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y18_N22 +cycloneive_io_ibuf \Pword[6]~input ( + .i(Pword[6]), + .ibar(gnd), + .o(\Pword[6]~input_o )); +// synopsys translate_off +defparam \Pword[6]~input .bus_hold = "false"; +defparam \Pword[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N18 +cycloneive_lcell_comb \F_acc[22]~70 ( +// Equation(s): +// \F_acc[22]~70_combout = (F_acc[22] & (\F_acc[21]~69 $ (GND))) # (!F_acc[22] & (!\F_acc[21]~69 & VCC)) +// \F_acc[22]~71 = CARRY((F_acc[22] & !\F_acc[21]~69 )) + + .dataa(gnd), + .datab(F_acc[22]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[21]~69 ), + .combout(\F_acc[22]~70_combout ), + .cout(\F_acc[22]~71 )); +// synopsys translate_off +defparam \F_acc[22]~70 .lut_mask = 16'hC30C; +defparam \F_acc[22]~70 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N19 +dffeas \F_acc[22] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[22]~70_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[22]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[22] .is_wysiwyg = "true"; +defparam \F_acc[22] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N22 +cycloneive_lcell_comb \rom_address[6]~12 ( +// Equation(s): +// \rom_address[6]~12_combout = ((\Pword[6]~input_o $ (F_acc[22] $ (!\rom_address[5]~11 )))) # (GND) +// \rom_address[6]~13 = CARRY((\Pword[6]~input_o & ((F_acc[22]) # (!\rom_address[5]~11 ))) # (!\Pword[6]~input_o & (F_acc[22] & !\rom_address[5]~11 ))) + + .dataa(\Pword[6]~input_o ), + .datab(F_acc[22]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[5]~11 ), + .combout(\rom_address[6]~12_combout ), + .cout(\rom_address[6]~13 )); +// synopsys translate_off +defparam \rom_address[6]~12 .lut_mask = 16'h698E; +defparam \rom_address[6]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y22_N15 +cycloneive_io_ibuf \Pword[7]~input ( + .i(Pword[7]), + .ibar(gnd), + .o(\Pword[7]~input_o )); +// synopsys translate_off +defparam \Pword[7]~input .bus_hold = "false"; +defparam \Pword[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N20 +cycloneive_lcell_comb \F_acc[23]~72 ( +// Equation(s): +// \F_acc[23]~72_combout = (F_acc[23] & (!\F_acc[22]~71 )) # (!F_acc[23] & ((\F_acc[22]~71 ) # (GND))) +// \F_acc[23]~73 = CARRY((!\F_acc[22]~71 ) # (!F_acc[23])) + + .dataa(gnd), + .datab(F_acc[23]), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[22]~71 ), + .combout(\F_acc[23]~72_combout ), + .cout(\F_acc[23]~73 )); +// synopsys translate_off +defparam \F_acc[23]~72 .lut_mask = 16'h3C3F; +defparam \F_acc[23]~72 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N21 +dffeas \F_acc[23] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[23]~72_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[23]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[23] .is_wysiwyg = "true"; +defparam \F_acc[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N24 +cycloneive_lcell_comb \rom_address[7]~14 ( +// Equation(s): +// \rom_address[7]~14_combout = (\Pword[7]~input_o & ((F_acc[23] & (\rom_address[6]~13 & VCC)) # (!F_acc[23] & (!\rom_address[6]~13 )))) # (!\Pword[7]~input_o & ((F_acc[23] & (!\rom_address[6]~13 )) # (!F_acc[23] & ((\rom_address[6]~13 ) # (GND))))) +// \rom_address[7]~15 = CARRY((\Pword[7]~input_o & (!F_acc[23] & !\rom_address[6]~13 )) # (!\Pword[7]~input_o & ((!\rom_address[6]~13 ) # (!F_acc[23])))) + + .dataa(\Pword[7]~input_o ), + .datab(F_acc[23]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[6]~13 ), + .combout(\rom_address[7]~14_combout ), + .cout(\rom_address[7]~15 )); +// synopsys translate_off +defparam \rom_address[7]~14 .lut_mask = 16'h9617; +defparam \rom_address[7]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y19_N15 +cycloneive_io_ibuf \Pword[8]~input ( + .i(Pword[8]), + .ibar(gnd), + .o(\Pword[8]~input_o )); +// synopsys translate_off +defparam \Pword[8]~input .bus_hold = "false"; +defparam \Pword[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N22 +cycloneive_lcell_comb \F_acc[24]~74 ( +// Equation(s): +// \F_acc[24]~74_combout = (F_acc[24] & (\F_acc[23]~73 $ (GND))) # (!F_acc[24] & (!\F_acc[23]~73 & VCC)) +// \F_acc[24]~75 = CARRY((F_acc[24] & !\F_acc[23]~73 )) + + .dataa(F_acc[24]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\F_acc[23]~73 ), + .combout(\F_acc[24]~74_combout ), + .cout(\F_acc[24]~75 )); +// synopsys translate_off +defparam \F_acc[24]~74 .lut_mask = 16'hA50A; +defparam \F_acc[24]~74 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N23 +dffeas \F_acc[24] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[24]~74_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[24]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[24] .is_wysiwyg = "true"; +defparam \F_acc[24] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N26 +cycloneive_lcell_comb \rom_address[8]~16 ( +// Equation(s): +// \rom_address[8]~16_combout = ((\Pword[8]~input_o $ (F_acc[24] $ (!\rom_address[7]~15 )))) # (GND) +// \rom_address[8]~17 = CARRY((\Pword[8]~input_o & ((F_acc[24]) # (!\rom_address[7]~15 ))) # (!\Pword[8]~input_o & (F_acc[24] & !\rom_address[7]~15 ))) + + .dataa(\Pword[8]~input_o ), + .datab(F_acc[24]), + .datac(gnd), + .datad(vcc), + .cin(\rom_address[7]~15 ), + .combout(\rom_address[8]~16_combout ), + .cout(\rom_address[8]~17 )); +// synopsys translate_off +defparam \rom_address[8]~16 .lut_mask = 16'h698E; +defparam \rom_address[8]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y24_N8 +cycloneive_io_ibuf \Pword[9]~input ( + .i(Pword[9]), + .ibar(gnd), + .o(\Pword[9]~input_o )); +// synopsys translate_off +defparam \Pword[9]~input .bus_hold = "false"; +defparam \Pword[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y19_N24 +cycloneive_lcell_comb \F_acc[25]~76 ( +// Equation(s): +// \F_acc[25]~76_combout = \F_acc[24]~75 $ (F_acc[25]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(F_acc[25]), + .cin(\F_acc[24]~75 ), + .combout(\F_acc[25]~76_combout ), + .cout()); +// synopsys translate_off +defparam \F_acc[25]~76 .lut_mask = 16'h0FF0; +defparam \F_acc[25]~76 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y19_N25 +dffeas \F_acc[25] ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\F_acc[25]~76_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(F_acc[25]), + .prn(vcc)); +// synopsys translate_off +defparam \F_acc[25] .is_wysiwyg = "true"; +defparam \F_acc[25] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y19_N28 +cycloneive_lcell_comb \rom_address[9]~18 ( +// Equation(s): +// \rom_address[9]~18_combout = \Pword[9]~input_o $ (\rom_address[8]~17 $ (F_acc[25])) + + .dataa(gnd), + .datab(\Pword[9]~input_o ), + .datac(gnd), + .datad(F_acc[25]), + .cin(\rom_address[8]~17 ), + .combout(\rom_address[9]~18_combout ), + .cout()); +// synopsys translate_off +defparam \rom_address[9]~18 .lut_mask = 16'hC33C; +defparam \rom_address[9]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: M9K_X15_Y12_N0 +cycloneive_ram_block \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 ( + .portawe(vcc), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\clk_200m~inputclkctrl_outclk ), + .clk1(gnd), + .ena0(vcc), + .ena1(vcc), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain(9'b000000000), + .portaaddr({\rom_address[9]~18_combout ,\rom_address[8]~16_combout ,\rom_address[7]~14_combout ,\rom_address[6]~12_combout ,\rom_address[5]~10_combout ,\rom_address[4]~8_combout ,\rom_address[3]~6_combout ,\rom_address[2]~4_combout ,\rom_address[1]~2_combout , +\rom_address[0]~0_combout }), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr(10'b0000000000), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(\spwm_sin|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ), + .portbdataout()); +// synopsys translate_off +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .init_file = "sin9bit_1024.mif"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .init_file_layout = "port_a"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .logical_ram_name = "spwm_sin:spwm_sin|altsyncram:altsyncram_component|altsyncram_sl91:auto_generated|ALTSYNCRAM"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .operation_mode = "rom"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_clear = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_address_width = 10; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clear = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_out_clock = "clock0"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_data_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_address = 0; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_first_bit_number = 0; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_last_address = 1023; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 1024; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_logical_ram_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_a_write_enable_clock = "none"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_b_address_width = 10; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .port_b_data_width = 9; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .ram_block_type = "M9K"; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init4 = 1024'h7F3F1F6F97C3D9EAF3793C1DEED763A9D2E773395C6E27037DBADC6D365AED66AB4DA4D067B3598CA64B218CC561B0980BF5F2F176B95C2DD6AB4592C560AE56AAD54A953A994AA3512813E9E4E26D34984BA592893492411E8E46A2D148943A190A8441205007F3E9F0F67A3C1DCEC753A1C8E270379B8DA6B351A4D0673319; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init3 = 2048'h0C66230980BE5E2E970B65A2C15CAC552A14CA4512813C9C4D2612C94492411C8C45229108642209007E3E1E8F0783B1D0E470371B8D86A34198CC6431180C05E2E168B4582B158A852291409C4E2612894482411888442110880401F0F8783C1D0E870381B0D86834190C86030180B85C2E160B0542A150A85028140984C26130904824120884422110884020100804020100803C1E0F0783C1E0F0783C1E0F0783C1E0F0783C1E0F0783C20100804020100804022110884422120904824130984C26140A0502A150A8542C160B85C2E180C06032190D068361B0E0703A1D0F0783E1F100804221110884624120944A261389C5029148A8562B160B45A2E178; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init2 = 2048'hC06031190CC66341A8D86E371C0E4743B1E0F07A3E1F9008242219108A452311C90492512C984D2713CA0512914CA8552B15CB05A2D970BA5E2F980C26231990CC67341A4D46B369B8DE70389C8E8753B1DCF07A3D9F0FA7F40205048442A190E894522D1A8E47A4124934A2592E984D26D389E4FA8144A352A994EA9552AD5AAE582C564B45AADD70B95DAF17CBF6030986C56332192CA663359ED06934DAAD66BB65B4DC6EB7DC0E271B95CCE774BA9D8ED77BC1E4F37ABD9F0F97DBF1FCFF8040A070583422130B8643A1F11894522B178C466371C8F47E4322924964F2894CAE592E97CC665349ACDA71399DCF27D3FA050A8745A351E934AA65369D50A8; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init1 = 2048'hD4EA955ABD62B35BAE57ABF60B158EC966B3DA2D56BB65BADF70B8DCEE975BBDE2F37ABE5F6FD7FC0E0B0784C361F1189C56331B8EC7E432393CA6572D97CC66B379CCEE7B3FA0D0E8B47A4D369F51A9D56AF59ADD76BF61B1D96CF69B5DB6DF71B9DCEEB77BCDEEFB7FC0E0F0B85C3E27178DC7E3F2393CAE5F2F99CDE773B9FD0E8F47A5D3E9F53ABD5EB75FAFD8ECF67B5DAEDF73B9DDEEF7BBDDFEFF83C1E1F0F8BC5E3F1F93C9E5F2F9BCDE6F3F9FCFE8F47A7D3E9F4FABD5EAF5FAFD7EBF67B3D9ECF6FB7DBEDF6FBBDDEEF77BBDDEEF77BFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDFEFF7FBFDDEEF77BBDDEEF77BBDBEDF6FB7DBECF67B3D9EBF; +defparam \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 .mem_init0 = 2048'h5FAFD7EAF57ABD3E9F4FA7D1E8F3F9FCFE6F379BCBE5F2793C7E3F178BC3E1F0783BFDFEF77BBBDDEE773B7DAED767B3D8EBF5FADD5EAF53A7D3E9747A3D0E7F3B9DCDE672F97CAE4F238FC7E371789C3E170B83C0DFEFB7BBCDDEEB73B9DC6DF6DB5DA6CF65B1D86BF5DADD66AF55A9D469F4DA4D1E8B43A0CFE7B3B9CCDE6B3197CB6572993C8E431F8EC6E331589C461F0D84C1E0B037FBF5F6F97ABCDE2EF75BA5CEE370B7DBAD96BB55A2CF66B258EC560AFD7AB95BACD62AF55AA54EA350A7536994AA4D1E8D45A1D0A813F9F4F277399C4DA6B34994C65F2E964AE532893C96492290C7E3D1C8DC6631178AC52251187C3A190B84C220D0581C0A00FF; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N20 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][11]~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][11]~0_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [7] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [4]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [6]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [5])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][11]~0 .lut_mask = 16'hCCC8; +defparam \modulation|Mult0|mult_core|romout[1][11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][10] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][10]~combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [6] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [4] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [7])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [6] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [7]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][10]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][10] .lut_mask = 16'hC1C8; +defparam \modulation|Mult0|mult_core|romout[1][10] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][9] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][9]~combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [4] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (\spwm_sin|altsyncram_component|auto_generated|q_a [6] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [5])) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [6]) # (\spwm_sin|altsyncram_component|auto_generated|q_a [7])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][9]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][9] .lut_mask = 16'h0AD4; +defparam \modulation|Mult0|mult_core|romout[1][9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][8]~1 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][8]~1_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (\spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (((!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [6]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [4] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [6])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][8]~1 .lut_mask = 16'hA856; +defparam \modulation|Mult0|mult_core|romout[1][8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N30 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][11]~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][11]~2_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][11]~2_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][11]~2 .lut_mask = 16'hCCC8; +defparam \modulation|Mult0|mult_core|romout[0][11]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N4 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][7] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][7]~combout = \spwm_sin|altsyncram_component|auto_generated|q_a [6] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [5]) # ((!\spwm_sin|altsyncram_component|auto_generated|q_a [7] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [4])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][7]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][7] .lut_mask = 16'h45BA; +defparam \modulation|Mult0|mult_core|romout[1][7] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][6] ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][6]~combout = \spwm_sin|altsyncram_component|auto_generated|q_a [5] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [4] & !\spwm_sin|altsyncram_component|auto_generated|q_a [7]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(gnd), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][6]~combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][6] .lut_mask = 16'hF50A; +defparam \modulation|Mult0|mult_core|romout[1][6] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N28 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][10]~3 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][10]~3_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [2] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & +// \spwm_sin|altsyncram_component|auto_generated|q_a [0])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [2] & (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [0]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][10]~3_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][10]~3 .lut_mask = 16'hA2A4; +defparam \modulation|Mult0|mult_core|romout[0][10]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N26 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][9]~5 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][9]~5_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [1] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [0]))) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [1] & (\spwm_sin|altsyncram_component|auto_generated|q_a [2] & !\spwm_sin|altsyncram_component|auto_generated|q_a [0])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][9]~5_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][9]~5 .lut_mask = 16'h380E; +defparam \modulation|Mult0|mult_core|romout[0][9]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[1][5]~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[1][5]~4_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (\spwm_sin|altsyncram_component|auto_generated|q_a [7]) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datab(gnd), + .datac(gnd), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [7]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[1][5]~4_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[1][5]~4 .lut_mask = 16'h55AA; +defparam \modulation|Mult0|mult_core|romout[1][5]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][8]~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][8]~6_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (\spwm_sin|altsyncram_component|auto_generated|q_a [0] $ (((!\spwm_sin|altsyncram_component|auto_generated|q_a [2] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [1]))))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [3] & (!\spwm_sin|altsyncram_component|auto_generated|q_a [0] & ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [1])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][8]~6_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][8]~6 .lut_mask = 16'hC836; +defparam \modulation|Mult0|mult_core|romout[0][8]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N2 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][7]~7 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][7]~7_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [2] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [0] & +// !\spwm_sin|altsyncram_component|auto_generated|q_a [3])))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][7]~7 .lut_mask = 16'h0DF2; +defparam \modulation|Mult0|mult_core|romout[0][7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \modulation|Mult0|mult_core|romout[0][6]~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|romout[0][6]~8_combout = \spwm_sin|altsyncram_component|auto_generated|q_a [1] $ (((\spwm_sin|altsyncram_component|auto_generated|q_a [0] & !\spwm_sin|altsyncram_component|auto_generated|q_a [3]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .datac(gnd), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|romout[0][6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|romout[0][6]~8 .lut_mask = 16'hDD22; +defparam \modulation|Mult0|mult_core|romout[0][6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N6 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout = (\modulation|Mult0|mult_core|romout[0][6]~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [4] $ (VCC))) # (!\modulation|Mult0|mult_core|romout[0][6]~8_combout & +// (\spwm_sin|altsyncram_component|auto_generated|q_a [4] & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 = CARRY((\modulation|Mult0|mult_core|romout[0][6]~8_combout & \spwm_sin|altsyncram_component|auto_generated|q_a [4])) + + .dataa(\modulation|Mult0|mult_core|romout[0][6]~8_combout ), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [4]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\modulation|Mult0|mult_core|romout[0][7]~7_combout & +// (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 & VCC)) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )))) # +// (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((\modulation|Mult0|mult_core|romout[0][7]~7_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 )) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & +// ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [5] & (!\modulation|Mult0|mult_core|romout[0][7]~7_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 +// )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [5] & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ) # (!\modulation|Mult0|mult_core|romout[0][7]~7_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [5]), + .datab(\modulation|Mult0|mult_core|romout[0][7]~7_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~1 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout = ((\spwm_sin|altsyncram_component|auto_generated|q_a [6] $ (\modulation|Mult0|mult_core|romout[0][8]~6_combout $ +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 )))) # (GND) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [6] & ((\modulation|Mult0|mult_core|romout[0][8]~6_combout ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [6] & (\modulation|Mult0|mult_core|romout[0][8]~6_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 +// ))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [6]), + .datab(\modulation|Mult0|mult_core|romout[0][8]~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~3 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N12 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout = (\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((\modulation|Mult0|mult_core|romout[1][5]~4_combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 +// & VCC)) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )))) # (!\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((\modulation|Mult0|mult_core|romout[1][5]~4_combout & +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 = CARRY((\modulation|Mult0|mult_core|romout[0][9]~5_combout & (!\modulation|Mult0|mult_core|romout[1][5]~4_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 )) +// # (!\modulation|Mult0|mult_core|romout[0][9]~5_combout & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ) # (!\modulation|Mult0|mult_core|romout[1][5]~4_combout )))) + + .dataa(\modulation|Mult0|mult_core|romout[0][9]~5_combout ), + .datab(\modulation|Mult0|mult_core|romout[1][5]~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~5 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N14 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout = ((\modulation|Mult0|mult_core|romout[1][6]~combout $ (\modulation|Mult0|mult_core|romout[0][10]~3_combout $ (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 +// )))) # (GND) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 = CARRY((\modulation|Mult0|mult_core|romout[1][6]~combout & ((\modulation|Mult0|mult_core|romout[0][10]~3_combout ) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 +// ))) # (!\modulation|Mult0|mult_core|romout[1][6]~combout & (\modulation|Mult0|mult_core|romout[0][10]~3_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ))) + + .dataa(\modulation|Mult0|mult_core|romout[1][6]~combout ), + .datab(\modulation|Mult0|mult_core|romout[0][10]~3_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~7 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N16 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout = (\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((\modulation|Mult0|mult_core|romout[1][7]~combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 +// & VCC)) # (!\modulation|Mult0|mult_core|romout[1][7]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )))) # (!\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((\modulation|Mult0|mult_core|romout[1][7]~combout & +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )) # (!\modulation|Mult0|mult_core|romout[1][7]~combout & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 = CARRY((\modulation|Mult0|mult_core|romout[0][11]~2_combout & (!\modulation|Mult0|mult_core|romout[1][7]~combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 )) +// # (!\modulation|Mult0|mult_core|romout[0][11]~2_combout & ((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ) # (!\modulation|Mult0|mult_core|romout[1][7]~combout )))) + + .dataa(\modulation|Mult0|mult_core|romout[0][11]~2_combout ), + .datab(\modulation|Mult0|mult_core|romout[1][7]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~9 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N18 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout = (\modulation|Mult0|mult_core|romout[1][8]~1_combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 $ (GND))) # +// (!\modulation|Mult0|mult_core|romout[1][8]~1_combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 = CARRY((\modulation|Mult0|mult_core|romout[1][8]~1_combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 )) + + .dataa(\modulation|Mult0|mult_core|romout[1][8]~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~11 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 .lut_mask = 16'hA50A; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N20 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout = (\modulation|Mult0|mult_core|romout[1][9]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 )) # (!\modulation|Mult0|mult_core|romout[1][9]~combout +// & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ) # (GND))) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 = CARRY((!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ) # (!\modulation|Mult0|mult_core|romout[1][9]~combout )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|romout[1][9]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~13 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 .lut_mask = 16'h3C3F; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N22 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout = (\modulation|Mult0|mult_core|romout[1][10]~combout & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 $ (GND))) # +// (!\modulation|Mult0|mult_core|romout[1][10]~combout & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 & VCC)) +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 = CARRY((\modulation|Mult0|mult_core|romout[1][10]~combout & !\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|romout[1][10]~combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~15 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ), + .cout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 .lut_mask = 16'hC30C; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N24 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout = \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 $ (\modulation|Mult0|mult_core|romout[1][11]~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\modulation|Mult0|mult_core|romout[1][11]~0_combout ), + .cin(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~17 ), + .combout(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 .lut_mask = 16'h0FF0; +defparam \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N0 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [8] $ (VCC))) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & VCC)) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout & \spwm_sin|altsyncram_component|auto_generated|q_a [8])) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8_combout ), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .lut_mask = 16'h6688; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N2 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # (GND))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 = CARRY((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout )) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10_combout ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .lut_mask = 16'h5A5F; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N4 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout = (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 $ +// (GND))) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 & VCC)) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout & !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 )) + + .dataa(gnd), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~3 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .lut_mask = 16'hC30C; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N6 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 & VCC)) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )))) +// # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N8 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout = ((\spwm_sin|altsyncram_component|auto_generated|q_a [8] $ (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout $ +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 )))) # (GND) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ))) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~7 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .lut_mask = 16'h698E; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N10 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 & VCC)) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )))) +// # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # (GND))))) +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 = CARRY((\spwm_sin|altsyncram_component|auto_generated|q_a [8] & (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout & +// !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 )) # (!\spwm_sin|altsyncram_component|auto_generated|q_a [8] & ((!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ) # +// (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout )))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [8]), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ), + .cout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .lut_mask = 16'h9617; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X13_Y12_N12 +cycloneive_lcell_comb \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 ( +// Equation(s): +// \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout = !\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~11 ), + .combout(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .lut_mask = 16'h0F0F; +defparam \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \modulation|LessThan0~0 ( +// Equation(s): +// \modulation|LessThan0~0_combout = (\spwm_sin|altsyncram_component|auto_generated|q_a [0]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [1]) # ((\spwm_sin|altsyncram_component|auto_generated|q_a [2]) # +// (\spwm_sin|altsyncram_component|auto_generated|q_a [3]))) + + .dataa(\spwm_sin|altsyncram_component|auto_generated|q_a [0]), + .datab(\spwm_sin|altsyncram_component|auto_generated|q_a [1]), + .datac(\spwm_sin|altsyncram_component|auto_generated|q_a [2]), + .datad(\spwm_sin|altsyncram_component|auto_generated|q_a [3]), + .cin(gnd), + .combout(\modulation|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~0 .lut_mask = 16'hFFFE; +defparam \modulation|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \modulation|LessThan0~1 ( +// Equation(s): +// \modulation|LessThan0~1_combout = (\modulation|LessThan0~0_combout ) # ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ) # (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout )) + + .dataa(gnd), + .datab(\modulation|LessThan0~0_combout ), + .datac(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0_combout ), + .datad(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2_combout ), + .cin(gnd), + .combout(\modulation|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~1 .lut_mask = 16'hFFFC; +defparam \modulation|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \modulation|LessThan0~3 ( +// Equation(s): +// \modulation|LessThan0~3_cout = CARRY(\modulation|LessThan0~1_combout ) + + .dataa(gnd), + .datab(\modulation|LessThan0~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\modulation|LessThan0~3_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~3 .lut_mask = 16'h00CC; +defparam \modulation|LessThan0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \modulation|LessThan0~5 ( +// Equation(s): +// \modulation|LessThan0~5_cout = CARRY((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout & (\tri_out[0]~reg0_q & !\modulation|LessThan0~3_cout )) # (!\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout & +// ((\tri_out[0]~reg0_q ) # (!\modulation|LessThan0~3_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4_combout ), + .datab(\tri_out[0]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~3_cout ), + .combout(), + .cout(\modulation|LessThan0~5_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~5 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \modulation|LessThan0~7 ( +// Equation(s): +// \modulation|LessThan0~7_cout = CARRY((\tri_out[1]~reg0_q & (\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout & !\modulation|LessThan0~5_cout )) # (!\tri_out[1]~reg0_q & +// ((\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ) # (!\modulation|LessThan0~5_cout )))) + + .dataa(\tri_out[1]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~5_cout ), + .combout(), + .cout(\modulation|LessThan0~7_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~7 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \modulation|LessThan0~9 ( +// Equation(s): +// \modulation|LessThan0~9_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout & (\tri_out[2]~reg0_q & !\modulation|LessThan0~7_cout )) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout & ((\tri_out[2]~reg0_q ) # (!\modulation|LessThan0~7_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0_combout ), + .datab(\tri_out[2]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~7_cout ), + .combout(), + .cout(\modulation|LessThan0~9_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~9 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \modulation|LessThan0~11 ( +// Equation(s): +// \modulation|LessThan0~11_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout & ((!\modulation|LessThan0~9_cout ) # (!\tri_out[3]~reg0_q ))) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout & (!\tri_out[3]~reg0_q & !\modulation|LessThan0~9_cout ))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2_combout ), + .datab(\tri_out[3]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~9_cout ), + .combout(), + .cout(\modulation|LessThan0~11_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~11 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \modulation|LessThan0~13 ( +// Equation(s): +// \modulation|LessThan0~13_cout = CARRY((\tri_out[4]~reg0_q & ((!\modulation|LessThan0~11_cout ) # (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ))) # (!\tri_out[4]~reg0_q & +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout & !\modulation|LessThan0~11_cout ))) + + .dataa(\tri_out[4]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~11_cout ), + .combout(), + .cout(\modulation|LessThan0~13_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~13 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \modulation|LessThan0~15 ( +// Equation(s): +// \modulation|LessThan0~15_cout = CARRY((\tri_out[5]~reg0_q & (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout & !\modulation|LessThan0~13_cout )) # (!\tri_out[5]~reg0_q & +// ((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ) # (!\modulation|LessThan0~13_cout )))) + + .dataa(\tri_out[5]~reg0_q ), + .datab(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~13_cout ), + .combout(), + .cout(\modulation|LessThan0~15_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~15 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \modulation|LessThan0~17 ( +// Equation(s): +// \modulation|LessThan0~17_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout & (\tri_out[6]~reg0_q & !\modulation|LessThan0~15_cout )) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout & ((\tri_out[6]~reg0_q ) # (!\modulation|LessThan0~15_cout )))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8_combout ), + .datab(\tri_out[6]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~15_cout ), + .combout(), + .cout(\modulation|LessThan0~17_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~17 .lut_mask = 16'h004D; +defparam \modulation|LessThan0~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \modulation|LessThan0~19 ( +// Equation(s): +// \modulation|LessThan0~19_cout = CARRY((\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout & ((!\modulation|LessThan0~17_cout ) # (!\tri_out[7]~reg0_q ))) # +// (!\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout & (!\tri_out[7]~reg0_q & !\modulation|LessThan0~17_cout ))) + + .dataa(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10_combout ), + .datab(\tri_out[7]~reg0_q ), + .datac(gnd), + .datad(vcc), + .cin(\modulation|LessThan0~17_cout ), + .combout(), + .cout(\modulation|LessThan0~19_cout )); +// synopsys translate_off +defparam \modulation|LessThan0~19 .lut_mask = 16'h002B; +defparam \modulation|LessThan0~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \modulation|LessThan0~20 ( +// Equation(s): +// \modulation|LessThan0~20_combout = (\tri_out[8]~reg0_q & (\modulation|LessThan0~19_cout & \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout )) # (!\tri_out[8]~reg0_q & ((\modulation|LessThan0~19_cout ) # +// (\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ))) + + .dataa(gnd), + .datab(\tri_out[8]~reg0_q ), + .datac(gnd), + .datad(\modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12_combout ), + .cin(\modulation|LessThan0~19_cout ), + .combout(\modulation|LessThan0~20_combout ), + .cout()); +// synopsys translate_off +defparam \modulation|LessThan0~20 .lut_mask = 16'hF330; +defparam \modulation|LessThan0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y12_N23 +dffeas \modulation|out ( + .clk(\clk_200m~inputclkctrl_outclk ), + .d(\modulation|LessThan0~20_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\modulation|out~q ), + .prn(vcc)); +// synopsys translate_off +defparam \modulation|out .is_wysiwyg = "true"; +defparam \modulation|out .power_up = "low"; +// synopsys translate_on + +assign tri_out[0] = \tri_out[0]~output_o ; + +assign tri_out[1] = \tri_out[1]~output_o ; + +assign tri_out[2] = \tri_out[2]~output_o ; + +assign tri_out[3] = \tri_out[3]~output_o ; + +assign tri_out[4] = \tri_out[4]~output_o ; + +assign tri_out[5] = \tri_out[5]~output_o ; + +assign tri_out[6] = \tri_out[6]~output_o ; + +assign tri_out[7] = \tri_out[7]~output_o ; + +assign tri_out[8] = \tri_out[8]~output_o ; + +assign sin_out[0] = \sin_out[0]~output_o ; + +assign sin_out[1] = \sin_out[1]~output_o ; + +assign sin_out[2] = \sin_out[2]~output_o ; + +assign sin_out[3] = \sin_out[3]~output_o ; + +assign sin_out[4] = \sin_out[4]~output_o ; + +assign sin_out[5] = \sin_out[5]~output_o ; + +assign sin_out[6] = \sin_out[6]~output_o ; + +assign sin_out[7] = \sin_out[7]~output_o ; + +assign sin_out[8] = \sin_out[8]~output_o ; + +assign spwm_out = \spwm_out~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_DATA0~~ibuf_o ; + + +endmodule diff --git a/spwm/simulation/modelsim/spwm_min_1200mv_0c_v_fast.sdo b/spwm/simulation/modelsim/spwm_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..55208bb --- /dev/null +++ b/spwm/simulation/modelsim/spwm_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,2573 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE10F17C8, +// with speed grade M, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "spwm") + (DATE "12/10/2018 20:55:32") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (443:443:443) (499:499:499)) + (IOPATH i o (1602:1602:1602) (1605:1605:1605)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (587:587:587) (658:658:658)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (597:597:597) (673:673:673)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (433:433:433) (491:491:491)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (629:629:629) (715:715:715)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (609:609:609) (683:683:683)) + (IOPATH i o (1582:1582:1582) (1585:1585:1585)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (441:441:441) (503:503:503)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (561:561:561) (632:632:632)) + (IOPATH i o (1602:1602:1602) (1605:1605:1605)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (443:443:443) (507:507:507)) + (IOPATH i o (1582:1582:1582) (1585:1585:1585)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (693:693:693) (781:781:781)) + (IOPATH i o (1602:1602:1602) (1605:1605:1605)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (788:788:788) (879:879:879)) + (IOPATH i o (1545:1545:1545) (1550:1550:1550)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (793:793:793) (891:891:891)) + (IOPATH i o (1572:1572:1572) (1575:1575:1575)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (776:776:776) (875:875:875)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (745:745:745) (836:836:836)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (758:758:758) (845:845:845)) + (IOPATH i o (1589:1589:1589) (1614:1614:1614)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (708:708:708) (797:797:797)) + (IOPATH i o (1599:1599:1599) (1624:1624:1624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (945:945:945) (1059:1059:1059)) + (IOPATH i o (1572:1572:1572) (1575:1575:1575)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (798:798:798) (891:891:891)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE spwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (672:672:672) (772:772:772)) + (IOPATH i o (1592:1592:1592) (1595:1595:1595)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk_200m\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_200m\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (108:108:108) (89:89:89)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (210:210:210)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (108:108:108) (89:89:89)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[0\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (782:782:782)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (774:774:774) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (200:200:200)) + (PORT datab (312:312:312) (362:362:362)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (388:388:388)) + (PORT datab (152:152:152) (204:204:204)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[2\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (782:782:782)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (774:774:774) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (387:387:387)) + (PORT datab (146:146:146) (196:196:196)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[3\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (782:782:782)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (774:774:774) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (386:386:386)) + (PORT datab (147:147:147) (197:197:197)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[4\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (782:782:782)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (774:774:774) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (386:386:386)) + (PORT datab (142:142:142) (190:190:190)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[5\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (782:782:782)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (774:774:774) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (386:386:386)) + (PORT datab (226:226:226) (288:288:288)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[6\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (782:782:782)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (774:774:774) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (385:385:385)) + (PORT datab (146:146:146) (195:195:195)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[7\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (782:782:782)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (774:774:774) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (309:309:309) (380:380:380)) + (PORT datad (292:292:292) (335:335:335)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[8\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (782:782:782)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (774:774:774) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~12) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (202:202:202)) + (PORT datab (152:152:152) (204:204:204)) + (PORT datac (298:298:298) (359:359:359)) + (PORT datad (135:135:135) (175:175:175)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~11) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (283:283:283)) + (PORT datab (148:148:148) (199:199:199)) + (PORT datac (138:138:138) (183:183:183)) + (PORT datad (135:135:135) (174:174:174)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE updown) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (782:782:782)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (774:774:774) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~13) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (203:203:203)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datac (132:132:132) (175:175:175)) + (PORT datad (148:148:148) (187:187:187)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~14) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datad (162:162:162) (188:188:188)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[1\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (764:764:764) (782:782:782)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (774:774:774) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (668:668:668)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (707:707:707)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (697:697:697)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (697:697:697)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (657:657:657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (181:181:181)) + (PORT datab (1621:1621:1621) (1819:1819:1819)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (1732:1732:1732) (1927:1927:1927)) + (PORT datab (130:130:130) (177:177:177)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (1748:1748:1748) (1955:1955:1955)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (1844:1844:1844) (2058:2058:2058)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[4\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (1737:1737:1737) (1942:1942:1942)) + (PORT datab (129:129:129) (177:177:177)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[5\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (1763:1763:1763) (1974:1974:1974)) + (PORT datab (129:129:129) (177:177:177)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[6\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (1713:1713:1713) (1909:1909:1909)) + (PORT datab (130:130:130) (177:177:177)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[7\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (1640:1640:1640) (1833:1833:1833)) + (PORT datab (130:130:130) (177:177:177)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[8\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (180:180:180)) + (PORT datab (1717:1717:1717) (1911:1911:1911)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[9\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (1748:1748:1748) (1950:1950:1950)) + (PORT datab (130:130:130) (177:177:177)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[10\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (181:181:181)) + (PORT datab (1712:1712:1712) (1911:1911:1911)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[11\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (1618:1618:1618) (1810:1810:1810)) + (PORT datab (129:129:129) (177:177:177)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[12\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (129:129:129) (180:180:180)) + (PORT datab (1632:1632:1632) (1822:1822:1822)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (770:770:770) (788:788:788)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (780:780:780) (753:753:753)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[13\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (1751:1751:1751) (1953:1953:1953)) + (PORT datab (129:129:129) (177:177:177)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[14\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (1734:1734:1734) (1947:1947:1947)) + (PORT datab (129:129:129) (177:177:177)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[15\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (1679:1679:1679) (1863:1863:1863)) + (PORT datab (130:130:130) (178:178:178)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[16\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1676:1676:1676) (1890:1890:1890)) + (PORT datab (209:209:209) (261:261:261)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[17\]\~60) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (688:688:688)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (265:265:265)) + (PORT datab (1841:1841:1841) (2050:2050:2050)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[18\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (280:280:280)) + (PORT datab (1699:1699:1699) (1903:1903:1903)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[19\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (658:658:658)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (281:281:281)) + (PORT datab (1845:1845:1845) (2060:2060:2060)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[20\]\~66) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (268:268:268)) + (PORT datab (1669:1669:1669) (1852:1852:1852)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[21\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (267:267:267)) + (PORT datab (1741:1741:1741) (1962:1962:1962)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[22\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1842:1842:1842) (2058:2058:2058)) + (PORT datab (209:209:209) (262:262:262)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[23\]\~72) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1870:1870:1870) (2089:2089:2089)) + (PORT datab (224:224:224) (277:277:277)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (668:668:668)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[24\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[8\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1663:1663:1663) (1849:1849:1849)) + (PORT datab (208:208:208) (262:262:262)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (657:657:657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[25\]\~76) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[25\]) + (DELAY + (ABSOLUTE + (PORT clk (769:769:769) (787:787:787)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (779:779:779) (752:752:752)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[9\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (1727:1727:1727) (1938:1938:1938)) + (PORT datad (206:206:206) (251:251:251)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (730:730:730) (819:819:819)) + (PORT d[1] (751:751:751) (846:846:846)) + (PORT d[2] (906:906:906) (1016:1016:1016)) + (PORT d[3] (920:920:920) (1037:1037:1037)) + (PORT d[4] (877:877:877) (1026:1026:1026)) + (PORT d[5] (891:891:891) (1002:1002:1002)) + (PORT d[6] (912:912:912) (1027:1027:1027)) + (PORT d[7] (914:914:914) (1030:1030:1030)) + (PORT d[8] (900:900:900) (1010:1010:1010)) + (PORT d[9] (886:886:886) (1035:1035:1035)) + (PORT clk (941:941:941) (974:974:974)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (941:941:941) (974:974:974)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (942:942:942) (975:975:975)) + (IOPATH (posedge clk) pulse (0:0:0) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (923:923:923) (955:955:955)) + (IOPATH (posedge clk) q (164:164:164) (167:167:167)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (463:463:463) (487:487:487)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (464:464:464) (488:488:488)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (464:464:464) (488:488:488)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (464:464:464) (488:488:488)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (500:500:500)) + (PORT datab (410:410:410) (480:480:480)) + (PORT datac (403:403:403) (478:478:478)) + (PORT datad (381:381:381) (439:439:439)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[10\]) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (497:497:497)) + (PORT datab (419:419:419) (496:496:496)) + (PORT datac (382:382:382) (438:438:438)) + (PORT datad (394:394:394) (458:458:458)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[9\]) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (273:273:273)) + (PORT datab (228:228:228) (274:274:274)) + (PORT datac (212:212:212) (259:259:259)) + (PORT datad (212:212:212) (253:253:253)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (281:281:281)) + (PORT datab (230:230:230) (278:278:278)) + (PORT datac (211:211:211) (255:255:255)) + (PORT datad (209:209:209) (249:249:249)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[11\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (416:416:416)) + (PORT datab (339:339:339) (397:397:397)) + (PORT datac (317:317:317) (367:367:367)) + (PORT datad (325:325:325) (378:378:378)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (389:389:389)) + (PORT datab (310:310:310) (364:364:364)) + (PORT datac (303:303:303) (349:349:349)) + (PORT datad (323:323:323) (377:377:377)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (266:266:266)) + (PORT datac (218:218:218) (265:265:265)) + (PORT datad (214:214:214) (255:255:255)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (415:415:415)) + (PORT datab (339:339:339) (397:397:397)) + (PORT datac (317:317:317) (367:367:367)) + (PORT datad (325:325:325) (378:378:378)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[9\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (415:415:415)) + (PORT datab (340:340:340) (398:398:398)) + (PORT datac (318:318:318) (367:367:367)) + (PORT datad (324:324:324) (378:378:378)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (496:496:496)) + (PORT datad (394:394:394) (458:458:458)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[8\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (405:405:405)) + (PORT datab (346:346:346) (405:405:405)) + (PORT datac (320:320:320) (370:370:370)) + (PORT datad (321:321:321) (373:373:373)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (402:402:402)) + (PORT datab (346:346:346) (405:405:405)) + (PORT datac (320:320:320) (369:369:369)) + (PORT datad (317:317:317) (378:378:378)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (268:268:268)) + (PORT datab (221:221:221) (265:265:265)) + (PORT datad (205:205:205) (243:243:243)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (161:161:161) (176:176:176)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (357:357:357)) + (PORT datab (317:317:317) (370:370:370)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (389:389:389)) + (PORT datab (102:102:102) (131:131:131)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (405:405:405)) + (PORT datab (103:103:103) (132:132:132)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (320:320:320) (373:373:373)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (336:336:336)) + (PORT datab (104:104:104) (133:133:133)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (103:103:103) (132:132:132)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (277:277:277) (322:322:322)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT datab (292:292:292) (338:338:338)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (381:381:381)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~18) + (DELAY + (ABSOLUTE + (PORT datad (335:335:335) (393:393:393)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (211:211:211)) + (PORT datab (368:368:368) (430:430:430)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (213:213:213)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT datab (171:171:171) (209:209:209)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (452:452:452)) + (PORT datab (186:186:186) (223:223:223)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (452:452:452)) + (PORT datab (171:171:171) (209:209:209)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (453:453:453)) + (PORT datab (186:186:186) (223:223:223)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (269:269:269)) + (PORT datab (223:223:223) (268:268:268)) + (PORT datac (191:191:191) (229:229:229)) + (PORT datad (204:204:204) (241:241:241)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (297:297:297) (335:335:335)) + (PORT datad (296:296:296) (331:331:331)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (130:130:130)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (345:345:345)) + (PORT datab (566:566:566) (663:663:663)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (888:888:888)) + (PORT datab (325:325:325) (374:374:374)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (223:223:223)) + (PORT datab (701:701:701) (824:824:824)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (223:223:223)) + (PORT datab (680:680:680) (791:791:791)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (686:686:686)) + (PORT datab (170:170:170) (206:206:206)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (667:667:667)) + (PORT datab (172:172:172) (206:206:206)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (171:171:171) (210:210:210)) + (PORT datab (563:563:563) (666:666:666)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (225:225:225)) + (PORT datab (550:550:550) (653:653:653)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~20) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (684:684:684)) + (PORT datad (168:168:168) (196:196:196)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE modulation\|out) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (1002:1002:1002)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) +) diff --git a/spwm/simulation/modelsim/spwm_modelsim.xrf b/spwm/simulation/modelsim/spwm_modelsim.xrf new file mode 100644 index 0000000..ca21d58 --- /dev/null +++ b/spwm/simulation/modelsim/spwm_modelsim.xrf @@ -0,0 +1,222 @@ +vendor_name = ModelSim +source_file = 1, F:/Code/FPGA/reserve/spwm/rtl/spwm.v +source_file = 1, F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v +source_file = 1, F:/Code/FPGA/reserve/spwm/spwm_sin.qip +source_file = 1, F:/Code/FPGA/reserve/spwm/spwm_sin.v +source_file = 1, F:/Code/FPGA/reserve/spwm/rtl/modulation.v +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/altsyncram.tdf +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/stratix_ram_block.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mux.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_decode.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/aglobal181.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/a_rdenreg.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/altrom.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/altram.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/altdpram.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/cbx.lst +source_file = 1, F:/Code/FPGA/reserve/spwm/db/altsyncram_sl91.tdf +source_file = 1, F:/Code/FPGA/reserve/spwm/sin9bit_1024.mif +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_mult.tdf +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/multcore.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/bypassff.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/altshift.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/multcore.tdf +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/csa_add.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/muleabz.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/mul_lfrg.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/mul_boothc.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/alt_ded_mult.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/alt_ded_mult_y.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/dffpipe.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/mpar_add.tdf +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/lpm_add_sub.tdf +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/addcore.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/look_add.inc +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc +source_file = 1, F:/Code/FPGA/reserve/spwm/db/add_sub_lgh.tdf +source_file = 1, F:/Code/FPGA/reserve/spwm/db/add_sub_pgh.tdf +source_file = 1, d:/intelfpga/18.1/quartus/libraries/megafunctions/altshift.tdf +design_name = spwm +instance = comp, \tri_out[0]~output , tri_out[0]~output, spwm, 1 +instance = comp, \tri_out[1]~output , tri_out[1]~output, spwm, 1 +instance = comp, \tri_out[2]~output , tri_out[2]~output, spwm, 1 +instance = comp, \tri_out[3]~output , tri_out[3]~output, spwm, 1 +instance = comp, \tri_out[4]~output , tri_out[4]~output, spwm, 1 +instance = comp, \tri_out[5]~output , tri_out[5]~output, spwm, 1 +instance = comp, \tri_out[6]~output , tri_out[6]~output, spwm, 1 +instance = comp, \tri_out[7]~output , tri_out[7]~output, spwm, 1 +instance = comp, \tri_out[8]~output , tri_out[8]~output, spwm, 1 +instance = comp, \sin_out[0]~output , sin_out[0]~output, spwm, 1 +instance = comp, \sin_out[1]~output , sin_out[1]~output, spwm, 1 +instance = comp, \sin_out[2]~output , sin_out[2]~output, spwm, 1 +instance = comp, \sin_out[3]~output , sin_out[3]~output, spwm, 1 +instance = comp, \sin_out[4]~output , sin_out[4]~output, spwm, 1 +instance = comp, \sin_out[5]~output , sin_out[5]~output, spwm, 1 +instance = comp, \sin_out[6]~output , sin_out[6]~output, spwm, 1 +instance = comp, \sin_out[7]~output , sin_out[7]~output, spwm, 1 +instance = comp, \sin_out[8]~output , sin_out[8]~output, spwm, 1 +instance = comp, \spwm_out~output , spwm_out~output, spwm, 1 +instance = comp, \clk_200m~input , clk_200m~input, spwm, 1 +instance = comp, \clk_200m~inputclkctrl , clk_200m~inputclkctrl, spwm, 1 +instance = comp, \tri_out[0]~9 , tri_out[0]~9, spwm, 1 +instance = comp, \rst_n~input , rst_n~input, spwm, 1 +instance = comp, \rst_n~inputclkctrl , rst_n~inputclkctrl, spwm, 1 +instance = comp, \tri_out[0]~reg0 , tri_out[0]~reg0, spwm, 1 +instance = comp, \tri_out[1]~15 , tri_out[1]~15, spwm, 1 +instance = comp, \tri_out[2]~17 , tri_out[2]~17, spwm, 1 +instance = comp, \tri_out[2]~reg0 , tri_out[2]~reg0, spwm, 1 +instance = comp, \tri_out[3]~19 , tri_out[3]~19, spwm, 1 +instance = comp, \tri_out[3]~reg0 , tri_out[3]~reg0, spwm, 1 +instance = comp, \tri_out[4]~21 , tri_out[4]~21, spwm, 1 +instance = comp, \tri_out[4]~reg0 , tri_out[4]~reg0, spwm, 1 +instance = comp, \tri_out[5]~23 , tri_out[5]~23, spwm, 1 +instance = comp, \tri_out[5]~reg0 , tri_out[5]~reg0, spwm, 1 +instance = comp, \tri_out[6]~25 , tri_out[6]~25, spwm, 1 +instance = comp, \tri_out[6]~reg0 , tri_out[6]~reg0, spwm, 1 +instance = comp, \tri_out[7]~27 , tri_out[7]~27, spwm, 1 +instance = comp, \tri_out[7]~reg0 , tri_out[7]~reg0, spwm, 1 +instance = comp, \tri_out[8]~29 , tri_out[8]~29, spwm, 1 +instance = comp, \tri_out[8]~reg0 , tri_out[8]~reg0, spwm, 1 +instance = comp, \tri_out~12 , tri_out~12, spwm, 1 +instance = comp, \tri_out~11 , tri_out~11, spwm, 1 +instance = comp, \tri_out~13 , tri_out~13, spwm, 1 +instance = comp, \tri_out~14 , tri_out~14, spwm, 1 +instance = comp, \tri_out[1]~reg0 , tri_out[1]~reg0, spwm, 1 +instance = comp, \Pword[0]~input , Pword[0]~input, spwm, 1 +instance = comp, \Fword[15]~input , Fword[15]~input, spwm, 1 +instance = comp, \Fword[14]~input , Fword[14]~input, spwm, 1 +instance = comp, \Fword[13]~input , Fword[13]~input, spwm, 1 +instance = comp, \Fword[12]~input , Fword[12]~input, spwm, 1 +instance = comp, \Fword[11]~input , Fword[11]~input, spwm, 1 +instance = comp, \Fword[10]~input , Fword[10]~input, spwm, 1 +instance = comp, \Fword[9]~input , Fword[9]~input, spwm, 1 +instance = comp, \Fword[8]~input , Fword[8]~input, spwm, 1 +instance = comp, \Fword[7]~input , Fword[7]~input, spwm, 1 +instance = comp, \Fword[6]~input , Fword[6]~input, spwm, 1 +instance = comp, \Fword[5]~input , Fword[5]~input, spwm, 1 +instance = comp, \Fword[4]~input , Fword[4]~input, spwm, 1 +instance = comp, \Fword[3]~input , Fword[3]~input, spwm, 1 +instance = comp, \Fword[2]~input , Fword[2]~input, spwm, 1 +instance = comp, \Fword[1]~input , Fword[1]~input, spwm, 1 +instance = comp, \Fword[0]~input , Fword[0]~input, spwm, 1 +instance = comp, \F_acc[0]~26 , F_acc[0]~26, spwm, 1 +instance = comp, \F_acc[0] , F_acc[0], spwm, 1 +instance = comp, \F_acc[1]~28 , F_acc[1]~28, spwm, 1 +instance = comp, \F_acc[1] , F_acc[1], spwm, 1 +instance = comp, \F_acc[2]~30 , F_acc[2]~30, spwm, 1 +instance = comp, \F_acc[2] , F_acc[2], spwm, 1 +instance = comp, \F_acc[3]~32 , F_acc[3]~32, spwm, 1 +instance = comp, \F_acc[3] , F_acc[3], spwm, 1 +instance = comp, \F_acc[4]~34 , F_acc[4]~34, spwm, 1 +instance = comp, \F_acc[4] , F_acc[4], spwm, 1 +instance = comp, \F_acc[5]~36 , F_acc[5]~36, spwm, 1 +instance = comp, \F_acc[5] , F_acc[5], spwm, 1 +instance = comp, \F_acc[6]~38 , F_acc[6]~38, spwm, 1 +instance = comp, \F_acc[6] , F_acc[6], spwm, 1 +instance = comp, \F_acc[7]~40 , F_acc[7]~40, spwm, 1 +instance = comp, \F_acc[7] , F_acc[7], spwm, 1 +instance = comp, \F_acc[8]~42 , F_acc[8]~42, spwm, 1 +instance = comp, \F_acc[8] , F_acc[8], spwm, 1 +instance = comp, \F_acc[9]~44 , F_acc[9]~44, spwm, 1 +instance = comp, \F_acc[9] , F_acc[9], spwm, 1 +instance = comp, \F_acc[10]~46 , F_acc[10]~46, spwm, 1 +instance = comp, \F_acc[10] , F_acc[10], spwm, 1 +instance = comp, \F_acc[11]~48 , F_acc[11]~48, spwm, 1 +instance = comp, \F_acc[11] , F_acc[11], spwm, 1 +instance = comp, \F_acc[12]~50 , F_acc[12]~50, spwm, 1 +instance = comp, \F_acc[12] , F_acc[12], spwm, 1 +instance = comp, \F_acc[13]~52 , F_acc[13]~52, spwm, 1 +instance = comp, \F_acc[13] , F_acc[13], spwm, 1 +instance = comp, \F_acc[14]~54 , F_acc[14]~54, spwm, 1 +instance = comp, \F_acc[14] , F_acc[14], spwm, 1 +instance = comp, \F_acc[15]~56 , F_acc[15]~56, spwm, 1 +instance = comp, \F_acc[15] , F_acc[15], spwm, 1 +instance = comp, \F_acc[16]~58 , F_acc[16]~58, spwm, 1 +instance = comp, \F_acc[16] , F_acc[16], spwm, 1 +instance = comp, \rom_address[0]~0 , rom_address[0]~0, spwm, 1 +instance = comp, \F_acc[17]~60 , F_acc[17]~60, spwm, 1 +instance = comp, \F_acc[17] , F_acc[17], spwm, 1 +instance = comp, \Pword[1]~input , Pword[1]~input, spwm, 1 +instance = comp, \rom_address[1]~2 , rom_address[1]~2, spwm, 1 +instance = comp, \F_acc[18]~62 , F_acc[18]~62, spwm, 1 +instance = comp, \F_acc[18] , F_acc[18], spwm, 1 +instance = comp, \Pword[2]~input , Pword[2]~input, spwm, 1 +instance = comp, \rom_address[2]~4 , rom_address[2]~4, spwm, 1 +instance = comp, \F_acc[19]~64 , F_acc[19]~64, spwm, 1 +instance = comp, \F_acc[19] , F_acc[19], spwm, 1 +instance = comp, \Pword[3]~input , Pword[3]~input, spwm, 1 +instance = comp, \rom_address[3]~6 , rom_address[3]~6, spwm, 1 +instance = comp, \F_acc[20]~66 , F_acc[20]~66, spwm, 1 +instance = comp, \F_acc[20] , F_acc[20], spwm, 1 +instance = comp, \Pword[4]~input , Pword[4]~input, spwm, 1 +instance = comp, \rom_address[4]~8 , rom_address[4]~8, spwm, 1 +instance = comp, \F_acc[21]~68 , F_acc[21]~68, spwm, 1 +instance = comp, \F_acc[21] , F_acc[21], spwm, 1 +instance = comp, \Pword[5]~input , Pword[5]~input, spwm, 1 +instance = comp, \rom_address[5]~10 , rom_address[5]~10, spwm, 1 +instance = comp, \Pword[6]~input , Pword[6]~input, spwm, 1 +instance = comp, \F_acc[22]~70 , F_acc[22]~70, spwm, 1 +instance = comp, \F_acc[22] , F_acc[22], spwm, 1 +instance = comp, \rom_address[6]~12 , rom_address[6]~12, spwm, 1 +instance = comp, \Pword[7]~input , Pword[7]~input, spwm, 1 +instance = comp, \F_acc[23]~72 , F_acc[23]~72, spwm, 1 +instance = comp, \F_acc[23] , F_acc[23], spwm, 1 +instance = comp, \rom_address[7]~14 , rom_address[7]~14, spwm, 1 +instance = comp, \Pword[8]~input , Pword[8]~input, spwm, 1 +instance = comp, \F_acc[24]~74 , F_acc[24]~74, spwm, 1 +instance = comp, \F_acc[24] , F_acc[24], spwm, 1 +instance = comp, \rom_address[8]~16 , rom_address[8]~16, spwm, 1 +instance = comp, \Pword[9]~input , Pword[9]~input, spwm, 1 +instance = comp, \F_acc[25]~76 , F_acc[25]~76, spwm, 1 +instance = comp, \F_acc[25] , F_acc[25], spwm, 1 +instance = comp, \rom_address[9]~18 , rom_address[9]~18, spwm, 1 +instance = comp, \spwm_sin|altsyncram_component|auto_generated|ram_block1a0 , spwm_sin|altsyncram_component|auto_generated|ram_block1a0, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[1][11]~0 , modulation|Mult0|mult_core|romout[1][11]~0, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[1][10] , modulation|Mult0|mult_core|romout[1][10], spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[1][9] , modulation|Mult0|mult_core|romout[1][9], spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[1][8]~1 , modulation|Mult0|mult_core|romout[1][8]~1, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[0][11]~2 , modulation|Mult0|mult_core|romout[0][11]~2, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[1][7] , modulation|Mult0|mult_core|romout[1][7], spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[1][6] , modulation|Mult0|mult_core|romout[1][6], spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[0][10]~3 , modulation|Mult0|mult_core|romout[0][10]~3, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[0][9]~5 , modulation|Mult0|mult_core|romout[0][9]~5, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[1][5]~4 , modulation|Mult0|mult_core|romout[1][5]~4, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[0][8]~6 , modulation|Mult0|mult_core|romout[0][8]~6, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[0][7]~7 , modulation|Mult0|mult_core|romout[0][7]~7, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|romout[0][6]~8 , modulation|Mult0|mult_core|romout[0][6]~8, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0 , modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~0, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2 , modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~2, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4 , modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~4, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6 , modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~6, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8 , modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~8, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10 , modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~10, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12 , modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~12, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14 , modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~14, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16 , modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~16, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18 , modulation|Mult0|mult_core|padder|adder[0]|auto_generated|op_1~18, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0 , modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~0, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2 , modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~2, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4 , modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~4, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6 , modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~6, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8 , modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~8, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10 , modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~10, spwm, 1 +instance = comp, \modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12 , modulation|Mult0|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~12, spwm, 1 +instance = comp, \modulation|LessThan0~0 , modulation|LessThan0~0, spwm, 1 +instance = comp, \modulation|LessThan0~1 , modulation|LessThan0~1, spwm, 1 +instance = comp, \modulation|LessThan0~3 , modulation|LessThan0~3, spwm, 1 +instance = comp, \modulation|LessThan0~5 , modulation|LessThan0~5, spwm, 1 +instance = comp, \modulation|LessThan0~7 , modulation|LessThan0~7, spwm, 1 +instance = comp, \modulation|LessThan0~9 , modulation|LessThan0~9, spwm, 1 +instance = comp, \modulation|LessThan0~11 , modulation|LessThan0~11, spwm, 1 +instance = comp, \modulation|LessThan0~13 , modulation|LessThan0~13, spwm, 1 +instance = comp, \modulation|LessThan0~15 , modulation|LessThan0~15, spwm, 1 +instance = comp, \modulation|LessThan0~17 , modulation|LessThan0~17, spwm, 1 +instance = comp, \modulation|LessThan0~19 , modulation|LessThan0~19, spwm, 1 +instance = comp, \modulation|LessThan0~20 , modulation|LessThan0~20, spwm, 1 +instance = comp, \modulation|out , modulation|out, spwm, 1 +design_name = hard_block +instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, hard_block, 1 +instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, hard_block, 1 diff --git a/spwm/simulation/modelsim/spwm_run_msim_gate_verilog.do b/spwm/simulation/modelsim/spwm_run_msim_gate_verilog.do new file mode 100644 index 0000000..f9653b4 --- /dev/null +++ b/spwm/simulation/modelsim/spwm_run_msim_gate_verilog.do @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {spwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/testbench {F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" spwm_tb + +add wave * +view structure +view signals +run -all diff --git a/spwm/simulation/modelsim/spwm_run_msim_rtl_verilog.do b/spwm/simulation/modelsim/spwm_run_msim_rtl_verilog.do new file mode 100644 index 0000000..4ad1b02 --- /dev/null +++ b/spwm/simulation/modelsim/spwm_run_msim_rtl_verilog.do @@ -0,0 +1,19 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl {F:/Code/FPGA/reserve/spwm/rtl/spwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm {F:/Code/FPGA/reserve/spwm/spwm_sin.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl {F:/Code/FPGA/reserve/spwm/rtl/modulation.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/testbench {F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" spwm_tb + +add wave * +view structure +view signals +run -all diff --git a/spwm/simulation/modelsim/spwm_run_msim_rtl_verilog.do.bak b/spwm/simulation/modelsim/spwm_run_msim_rtl_verilog.do.bak new file mode 100644 index 0000000..4ad1b02 --- /dev/null +++ b/spwm/simulation/modelsim/spwm_run_msim_rtl_verilog.do.bak @@ -0,0 +1,19 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl {F:/Code/FPGA/reserve/spwm/rtl/spwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm {F:/Code/FPGA/reserve/spwm/spwm_sin.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl {F:/Code/FPGA/reserve/spwm/rtl/modulation.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/testbench {F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" spwm_tb + +add wave * +view structure +view signals +run -all diff --git a/spwm/simulation/modelsim/spwm_run_msim_rtl_verilog.do.bak1 b/spwm/simulation/modelsim/spwm_run_msim_rtl_verilog.do.bak1 new file mode 100644 index 0000000..4ad1b02 --- /dev/null +++ b/spwm/simulation/modelsim/spwm_run_msim_rtl_verilog.do.bak1 @@ -0,0 +1,19 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl {F:/Code/FPGA/reserve/spwm/rtl/spwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm {F:/Code/FPGA/reserve/spwm/spwm_sin.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/rtl {F:/Code/FPGA/reserve/spwm/rtl/modulation.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/spwm/testbench {F:/Code/FPGA/reserve/spwm/testbench/spwm_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" spwm_tb + +add wave * +view structure +view signals +run -all diff --git a/spwm/simulation/modelsim/spwm_v.sdo b/spwm/simulation/modelsim/spwm_v.sdo new file mode 100644 index 0000000..afaa4ac --- /dev/null +++ b/spwm/simulation/modelsim/spwm_v.sdo @@ -0,0 +1,2573 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "spwm") + (DATE "12/10/2018 20:55:32") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1131:1131:1131) (1059:1059:1059)) + (IOPATH i o (3147:3147:3147) (3095:3095:3095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1455:1455:1455) (1357:1357:1357)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1494:1494:1494) (1382:1382:1382)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1099:1099:1099) (1037:1037:1037)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1556:1556:1556) (1453:1453:1453)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1503:1503:1503) (1406:1406:1406)) + (IOPATH i o (3127:3127:3127) (3075:3075:3075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1114:1114:1114) (1062:1062:1062)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1452:1452:1452) (1323:1323:1323)) + (IOPATH i o (3147:3147:3147) (3095:3095:3095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tri_out\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1119:1119:1119) (1061:1061:1061)) + (IOPATH i o (3127:3127:3127) (3075:3075:3075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1630:1630:1630) (1516:1516:1516)) + (IOPATH i o (3147:3147:3147) (3095:3095:3095)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2014:2014:2014) (1771:1771:1771)) + (IOPATH i o (3048:3048:3048) (3009:3009:3009)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1887:1887:1887) (1734:1734:1734)) + (IOPATH i o (3117:3117:3117) (3065:3065:3065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1866:1866:1866) (1705:1705:1705)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1790:1790:1790) (1635:1635:1635)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1935:1935:1935) (1695:1695:1695)) + (IOPATH i o (3128:3128:3128) (3105:3105:3105)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1766:1766:1766) (1601:1601:1601)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2263:2263:2263) (2058:2058:2058)) + (IOPATH i o (3117:3117:3117) (3065:3065:3065)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sin_out\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1913:1913:1913) (1755:1755:1755)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE spwm_out\~output) + (DELAY + (ABSOLUTE + (PORT i (1617:1617:1617) (1548:1548:1548)) + (IOPATH i o (3137:3137:3137) (3085:3085:3085)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk_200m\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_200m\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (482:482:482)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[0\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (869:869:869) (777:777:777)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (841:841:841)) + (PORT datab (377:377:377) (465:465:465)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[2\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (840:840:840)) + (PORT datab (369:369:369) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[3\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (840:840:840)) + (PORT datab (368:368:368) (451:451:451)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[4\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (839:839:839)) + (PORT datab (360:360:360) (437:437:437)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[5\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (839:839:839)) + (PORT datab (587:587:587) (632:632:632)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[6\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (838:838:838)) + (PORT datab (368:368:368) (447:447:447)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[7\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (825:825:825)) + (PORT datad (808:808:808) (727:727:727)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[8\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~12) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (459:459:459)) + (PORT datab (376:376:376) (464:464:464)) + (PORT datac (787:787:787) (780:780:780)) + (PORT datad (329:329:329) (405:405:405)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~11) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (626:626:626)) + (PORT datab (369:369:369) (452:452:452)) + (PORT datac (335:335:335) (427:427:427)) + (PORT datad (329:329:329) (406:406:406)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE updown) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~13) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (462:462:462)) + (PORT datab (331:331:331) (407:407:407)) + (PORT datac (325:325:325) (410:410:410)) + (PORT datad (354:354:354) (432:432:432)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE tri_out\~14) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (280:280:280) (306:306:306)) + (PORT datad (442:442:442) (418:418:418)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE tri_out\[1\]\~reg0) + (DELAY + (ABSOLUTE + (PORT clk (1634:1634:1634) (1664:1664:1664)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1694:1694:1694) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (774:774:774) (821:821:821)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Fword\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[0\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (418:418:418)) + (PORT datab (3363:3363:3363) (3595:3595:3595)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[1\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (3654:3654:3654) (3827:3827:3827)) + (PORT datab (332:332:332) (408:408:408)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (418:418:418)) + (PORT datab (3703:3703:3703) (3874:3874:3874)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[3\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (418:418:418)) + (PORT datab (3987:3987:3987) (4091:4091:4091)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[4\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (3655:3655:3655) (3847:3847:3847)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[5\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (3754:3754:3754) (3918:3918:3918)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[6\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (3583:3583:3583) (3781:3781:3781)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[7\]\~40) + (DELAY + (ABSOLUTE + (PORT dataa (3421:3421:3421) (3630:3630:3630)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[8\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (419:419:419)) + (PORT datab (3618:3618:3618) (3786:3786:3786)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[9\]\~44) + (DELAY + (ABSOLUTE + (PORT dataa (3696:3696:3696) (3868:3868:3868)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[10\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (418:418:418)) + (PORT datab (3591:3591:3591) (3784:3784:3784)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[11\]\~48) + (DELAY + (ABSOLUTE + (PORT dataa (3335:3335:3335) (3582:3582:3582)) + (PORT datab (332:332:332) (408:408:408)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[12\]\~50) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (417:417:417)) + (PORT datab (3386:3386:3386) (3605:3605:3605)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[13\]\~52) + (DELAY + (ABSOLUTE + (PORT dataa (3731:3731:3731) (3898:3898:3898)) + (PORT datab (332:332:332) (407:407:407)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[14\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (3702:3702:3702) (3890:3890:3890)) + (PORT datab (332:332:332) (408:408:408)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[15\]\~56) + (DELAY + (ABSOLUTE + (PORT dataa (3614:3614:3614) (3744:3744:3744)) + (PORT datab (333:333:333) (408:408:408)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[16\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3565:3565:3565) (3764:3764:3764)) + (PORT datab (565:565:565) (585:585:585)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[17\]\~60) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (593:593:593)) + (PORT datab (3993:3993:3993) (4104:4104:4104)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[18\]\~62) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (629:629:629)) + (PORT datab (3600:3600:3600) (3783:3783:3783)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[19\]\~64) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (726:726:726) (772:772:772)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[3\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (629:629:629)) + (PORT datab (3994:3994:3994) (4125:4125:4125)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[20\]\~66) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[4\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (598:598:598)) + (PORT datab (3578:3578:3578) (3713:3713:3713)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[21\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (597:597:597)) + (PORT datab (3674:3674:3674) (3888:3888:3888)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[22\]\~70) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[6\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (3983:3983:3983) (4122:4122:4122)) + (PORT datab (558:558:558) (584:584:584)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[23\]\~72) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[7\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (4049:4049:4049) (4173:4173:4173)) + (PORT datab (613:613:613) (618:618:618)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (736:736:736) (782:782:782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[24\]\~74) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[8\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (3571:3571:3571) (3711:3711:3711)) + (PORT datab (558:558:558) (584:584:584)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE Pword\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE F_acc\[25\]\~76) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (392:392:392)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE F_acc\[25\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1671:1671:1671)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1701:1701:1701) (1653:1653:1653)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rom_address\[9\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (3657:3657:3657) (3851:3851:3851)) + (PORT datad (554:554:554) (568:568:568)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1796:1796:1796) (1630:1630:1630)) + (PORT d[1] (1875:1875:1875) (1676:1676:1676)) + (PORT d[2] (2226:2226:2226) (2004:2004:2004)) + (PORT d[3] (2287:2287:2287) (2057:2057:2057)) + (PORT d[4] (2093:2093:2093) (2053:2053:2053)) + (PORT d[5] (2187:2187:2187) (1984:1984:1984)) + (PORT d[6] (2236:2236:2236) (2029:2029:2029)) + (PORT d[7] (2257:2257:2257) (2031:2031:2031)) + (PORT d[8] (2216:2216:2216) (2005:2005:2005)) + (PORT d[9] (2152:2152:2152) (2050:2050:2050)) + (PORT clk (2036:2036:2036) (2082:2082:2082)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2036:2036:2036) (2082:2082:2082)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2037:2037:2037) (2083:2083:2083)) + (IOPATH (posedge clk) pulse (0:0:0) (3134:3134:3134)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.dataout_a_register) + (DELAY + (ABSOLUTE + (PORT clk (1988:1988:1988) (2035:2035:2035)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (959:959:959) (976:976:976)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (960:960:960) (977:977:977)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (960:960:960) (977:977:977)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE spwm_sin\|altsyncram_component\|auto_generated\|ram_block1a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (960:960:960) (977:977:977)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1010:1010:1010) (979:979:979)) + (PORT datab (1006:1006:1006) (946:946:946)) + (PORT datac (992:992:992) (940:940:940)) + (PORT datad (913:913:913) (861:861:861)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[10\]) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (976:976:976)) + (PORT datab (1042:1042:1042) (976:976:976)) + (PORT datac (920:920:920) (858:858:858)) + (PORT datad (949:949:949) (901:901:901)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[9\]) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (549:549:549)) + (PORT datab (590:590:590) (553:553:553)) + (PORT datac (545:545:545) (525:525:525)) + (PORT datad (538:538:538) (516:516:516)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (571:571:571)) + (PORT datab (597:597:597) (563:563:563)) + (PORT datac (539:539:539) (516:516:516)) + (PORT datad (513:513:513) (500:500:500)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[11\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (834:834:834)) + (PORT datab (868:868:868) (804:804:804)) + (PORT datac (798:798:798) (747:747:747)) + (PORT datad (816:816:816) (762:762:762)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[7\]) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (784:784:784)) + (PORT datab (789:789:789) (734:734:734)) + (PORT datac (773:773:773) (714:714:714)) + (PORT datad (840:840:840) (766:766:766)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[6\]) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (543:543:543)) + (PORT datac (550:550:550) (531:531:531)) + (PORT datad (539:539:539) (517:517:517)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[10\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (833:833:833)) + (PORT datab (868:868:868) (804:804:804)) + (PORT datac (798:798:798) (747:747:747)) + (PORT datad (816:816:816) (761:761:761)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[9\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (833:833:833)) + (PORT datab (868:868:868) (805:805:805)) + (PORT datac (799:799:799) (747:747:747)) + (PORT datad (815:815:815) (761:761:761)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[1\]\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1007:1007:1007) (976:976:976)) + (PORT datad (949:949:949) (901:901:901)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[8\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (823:823:823)) + (PORT datab (874:874:874) (812:812:812)) + (PORT datac (801:801:801) (751:751:751)) + (PORT datad (812:812:812) (757:757:757)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (815:815:815)) + (PORT datab (874:874:874) (811:811:811)) + (PORT datac (801:801:801) (750:750:750)) + (PORT datad (812:812:812) (766:766:766)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|romout\[0\]\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (541:541:541)) + (PORT datab (581:581:581) (542:542:542)) + (PORT datad (524:524:524) (497:497:497)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (771:771:771)) + (PORT datab (813:813:813) (751:751:751)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (784:784:784)) + (PORT datab (275:275:275) (299:299:299)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (824:824:824)) + (PORT datab (275:275:275) (300:300:300)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (823:823:823) (772:772:772)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (727:727:727)) + (PORT datab (276:276:276) (301:301:301)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (276:276:276) (301:301:301)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (759:759:759) (695:695:695)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT datab (803:803:803) (724:724:724)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT datab (834:834:834) (784:784:784)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|adder\[0\]\|auto_generated\|op_1\~18) + (DELAY + (ABSOLUTE + (PORT datad (869:869:869) (809:809:809)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (464:464:464)) + (PORT datab (909:909:909) (850:850:850)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (472:472:472)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT datab (475:475:475) (459:459:459)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (895:895:895)) + (PORT datab (530:530:530) (493:493:493)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (896:896:896)) + (PORT datab (475:475:475) (459:459:459)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (897:897:897)) + (PORT datab (530:530:530) (493:493:493)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|Mult0\|mult_core\|padder\|sub_par_add\|adder\[0\]\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (542:542:542)) + (PORT datab (584:584:584) (546:546:546)) + (PORT datac (482:482:482) (465:465:465)) + (PORT datad (523:523:523) (495:495:495)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (809:809:809) (730:730:730)) + (PORT datad (784:784:784) (710:710:710)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT datab (274:274:274) (299:299:299)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (745:745:745)) + (PORT datab (1394:1394:1394) (1354:1354:1354)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1937:1937:1937) (1823:1823:1823)) + (PORT datab (871:871:871) (796:796:796)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (495:495:495)) + (PORT datab (1709:1709:1709) (1659:1659:1659)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (493:493:493)) + (PORT datab (1738:1738:1738) (1632:1632:1632)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1402:1402:1402) (1394:1394:1394)) + (PORT datab (471:471:471) (451:451:451)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1404:1404:1404) (1360:1360:1360)) + (PORT datab (483:483:483) (452:452:452)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (473:473:473) (461:461:461)) + (PORT datab (1380:1380:1380) (1355:1355:1355)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (496:496:496)) + (PORT datab (1349:1349:1349) (1329:1329:1329)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE modulation\|LessThan0\~20) + (DELAY + (ABSOLUTE + (PORT datab (1388:1388:1388) (1381:1381:1381)) + (PORT datad (468:468:468) (436:436:436)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE modulation\|out) + (DELAY + (ABSOLUTE + (PORT clk (2121:2121:2121) (2132:2132:2132)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) +) diff --git a/spwm/simulation/modelsim/vsim.wlf b/spwm/simulation/modelsim/vsim.wlf new file mode 100644 index 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fb; + 1022 : fc; + 1023 : fe; +END; diff --git a/spwm/spwm.qpf b/spwm/spwm.qpf new file mode 100644 index 0000000..3a1feb5 --- /dev/null +++ b/spwm/spwm.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 18:46:58 December 08, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "18:46:58 December 08, 2018" + +# Revisions + +PROJECT_REVISION = "spwm" diff --git a/spwm/spwm.qsf b/spwm/spwm.qsf new file mode 100644 index 0000000..d409a9f --- /dev/null +++ b/spwm/spwm.qsf @@ -0,0 +1,70 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 18:46:58 December 08, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# spwm_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE10F17C8 +set_global_assignment -name TOP_LEVEL_ENTITY spwm +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:46:58 DECEMBER 08, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH spwm_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME spwm_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id spwm_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME spwm_tb -section_id spwm_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/spwm_tb.v -section_id spwm_tb +set_global_assignment -name VERILOG_FILE rtl/spwm.v +set_global_assignment -name VERILOG_FILE testbench/spwm_tb.v +set_global_assignment -name QIP_FILE spwm_sin.qip +set_global_assignment -name VERILOG_FILE rtl/modulation.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/spwm/spwm.qws b/spwm/spwm.qws new file mode 100644 index 0000000..bb54d8e Binary files /dev/null and b/spwm/spwm.qws differ diff --git a/spwm/spwm_nativelink_simulation.rpt b/spwm/spwm_nativelink_simulation.rpt new file mode 100644 index 0000000..d5a5e18 --- /dev/null +++ b/spwm/spwm_nativelink_simulation.rpt @@ -0,0 +1,23 @@ +Info: Start Nativelink Simulation process +Info: NativeLink has detected Verilog design -- Verilog simulation models will be used + +========= EDA Simulation Settings ===================== + +Sim Mode : RTL +Family : cycloneive +Quartus root : d:/intelfpga/18.1/quartus/bin64/ +Quartus sim root : d:/intelfpga/18.1/quartus/eda/sim_lib +Simulation Tool : modelsim-altera +Simulation Language : verilog +Simulation Mode : GUI +Sim Output File : +Sim SDF file : +Sim dir : simulation\modelsim + +======================================================= + +Info: Starting NativeLink simulation with ModelSim-Altera software +Sourced NativeLink script d:/intelfpga/18.1/quartus/common/tcl/internal/nativelink/modelsim.tcl +Warning: File spwm_run_msim_rtl_verilog.do already exists - backing up current file as spwm_run_msim_rtl_verilog.do.bak1 +Info: Spawning ModelSim-Altera Simulation software +Info: NativeLink simulation flow was successful diff --git a/spwm/spwm_sin.qip b/spwm/spwm_sin.qip new file mode 100644 index 0000000..bd02b9d --- /dev/null +++ b/spwm/spwm_sin.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "spwm_sin.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "spwm_sin_bb.v"] diff --git a/spwm/spwm_sin.v b/spwm/spwm_sin.v new file mode 100644 index 0000000..5ee0130 --- /dev/null +++ b/spwm/spwm_sin.v @@ -0,0 +1,159 @@ +// megafunction wizard: %ROM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: spwm_sin.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Standard Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module spwm_sin ( + address, + clock, + q); + + input [9:0] address; + input clock; + output [8:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [8:0] sub_wire0; + wire [8:0] q = sub_wire0[8:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_a ({9{1'b1}}), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_a (1'b0), + .wren_b (1'b0)); + defparam + altsyncram_component.address_aclr_a = "NONE", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "sin9bit_1024.mif", + altsyncram_component.intended_device_family = "Cyclone IV E", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "ROM", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 9, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "sin9bit_1024.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "9" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "sin9bit_1024.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]" +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 9 0 @q_a 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/spwm/spwm_sin_bb.v b/spwm/spwm_sin_bb.v new file mode 100644 index 0000000..8f722f2 --- /dev/null +++ b/spwm/spwm_sin_bb.v @@ -0,0 +1,110 @@ +// megafunction wizard: %ROM: 1-PORT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: spwm_sin.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.0 Build 625 09/12/2018 SJ Standard Edition +// ************************************************************ + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module spwm_sin ( + address, + clock, + q); + + input [9:0] address; + input clock; + output [8:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "sin9bit_1024.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "9" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "sin9bit_1024.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]" +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 9 0 @q_a 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL spwm_sin_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/spwm/testbench/spwm_tb.v b/spwm/testbench/spwm_tb.v new file mode 100644 index 0000000..a1aaea8 --- /dev/null +++ b/spwm/testbench/spwm_tb.v @@ -0,0 +1,69 @@ +`timescale 1ns/1ps + +`define clk_period 12.5 + +module spwm_tb; + +//source define + + reg clk; + reg rst_n; + reg [15:0] Fword; + reg [9:0] Pword; + reg [7:0] depth; + wire [9:0] tri_out; + wire [8:0] sin_out; + wire spwm_out; +//probe define + + +//instant user module +spwm spwm( + + .clk_200m(clk), + .rst_n(rst_n), + .tri_out(tri_out), + .sin_out(sin_out), + .Fword(Fword), + .Pword(Pword), + .depth(depth), + .spwm_out(spwm_out) + +); + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + //integer i; + + initial begin + rst_n = 0; + Pword = 0; + Fword = 1365; + depth = 128; + #100; + rst_n = 1; + repeat(5) + begin + #(`clk_period*50000); + end + depth = 200; + repeat(5) + begin + #(`clk_period*50000); + end + Fword = 682; + repeat(10) + begin + #(`clk_period*50000); + end + Fword = 136; + repeat(20) + begin + #(`clk_period*50000); + end + $stop; + end + +endmodule diff --git a/spwm/testbench/spwm_tb.v.bak b/spwm/testbench/spwm_tb.v.bak new file mode 100644 index 0000000..a6ee5cc --- /dev/null +++ b/spwm/testbench/spwm_tb.v.bak @@ -0,0 +1,44 @@ +`timescale 1ns/1ns + +`define clk_period 20 + +module spwm_tb; + +//source define + + + + + + + +//probe define + + + + + +//instant user module +spwm( + + clk, + rst_n, + count_out + +); +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + integer i; + + initial begin + + + + + + $stop; + end + +endmodule diff --git a/timer_pwm/db/.cmp.kpt b/timer_pwm/db/.cmp.kpt new file mode 100644 index 0000000..7a344f9 Binary files /dev/null and b/timer_pwm/db/.cmp.kpt differ diff --git a/timer_pwm/db/my_pll_altpll.v b/timer_pwm/db/my_pll_altpll.v new file mode 100644 index 0000000..30af120 --- /dev/null +++ b/timer_pwm/db/my_pll_altpll.v @@ -0,0 +1,109 @@ +//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=3 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=my_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="ON" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +//VERSION_BEGIN 18.0 cbx_altclkbuf 2018:04:24:18:04:18:SJ cbx_altiobuf_bidir 2018:04:24:18:04:18:SJ cbx_altiobuf_in 2018:04:24:18:04:18:SJ cbx_altiobuf_out 2018:04:24:18:04:18:SJ cbx_altpll 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_counter 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END +//CBXI_INSTANCE_NAME="my_pll_altpll_altpll_component" +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + + +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + + +//synthesis_resources = cycloneive_pll 1 reg 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *) +module my_pll_altpll + ( + areset, + clk, + inclk, + locked) /* synthesis synthesis_clearbox=1 */; + input areset; + output [4:0] clk; + input [1:0] inclk; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; + tri0 [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + reg pll_lock_sync; + wire [4:0] wire_pll1_clk; + wire wire_pll1_fbout; + wire wire_pll1_locked; + + // synopsys translate_off + initial + pll_lock_sync = 0; + // synopsys translate_on + always @ ( posedge wire_pll1_locked or posedge areset) + if (areset == 1'b1) pll_lock_sync <= 1'b0; + else pll_lock_sync <= 1'b1; + cycloneive_pll pll1 + ( + .activeclock(), + .areset(areset), + .clk(wire_pll1_clk), + .clkbad(), + .fbin(wire_pll1_fbout), + .fbout(wire_pll1_fbout), + .inclk(inclk), + .locked(wire_pll1_locked), + .phasedone(), + .scandataout(), + .scandone(), + .vcooverrange(), + .vcounderrange() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .clkswitch(1'b0), + .configupdate(1'b0), + .pfdena(1'b1), + .phasecounterselect({3{1'b0}}), + .phasestep(1'b0), + .phaseupdown(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + defparam + pll1.bandwidth_type = "auto", + pll1.clk0_divide_by = 1, + pll1.clk0_duty_cycle = 50, + pll1.clk0_multiply_by = 3, + pll1.clk0_phase_shift = "0", + pll1.compensate_clock = "clk0", + pll1.inclk0_input_frequency = 20000, + pll1.operation_mode = "normal", + pll1.pll_type = "auto", + pll1.self_reset_on_loss_lock = "on", + pll1.lpm_type = "cycloneive_pll"; + assign + clk = {wire_pll1_clk[4:0]}, + locked = (wire_pll1_locked & pll_lock_sync); +endmodule //my_pll_altpll +//VALID FILE diff --git a/timer_pwm/db/my_pll_altpll1.v b/timer_pwm/db/my_pll_altpll1.v new file mode 100644 index 0000000..81e419b --- /dev/null +++ b/timer_pwm/db/my_pll_altpll1.v @@ -0,0 +1,109 @@ +//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=4 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=my_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="ON" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +//VERSION_BEGIN 18.0 cbx_altclkbuf 2018:04:24:18:04:18:SJ cbx_altiobuf_bidir 2018:04:24:18:04:18:SJ cbx_altiobuf_in 2018:04:24:18:04:18:SJ cbx_altiobuf_out 2018:04:24:18:04:18:SJ cbx_altpll 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_counter 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END +//CBXI_INSTANCE_NAME="timer_pwm_top_my_pll_my_pll_altpll_altpll_component" +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + + +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + + +//synthesis_resources = cycloneive_pll 1 reg 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *) +module my_pll_altpll1 + ( + areset, + clk, + inclk, + locked) /* synthesis synthesis_clearbox=1 */; + input areset; + output [4:0] clk; + input [1:0] inclk; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; + tri0 [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + reg pll_lock_sync; + wire [4:0] wire_pll1_clk; + wire wire_pll1_fbout; + wire wire_pll1_locked; + + // synopsys translate_off + initial + pll_lock_sync = 0; + // synopsys translate_on + always @ ( posedge wire_pll1_locked or posedge areset) + if (areset == 1'b1) pll_lock_sync <= 1'b0; + else pll_lock_sync <= 1'b1; + cycloneive_pll pll1 + ( + .activeclock(), + .areset(areset), + .clk(wire_pll1_clk), + .clkbad(), + .fbin(wire_pll1_fbout), + .fbout(wire_pll1_fbout), + .inclk(inclk), + .locked(wire_pll1_locked), + .phasedone(), + .scandataout(), + .scandone(), + .vcooverrange(), + .vcounderrange() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .clkswitch(1'b0), + .configupdate(1'b0), + .pfdena(1'b1), + .phasecounterselect({3{1'b0}}), + .phasestep(1'b0), + .phaseupdown(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + defparam + pll1.bandwidth_type = "auto", + pll1.clk0_divide_by = 1, + pll1.clk0_duty_cycle = 50, + pll1.clk0_multiply_by = 4, + pll1.clk0_phase_shift = "0", + pll1.compensate_clock = "clk0", + pll1.inclk0_input_frequency = 20000, + pll1.operation_mode = "normal", + pll1.pll_type = "auto", + pll1.self_reset_on_loss_lock = "on", + pll1.lpm_type = "cycloneive_pll"; + assign + clk = {wire_pll1_clk[4:0]}, + locked = (wire_pll1_locked & pll_lock_sync); +endmodule //my_pll_altpll1 +//VALID FILE diff --git a/timer_pwm/db/prev_cmp_timer_pwm.qmsg b/timer_pwm/db/prev_cmp_timer_pwm.qmsg new file mode 100644 index 0000000..d869728 --- /dev/null +++ b/timer_pwm/db/prev_cmp_timer_pwm.qmsg @@ -0,0 +1,15 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541230945706 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541230945721 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 03 15:42:25 2018 " "Processing started: Sat Nov 03 15:42:25 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541230945721 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230945721 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off timer_pwm -c timer_pwm " "Command: quartus_map --read_settings_files=on --write_settings_files=off timer_pwm -c timer_pwm" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230945721 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1541230946393 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1541230946393 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timer_pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file timer_pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer_pwm " "Found entity 1: timer_pwm" { } { { "timer_pwm.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541230958434 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230958434 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ip/my_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file ip/my_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_pll " "Found entity 1: my_pll" { } { { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541230958438 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230958438 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testbench/my_pll_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file testbench/my_pll_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_pll_tb " "Found entity 1: my_pll_tb" { } { { "testbench/my_pll_tb.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/testbench/my_pll_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541230958442 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230958442 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/timer_pwm_top.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/timer_pwm_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer_pwm_top " "Found entity 1: timer_pwm_top" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541230958446 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230958446 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testbench/timer_pwm_top_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file testbench/timer_pwm_top_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer_pwm_top_tb " "Found entity 1: timer_pwm_top_tb" { } { { "testbench/timer_pwm_top_tb.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541230958449 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230958449 ""} +{ "Error" "EVRFX_VERI_UNDEF_TOP_PORT" "tim_ccr2 timer_pwm.v(18) " "Verilog HDL Module Declaration error at timer_pwm.v(18): top module port \"tim_ccr2\" is not found in the port list" { } { { "timer_pwm.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v" 18 0 0 } } } 0 10206 "Verilog HDL Module Declaration error at %2!s!: top module port \"%1!s!\" is not found in the port list" 0 0 "Analysis & Synthesis" 0 -1 1541230958449 ""} +{ "Error" "EVRFX_VERI_UNDEF_TOP_PORT" "tim_ccr3 timer_pwm.v(19) " "Verilog HDL Module Declaration error at timer_pwm.v(19): top module port \"tim_ccr3\" is not found in the port list" { } { { "timer_pwm.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v" 19 0 0 } } } 0 10206 "Verilog HDL Module Declaration error at %2!s!: top module port \"%1!s!\" is not found in the port list" 0 0 "Analysis & Synthesis" 0 -1 1541230958449 ""} +{ "Error" "EVRFX_VERI_UNDEF_TOP_PORT" "tim_ccr4 timer_pwm.v(20) " "Verilog HDL Module Declaration error at timer_pwm.v(20): top module port \"tim_ccr4\" is not found in the port list" { } { { "timer_pwm.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v" 20 0 0 } } } 0 10206 "Verilog HDL Module Declaration error at %2!s!: top module port \"%1!s!\" is not found in the port list" 0 0 "Analysis & Synthesis" 0 -1 1541230958450 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4730 " "Peak virtual memory: 4730 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541230958507 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sat Nov 03 15:42:38 2018 " "Processing ended: Sat Nov 03 15:42:38 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541230958507 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541230958507 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:31 " "Total CPU time (on all processors): 00:00:31" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541230958507 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230958507 ""} +{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 5 s 1 " "Quartus Prime Full Compilation was unsuccessful. 5 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230959193 ""} diff --git a/timer_pwm/db/timer_pwm.(0).cnf.cdb b/timer_pwm/db/timer_pwm.(0).cnf.cdb new file mode 100644 index 0000000..b4a9b04 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(0).cnf.cdb differ diff --git a/timer_pwm/db/timer_pwm.(0).cnf.hdb b/timer_pwm/db/timer_pwm.(0).cnf.hdb new file mode 100644 index 0000000..163cd29 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(0).cnf.hdb differ diff --git a/timer_pwm/db/timer_pwm.(1).cnf.cdb b/timer_pwm/db/timer_pwm.(1).cnf.cdb new file mode 100644 index 0000000..ad499fb Binary files /dev/null and b/timer_pwm/db/timer_pwm.(1).cnf.cdb differ diff --git a/timer_pwm/db/timer_pwm.(1).cnf.hdb b/timer_pwm/db/timer_pwm.(1).cnf.hdb new file mode 100644 index 0000000..aeafba8 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(1).cnf.hdb differ diff --git a/timer_pwm/db/timer_pwm.(2).cnf.cdb b/timer_pwm/db/timer_pwm.(2).cnf.cdb new file mode 100644 index 0000000..4e7bbc0 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(2).cnf.cdb differ diff --git a/timer_pwm/db/timer_pwm.(2).cnf.hdb b/timer_pwm/db/timer_pwm.(2).cnf.hdb new file mode 100644 index 0000000..47bd5a2 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(2).cnf.hdb differ diff --git a/timer_pwm/db/timer_pwm.(3).cnf.cdb b/timer_pwm/db/timer_pwm.(3).cnf.cdb new file mode 100644 index 0000000..cc9c912 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(3).cnf.cdb differ diff --git a/timer_pwm/db/timer_pwm.(3).cnf.hdb b/timer_pwm/db/timer_pwm.(3).cnf.hdb new file mode 100644 index 0000000..bf349c0 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(3).cnf.hdb differ diff --git a/timer_pwm/db/timer_pwm.(4).cnf.cdb b/timer_pwm/db/timer_pwm.(4).cnf.cdb new file mode 100644 index 0000000..fd2b7a9 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(4).cnf.cdb differ diff --git a/timer_pwm/db/timer_pwm.(4).cnf.hdb b/timer_pwm/db/timer_pwm.(4).cnf.hdb new file mode 100644 index 0000000..f7c66f8 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(4).cnf.hdb differ diff --git a/timer_pwm/db/timer_pwm.(5).cnf.cdb b/timer_pwm/db/timer_pwm.(5).cnf.cdb new file mode 100644 index 0000000..4e10715 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(5).cnf.cdb differ diff --git a/timer_pwm/db/timer_pwm.(5).cnf.hdb b/timer_pwm/db/timer_pwm.(5).cnf.hdb new file mode 100644 index 0000000..611ddc9 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(5).cnf.hdb differ diff --git a/timer_pwm/db/timer_pwm.(6).cnf.cdb b/timer_pwm/db/timer_pwm.(6).cnf.cdb new file mode 100644 index 0000000..d5da095 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(6).cnf.cdb differ diff --git a/timer_pwm/db/timer_pwm.(6).cnf.hdb b/timer_pwm/db/timer_pwm.(6).cnf.hdb new file mode 100644 index 0000000..de784b3 Binary files /dev/null and b/timer_pwm/db/timer_pwm.(6).cnf.hdb differ diff --git a/timer_pwm/db/timer_pwm.ace_cmp.bpm b/timer_pwm/db/timer_pwm.ace_cmp.bpm new file mode 100644 index 0000000..46d6eff Binary files /dev/null and b/timer_pwm/db/timer_pwm.ace_cmp.bpm differ diff --git a/timer_pwm/db/timer_pwm.ace_cmp.cdb b/timer_pwm/db/timer_pwm.ace_cmp.cdb new file mode 100644 index 0000000..e180ff0 Binary files /dev/null and b/timer_pwm/db/timer_pwm.ace_cmp.cdb differ diff --git a/timer_pwm/db/timer_pwm.ace_cmp.hdb b/timer_pwm/db/timer_pwm.ace_cmp.hdb new file mode 100644 index 0000000..99af4d1 Binary files /dev/null and b/timer_pwm/db/timer_pwm.ace_cmp.hdb differ diff --git a/timer_pwm/db/timer_pwm.asm.qmsg b/timer_pwm/db/timer_pwm.asm.qmsg new file mode 100644 index 0000000..d2ddd7f --- /dev/null +++ b/timer_pwm/db/timer_pwm.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541231009846 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541231009864 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 03 15:43:29 2018 " "Processing started: Sat Nov 03 15:43:29 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541231009864 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1541231009864 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off timer_pwm -c timer_pwm " "Command: quartus_asm --read_settings_files=off --write_settings_files=off timer_pwm -c timer_pwm" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1541231009864 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1541231010358 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1541231010706 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1541231010729 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4692 " "Peak virtual memory: 4692 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541231010875 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 03 15:43:30 2018 " "Processing ended: Sat Nov 03 15:43:30 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541231010875 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541231010875 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541231010875 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1541231010875 ""} diff --git a/timer_pwm/db/timer_pwm.asm.rdb b/timer_pwm/db/timer_pwm.asm.rdb new file mode 100644 index 0000000..ee96603 Binary files /dev/null and b/timer_pwm/db/timer_pwm.asm.rdb differ diff --git a/timer_pwm/db/timer_pwm.asm_labs.ddb b/timer_pwm/db/timer_pwm.asm_labs.ddb new file mode 100644 index 0000000..a24ae44 Binary files /dev/null and b/timer_pwm/db/timer_pwm.asm_labs.ddb differ diff --git a/timer_pwm/db/timer_pwm.cbx.xml b/timer_pwm/db/timer_pwm.cbx.xml new file mode 100644 index 0000000..9e367f7 --- /dev/null +++ b/timer_pwm/db/timer_pwm.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/timer_pwm/db/timer_pwm.cmp.bpm b/timer_pwm/db/timer_pwm.cmp.bpm new file mode 100644 index 0000000..46d6eff Binary files /dev/null and b/timer_pwm/db/timer_pwm.cmp.bpm differ diff --git a/timer_pwm/db/timer_pwm.cmp.cdb b/timer_pwm/db/timer_pwm.cmp.cdb new file mode 100644 index 0000000..e180ff0 Binary files /dev/null and b/timer_pwm/db/timer_pwm.cmp.cdb differ diff --git a/timer_pwm/db/timer_pwm.cmp.hdb b/timer_pwm/db/timer_pwm.cmp.hdb new file mode 100644 index 0000000..99af4d1 Binary files /dev/null and b/timer_pwm/db/timer_pwm.cmp.hdb differ diff --git a/timer_pwm/db/timer_pwm.cmp.idb b/timer_pwm/db/timer_pwm.cmp.idb new file mode 100644 index 0000000..11a5163 Binary files /dev/null and b/timer_pwm/db/timer_pwm.cmp.idb differ diff --git a/timer_pwm/db/timer_pwm.cmp.logdb b/timer_pwm/db/timer_pwm.cmp.logdb new file mode 100644 index 0000000..88599a0 --- /dev/null +++ b/timer_pwm/db/timer_pwm.cmp.logdb @@ -0,0 +1,116 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;74;0;0;74;74;0;8;0;0;66;0;8;66;0;0;0;8;0;0;0;0;0;74;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,74;74;74;74;74;0;74;74;0;0;74;66;74;74;8;74;66;8;74;74;74;66;74;74;74;74;74;0;74;74, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,tim_cr[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[18],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[19],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[20],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[21],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[22],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[23],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[24],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[25],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[26],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[27],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[28],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[29],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[30],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_cr[31],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ch[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ch[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ch[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ch[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ch[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ch[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ch[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ch[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,rst_n,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,clk,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_ccr1[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tim_arr[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21, diff --git a/timer_pwm/db/timer_pwm.cmp.rdb b/timer_pwm/db/timer_pwm.cmp.rdb new file mode 100644 index 0000000..bbe0396 Binary files /dev/null and b/timer_pwm/db/timer_pwm.cmp.rdb differ diff --git a/timer_pwm/db/timer_pwm.cmp_merge.kpt b/timer_pwm/db/timer_pwm.cmp_merge.kpt new file mode 100644 index 0000000..cbb8b44 Binary files /dev/null and b/timer_pwm/db/timer_pwm.cmp_merge.kpt differ diff --git a/timer_pwm/db/timer_pwm.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/timer_pwm/db/timer_pwm.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd new file mode 100644 index 0000000..ad05395 Binary files /dev/null and b/timer_pwm/db/timer_pwm.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd differ diff --git a/timer_pwm/db/timer_pwm.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd b/timer_pwm/db/timer_pwm.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd new file mode 100644 index 0000000..26a6227 Binary files /dev/null and b/timer_pwm/db/timer_pwm.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd differ diff --git a/timer_pwm/db/timer_pwm.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd b/timer_pwm/db/timer_pwm.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd new file mode 100644 index 0000000..8ced8f4 Binary files /dev/null and b/timer_pwm/db/timer_pwm.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd differ diff --git a/timer_pwm/db/timer_pwm.db_info b/timer_pwm/db/timer_pwm.db_info new file mode 100644 index 0000000..595570e --- /dev/null +++ b/timer_pwm/db/timer_pwm.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +Version_Index = 469919232 +Creation_Time = Sat Nov 03 11:26:43 2018 diff --git a/timer_pwm/db/timer_pwm.eco.cdb b/timer_pwm/db/timer_pwm.eco.cdb new file mode 100644 index 0000000..468d5e1 Binary files /dev/null and b/timer_pwm/db/timer_pwm.eco.cdb differ diff --git a/timer_pwm/db/timer_pwm.eda.qmsg b/timer_pwm/db/timer_pwm.eda.qmsg new file mode 100644 index 0000000..e0c77fb --- /dev/null +++ b/timer_pwm/db/timer_pwm.eda.qmsg @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541231015768 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541231015781 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 03 15:43:35 2018 " "Processing started: Sat Nov 03 15:43:35 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541231015781 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1541231015781 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off timer_pwm -c timer_pwm " "Command: quartus_eda --read_settings_files=off --write_settings_files=off timer_pwm -c timer_pwm" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1541231015782 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1541231016472 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_8_1200mv_85c_slow.vo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_8_1200mv_85c_slow.vo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016639 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_8_1200mv_0c_slow.vo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_8_1200mv_0c_slow.vo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016673 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_min_1200mv_0c_fast.vo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_min_1200mv_0c_fast.vo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016712 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm.vo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm.vo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016748 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_8_1200mv_85c_v_slow.sdo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_8_1200mv_85c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016773 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_8_1200mv_0c_v_slow.sdo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_8_1200mv_0c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016798 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_min_1200mv_0c_v_fast.sdo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_min_1200mv_0c_v_fast.sdo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016824 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_v.sdo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_v.sdo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016854 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4660 " "Peak virtual memory: 4660 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541231016895 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 03 15:43:36 2018 " "Processing ended: Sat Nov 03 15:43:36 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541231016895 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541231016895 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541231016895 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1541231016895 ""} diff --git a/timer_pwm/db/timer_pwm.fit.qmsg b/timer_pwm/db/timer_pwm.fit.qmsg new file mode 100644 index 0000000..0716437 --- /dev/null +++ b/timer_pwm/db/timer_pwm.fit.qmsg @@ -0,0 +1,54 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1541231002981 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1541231002981 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "timer_pwm EP4CE10F17C8 " "Selected device EP4CE10F17C8 for design \"timer_pwm\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1541231003011 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1541231003077 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1541231003077 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|wire_pll1_clk\[0\] 4 1 0 0 " "Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v" 50 -1 0 } } { "" "" { Generic "F:/Code/FPGA/reserve/timer_pwm/" { { 0 { 0 ""} 0 143 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1541231003132 ""} } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v" 50 -1 0 } } { "" "" { Generic "F:/Code/FPGA/reserve/timer_pwm/" { { 0 { 0 ""} 0 143 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1541231003132 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1541231003203 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Device EP4CE6F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1541231003372 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1541231003372 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1541231003372 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1541231003372 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/timer_pwm/" { { 0 { 0 ""} 0 329 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541231003374 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/timer_pwm/" { { 0 { 0 ""} 0 331 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541231003374 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/timer_pwm/" { { 0 { 0 ""} 0 333 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541231003374 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/timer_pwm/" { { 0 { 0 ""} 0 335 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541231003374 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/timer_pwm/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1541231003374 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1541231003374 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1541231003375 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "74 74 " "No exact pin location assignment(s) for 74 pins of 74 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1541231003634 ""} +{ "Info" "ISTA_SDC_FOUND" "timer_pwm.out.sdc " "Reading SDC File: 'timer_pwm.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1541231003801 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "timer_pwm.out.sdc 41 clk_tim port " "Ignored filter at timer_pwm.out.sdc(41): clk_tim could not be matched with a port" { } { { "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" 41 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1541231003802 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock timer_pwm.out.sdc 41 Argument is an empty collection " "Ignored create_clock at timer_pwm.out.sdc(41): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name \{clk_tim\} -period 3.000 -waveform \{ 0.000 1.500 \} \[get_ports \{clk_tim\}\] " "create_clock -name \{clk_tim\} -period 3.000 -waveform \{ 0.000 1.500 \} \[get_ports \{clk_tim\}\]" { } { { "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" 41 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1541231003803 ""} } { { "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" 41 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1541231003803 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "generated clocks " "No user constrained generated clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1541231003806 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1541231003807 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1541231003807 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1541231003809 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1541231003809 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1541231003810 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1) " "Automatically promoted node my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1541231003827 ""} } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v" 92 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/timer_pwm/" { { 0 { 0 ""} 0 143 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1541231003827 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1541231003827 ""} } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 15 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/timer_pwm/" { { 0 { 0 ""} 0 287 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1541231003827 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|locked " "Automatically promoted node my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\|locked " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1541231003827 ""} } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v" 39 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/reserve/timer_pwm/" { { 0 { 0 ""} 0 149 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1541231003827 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1541231004042 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1541231004042 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1541231004042 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1541231004044 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1541231004044 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1541231004045 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1541231004045 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1541231004045 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1541231004058 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1541231004058 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1541231004058 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "72 unused 2.5V 64 8 0 " "Number of I/O pins in group: 72 (unused VREF, 2.5V VCCIO, 64 input, 8 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1541231004060 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1541231004060 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1541231004060 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 12 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541231004061 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 18 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541231004061 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 26 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541231004061 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 27 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541231004061 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 25 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541231004061 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 13 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541231004061 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 26 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541231004061 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 26 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1541231004061 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1541231004061 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1541231004061 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541231004114 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1541231004120 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1541231004643 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541231004688 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1541231004713 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1541231006039 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541231006040 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1541231006279 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X23_Y12 X34_Y24 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24" { } { { "loc" "" { Generic "F:/Code/FPGA/reserve/timer_pwm/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24"} { { 12 { 0 ""} 23 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1541231006704 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1541231006704 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1541231006877 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1541231006877 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1541231006877 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541231006882 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.14 " "Total time spent on timing analysis during the Fitter is 0.14 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1541231007023 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1541231007030 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1541231007165 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1541231007165 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1541231007310 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1541231007691 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/Code/FPGA/reserve/timer_pwm/output_files/timer_pwm.fit.smsg " "Generated suppressed messages file F:/Code/FPGA/reserve/timer_pwm/output_files/timer_pwm.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1541231008016 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5566 " "Peak virtual memory: 5566 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541231008354 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 03 15:43:28 2018 " "Processing ended: Sat Nov 03 15:43:28 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541231008354 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541231008354 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541231008354 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1541231008354 ""} diff --git a/timer_pwm/db/timer_pwm.hier_info b/timer_pwm/db/timer_pwm.hier_info new file mode 100644 index 0000000..f641398 --- /dev/null +++ b/timer_pwm/db/timer_pwm.hier_info @@ -0,0 +1,324 @@ +|timer_pwm_top +clk => clk.IN1 +rst_n => areset.IN1 +tim_cr[0] => tim_cr[0].IN1 +tim_cr[1] => tim_cr[1].IN1 +tim_cr[2] => tim_cr[2].IN1 +tim_cr[3] => tim_cr[3].IN1 +tim_cr[4] => tim_cr[4].IN1 +tim_cr[5] => tim_cr[5].IN1 +tim_cr[6] => tim_cr[6].IN1 +tim_cr[7] => tim_cr[7].IN1 +tim_cr[8] => tim_cr[8].IN1 +tim_cr[9] => tim_cr[9].IN1 +tim_cr[10] => tim_cr[10].IN1 +tim_cr[11] => tim_cr[11].IN1 +tim_cr[12] => tim_cr[12].IN1 +tim_cr[13] => tim_cr[13].IN1 +tim_cr[14] => tim_cr[14].IN1 +tim_cr[15] => tim_cr[15].IN1 +tim_cr[16] => tim_cr[16].IN1 +tim_cr[17] => tim_cr[17].IN1 +tim_cr[18] => tim_cr[18].IN1 +tim_cr[19] => tim_cr[19].IN1 +tim_cr[20] => tim_cr[20].IN1 +tim_cr[21] => tim_cr[21].IN1 +tim_cr[22] => tim_cr[22].IN1 +tim_cr[23] => tim_cr[23].IN1 +tim_cr[24] => tim_cr[24].IN1 +tim_cr[25] => tim_cr[25].IN1 +tim_cr[26] => tim_cr[26].IN1 +tim_cr[27] => tim_cr[27].IN1 +tim_cr[28] => tim_cr[28].IN1 +tim_cr[29] => tim_cr[29].IN1 +tim_cr[30] => tim_cr[30].IN1 +tim_cr[31] => tim_cr[31].IN1 +tim_arr[0] => tim_arr[0].IN1 +tim_arr[1] => tim_arr[1].IN1 +tim_arr[2] => tim_arr[2].IN1 +tim_arr[3] => tim_arr[3].IN1 +tim_arr[4] => tim_arr[4].IN1 +tim_arr[5] => tim_arr[5].IN1 +tim_arr[6] => tim_arr[6].IN1 +tim_arr[7] => tim_arr[7].IN1 +tim_arr[8] => tim_arr[8].IN1 +tim_arr[9] => tim_arr[9].IN1 +tim_arr[10] => tim_arr[10].IN1 +tim_arr[11] => tim_arr[11].IN1 +tim_arr[12] => tim_arr[12].IN1 +tim_arr[13] => tim_arr[13].IN1 +tim_arr[14] => tim_arr[14].IN1 +tim_arr[15] => tim_arr[15].IN1 +tim_ccr1[0] => tim_ccr1[0].IN1 +tim_ccr1[1] => tim_ccr1[1].IN1 +tim_ccr1[2] => tim_ccr1[2].IN1 +tim_ccr1[3] => tim_ccr1[3].IN1 +tim_ccr1[4] => tim_ccr1[4].IN1 +tim_ccr1[5] => tim_ccr1[5].IN1 +tim_ccr1[6] => tim_ccr1[6].IN1 +tim_ccr1[7] => tim_ccr1[7].IN1 +tim_ccr1[8] => tim_ccr1[8].IN1 +tim_ccr1[9] => tim_ccr1[9].IN1 +tim_ccr1[10] => tim_ccr1[10].IN1 +tim_ccr1[11] => tim_ccr1[11].IN1 +tim_ccr1[12] => tim_ccr1[12].IN1 +tim_ccr1[13] => tim_ccr1[13].IN1 +tim_ccr1[14] => tim_ccr1[14].IN1 +tim_ccr1[15] => tim_ccr1[15].IN1 +tim_ch[0] <= timer_pwm:timer_pwm.tim_ch +tim_ch[1] <= timer_pwm:timer_pwm.tim_ch +tim_ch[2] <= timer_pwm:timer_pwm.tim_ch +tim_ch[3] <= timer_pwm:timer_pwm.tim_ch +tim_ch[4] <= timer_pwm:timer_pwm.tim_ch +tim_ch[5] <= timer_pwm:timer_pwm.tim_ch +tim_ch[6] <= timer_pwm:timer_pwm.tim_ch +tim_ch[7] <= timer_pwm:timer_pwm.tim_ch + + +|timer_pwm_top|my_pll:my_pll +areset => areset.IN1 +inclk0 => sub_wire1[0].IN1 +c0 <= altpll:altpll_component.clk +locked <= altpll:altpll_component.locked + + +|timer_pwm_top|my_pll:my_pll|altpll:altpll_component +inclk[0] => my_pll_altpll1:auto_generated.inclk[0] +inclk[1] => my_pll_altpll1:auto_generated.inclk[1] +fbin => ~NO_FANOUT~ +pllena => ~NO_FANOUT~ +clkswitch => ~NO_FANOUT~ +areset => my_pll_altpll1:auto_generated.areset +pfdena => ~NO_FANOUT~ +clkena[0] => ~NO_FANOUT~ +clkena[1] => ~NO_FANOUT~ +clkena[2] => ~NO_FANOUT~ +clkena[3] => ~NO_FANOUT~ +clkena[4] => ~NO_FANOUT~ +clkena[5] => ~NO_FANOUT~ +extclkena[0] => ~NO_FANOUT~ +extclkena[1] => ~NO_FANOUT~ +extclkena[2] => ~NO_FANOUT~ +extclkena[3] => ~NO_FANOUT~ +scanclk => ~NO_FANOUT~ +scanclkena => ~NO_FANOUT~ +scanaclr => ~NO_FANOUT~ +scanread => ~NO_FANOUT~ +scanwrite => ~NO_FANOUT~ +scandata => ~NO_FANOUT~ +phasecounterselect[0] => ~NO_FANOUT~ +phasecounterselect[1] => ~NO_FANOUT~ +phasecounterselect[2] => ~NO_FANOUT~ +phasecounterselect[3] => ~NO_FANOUT~ +phaseupdown => ~NO_FANOUT~ +phasestep => ~NO_FANOUT~ +configupdate => ~NO_FANOUT~ +fbmimicbidir <> +clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE +clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE +clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE +clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE +clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE +extclk[0] <= +extclk[1] <= +extclk[2] <= +extclk[3] <= +clkbad[0] <= +clkbad[1] <= +enable1 <= +enable0 <= +activeclock <= +clkloss <= +locked <= my_pll_altpll1:auto_generated.locked +scandataout <= +scandone <= +sclkout0 <= +sclkout1 <= +phasedone <= +vcooverrange <= +vcounderrange <= +fbout <= +fref <= +icdrclk <= + + +|timer_pwm_top|my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated +areset => pll_lock_sync.ACLR +areset => pll1.ARESET +clk[0] <= pll1.CLK +clk[1] <= pll1.CLK1 +clk[2] <= pll1.CLK2 +clk[3] <= pll1.CLK3 +clk[4] <= pll1.CLK4 +inclk[0] => pll1.CLK +inclk[1] => pll1.CLK1 +locked <= locked.DB_MAX_OUTPUT_PORT_TYPE + + +|timer_pwm_top|timer_pwm:timer_pwm +clk_tim => r_tim_ccr1[0].CLK +clk_tim => r_tim_ccr1[1].CLK +clk_tim => r_tim_ccr1[2].CLK +clk_tim => r_tim_ccr1[3].CLK +clk_tim => r_tim_ccr1[4].CLK +clk_tim => r_tim_ccr1[5].CLK +clk_tim => r_tim_ccr1[6].CLK +clk_tim => r_tim_ccr1[7].CLK +clk_tim => r_tim_ccr1[8].CLK +clk_tim => r_tim_ccr1[9].CLK +clk_tim => r_tim_ccr1[10].CLK +clk_tim => r_tim_ccr1[11].CLK +clk_tim => r_tim_ccr1[12].CLK +clk_tim => r_tim_ccr1[13].CLK +clk_tim => r_tim_ccr1[14].CLK +clk_tim => r_tim_ccr1[15].CLK +clk_tim => r_tim_arr[0].CLK +clk_tim => r_tim_arr[1].CLK +clk_tim => r_tim_arr[2].CLK +clk_tim => r_tim_arr[3].CLK +clk_tim => r_tim_arr[4].CLK +clk_tim => r_tim_arr[5].CLK +clk_tim => r_tim_arr[6].CLK +clk_tim => r_tim_arr[7].CLK +clk_tim => r_tim_arr[8].CLK +clk_tim => r_tim_arr[9].CLK +clk_tim => r_tim_arr[10].CLK +clk_tim => r_tim_arr[11].CLK +clk_tim => r_tim_arr[12].CLK +clk_tim => r_tim_arr[13].CLK +clk_tim => r_tim_arr[14].CLK +clk_tim => r_tim_arr[15].CLK +clk_tim => cnt[0].CLK +clk_tim => cnt[1].CLK +clk_tim => cnt[2].CLK +clk_tim => cnt[3].CLK +clk_tim => cnt[4].CLK +clk_tim => cnt[5].CLK +clk_tim => cnt[6].CLK +clk_tim => cnt[7].CLK +clk_tim => cnt[8].CLK +clk_tim => cnt[9].CLK +clk_tim => cnt[10].CLK +clk_tim => cnt[11].CLK +clk_tim => cnt[12].CLK +clk_tim => cnt[13].CLK +clk_tim => cnt[14].CLK +clk_tim => cnt[15].CLK +clk_tim => tim_ch[0]~reg0.CLK +clk_tim => tim_ch[1]~reg0.CLK +rst_n => r_tim_ccr1[0].ACLR +rst_n => r_tim_ccr1[1].ACLR +rst_n => r_tim_ccr1[2].ACLR +rst_n => r_tim_ccr1[3].ACLR +rst_n => r_tim_ccr1[4].ACLR +rst_n => r_tim_ccr1[5].ACLR +rst_n => r_tim_ccr1[6].ACLR +rst_n => r_tim_ccr1[7].ACLR +rst_n => r_tim_ccr1[8].ACLR +rst_n => r_tim_ccr1[9].ACLR +rst_n => r_tim_ccr1[10].ACLR +rst_n => r_tim_ccr1[11].ACLR +rst_n => r_tim_ccr1[12].ACLR +rst_n => r_tim_ccr1[13].ACLR +rst_n => r_tim_ccr1[14].ACLR +rst_n => r_tim_ccr1[15].ACLR +rst_n => r_tim_arr[0].ACLR +rst_n => r_tim_arr[1].ACLR +rst_n => r_tim_arr[2].ACLR +rst_n => r_tim_arr[3].ACLR +rst_n => r_tim_arr[4].ACLR +rst_n => r_tim_arr[5].ACLR +rst_n => r_tim_arr[6].ACLR +rst_n => r_tim_arr[7].ACLR +rst_n => r_tim_arr[8].ACLR +rst_n => r_tim_arr[9].ACLR +rst_n => r_tim_arr[10].ACLR +rst_n => r_tim_arr[11].ACLR +rst_n => r_tim_arr[12].ACLR +rst_n => r_tim_arr[13].ACLR +rst_n => r_tim_arr[14].ACLR +rst_n => r_tim_arr[15].ACLR +rst_n => cnt[0].ACLR +rst_n => cnt[1].ACLR +rst_n => cnt[2].ACLR +rst_n => cnt[3].ACLR +rst_n => cnt[4].ACLR +rst_n => cnt[5].ACLR +rst_n => cnt[6].ACLR +rst_n => cnt[7].ACLR +rst_n => cnt[8].ACLR +rst_n => cnt[9].ACLR +rst_n => cnt[10].ACLR +rst_n => cnt[11].ACLR +rst_n => cnt[12].ACLR +rst_n => cnt[13].ACLR +rst_n => cnt[14].ACLR +rst_n => cnt[15].ACLR +tim_cr[0] => ~NO_FANOUT~ +tim_cr[1] => ~NO_FANOUT~ +tim_cr[2] => ~NO_FANOUT~ +tim_cr[3] => ~NO_FANOUT~ +tim_cr[4] => ~NO_FANOUT~ +tim_cr[5] => ~NO_FANOUT~ +tim_cr[6] => ~NO_FANOUT~ +tim_cr[7] => ~NO_FANOUT~ +tim_cr[8] => ~NO_FANOUT~ +tim_cr[9] => ~NO_FANOUT~ +tim_cr[10] => ~NO_FANOUT~ +tim_cr[11] => ~NO_FANOUT~ +tim_cr[12] => ~NO_FANOUT~ +tim_cr[13] => ~NO_FANOUT~ +tim_cr[14] => ~NO_FANOUT~ +tim_cr[15] => ~NO_FANOUT~ +tim_cr[16] => ~NO_FANOUT~ +tim_cr[17] => ~NO_FANOUT~ +tim_cr[18] => ~NO_FANOUT~ +tim_cr[19] => ~NO_FANOUT~ +tim_cr[20] => ~NO_FANOUT~ +tim_cr[21] => ~NO_FANOUT~ +tim_cr[22] => ~NO_FANOUT~ +tim_cr[23] => ~NO_FANOUT~ +tim_cr[24] => ~NO_FANOUT~ +tim_cr[25] => ~NO_FANOUT~ +tim_cr[26] => ~NO_FANOUT~ +tim_cr[27] => ~NO_FANOUT~ +tim_cr[28] => ~NO_FANOUT~ +tim_cr[29] => ~NO_FANOUT~ +tim_cr[30] => ~NO_FANOUT~ +tim_cr[31] => ~NO_FANOUT~ +tim_arr[0] => r_tim_arr[0].DATAIN +tim_arr[1] => r_tim_arr[1].DATAIN +tim_arr[2] => r_tim_arr[2].DATAIN +tim_arr[3] => r_tim_arr[3].DATAIN +tim_arr[4] => r_tim_arr[4].DATAIN +tim_arr[5] => r_tim_arr[5].DATAIN +tim_arr[6] => r_tim_arr[6].DATAIN +tim_arr[7] => r_tim_arr[7].DATAIN +tim_arr[8] => r_tim_arr[8].DATAIN +tim_arr[9] => r_tim_arr[9].DATAIN +tim_arr[10] => r_tim_arr[10].DATAIN +tim_arr[11] => r_tim_arr[11].DATAIN +tim_arr[12] => r_tim_arr[12].DATAIN +tim_arr[13] => r_tim_arr[13].DATAIN +tim_arr[14] => r_tim_arr[14].DATAIN +tim_arr[15] => r_tim_arr[15].DATAIN +tim_ccr1[0] => r_tim_ccr1[0].DATAIN +tim_ccr1[1] => r_tim_ccr1[1].DATAIN +tim_ccr1[2] => r_tim_ccr1[2].DATAIN +tim_ccr1[3] => r_tim_ccr1[3].DATAIN +tim_ccr1[4] => r_tim_ccr1[4].DATAIN +tim_ccr1[5] => r_tim_ccr1[5].DATAIN +tim_ccr1[6] => r_tim_ccr1[6].DATAIN +tim_ccr1[7] => r_tim_ccr1[7].DATAIN +tim_ccr1[8] => r_tim_ccr1[8].DATAIN +tim_ccr1[9] => r_tim_ccr1[9].DATAIN +tim_ccr1[10] => r_tim_ccr1[10].DATAIN +tim_ccr1[11] => r_tim_ccr1[11].DATAIN +tim_ccr1[12] => r_tim_ccr1[12].DATAIN +tim_ccr1[13] => r_tim_ccr1[13].DATAIN +tim_ccr1[14] => r_tim_ccr1[14].DATAIN +tim_ccr1[15] => r_tim_ccr1[15].DATAIN +tim_ch[0] <= tim_ch[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tim_ch[1] <= tim_ch[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/timer_pwm/db/timer_pwm.hif b/timer_pwm/db/timer_pwm.hif new file mode 100644 index 0000000..c411fd6 Binary files /dev/null and b/timer_pwm/db/timer_pwm.hif differ diff --git a/timer_pwm/db/timer_pwm.lpc.html b/timer_pwm/db/timer_pwm.lpc.html new file mode 100644 index 0000000..d5c571b --- /dev/null +++ b/timer_pwm/db/timer_pwm.lpc.html @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
timer_pwm660320200000000
my_pll|altpll_component|auto_generated3000600000000
my_pll2000200000000
diff --git a/timer_pwm/db/timer_pwm.lpc.rdb b/timer_pwm/db/timer_pwm.lpc.rdb new file mode 100644 index 0000000..e10c78f Binary files /dev/null and b/timer_pwm/db/timer_pwm.lpc.rdb differ diff --git a/timer_pwm/db/timer_pwm.lpc.txt b/timer_pwm/db/timer_pwm.lpc.txt new file mode 100644 index 0000000..0d0e9c7 --- /dev/null +++ b/timer_pwm/db/timer_pwm.lpc.txt @@ -0,0 +1,9 @@ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; timer_pwm ; 66 ; 0 ; 32 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; my_pll|altpll_component|auto_generated ; 3 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; my_pll ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/timer_pwm/db/timer_pwm.map.ammdb b/timer_pwm/db/timer_pwm.map.ammdb new file mode 100644 index 0000000..aff7571 Binary files /dev/null and b/timer_pwm/db/timer_pwm.map.ammdb differ diff --git a/timer_pwm/db/timer_pwm.map.bpm b/timer_pwm/db/timer_pwm.map.bpm new file mode 100644 index 0000000..fe30205 Binary files /dev/null and b/timer_pwm/db/timer_pwm.map.bpm differ diff --git a/timer_pwm/db/timer_pwm.map.cdb b/timer_pwm/db/timer_pwm.map.cdb new file mode 100644 index 0000000..761e4d9 Binary files /dev/null and b/timer_pwm/db/timer_pwm.map.cdb differ diff --git a/timer_pwm/db/timer_pwm.map.hdb b/timer_pwm/db/timer_pwm.map.hdb new file mode 100644 index 0000000..b9c8092 Binary files /dev/null and b/timer_pwm/db/timer_pwm.map.hdb differ diff --git a/timer_pwm/db/timer_pwm.map.kpt b/timer_pwm/db/timer_pwm.map.kpt new file mode 100644 index 0000000..81bacf4 Binary files /dev/null and b/timer_pwm/db/timer_pwm.map.kpt differ diff --git a/timer_pwm/db/timer_pwm.map.logdb b/timer_pwm/db/timer_pwm.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/timer_pwm/db/timer_pwm.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/timer_pwm/db/timer_pwm.map.qmsg b/timer_pwm/db/timer_pwm.map.qmsg new file mode 100644 index 0000000..206cf84 --- /dev/null +++ b/timer_pwm/db/timer_pwm.map.qmsg @@ -0,0 +1,26 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541230986569 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541230986582 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 03 15:43:06 2018 " "Processing started: Sat Nov 03 15:43:06 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541230986582 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230986582 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off timer_pwm -c timer_pwm " "Command: quartus_map --read_settings_files=on --write_settings_files=off timer_pwm -c timer_pwm" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230986583 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1541230987183 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1541230987183 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timer_pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file timer_pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer_pwm " "Found entity 1: timer_pwm" { } { { "timer_pwm.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541230999493 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230999493 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ip/my_pll.v 1 1 " "Found 1 design units, including 1 entities, in source file ip/my_pll.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_pll " "Found entity 1: my_pll" { } { { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541230999497 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230999497 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testbench/my_pll_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file testbench/my_pll_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_pll_tb " "Found entity 1: my_pll_tb" { } { { "testbench/my_pll_tb.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/testbench/my_pll_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541230999500 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230999500 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rtl/timer_pwm_top.v 1 1 " "Found 1 design units, including 1 entities, in source file rtl/timer_pwm_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer_pwm_top " "Found entity 1: timer_pwm_top" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541230999503 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230999503 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testbench/timer_pwm_top_tb.v 1 1 " "Found 1 design units, including 1 entities, in source file testbench/timer_pwm_top_tb.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer_pwm_top_tb " "Found entity 1: timer_pwm_top_tb" { } { { "testbench/timer_pwm_top_tb.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541230999507 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230999507 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "timer_pwm_top " "Elaborating entity \"timer_pwm_top\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1541230999563 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_pll my_pll:my_pll " "Elaborating entity \"my_pll\" for hierarchy \"my_pll:my_pll\"" { } { { "rtl/timer_pwm_top.v" "my_pll" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 34 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541230999589 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll my_pll:my_pll\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"my_pll:my_pll\|altpll:altpll_component\"" { } { { "ip/my_pll.v" "altpll_component" { Text "F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v" 103 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541230999649 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "my_pll:my_pll\|altpll:altpll_component " "Elaborated megafunction instantiation \"my_pll:my_pll\|altpll:altpll_component\"" { } { { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v" 103 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541230999653 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "my_pll:my_pll\|altpll:altpll_component " "Instantiated megafunction \"my_pll:my_pll\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 4 " "Parameter \"clk0_multiply_by\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=my_pll " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=my_pll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Parameter \"port_areset\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Parameter \"port_clk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock ON " "Parameter \"self_reset_on_loss_lock\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1541230999653 ""} } { { "ip/my_pll.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v" 103 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1541230999653 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/my_pll_altpll1.v 1 1 " "Found 1 design units, including 1 entities, in source file db/my_pll_altpll1.v" { { "Info" "ISGN_ENTITY_NAME" "1 my_pll_altpll1 " "Found entity 1: my_pll_altpll1" { } { { "db/my_pll_altpll1.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1541230999719 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1541230999719 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "my_pll_altpll1 my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated " "Elaborating entity \"my_pll_altpll1\" for hierarchy \"my_pll:my_pll\|altpll:altpll_component\|my_pll_altpll1:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541230999720 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer_pwm timer_pwm:timer_pwm " "Elaborating entity \"timer_pwm\" for hierarchy \"timer_pwm:timer_pwm\"" { } { { "rtl/timer_pwm_top.v" "timer_pwm" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 43 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541230999725 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "r_tim_cr timer_pwm.v(22) " "Verilog HDL or VHDL warning at timer_pwm.v(22): object \"r_tim_cr\" assigned a value but never read" { } { { "timer_pwm.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v" 22 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1541230999725 "|timer_pwm_top|timer_pwm:timer_pwm"} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1541231000200 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "tim_ch\[2\] GND " "Pin \"tim_ch\[2\]\" is stuck at GND" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 12 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1541231000221 "|timer_pwm_top|tim_ch[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "tim_ch\[3\] GND " "Pin \"tim_ch\[3\]\" is stuck at GND" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 12 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1541231000221 "|timer_pwm_top|tim_ch[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "tim_ch\[4\] GND " "Pin \"tim_ch\[4\]\" is stuck at GND" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 12 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1541231000221 "|timer_pwm_top|tim_ch[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "tim_ch\[5\] GND " "Pin \"tim_ch\[5\]\" is stuck at GND" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 12 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1541231000221 "|timer_pwm_top|tim_ch[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "tim_ch\[6\] GND " "Pin \"tim_ch\[6\]\" is stuck at GND" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 12 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1541231000221 "|timer_pwm_top|tim_ch[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "tim_ch\[7\] GND " "Pin \"tim_ch\[7\]\" is stuck at GND" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 12 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1541231000221 "|timer_pwm_top|tim_ch[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1541231000221 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1541231000312 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1541231000830 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1541231000830 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "32 " "Design contains 32 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[0\] " "No output dependent on input pin \"tim_cr\[0\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[0]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[1\] " "No output dependent on input pin \"tim_cr\[1\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[1]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[2\] " "No output dependent on input pin \"tim_cr\[2\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[2]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[3\] " "No output dependent on input pin \"tim_cr\[3\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[3]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[4\] " "No output dependent on input pin \"tim_cr\[4\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[4]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[5\] " "No output dependent on input pin \"tim_cr\[5\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[5]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[6\] " "No output dependent on input pin \"tim_cr\[6\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[6]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[7\] " "No output dependent on input pin \"tim_cr\[7\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[7]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[8\] " "No output dependent on input pin \"tim_cr\[8\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[8]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[9\] " "No output dependent on input pin \"tim_cr\[9\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[9]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[10\] " "No output dependent on input pin \"tim_cr\[10\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[10]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[11\] " "No output dependent on input pin \"tim_cr\[11\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[11]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[12\] " "No output dependent on input pin \"tim_cr\[12\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[12]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[13\] " "No output dependent on input pin \"tim_cr\[13\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[13]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[14\] " "No output dependent on input pin \"tim_cr\[14\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[14]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[15\] " "No output dependent on input pin \"tim_cr\[15\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[15]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[16\] " "No output dependent on input pin \"tim_cr\[16\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[16]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[17\] " "No output dependent on input pin \"tim_cr\[17\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[17]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[18\] " "No output dependent on input pin \"tim_cr\[18\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[18]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[19\] " "No output dependent on input pin \"tim_cr\[19\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[19]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[20\] " "No output dependent on input pin \"tim_cr\[20\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[20]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[21\] " "No output dependent on input pin \"tim_cr\[21\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[21]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[22\] " "No output dependent on input pin \"tim_cr\[22\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[22]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[23\] " "No output dependent on input pin \"tim_cr\[23\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[23]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[24\] " "No output dependent on input pin \"tim_cr\[24\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[24]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[25\] " "No output dependent on input pin \"tim_cr\[25\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[25]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[26\] " "No output dependent on input pin \"tim_cr\[26\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[26]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[27\] " "No output dependent on input pin \"tim_cr\[27\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[27]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[28\] " "No output dependent on input pin \"tim_cr\[28\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[28]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[29\] " "No output dependent on input pin \"tim_cr\[29\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[29]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[30\] " "No output dependent on input pin \"tim_cr\[30\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[30]"} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "tim_cr\[31\] " "No output dependent on input pin \"tim_cr\[31\]\"" { } { { "rtl/timer_pwm_top.v" "" { Text "F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v" 17 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1541231000895 "|timer_pwm_top|tim_cr[31]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1541231000895 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "159 " "Implemented 159 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "66 " "Implemented 66 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1541231000898 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1541231000898 ""} { "Info" "ICUT_CUT_TM_LCELLS" "84 " "Implemented 84 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1541231000898 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1541231000898 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1541231000898 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 43 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 43 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4791 " "Peak virtual memory: 4791 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541231000915 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 03 15:43:20 2018 " "Processing ended: Sat Nov 03 15:43:20 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541231000915 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541231000915 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:33 " "Total CPU time (on all processors): 00:00:33" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541231000915 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1541231000915 ""} diff --git a/timer_pwm/db/timer_pwm.map.rdb b/timer_pwm/db/timer_pwm.map.rdb new file mode 100644 index 0000000..df1ebfb Binary files /dev/null and b/timer_pwm/db/timer_pwm.map.rdb differ diff --git a/timer_pwm/db/timer_pwm.map_bb.cdb b/timer_pwm/db/timer_pwm.map_bb.cdb new file mode 100644 index 0000000..b04dcec Binary files /dev/null and b/timer_pwm/db/timer_pwm.map_bb.cdb differ diff --git a/timer_pwm/db/timer_pwm.map_bb.hdb b/timer_pwm/db/timer_pwm.map_bb.hdb new file mode 100644 index 0000000..9e59b4d Binary files /dev/null and b/timer_pwm/db/timer_pwm.map_bb.hdb differ diff --git a/timer_pwm/db/timer_pwm.map_bb.logdb b/timer_pwm/db/timer_pwm.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/timer_pwm/db/timer_pwm.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/timer_pwm/db/timer_pwm.npp.qmsg b/timer_pwm/db/timer_pwm.npp.qmsg new file mode 100644 index 0000000..fc255d8 --- /dev/null +++ b/timer_pwm/db/timer_pwm.npp.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541231068228 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541231068241 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 03 15:44:28 2018 " "Processing started: Sat Nov 03 15:44:28 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541231068241 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1541231068241 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp timer_pwm -c timer_pwm --netlist_type=sgate " "Command: quartus_npp timer_pwm -c timer_pwm --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1541231068242 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1541231068607 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4565 " "Peak virtual memory: 4565 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541231068621 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 03 15:44:28 2018 " "Processing ended: Sat Nov 03 15:44:28 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541231068621 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541231068621 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541231068621 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1541231068621 ""} diff --git a/timer_pwm/db/timer_pwm.pre_map.hdb b/timer_pwm/db/timer_pwm.pre_map.hdb new file mode 100644 index 0000000..80599d3 Binary files /dev/null and b/timer_pwm/db/timer_pwm.pre_map.hdb differ diff --git a/timer_pwm/db/timer_pwm.root_partition.map.reg_db.cdb b/timer_pwm/db/timer_pwm.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..65263fd Binary files /dev/null and b/timer_pwm/db/timer_pwm.root_partition.map.reg_db.cdb differ diff --git a/timer_pwm/db/timer_pwm.routing.rdb b/timer_pwm/db/timer_pwm.routing.rdb new file mode 100644 index 0000000..3068f7a Binary files /dev/null and b/timer_pwm/db/timer_pwm.routing.rdb differ diff --git a/timer_pwm/db/timer_pwm.rtlv.hdb b/timer_pwm/db/timer_pwm.rtlv.hdb new file mode 100644 index 0000000..8928eae Binary files /dev/null and b/timer_pwm/db/timer_pwm.rtlv.hdb differ diff --git a/timer_pwm/db/timer_pwm.rtlv_sg.cdb b/timer_pwm/db/timer_pwm.rtlv_sg.cdb new file mode 100644 index 0000000..8c425df Binary files /dev/null and b/timer_pwm/db/timer_pwm.rtlv_sg.cdb differ diff --git a/timer_pwm/db/timer_pwm.rtlv_sg_swap.cdb b/timer_pwm/db/timer_pwm.rtlv_sg_swap.cdb new file mode 100644 index 0000000..ed855fd Binary files /dev/null and b/timer_pwm/db/timer_pwm.rtlv_sg_swap.cdb differ diff --git a/timer_pwm/db/timer_pwm.sgate.nvd b/timer_pwm/db/timer_pwm.sgate.nvd new file mode 100644 index 0000000..35116b0 Binary files /dev/null and b/timer_pwm/db/timer_pwm.sgate.nvd differ diff --git a/timer_pwm/db/timer_pwm.sgate_sm.nvd b/timer_pwm/db/timer_pwm.sgate_sm.nvd new file mode 100644 index 0000000..74f2f5c Binary files /dev/null and b/timer_pwm/db/timer_pwm.sgate_sm.nvd differ diff --git a/timer_pwm/db/timer_pwm.sld_design_entry.sci b/timer_pwm/db/timer_pwm.sld_design_entry.sci new file mode 100644 index 0000000..f47c39c Binary files /dev/null and b/timer_pwm/db/timer_pwm.sld_design_entry.sci differ diff --git a/timer_pwm/db/timer_pwm.sld_design_entry_dsc.sci b/timer_pwm/db/timer_pwm.sld_design_entry_dsc.sci new file mode 100644 index 0000000..f47c39c Binary files /dev/null and b/timer_pwm/db/timer_pwm.sld_design_entry_dsc.sci differ diff --git a/timer_pwm/db/timer_pwm.smart_action.txt b/timer_pwm/db/timer_pwm.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/timer_pwm/db/timer_pwm.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/timer_pwm/db/timer_pwm.sta.qmsg b/timer_pwm/db/timer_pwm.sta.qmsg new file mode 100644 index 0000000..b739498 --- /dev/null +++ b/timer_pwm/db/timer_pwm.sta.qmsg @@ -0,0 +1,43 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541231012664 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541231012677 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 03 15:43:32 2018 " "Processing started: Sat Nov 03 15:43:32 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541231012677 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1541231012677 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta timer_pwm -c timer_pwm " "Command: quartus_sta timer_pwm -c timer_pwm" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1541231012677 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #2" { } { } 0 0 "qsta_default_script.tcl version: #2" 0 0 "Timing Analyzer" 0 0 1541231012855 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1541231013072 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1541231013072 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013140 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013140 ""} +{ "Info" "ISTA_SDC_FOUND" "timer_pwm.out.sdc " "Reading SDC File: 'timer_pwm.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1541231013317 ""} +{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "timer_pwm.out.sdc 41 clk_tim port " "Ignored filter at timer_pwm.out.sdc(41): clk_tim could not be matched with a port" { } { { "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" 41 -1 0 } } } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Timing Analyzer" 0 -1 1541231013319 ""} +{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "create_clock timer_pwm.out.sdc 41 Argument is an empty collection " "Ignored create_clock at timer_pwm.out.sdc(41): Argument is an empty collection" { { "Info" "ISTA_SDC_COMMAND" "create_clock -name \{clk_tim\} -period 3.000 -waveform \{ 0.000 1.500 \} \[get_ports \{clk_tim\}\] " "create_clock -name \{clk_tim\} -period 3.000 -waveform \{ 0.000 1.500 \} \[get_ports \{clk_tim\}\]" { } { { "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" 41 -1 0 } } } 0 332050 "%1!s!" 0 0 "Design Software" 0 -1 1541231013320 ""} } { { "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" "" { Text "F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc" 41 -1 0 } } } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Timing Analyzer" 0 -1 1541231013320 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "generated clocks \"derive_pll_clocks -create_base_clocks\" " "No user constrained generated clocks found in the design. Calling \"derive_pll_clocks -create_base_clocks\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013322 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 20.000 -waveform \{0.000 10.000\} -name clk clk " "create_clock -period 20.000 -waveform \{0.000 10.000\} -name clk clk" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1541231013323 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{my_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 4 -duty_cycle 50.00 -name \{my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{my_pll\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 4 -duty_cycle 50.00 -name \{my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1541231013323 ""} } { } 0 332110 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541231013323 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013323 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1541231013323 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1541231013324 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541231013324 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1541231013325 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1541231013335 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.652 " "Worst-case setup slack is 0.652" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013351 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013351 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.652 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.652 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013351 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013351 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.762 " "Worst-case hold slack is 0.762" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013354 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013354 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.762 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.762 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013354 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013354 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013357 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013361 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 2.222 " "Worst-case minimum pulse width slack is 2.222" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.222 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.222 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013364 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.934 0.000 clk " " 9.934 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013364 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013364 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1541231013389 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1541231013411 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1541231013607 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541231013665 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 0.953 " "Worst-case setup slack is 0.953" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013675 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013675 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.953 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.953 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013675 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013675 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.705 " "Worst-case hold slack is 0.705" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013679 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013679 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.705 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.705 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013679 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013679 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013682 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013686 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 2.220 " "Worst-case minimum pulse width slack is 2.220" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.220 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.220 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.943 0.000 clk " " 9.943 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013689 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013689 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1541231013717 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1541231013843 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.141 " "Worst-case setup slack is 3.141" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013848 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013848 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.141 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.141 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013848 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013848 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.304 " "Worst-case hold slack is 0.304" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013856 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013856 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.304 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.304 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013856 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013856 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013861 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1541231013865 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 2.298 " "Worst-case minimum pulse width slack is 2.298" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.298 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.298 0.000 my_pll\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.594 0.000 clk " " 9.594 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1541231013868 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1541231013868 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1541231014280 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1541231014281 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4774 " "Peak virtual memory: 4774 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541231014337 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 03 15:43:34 2018 " "Processing ended: Sat Nov 03 15:43:34 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541231014337 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541231014337 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541231014337 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1541231014337 ""} diff --git a/timer_pwm/db/timer_pwm.sta.rdb b/timer_pwm/db/timer_pwm.sta.rdb new file mode 100644 index 0000000..cb2e49d Binary files /dev/null and b/timer_pwm/db/timer_pwm.sta.rdb differ diff --git a/timer_pwm/db/timer_pwm.sta_cmp.8_slow_1200mv_85c.tdb b/timer_pwm/db/timer_pwm.sta_cmp.8_slow_1200mv_85c.tdb new file mode 100644 index 0000000..2b5bbf4 Binary files /dev/null and b/timer_pwm/db/timer_pwm.sta_cmp.8_slow_1200mv_85c.tdb differ diff --git a/timer_pwm/db/timer_pwm.taw.rdb b/timer_pwm/db/timer_pwm.taw.rdb new file mode 100644 index 0000000..494258b Binary files /dev/null and b/timer_pwm/db/timer_pwm.taw.rdb differ diff --git a/timer_pwm/db/timer_pwm.tis_db_list.ddb b/timer_pwm/db/timer_pwm.tis_db_list.ddb new file mode 100644 index 0000000..ade9cdb Binary files /dev/null and b/timer_pwm/db/timer_pwm.tis_db_list.ddb differ diff --git a/timer_pwm/db/timer_pwm.tiscmp.fast_1200mv_0c.ddb b/timer_pwm/db/timer_pwm.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..fa2d9d2 Binary files /dev/null and b/timer_pwm/db/timer_pwm.tiscmp.fast_1200mv_0c.ddb differ diff --git a/timer_pwm/db/timer_pwm.tiscmp.fastest_slow_1200mv_0c.ddb b/timer_pwm/db/timer_pwm.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..c68abbb Binary files /dev/null and b/timer_pwm/db/timer_pwm.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/timer_pwm/db/timer_pwm.tiscmp.fastest_slow_1200mv_85c.ddb b/timer_pwm/db/timer_pwm.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..3450fe8 Binary files /dev/null and b/timer_pwm/db/timer_pwm.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/timer_pwm/db/timer_pwm.tiscmp.slow_1200mv_0c.ddb b/timer_pwm/db/timer_pwm.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..6f547f9 Binary files /dev/null and b/timer_pwm/db/timer_pwm.tiscmp.slow_1200mv_0c.ddb differ diff --git a/timer_pwm/db/timer_pwm.tiscmp.slow_1200mv_85c.ddb b/timer_pwm/db/timer_pwm.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..d6f0902 Binary files /dev/null and b/timer_pwm/db/timer_pwm.tiscmp.slow_1200mv_85c.ddb differ diff --git a/timer_pwm/db/timer_pwm.vpr.ammdb b/timer_pwm/db/timer_pwm.vpr.ammdb new file mode 100644 index 0000000..156ee99 Binary files /dev/null and b/timer_pwm/db/timer_pwm.vpr.ammdb differ diff --git a/timer_pwm/db/timer_pwm_partition_pins.json b/timer_pwm/db/timer_pwm_partition_pins.json new file mode 100644 index 0000000..5ad858a --- /dev/null +++ b/timer_pwm/db/timer_pwm_partition_pins.json @@ -0,0 +1,149 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "tim_ch[0]", + "strict" : false + }, + { + "name" : "tim_ch[1]", + "strict" : false + }, + { + "name" : "rst_n", + "strict" : false + }, + { + "name" : "tim_ccr1[1]", + "strict" : false + }, + { + "name" : "tim_ccr1[0]", + "strict" : false + }, + { + "name" : "tim_ccr1[3]", + "strict" : false + }, + { + "name" : "tim_ccr1[2]", + "strict" : false + }, + { + "name" : "tim_ccr1[5]", + "strict" : false + }, + { + "name" : "tim_ccr1[4]", + "strict" : false + }, + { + "name" : "tim_ccr1[7]", + "strict" : false + }, + { + "name" : "tim_ccr1[6]", + "strict" : false + }, + { + "name" : "tim_ccr1[9]", + "strict" : false + }, + { + "name" : "tim_ccr1[8]", + "strict" : false + }, + { + "name" : "tim_ccr1[11]", + "strict" : false + }, + { + "name" : "tim_ccr1[10]", + "strict" : false + }, + { + "name" : "tim_ccr1[13]", + "strict" : false + }, + { + "name" : "tim_ccr1[12]", + "strict" : false + }, + { + "name" : "tim_ccr1[15]", + "strict" : false + }, + { + "name" : "tim_ccr1[14]", + "strict" : false + }, + { + "name" : "tim_arr[15]", + "strict" : false + }, + { + "name" : "tim_arr[14]", + "strict" : false + }, + { + "name" : "tim_arr[13]", + "strict" : false + }, + { + "name" : "tim_arr[12]", + "strict" : false + }, + { + "name" : "tim_arr[11]", + "strict" : false + }, + { + "name" : "tim_arr[10]", + "strict" : false + }, + { + "name" : "tim_arr[9]", + "strict" : false + }, + { + "name" : "tim_arr[8]", + "strict" : false + }, + { + "name" : "tim_arr[7]", + "strict" : false + }, + { + "name" : "tim_arr[6]", + "strict" : false + }, + { + "name" : "tim_arr[5]", + "strict" : false + }, + { + "name" : "tim_arr[4]", + "strict" : false + }, + { + "name" : "tim_arr[3]", + "strict" : false + }, + { + "name" : "tim_arr[2]", + "strict" : false + }, + { + "name" : "tim_arr[1]", + "strict" : false + }, + { + "name" : "tim_arr[0]", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/timer_pwm/greybox_tmp/cbx_args.txt b/timer_pwm/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..afdb41c --- /dev/null +++ b/timer_pwm/greybox_tmp/cbx_args.txt @@ -0,0 +1,61 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=1 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=4 +CLK0_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_USED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_UNUSED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=ON +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +areset +inclk +inclk +clk +locked diff --git a/timer_pwm/incremental_db/README b/timer_pwm/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/timer_pwm/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.db_info b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.db_info new file mode 100644 index 0000000..acbcdf3 --- /dev/null +++ b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +Version_Index = 469919232 +Creation_Time = Sat Nov 03 11:59:51 2018 diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.ammdb b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.ammdb new file mode 100644 index 0000000..e975d1b Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.ammdb differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.cdb b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.cdb new file mode 100644 index 0000000..5f137e2 Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.cdb differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.dfp b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.dfp differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.hdb b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.hdb new file mode 100644 index 0000000..c493606 Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.hdb differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.logdb b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.rcfdb b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.rcfdb new file mode 100644 index 0000000..f125e90 Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.cmp.rcfdb differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.cdb b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.cdb new file mode 100644 index 0000000..86001b3 Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.cdb differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.dpi b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.dpi new file mode 100644 index 0000000..c8e6d5c Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.dpi differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.cdb b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..b157235 Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.cdb differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.hb_info b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..998b03b Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.hb_info differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.hdb b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..491eadf Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.hdb differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.sig b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.sig new file mode 100644 index 0000000..61cab53 --- /dev/null +++ b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +1134bd18cd51941af488146b199ddb2a \ No newline at end of file diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hdb b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hdb new file mode 100644 index 0000000..89253c0 Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.hdb differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.kpt b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.kpt new file mode 100644 index 0000000..828ad15 Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.root_partition.map.kpt differ diff --git a/timer_pwm/incremental_db/compiled_partitions/timer_pwm.rrp.hdb b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.rrp.hdb new file mode 100644 index 0000000..c44d3f3 Binary files /dev/null and b/timer_pwm/incremental_db/compiled_partitions/timer_pwm.rrp.hdb differ diff --git a/timer_pwm/ip/.qsys_edit/filters.xml b/timer_pwm/ip/.qsys_edit/filters.xml new file mode 100644 index 0000000..d287b06 --- /dev/null +++ b/timer_pwm/ip/.qsys_edit/filters.xml @@ -0,0 +1,2 @@ + + diff --git a/timer_pwm/ip/.qsys_edit/preferences.xml b/timer_pwm/ip/.qsys_edit/preferences.xml new file mode 100644 index 0000000..430fae8 --- /dev/null +++ b/timer_pwm/ip/.qsys_edit/preferences.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/timer_pwm/ip/my_pll.ppf b/timer_pwm/ip/my_pll.ppf new file mode 100644 index 0000000..70fdbbc --- /dev/null +++ b/timer_pwm/ip/my_pll.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/timer_pwm/ip/my_pll.qip b/timer_pwm/ip/my_pll.qip new file mode 100644 index 0000000..bcfd32c --- /dev/null +++ b/timer_pwm/ip/my_pll.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "my_pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "my_pll_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "my_pll.ppf"] diff --git a/timer_pwm/ip/my_pll.v b/timer_pwm/ip/my_pll.v new file mode 100644 index 0000000..804a11b --- /dev/null +++ b/timer_pwm/ip/my_pll.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: my_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Standard Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module my_pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [0:0] sub_wire2 = 1'h0; + wire [4:0] sub_wire3; + wire sub_wire5; + wire sub_wire0 = inclk0; + wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; + wire [0:0] sub_wire4 = sub_wire3[0:0]; + wire c0 = sub_wire4; + wire locked = sub_wire5; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire1), + .clk (sub_wire3), + .locked (sub_wire5), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 4, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=my_pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "ON", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "150.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "my_pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/timer_pwm/ip/my_pll_bb.v b/timer_pwm/ip/my_pll_bb.v new file mode 100644 index 0000000..fb6ef4e --- /dev/null +++ b/timer_pwm/ip/my_pll_bb.v @@ -0,0 +1,210 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: my_pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Standard Edition +// ************************************************************ + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module my_pll ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "150.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "my_pll.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL my_pll_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/timer_pwm/output_files/timer_pwm.asm.rpt b/timer_pwm/output_files/timer_pwm.asm.rpt new file mode 100644 index 0000000..dd1a5fb --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.asm.rpt @@ -0,0 +1,91 @@ +Assembler report for timer_pwm +Sat Nov 03 15:43:30 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: F:/Code/FPGA/reserve/timer_pwm/output_files/timer_pwm.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Nov 03 15:43:30 2018 ; +; Revision Name ; timer_pwm ; +; Top-level Entity Name ; timer_pwm_top ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-----------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------+ +; F:/Code/FPGA/reserve/timer_pwm/output_files/timer_pwm.sof ; ++-----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Assembler Device Options: F:/Code/FPGA/reserve/timer_pwm/output_files/timer_pwm.sof ; ++----------------+--------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------------------+ +; JTAG usercode ; 0x0008F9B6 ; +; Checksum ; 0x0008F9B6 ; ++----------------+--------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + Info: Processing started: Sat Nov 03 15:43:29 2018 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off timer_pwm -c timer_pwm +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4692 megabytes + Info: Processing ended: Sat Nov 03 15:43:30 2018 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/timer_pwm/output_files/timer_pwm.done b/timer_pwm/output_files/timer_pwm.done new file mode 100644 index 0000000..37a7231 --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.done @@ -0,0 +1 @@ +Sat Nov 03 15:44:29 2018 diff --git a/timer_pwm/output_files/timer_pwm.eda.rpt b/timer_pwm/output_files/timer_pwm.eda.rpt new file mode 100644 index 0000000..ec7c635 --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.eda.rpt @@ -0,0 +1,108 @@ +EDA Netlist Writer report for timer_pwm +Sat Nov 03 15:43:36 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Sat Nov 03 15:43:36 2018 ; +; Revision Name ; timer_pwm ; +; Top-level Entity Name ; timer_pwm_top ; +; Family ; Cyclone IV E ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate functional simulation netlist ; Off ; +; Time scale ; 1 ps ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++---------------------------------------------------------------------------------------+ +; Generated Files ; ++---------------------------------------------------------------------------------------+ +; F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo ; +; F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_0c_slow.vo ; +; F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_min_1200mv_0c_fast.vo ; +; F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm.vo ; +; F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_v_slow.sdo ; +; F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_0c_v_slow.sdo ; +; F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_min_1200mv_0c_v_fast.sdo ; +; F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_v.sdo ; ++---------------------------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + Info: Processing started: Sat Nov 03 15:43:35 2018 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off timer_pwm -c timer_pwm +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file timer_pwm_8_1200mv_85c_slow.vo in folder "F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file timer_pwm_8_1200mv_0c_slow.vo in folder "F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file timer_pwm_min_1200mv_0c_fast.vo in folder "F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file timer_pwm.vo in folder "F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file timer_pwm_8_1200mv_85c_v_slow.sdo in folder "F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file timer_pwm_8_1200mv_0c_v_slow.sdo in folder "F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file timer_pwm_min_1200mv_0c_v_fast.sdo in folder "F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file timer_pwm_v.sdo in folder "F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 4660 megabytes + Info: Processing ended: Sat Nov 03 15:43:36 2018 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/timer_pwm/output_files/timer_pwm.fit.rpt b/timer_pwm/output_files/timer_pwm.fit.rpt new file mode 100644 index 0000000..a1f9b44 --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.fit.rpt @@ -0,0 +1,1581 @@ +Fitter report for timer_pwm +Sat Nov 03 15:43:28 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. PLL Summary + 17. PLL Usage + 18. I/O Assignment Warnings + 19. Fitter Resource Utilization by Entity + 20. Delay Chain Summary + 21. Pad To Core Delay Chain Fanout + 22. Control Signals + 23. Global & Other Fast Signals + 24. Routing Usage Summary + 25. LAB Logic Elements + 26. LAB-wide Signals + 27. LAB Signals Sourced + 28. LAB Signals Sourced Out + 29. LAB Distinct Inputs + 30. I/O Rules Summary + 31. I/O Rules Details + 32. I/O Rules Matrix + 33. Fitter Device Options + 34. Operating Settings and Conditions + 35. Fitter Messages + 36. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Sat Nov 03 15:43:28 2018 ; +; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ; +; Revision Name ; timer_pwm ; +; Top-level Entity Name ; timer_pwm_top ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Total logic elements ; 66 / 10,320 ( < 1 % ) ; +; Total combinational functions ; 51 / 10,320 ( < 1 % ) ; +; Dedicated logic registers ; 51 / 10,320 ( < 1 % ) ; +; Total registers ; 51 ; +; Total pins ; 74 / 180 ( 41 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; Total PLLs ; 1 / 2 ( 50 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP4CE10F17C8 ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.4% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 264 ) ; 0.00 % ( 0 / 264 ) ; 0.00 % ( 0 / 264 ) ; +; -- Achieved ; 0.00 % ( 0 / 264 ) ; 0.00 % ( 0 / 264 ) ; 0.00 % ( 0 / 264 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 252 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 12 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in F:/Code/FPGA/reserve/timer_pwm/output_files/timer_pwm.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 66 / 10,320 ( < 1 % ) ; +; -- Combinational with no register ; 15 ; +; -- Register only ; 15 ; +; -- Combinational with a register ; 36 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 15 ; +; -- 3 input functions ; 16 ; +; -- <=2 input functions ; 20 ; +; -- Register only ; 15 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 21 ; +; -- arithmetic mode ; 30 ; +; ; ; +; Total registers* ; 51 / 11,172 ( < 1 % ) ; +; -- Dedicated logic registers ; 51 / 10,320 ( < 1 % ) ; +; -- I/O registers ; 0 / 852 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 6 / 645 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 74 / 180 ( 41 % ) ; +; -- Clock pins ; 2 / 3 ( 67 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; M9Ks ; 0 / 46 ( 0 % ) ; +; Total block memory bits ; 0 / 423,936 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; PLLs ; 1 / 2 ( 50 % ) ; +; Global signals ; 3 ; +; -- Global clocks ; 3 / 10 ( 30 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.2% / 0.2% / 0.2% ; +; Peak interconnect usage (total/H/V) ; 0.6% / 0.7% / 0.5% ; +; Maximum fan-out ; 50 ; +; Highest non-global fan-out ; 16 ; +; Total fan-out ; 412 ; +; Average fan-out ; 1.49 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 66 / 10320 ( < 1 % ) ; 0 / 10320 ( 0 % ) ; +; -- Combinational with no register ; 15 ; 0 ; +; -- Register only ; 15 ; 0 ; +; -- Combinational with a register ; 36 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 15 ; 0 ; +; -- 3 input functions ; 16 ; 0 ; +; -- <=2 input functions ; 20 ; 0 ; +; -- Register only ; 15 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 21 ; 0 ; +; -- arithmetic mode ; 30 ; 0 ; +; ; ; ; +; Total registers ; 51 ; 0 ; +; -- Dedicated logic registers ; 51 / 10320 ( < 1 % ) ; 0 / 10320 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 6 / 645 ( < 1 % ) ; 0 / 645 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 74 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; 0 / 46 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; PLL ; 0 / 2 ( 0 % ) ; 1 / 2 ( 50 % ) ; +; Clock control block ; 2 / 12 ( 16 % ) ; 1 / 12 ( 8 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 52 ; 2 ; +; -- Registered Input Connections ; 51 ; 0 ; +; -- Output Connections ; 2 ; 52 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 405 ; 61 ; +; -- Registered Connections ; 150 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 54 ; +; -- hard_block:auto_generated_inst ; 54 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 66 ; 2 ; +; -- Output Ports ; 8 ; 2 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; clk ; E1 ; 1 ; 0 ; 11 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; rst_n ; M2 ; 2 ; 0 ; 11 ; 14 ; 2 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[0] ; A15 ; 7 ; 21 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[10] ; M1 ; 2 ; 0 ; 11 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[11] ; E9 ; 7 ; 18 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[12] ; F11 ; 7 ; 23 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[13] ; A10 ; 7 ; 21 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[14] ; D9 ; 7 ; 18 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[15] ; C9 ; 7 ; 18 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[1] ; F10 ; 7 ; 23 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[2] ; B10 ; 7 ; 21 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[3] ; D8 ; 8 ; 13 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[4] ; A8 ; 8 ; 16 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[5] ; C11 ; 7 ; 23 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[6] ; F9 ; 7 ; 23 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[7] ; F8 ; 8 ; 13 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[8] ; B8 ; 8 ; 16 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_arr[9] ; B9 ; 7 ; 16 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[0] ; A14 ; 7 ; 28 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[10] ; D12 ; 7 ; 30 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[11] ; C14 ; 7 ; 32 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[12] ; A11 ; 7 ; 25 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[13] ; B13 ; 7 ; 30 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[14] ; A13 ; 7 ; 30 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[15] ; B11 ; 7 ; 25 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[1] ; D15 ; 6 ; 34 ; 19 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[2] ; C16 ; 6 ; 34 ; 20 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[3] ; E11 ; 7 ; 28 ; 24 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[4] ; B14 ; 7 ; 28 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[5] ; E10 ; 7 ; 28 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[6] ; D11 ; 7 ; 32 ; 24 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[7] ; G11 ; 6 ; 34 ; 20 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[8] ; A12 ; 7 ; 25 ; 24 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_ccr1[9] ; B12 ; 7 ; 25 ; 24 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[0] ; T12 ; 4 ; 25 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[10] ; C8 ; 8 ; 13 ; 24 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[11] ; T15 ; 4 ; 30 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[12] ; L3 ; 2 ; 0 ; 7 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[13] ; M9 ; 4 ; 21 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[14] ; M12 ; 5 ; 34 ; 2 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[15] ; B16 ; 6 ; 34 ; 18 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[16] ; N9 ; 4 ; 21 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[17] ; M6 ; 3 ; 7 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[18] ; T7 ; 3 ; 13 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[19] ; D6 ; 8 ; 3 ; 24 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[1] ; N16 ; 5 ; 34 ; 7 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[20] ; P6 ; 3 ; 7 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[21] ; T10 ; 4 ; 21 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[22] ; K10 ; 4 ; 25 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[23] ; F6 ; 8 ; 11 ; 24 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[24] ; F7 ; 8 ; 11 ; 24 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[25] ; N14 ; 5 ; 34 ; 4 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[26] ; P8 ; 3 ; 16 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[27] ; J2 ; 2 ; 0 ; 10 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[28] ; L4 ; 2 ; 0 ; 6 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[29] ; B7 ; 8 ; 11 ; 24 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[2] ; N5 ; 3 ; 7 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[30] ; P11 ; 4 ; 28 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[31] ; A9 ; 7 ; 16 ; 24 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[3] ; N12 ; 4 ; 32 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[4] ; L8 ; 3 ; 13 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[5] ; L11 ; 4 ; 32 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[6] ; R13 ; 4 ; 28 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[7] ; M11 ; 4 ; 32 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[8] ; A4 ; 8 ; 5 ; 24 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; tim_cr[9] ; R7 ; 3 ; 11 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; ++--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; tim_ch[0] ; D14 ; 7 ; 32 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tim_ch[1] ; C15 ; 6 ; 34 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tim_ch[2] ; N3 ; 3 ; 1 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tim_ch[3] ; B6 ; 8 ; 9 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tim_ch[4] ; P9 ; 4 ; 25 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tim_ch[5] ; R16 ; 5 ; 34 ; 5 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tim_ch[6] ; M7 ; 3 ; 9 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; tim_ch[7] ; T9 ; 4 ; 18 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; C1 ; DIFFIO_L1n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; D2 ; DIFFIO_L2p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; F4 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; H1 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; H2 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; H5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; J3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; H14 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; H13 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; H12 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; F16 ; DIFFIO_R3n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; +; F8 ; DIFFIO_T10p, DATA3 ; Use as regular IO ; tim_arr[7] ; Dual Purpose Pin ; +; B7 ; DIFFIO_T9p, DATA4 ; Use as regular IO ; tim_cr[29] ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++-------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-------------------+---------------+--------------+ +; 1 ; 5 / 17 ( 29 % ) ; 2.5V ; -- ; +; 2 ; 5 / 19 ( 26 % ) ; 2.5V ; -- ; +; 3 ; 9 / 26 ( 35 % ) ; 2.5V ; -- ; +; 4 ; 13 / 27 ( 48 % ) ; 2.5V ; -- ; +; 5 ; 4 / 25 ( 16 % ) ; 2.5V ; -- ; +; 6 ; 6 / 14 ( 43 % ) ; 2.5V ; -- ; +; 7 ; 26 / 26 ( 100 % ) ; 2.5V ; -- ; +; 8 ; 11 / 26 ( 42 % ) ; 2.5V ; -- ; ++----------+-------------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A2 ; 194 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 200 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A4 ; 196 ; 8 ; tim_cr[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A5 ; 192 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A6 ; 188 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 183 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A8 ; 177 ; 8 ; tim_arr[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A9 ; 175 ; 7 ; tim_cr[31] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A10 ; 168 ; 7 ; tim_arr[13] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A11 ; 161 ; 7 ; tim_ccr1[12] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A12 ; 159 ; 7 ; tim_ccr1[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A13 ; 153 ; 7 ; tim_ccr1[14] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A14 ; 155 ; 7 ; tim_ccr1[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A15 ; 167 ; 7 ; tim_arr[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 201 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B4 ; 197 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; 195 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B6 ; 189 ; 8 ; tim_ch[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B7 ; 184 ; 8 ; tim_cr[29] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B8 ; 178 ; 8 ; tim_arr[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B9 ; 176 ; 7 ; tim_arr[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B10 ; 169 ; 7 ; tim_arr[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B11 ; 162 ; 7 ; tim_ccr1[15] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B12 ; 160 ; 7 ; tim_ccr1[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B13 ; 154 ; 7 ; tim_ccr1[13] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B14 ; 156 ; 7 ; tim_ccr1[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B16 ; 141 ; 6 ; tim_cr[15] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; C1 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; C2 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C3 ; 202 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C4 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 187 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; C7 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C8 ; 179 ; 8 ; tim_cr[10] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C9 ; 172 ; 7 ; tim_arr[15] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C10 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C11 ; 163 ; 7 ; tim_arr[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C14 ; 149 ; 7 ; tim_ccr1[11] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; C15 ; 147 ; 6 ; tim_ch[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; C16 ; 146 ; 6 ; tim_ccr1[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; D1 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; D3 ; 203 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D4 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D5 ; 198 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D6 ; 199 ; 8 ; tim_cr[19] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D8 ; 180 ; 8 ; tim_arr[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D9 ; 173 ; 7 ; tim_arr[14] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 151 ; 7 ; tim_ccr1[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D12 ; 152 ; 7 ; tim_ccr1[10] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D13 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; D14 ; 150 ; 7 ; tim_ch[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D15 ; 144 ; 6 ; tim_ccr1[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; D16 ; 143 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 24 ; 1 ; clk ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E5 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E6 ; 191 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E7 ; 190 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; 181 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E9 ; 174 ; 7 ; tim_arr[11] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E10 ; 158 ; 7 ; tim_ccr1[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E11 ; 157 ; 7 ; tim_ccr1[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; E12 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E15 ; 128 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; E16 ; 127 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; F1 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; F4 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; F5 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F6 ; 185 ; 8 ; tim_cr[23] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F7 ; 186 ; 8 ; tim_cr[24] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F8 ; 182 ; 8 ; tim_arr[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F9 ; 165 ; 7 ; tim_arr[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F10 ; 164 ; 7 ; tim_arr[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F11 ; 166 ; 7 ; tim_arr[12] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; F12 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; 138 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F14 ; 142 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; F15 ; 140 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F16 ; 139 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G1 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G2 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 10 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G11 ; 145 ; 6 ; tim_ccr1[7] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G12 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G12 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; 137 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G16 ; 136 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H2 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H3 ; 19 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; H4 ; 18 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; H5 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H12 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; H13 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; H14 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J1 ; 28 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J2 ; 27 ; 2 ; tim_cr[27] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; J3 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 21 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; J5 ; 20 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; J6 ; 29 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J11 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J12 ; 123 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J13 ; 124 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J14 ; 122 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J15 ; 121 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J16 ; 120 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K1 ; 33 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 32 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K5 ; 39 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K6 ; 30 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K8 ; 60 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K9 ; 76 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; K10 ; 87 ; 4 ; tim_cr[22] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; K11 ; 110 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K12 ; 105 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K15 ; 119 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K16 ; 118 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 35 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; 34 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L3 ; 36 ; 2 ; tim_cr[12] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L4 ; 40 ; 2 ; tim_cr[28] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; L5 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L6 ; 31 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L7 ; 65 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L8 ; 68 ; 3 ; tim_cr[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; L9 ; 77 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L10 ; 88 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L11 ; 99 ; 4 ; tim_cr[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; L12 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L13 ; 114 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L14 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; L15 ; 116 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L16 ; 115 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 26 ; 2 ; tim_arr[10] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M2 ; 25 ; 2 ; rst_n ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; 57 ; 3 ; tim_cr[17] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; M7 ; 59 ; 3 ; tim_ch[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; M8 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M9 ; 78 ; 4 ; tim_cr[13] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; M10 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M11 ; 100 ; 4 ; tim_cr[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; M12 ; 103 ; 5 ; tim_cr[14] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M15 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M16 ; 125 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 38 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; 37 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N3 ; 45 ; 3 ; tim_ch[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N4 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N5 ; 55 ; 3 ; tim_cr[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N6 ; 56 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N9 ; 79 ; 4 ; tim_cr[16] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N12 ; 101 ; 4 ; tim_cr[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; N13 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N14 ; 106 ; 5 ; tim_cr[25] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N15 ; 112 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N16 ; 111 ; 5 ; tim_cr[1] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; P1 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P2 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P4 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; 58 ; 3 ; tim_cr[20] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; P7 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 71 ; 3 ; tim_cr[26] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; P9 ; 89 ; 4 ; tim_ch[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; P10 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P11 ; 90 ; 4 ; tim_cr[30] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P14 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P15 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 108 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R1 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; 47 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R4 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R5 ; 61 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R6 ; 63 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R7 ; 66 ; 3 ; tim_cr[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R8 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R9 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R10 ; 80 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R12 ; 85 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R13 ; 91 ; 4 ; tim_cr[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; R14 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; 109 ; 5 ; tim_ch[5] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; T1 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T2 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T3 ; 48 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T4 ; 54 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T5 ; 62 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T6 ; 64 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T7 ; 67 ; 3 ; tim_cr[18] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T8 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T9 ; 75 ; 4 ; tim_ch[7] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T10 ; 81 ; 4 ; tim_cr[21] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T11 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T12 ; 86 ; 4 ; tim_cr[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T13 ; 92 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T14 ; 95 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T15 ; 96 ; 4 ; tim_cr[11] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; T16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++----------------------------------------------------------------------------------------------------------+ +; PLL Summary ; ++-------------------------------+--------------------------------------------------------------------------+ +; Name ; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|pll1 ; ++-------------------------------+--------------------------------------------------------------------------+ +; SDC pin name ; my_pll|altpll_component|auto_generated|pll1 ; +; PLL mode ; Normal ; +; Compensate clock ; clock0 ; +; Compensated input/output pins ; -- ; +; Switchover type ; -- ; +; Input frequency 0 ; 50.0 MHz ; +; Input frequency 1 ; -- ; +; Nominal PFD frequency ; 50.0 MHz ; +; Nominal VCO frequency ; 600.0 MHz ; +; VCO post scale K counter ; 2 ; +; VCO frequency control ; Auto ; +; VCO phase shift step ; 208 ps ; +; VCO multiply ; -- ; +; VCO divide ; -- ; +; Freq min lock ; 25.0 MHz ; +; Freq max lock ; 54.18 MHz ; +; M VCO Tap ; 0 ; +; M Initial ; 1 ; +; M value ; 12 ; +; N value ; 1 ; +; Charge pump current ; setting 1 ; +; Loop filter resistance ; setting 27 ; +; Loop filter capacitance ; setting 0 ; +; Bandwidth ; 680 kHz to 980 kHz ; +; Bandwidth type ; Medium ; +; Real time reconfigurable ; Off ; +; Scan chain MIF file ; -- ; +; Preserve PLL counter order ; Off ; +; PLL location ; PLL_1 ; +; Inclk0 signal ; clk ; +; Inclk1 signal ; -- ; +; Inclk0 signal type ; Dedicated Pin ; +; Inclk1 signal type ; -- ; ++-------------------------------+--------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Usage ; ++--------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+----------------------------------------------------+ +; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ; ++--------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+----------------------------------------------------+ +; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|wire_pll1_clk[0] ; clock0 ; 4 ; 1 ; 200.0 MHz ; 0 (0 ps) ; 15.00 (208 ps) ; 50/50 ; C0 ; 3 ; 2/1 Odd ; -- ; 1 ; 0 ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; ++--------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+----------------------------------------------------+ + + ++----------------------------------------------+ +; I/O Assignment Warnings ; ++--------------+-------------------------------+ +; Pin Name ; Reason ; ++--------------+-------------------------------+ +; tim_cr[0] ; Incomplete set of assignments ; +; tim_cr[1] ; Incomplete set of assignments ; +; tim_cr[2] ; Incomplete set of assignments ; +; tim_cr[3] ; Incomplete set of assignments ; +; tim_cr[4] ; Incomplete set of assignments ; +; tim_cr[5] ; Incomplete set of assignments ; +; tim_cr[6] ; Incomplete set of assignments ; +; tim_cr[7] ; Incomplete set of assignments ; +; tim_cr[8] ; Incomplete set of assignments ; +; tim_cr[9] ; Incomplete set of assignments ; +; tim_cr[10] ; Incomplete set of assignments ; +; tim_cr[11] ; Incomplete set of assignments ; +; tim_cr[12] ; Incomplete set of assignments ; +; tim_cr[13] ; Incomplete set of assignments ; +; tim_cr[14] ; Incomplete set of assignments ; +; tim_cr[15] ; Incomplete set of assignments ; +; tim_cr[16] ; Incomplete set of assignments ; +; tim_cr[17] ; Incomplete set of assignments ; +; tim_cr[18] ; Incomplete set of assignments ; +; tim_cr[19] ; Incomplete set of assignments ; +; tim_cr[20] ; Incomplete set of assignments ; +; tim_cr[21] ; Incomplete set of assignments ; +; tim_cr[22] ; Incomplete set of assignments ; +; tim_cr[23] ; Incomplete set of assignments ; +; tim_cr[24] ; Incomplete set of assignments ; +; tim_cr[25] ; Incomplete set of assignments ; +; tim_cr[26] ; Incomplete set of assignments ; +; tim_cr[27] ; Incomplete set of assignments ; +; tim_cr[28] ; Incomplete set of assignments ; +; tim_cr[29] ; Incomplete set of assignments ; +; tim_cr[30] ; Incomplete set of assignments ; +; tim_cr[31] ; Incomplete set of assignments ; +; tim_ch[0] ; Incomplete set of assignments ; +; tim_ch[1] ; Incomplete set of assignments ; +; tim_ch[2] ; Incomplete set of assignments ; +; tim_ch[3] ; Incomplete set of assignments ; +; tim_ch[4] ; Incomplete set of assignments ; +; tim_ch[5] ; Incomplete set of assignments ; +; tim_ch[6] ; Incomplete set of assignments ; +; tim_ch[7] ; Incomplete set of assignments ; +; rst_n ; Incomplete set of assignments ; +; clk ; Incomplete set of assignments ; +; tim_ccr1[1] ; Incomplete set of assignments ; +; tim_ccr1[0] ; Incomplete set of assignments ; +; tim_ccr1[3] ; Incomplete set of assignments ; +; tim_ccr1[2] ; Incomplete set of assignments ; +; tim_ccr1[5] ; Incomplete set of assignments ; +; tim_ccr1[4] ; Incomplete set of assignments ; +; tim_ccr1[7] ; Incomplete set of assignments ; +; tim_ccr1[6] ; Incomplete set of assignments ; +; tim_ccr1[9] ; Incomplete set of assignments ; +; tim_ccr1[8] ; Incomplete set of assignments ; +; tim_ccr1[11] ; Incomplete set of assignments ; +; tim_ccr1[10] ; Incomplete set of assignments ; +; tim_ccr1[13] ; Incomplete set of assignments ; +; tim_ccr1[12] ; Incomplete set of assignments ; +; tim_ccr1[15] ; Incomplete set of assignments ; +; tim_ccr1[14] ; Incomplete set of assignments ; +; tim_arr[15] ; Incomplete set of assignments ; +; tim_arr[14] ; Incomplete set of assignments ; +; tim_arr[13] ; Incomplete set of assignments ; +; tim_arr[12] ; Incomplete set of assignments ; +; tim_arr[11] ; Incomplete set of assignments ; +; tim_arr[10] ; Incomplete set of assignments ; +; tim_arr[9] ; Incomplete set of assignments ; +; tim_arr[8] ; Incomplete set of assignments ; +; tim_arr[7] ; Incomplete set of assignments ; +; tim_arr[6] ; Incomplete set of assignments ; +; tim_arr[5] ; Incomplete set of assignments ; +; tim_arr[4] ; Incomplete set of assignments ; +; tim_arr[3] ; Incomplete set of assignments ; +; tim_arr[2] ; Incomplete set of assignments ; +; tim_arr[1] ; Incomplete set of assignments ; +; tim_arr[0] ; Incomplete set of assignments ; +; tim_cr[0] ; Missing location assignment ; +; tim_cr[1] ; Missing location assignment ; +; tim_cr[2] ; Missing location assignment ; +; tim_cr[3] ; Missing location assignment ; +; tim_cr[4] ; Missing location assignment ; +; tim_cr[5] ; Missing location assignment ; +; tim_cr[6] ; Missing location assignment ; +; tim_cr[7] ; Missing location assignment ; +; tim_cr[8] ; Missing location assignment ; +; tim_cr[9] ; Missing location assignment ; +; tim_cr[10] ; Missing location assignment ; +; tim_cr[11] ; Missing location assignment ; +; tim_cr[12] ; Missing location assignment ; +; tim_cr[13] ; Missing location assignment ; +; tim_cr[14] ; Missing location assignment ; +; tim_cr[15] ; Missing location assignment ; +; tim_cr[16] ; Missing location assignment ; +; tim_cr[17] ; Missing location assignment ; +; tim_cr[18] ; Missing location assignment ; +; tim_cr[19] ; Missing location assignment ; +; tim_cr[20] ; Missing location assignment ; +; tim_cr[21] ; Missing location assignment ; +; tim_cr[22] ; Missing location assignment ; +; tim_cr[23] ; Missing location assignment ; +; tim_cr[24] ; Missing location assignment ; +; tim_cr[25] ; Missing location assignment ; +; tim_cr[26] ; Missing location assignment ; +; tim_cr[27] ; Missing location assignment ; +; tim_cr[28] ; Missing location assignment ; +; tim_cr[29] ; Missing location assignment ; +; tim_cr[30] ; Missing location assignment ; +; tim_cr[31] ; Missing location assignment ; +; tim_ch[0] ; Missing location assignment ; +; tim_ch[1] ; Missing location assignment ; +; tim_ch[2] ; Missing location assignment ; +; tim_ch[3] ; Missing location assignment ; +; tim_ch[4] ; Missing location assignment ; +; tim_ch[5] ; Missing location assignment ; +; tim_ch[6] ; Missing location assignment ; +; tim_ch[7] ; Missing location assignment ; +; rst_n ; Missing location assignment ; +; clk ; Missing location assignment ; +; tim_ccr1[1] ; Missing location assignment ; +; tim_ccr1[0] ; Missing location assignment ; +; tim_ccr1[3] ; Missing location assignment ; +; tim_ccr1[2] ; Missing location assignment ; +; tim_ccr1[5] ; Missing location assignment ; +; tim_ccr1[4] ; Missing location assignment ; +; tim_ccr1[7] ; Missing location assignment ; +; tim_ccr1[6] ; Missing location assignment ; +; tim_ccr1[9] ; Missing location assignment ; +; tim_ccr1[8] ; Missing location assignment ; +; tim_ccr1[11] ; Missing location assignment ; +; tim_ccr1[10] ; Missing location assignment ; +; tim_ccr1[13] ; Missing location assignment ; +; tim_ccr1[12] ; Missing location assignment ; +; tim_ccr1[15] ; Missing location assignment ; +; tim_ccr1[14] ; Missing location assignment ; +; tim_arr[15] ; Missing location assignment ; +; tim_arr[14] ; Missing location assignment ; +; tim_arr[13] ; Missing location assignment ; +; tim_arr[12] ; Missing location assignment ; +; tim_arr[11] ; Missing location assignment ; +; tim_arr[10] ; Missing location assignment ; +; tim_arr[9] ; Missing location assignment ; +; tim_arr[8] ; Missing location assignment ; +; tim_arr[7] ; Missing location assignment ; +; tim_arr[6] ; Missing location assignment ; +; tim_arr[5] ; Missing location assignment ; +; tim_arr[4] ; Missing location assignment ; +; tim_arr[3] ; Missing location assignment ; +; tim_arr[2] ; Missing location assignment ; +; tim_arr[1] ; Missing location assignment ; +; tim_arr[0] ; Missing location assignment ; ++--------------+-------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------+----------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------+----------------+--------------+ +; |timer_pwm_top ; 66 (0) ; 51 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 ; 0 ; 15 (0) ; 15 (0) ; 36 (0) ; |timer_pwm_top ; timer_pwm_top ; work ; +; |my_pll:my_pll| ; 2 (0) ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 1 (0) ; |timer_pwm_top|my_pll:my_pll ; my_pll ; work ; +; |altpll:altpll_component| ; 2 (0) ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 1 (0) ; |timer_pwm_top|my_pll:my_pll|altpll:altpll_component ; altpll ; work ; +; |my_pll_altpll1:auto_generated| ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; |timer_pwm_top|my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated ; my_pll_altpll1 ; work ; +; |timer_pwm:timer_pwm| ; 64 (64) ; 50 (50) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 15 (15) ; 35 (35) ; |timer_pwm_top|timer_pwm:timer_pwm ; timer_pwm ; work ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------------------------------------------------------------+----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++--------------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++--------------+----------+---------------+---------------+-----------------------+-----+------+ +; tim_cr[0] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[1] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[2] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[3] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[4] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[5] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[6] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[7] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[8] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[9] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[10] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[11] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[12] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[13] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[14] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[15] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[16] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[17] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[18] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[19] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[20] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[21] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[22] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[23] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[24] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[25] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[26] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[27] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[28] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[29] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[30] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_cr[31] ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_ch[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tim_ch[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tim_ch[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tim_ch[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tim_ch[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tim_ch[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tim_ch[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; tim_ch[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; rst_n ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; clk ; Input ; -- ; -- ; -- ; -- ; -- ; +; tim_ccr1[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_ccr1[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_ccr1[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; tim_ccr1[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; tim_ccr1[5] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; tim_ccr1[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_ccr1[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_ccr1[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_ccr1[9] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_ccr1[8] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; tim_ccr1[11] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_ccr1[10] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_ccr1[13] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_ccr1[12] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_ccr1[15] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_ccr1[14] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_arr[15] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; tim_arr[14] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_arr[13] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_arr[12] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; tim_arr[11] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_arr[10] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; tim_arr[9] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_arr[8] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; tim_arr[7] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; tim_arr[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_arr[5] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_arr[4] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_arr[3] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_arr[2] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; tim_arr[1] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; +; tim_arr[0] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ; ++--------------+----------+---------------+---------------+-----------------------+-----+------+ + + ++--------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++--------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++--------------------------------------------------+-------------------+---------+ +; tim_cr[0] ; ; ; +; tim_cr[1] ; ; ; +; tim_cr[2] ; ; ; +; tim_cr[3] ; ; ; +; tim_cr[4] ; ; ; +; tim_cr[5] ; ; ; +; tim_cr[6] ; ; ; +; tim_cr[7] ; ; ; +; tim_cr[8] ; ; ; +; tim_cr[9] ; ; ; +; tim_cr[10] ; ; ; +; tim_cr[11] ; ; ; +; tim_cr[12] ; ; ; +; tim_cr[13] ; ; ; +; tim_cr[14] ; ; ; +; tim_cr[15] ; ; ; +; tim_cr[16] ; ; ; +; tim_cr[17] ; ; ; +; tim_cr[18] ; ; ; +; tim_cr[19] ; ; ; +; tim_cr[20] ; ; ; +; tim_cr[21] ; ; ; +; tim_cr[22] ; ; ; +; tim_cr[23] ; ; ; +; tim_cr[24] ; ; ; +; tim_cr[25] ; ; ; +; tim_cr[26] ; ; ; +; tim_cr[27] ; ; ; +; tim_cr[28] ; ; ; +; tim_cr[29] ; ; ; +; tim_cr[30] ; ; ; +; tim_cr[31] ; ; ; +; rst_n ; ; ; +; clk ; ; ; +; tim_ccr1[1] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[1] ; 0 ; 6 ; +; tim_ccr1[0] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[0] ; 0 ; 6 ; +; tim_ccr1[3] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[3]~feeder ; 1 ; 6 ; +; tim_ccr1[2] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[2] ; 1 ; 6 ; +; tim_ccr1[5] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[5]~feeder ; 1 ; 6 ; +; tim_ccr1[4] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[4] ; 0 ; 6 ; +; tim_ccr1[7] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[7]~feeder ; 0 ; 6 ; +; tim_ccr1[6] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[6] ; 0 ; 6 ; +; tim_ccr1[9] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[9]~feeder ; 0 ; 6 ; +; tim_ccr1[8] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[8] ; 1 ; 6 ; +; tim_ccr1[11] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[11] ; 0 ; 6 ; +; tim_ccr1[10] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[10] ; 0 ; 6 ; +; tim_ccr1[13] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[13]~feeder ; 0 ; 6 ; +; tim_ccr1[12] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[12] ; 0 ; 6 ; +; tim_ccr1[15] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[15]~feeder ; 0 ; 6 ; +; tim_ccr1[14] ; ; ; +; - timer_pwm:timer_pwm|r_tim_ccr1[14] ; 0 ; 6 ; +; tim_arr[15] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[15]~feeder ; 1 ; 6 ; +; tim_arr[14] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[14]~feeder ; 0 ; 6 ; +; tim_arr[13] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[13] ; 0 ; 6 ; +; tim_arr[12] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[12] ; 1 ; 6 ; +; tim_arr[11] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[11]~feeder ; 0 ; 6 ; +; tim_arr[10] ; ; ; +; tim_arr[9] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[9] ; 0 ; 6 ; +; tim_arr[8] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[8] ; 1 ; 6 ; +; tim_arr[7] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[7] ; 1 ; 6 ; +; tim_arr[6] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[6] ; 0 ; 6 ; +; tim_arr[5] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[5] ; 0 ; 6 ; +; tim_arr[4] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[4]~feeder ; 0 ; 6 ; +; tim_arr[3] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[3] ; 0 ; 6 ; +; tim_arr[2] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[2]~feeder ; 0 ; 6 ; +; tim_arr[1] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[1] ; 1 ; 6 ; +; tim_arr[0] ; ; ; +; - timer_pwm:timer_pwm|r_tim_arr[0] ; 1 ; 6 ; ++--------------------------------------------------+-------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++--------------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++--------------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; clk ; PIN_E1 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|locked ; LCCOMB_X1_Y8_N14 ; 48 ; Async. clear ; yes ; Global Clock ; GCLK0 ; -- ; +; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|wire_pll1_clk[0] ; PLL_1 ; 50 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; +; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|wire_pll1_locked ; PLL_1 ; 2 ; Clock ; no ; -- ; -- ; -- ; +; rst_n ; PIN_M2 ; 2 ; Async. clear ; yes ; Global Clock ; GCLK4 ; -- ; +; timer_pwm:timer_pwm|LessThan0~30 ; LCCOMB_X24_Y21_N30 ; 16 ; Sync. clear ; no ; -- ; -- ; -- ; +; timer_pwm:timer_pwm|tim_ch[0]~0 ; LCCOMB_X28_Y21_N14 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; ++--------------------------------------------------------------------------------------+--------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++--------------------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++--------------------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|locked ; LCCOMB_X1_Y8_N14 ; 48 ; 0 ; Global Clock ; GCLK0 ; -- ; +; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|wire_pll1_clk[0] ; PLL_1 ; 50 ; 0 ; Global Clock ; GCLK3 ; -- ; +; rst_n ; PIN_M2 ; 2 ; 0 ; Global Clock ; GCLK4 ; -- ; ++--------------------------------------------------------------------------------------+------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+-----------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+-----------------------+ +; Block interconnects ; 88 / 32,401 ( < 1 % ) ; +; C16 interconnects ; 2 / 1,326 ( < 1 % ) ; +; C4 interconnects ; 35 / 21,816 ( < 1 % ) ; +; Direct links ; 30 / 32,401 ( < 1 % ) ; +; Global clocks ; 3 / 10 ( 30 % ) ; +; Local interconnects ; 42 / 10,320 ( < 1 % ) ; +; R24 interconnects ; 5 / 1,289 ( < 1 % ) ; +; R4 interconnects ; 48 / 28,186 ( < 1 % ) ; ++-----------------------+-----------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 11.00) ; Number of LABs (Total = 6) ; ++---------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 1 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 1 ; +; 15 ; 0 ; +; 16 ; 2 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 2.17) ; Number of LABs (Total = 6) ; ++------------------------------------+-----------------------------+ +; 1 Async. clear ; 6 ; +; 1 Clock ; 6 ; +; 1 Sync. clear ; 1 ; ++------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 16.50) ; Number of LABs (Total = 6) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 1 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 1 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 1 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 1 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 0 ; +; 29 ; 0 ; +; 30 ; 0 ; +; 31 ; 0 ; +; 32 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 5.00) ; Number of LABs (Total = 6) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 14.50) ; Number of LABs (Total = 6) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 1 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 1 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 0 ; +; 29 ; 0 ; +; 30 ; 0 ; +; 31 ; 0 ; +; 32 ; 0 ; +; 33 ; 0 ; +; 34 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 ; 0 ; 0 ; 74 ; 74 ; 0 ; 8 ; 0 ; 0 ; 66 ; 0 ; 8 ; 66 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 74 ; 74 ; 74 ; 74 ; 74 ; 0 ; 74 ; 74 ; 0 ; 0 ; 74 ; 66 ; 74 ; 74 ; 8 ; 74 ; 66 ; 8 ; 74 ; 74 ; 74 ; 66 ; 74 ; 74 ; 74 ; 74 ; 74 ; 0 ; 74 ; 74 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; tim_cr[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[16] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[17] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[18] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[19] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[20] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[21] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[22] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[23] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[24] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[25] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[26] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[27] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[28] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[29] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[30] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_cr[31] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ch[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ch[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ch[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ch[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ch[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ch[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ch[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ch[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; rst_n ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; clk ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_ccr1[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tim_arr[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 C ; +; High Junction Temperature ; 85 C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119006): Selected device EP4CE10F17C8 for design "timer_pwm" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (15535): Implemented PLL "my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|pll1" as Cyclone IV E PLL type File: F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v Line: 50 + Info (15099): Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|wire_pll1_clk[0] port File: F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v Line: 50 +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE6F17C8 is compatible + Info (176445): Device EP4CE15F17C8 is compatible + Info (176445): Device EP4CE22F17C8 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 74 pins of 74 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Info (332104): Reading SDC File: 'timer_pwm.out.sdc' +Warning (332174): Ignored filter at timer_pwm.out.sdc(41): clk_tim could not be matched with a port File: F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc Line: 41 +Warning (332049): Ignored create_clock at timer_pwm.out.sdc(41): Argument is an empty collection File: F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc Line: 41 + Info (332050): create_clock -name {clk_tim} -period 3.000 -waveform { 0.000 1.500 } [get_ports {clk_tim}] File: F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc Line: 41 +Info (332144): No user constrained generated clocks found in the design +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_1) File: F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v Line: 92 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info (176353): Automatically promoted node rst_n~input (placed in PIN M2 (CLK2, DIFFCLK_1p)) File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 15 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info (176353): Automatically promoted node my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|locked File: F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v Line: 39 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 72 (unused VREF, 2.5V VCCIO, 64 input, 8 output, 0 bidirectional) + Info (176212): I/O standards used: 2.5 V. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 12 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 18 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 27 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 25 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 13 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 26 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.14 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 +Info (144001): Generated suppressed messages file F:/Code/FPGA/reserve/timer_pwm/output_files/timer_pwm.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 5566 megabytes + Info: Processing ended: Sat Nov 03 15:43:28 2018 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:08 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in F:/Code/FPGA/reserve/timer_pwm/output_files/timer_pwm.fit.smsg. + + diff --git a/timer_pwm/output_files/timer_pwm.fit.smsg b/timer_pwm/output_files/timer_pwm.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/timer_pwm/output_files/timer_pwm.fit.summary b/timer_pwm/output_files/timer_pwm.fit.summary new file mode 100644 index 0000000..81cf83c --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Sat Nov 03 15:43:28 2018 +Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Standard Edition +Revision Name : timer_pwm +Top-level Entity Name : timer_pwm_top +Family : Cyclone IV E +Device : EP4CE10F17C8 +Timing Models : Final +Total logic elements : 66 / 10,320 ( < 1 % ) + Total combinational functions : 51 / 10,320 ( < 1 % ) + Dedicated logic registers : 51 / 10,320 ( < 1 % ) +Total registers : 51 +Total pins : 74 / 180 ( 41 % ) +Total virtual pins : 0 +Total memory bits : 0 / 423,936 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 46 ( 0 % ) +Total PLLs : 1 / 2 ( 50 % ) diff --git a/timer_pwm/output_files/timer_pwm.flow.rpt b/timer_pwm/output_files/timer_pwm.flow.rpt new file mode 100644 index 0000000..321667f --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.flow.rpt @@ -0,0 +1,144 @@ +Flow report for timer_pwm +Sat Nov 03 15:43:36 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Sat Nov 03 15:43:36 2018 ; +; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ; +; Revision Name ; timer_pwm ; +; Top-level Entity Name ; timer_pwm_top ; +; Family ; Cyclone IV E ; +; Device ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Total logic elements ; 66 / 10,320 ( < 1 % ) ; +; Total combinational functions ; 51 / 10,320 ( < 1 % ) ; +; Dedicated logic registers ; 51 / 10,320 ( < 1 % ) ; +; Total registers ; 51 ; +; Total pins ; 74 / 180 ( 41 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 423,936 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ; +; Total PLLs ; 1 / 2 ( 50 % ) ; ++------------------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 11/03/2018 15:43:07 ; +; Main task ; Compilation ; +; Revision Name ; timer_pwm ; ++-------------------+---------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++--------------------------------------+----------------------------------------+---------------+---------------+------------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++--------------------------------------+----------------------------------------+---------------+---------------+------------------+ +; COMPILER_SIGNATURE_ID ; 93383153531551.154123098614980 ; -- ; -- ; -- ; +; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; my_pll_tb ; +; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; timer_pwm_top_tb ; +; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; timer_pwm_top_tb ; -- ; -- ; eda_simulation ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; +; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ; +; EDA_TEST_BENCH_FILE ; testbench/my_pll_tb.v ; -- ; -- ; my_pll_tb ; +; EDA_TEST_BENCH_FILE ; testbench/timer_pwm_top_tb.v ; -- ; -- ; timer_pwm_top_tb ; +; EDA_TEST_BENCH_MODULE_NAME ; my_pll_tb ; -- ; -- ; my_pll_tb ; +; EDA_TEST_BENCH_MODULE_NAME ; timer_pwm_top_tb ; -- ; -- ; timer_pwm_top_tb ; +; EDA_TEST_BENCH_NAME ; my_pll_tb ; -- ; -- ; eda_simulation ; +; EDA_TEST_BENCH_NAME ; timer_pwm_top_tb ; -- ; -- ; eda_simulation ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; ip/my_pll_bb.v ; -- ; -- ; -- ; +; MISC_FILE ; ip/my_pll.ppf ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; timer_pwm_top ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; timer_pwm_top ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; timer_pwm_top ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; TOP_LEVEL_ENTITY ; timer_pwm_top ; timer_pwm ; -- ; -- ; ++--------------------------------------+----------------------------------------+---------------+---------------+------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:14 ; 1.0 ; 4791 MB ; 00:00:33 ; +; Fitter ; 00:00:06 ; 1.0 ; 5566 MB ; 00:00:07 ; +; Assembler ; 00:00:01 ; 1.0 ; 4692 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:02 ; 1.0 ; 4774 MB ; 00:00:02 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4660 MB ; 00:00:01 ; +; Total ; 00:00:24 ; -- ; -- ; 00:00:44 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; Timing Analyzer ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; +; EDA Netlist Writer ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ; ++----------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off timer_pwm -c timer_pwm +quartus_fit --read_settings_files=off --write_settings_files=off timer_pwm -c timer_pwm +quartus_asm --read_settings_files=off --write_settings_files=off timer_pwm -c timer_pwm +quartus_sta timer_pwm -c timer_pwm +quartus_eda --read_settings_files=off --write_settings_files=off timer_pwm -c timer_pwm + + + diff --git a/timer_pwm/output_files/timer_pwm.jdi b/timer_pwm/output_files/timer_pwm.jdi new file mode 100644 index 0000000..251b921 --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/timer_pwm/output_files/timer_pwm.map.rpt b/timer_pwm/output_files/timer_pwm.map.rpt new file mode 100644 index 0000000..1863334 --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.map.rpt @@ -0,0 +1,845 @@ +Analysis & Synthesis report for timer_pwm +Sat Nov 03 15:43:20 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis IP Cores Summary + 9. General Register Statistics + 10. Multiplexer Restructuring Statistics (Restructuring Performed) + 11. Parameter Settings for User Entity Instance: my_pll:my_pll|altpll:altpll_component + 12. altpll Parameter Settings by Entity Instance + 13. Port Connectivity Checks: "timer_pwm:timer_pwm" + 14. Post-Synthesis Netlist Statistics for Top Partition + 15. Elapsed Time Per Partition + 16. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sat Nov 03 15:43:20 2018 ; +; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ; +; Revision Name ; timer_pwm ; +; Top-level Entity Name ; timer_pwm_top ; +; Family ; Cyclone IV E ; +; Total logic elements ; 83 ; +; Total combinational functions ; 50 ; +; Dedicated logic registers ; 51 ; +; Total registers ; 51 ; +; Total pins ; 74 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 1 ; ++------------------------------------+-------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP4CE10F17C8 ; ; +; Top-level entity name ; timer_pwm_top ; timer_pwm ; +; Family name ; Cyclone IV E ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.0% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+ +; timer_pwm.v ; yes ; User Verilog HDL File ; F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v ; ; +; ip/my_pll.v ; yes ; User Wizard-Generated File ; F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v ; ; +; rtl/timer_pwm_top.v ; yes ; User Verilog HDL File ; F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v ; ; +; altpll.tdf ; yes ; Megafunction ; d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf ; ; +; aglobal180.inc ; yes ; Megafunction ; d:/intelfpga/18.0/quartus/libraries/megafunctions/aglobal180.inc ; ; +; stratix_pll.inc ; yes ; Megafunction ; d:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_pll.inc ; ; +; stratixii_pll.inc ; yes ; Megafunction ; d:/intelfpga/18.0/quartus/libraries/megafunctions/stratixii_pll.inc ; ; +; cycloneii_pll.inc ; yes ; Megafunction ; d:/intelfpga/18.0/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; +; db/my_pll_altpll1.v ; yes ; Auto-Generated Megafunction ; F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v ; ; ++----------------------------------+-----------------+------------------------------+---------------------------------------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+--------------------------------------------------------------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+--------------------------------------------------------------------------------------+ +; Estimated Total logic elements ; 83 ; +; ; ; +; Total combinational functions ; 50 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 15 ; +; -- 3 input functions ; 16 ; +; -- <=2 input functions ; 19 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 20 ; +; -- arithmetic mode ; 30 ; +; ; ; +; Total registers ; 51 ; +; -- Dedicated logic registers ; 51 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 74 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Total PLLs ; 1 ; +; -- PLLs ; 1 ; +; ; ; +; Maximum fan-out node ; my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated|wire_pll1_clk[0] ; +; Maximum fan-out ; 53 ; +; Total fan-out ; 391 ; +; Average fan-out ; 1.56 ; ++---------------------------------------------+--------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------+----------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------+----------------+--------------+ +; |timer_pwm_top ; 50 (0) ; 51 (0) ; 0 ; 0 ; 0 ; 0 ; 74 ; 0 ; |timer_pwm_top ; timer_pwm_top ; work ; +; |my_pll:my_pll| ; 1 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |timer_pwm_top|my_pll:my_pll ; my_pll ; work ; +; |altpll:altpll_component| ; 1 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |timer_pwm_top|my_pll:my_pll|altpll:altpll_component ; altpll ; work ; +; |my_pll_altpll1:auto_generated| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |timer_pwm_top|my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated ; my_pll_altpll1 ; work ; +; |timer_pwm:timer_pwm| ; 49 (49) ; 50 (50) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |timer_pwm_top|timer_pwm:timer_pwm ; timer_pwm ; work ; ++------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------+----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+------------------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+------------------------------+-----------------+ +; Altera ; ALTPLL ; 18.0 ; N/A ; N/A ; |timer_pwm_top|my_pll:my_pll ; ip/my_pll.v ; ++--------+--------------+---------+--------------+--------------+------------------------------+-----------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 51 ; +; Number of registers using Synchronous Clear ; 16 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 49 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 2 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+ +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |timer_pwm_top|timer_pwm:timer_pwm|tim_ch[0] ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+ + + ++------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: my_pll:my_pll|altpll:altpll_component ; ++-------------------------------+--------------------------+-------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+--------------------------+-------------------------+ +; OPERATION_MODE ; NORMAL ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; LPM_HINT ; CBX_MODULE_PREFIX=my_pll ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; ON ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 1 ; Untyped ; +; CLK1_MULTIPLY_BY ; 1 ; Untyped ; +; CLK0_MULTIPLY_BY ; 4 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 1 ; Untyped ; +; CLK1_DIVIDE_BY ; 1 ; Untyped ; +; CLK0_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Untyped ; +; CLK1_DUTY_CYCLE ; 50 ; Untyped ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK2 ; PORT_UNUSED ; Untyped ; +; PORT_CLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_USED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_USED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; my_pll_altpll1 ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+--------------------------+-------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------+ +; altpll Parameter Settings by Entity Instance ; ++-------------------------------+---------------------------------------+ +; Name ; Value ; ++-------------------------------+---------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; my_pll:my_pll|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 20000 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; ++-------------------------------+---------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "timer_pwm:timer_pwm" ; ++--------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; tim_ch ; Output ; Warning ; Output or bidir port (2 bits) is smaller than the port expression (8 bits) it drives. The 6 most-significant bit(s) in the port expression will be connected to GND. ; ++--------+--------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 74 ; +; cycloneiii_ff ; 51 ; +; CLR ; 33 ; +; CLR SCLR ; 16 ; +; ENA ; 2 ; +; cycloneiii_lcell_comb ; 51 ; +; arith ; 30 ; +; 2 data inputs ; 15 ; +; 3 data inputs ; 15 ; +; normal ; 21 ; +; 0 data inputs ; 1 ; +; 1 data inputs ; 2 ; +; 2 data inputs ; 2 ; +; 3 data inputs ; 1 ; +; 4 data inputs ; 15 ; +; cycloneiii_pll ; 1 ; +; ; ; +; Max LUT depth ; 3.00 ; +; Average LUT depth ; 1.84 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + Info: Processing started: Sat Nov 03 15:43:06 2018 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off timer_pwm -c timer_pwm +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file timer_pwm.v + Info (12023): Found entity 1: timer_pwm File: F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file ip/my_pll.v + Info (12023): Found entity 1: my_pll File: F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v Line: 39 +Info (12021): Found 1 design units, including 1 entities, in source file testbench/my_pll_tb.v + Info (12023): Found entity 1: my_pll_tb File: F:/Code/FPGA/reserve/timer_pwm/testbench/my_pll_tb.v Line: 5 +Info (12021): Found 1 design units, including 1 entities, in source file rtl/timer_pwm_top.v + Info (12023): Found entity 1: timer_pwm_top File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file testbench/timer_pwm_top_tb.v + Info (12023): Found entity 1: timer_pwm_top_tb File: F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v Line: 5 +Info (12127): Elaborating entity "timer_pwm_top" for the top level hierarchy +Info (12128): Elaborating entity "my_pll" for hierarchy "my_pll:my_pll" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 34 +Info (12128): Elaborating entity "altpll" for hierarchy "my_pll:my_pll|altpll:altpll_component" File: F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v Line: 103 +Info (12130): Elaborated megafunction instantiation "my_pll:my_pll|altpll:altpll_component" File: F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v Line: 103 +Info (12133): Instantiated megafunction "my_pll:my_pll|altpll:altpll_component" with the following parameter: File: F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v Line: 103 + Info (12134): Parameter "bandwidth_type" = "AUTO" + Info (12134): Parameter "clk0_divide_by" = "1" + Info (12134): Parameter "clk0_duty_cycle" = "50" + Info (12134): Parameter "clk0_multiply_by" = "4" + Info (12134): Parameter "clk0_phase_shift" = "0" + Info (12134): Parameter "compensate_clock" = "CLK0" + Info (12134): Parameter "inclk0_input_frequency" = "20000" + Info (12134): Parameter "intended_device_family" = "Cyclone IV E" + Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=my_pll" + Info (12134): Parameter "lpm_type" = "altpll" + Info (12134): Parameter "operation_mode" = "NORMAL" + Info (12134): Parameter "pll_type" = "AUTO" + Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" + Info (12134): Parameter "port_areset" = "PORT_USED" + Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" + Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" + Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" + Info (12134): Parameter "port_fbin" = "PORT_UNUSED" + Info (12134): Parameter "port_inclk0" = "PORT_USED" + Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_locked" = "PORT_USED" + Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" + Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" + Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" + Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" + Info (12134): Parameter "port_pllena" = "PORT_UNUSED" + Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" + Info (12134): Parameter "port_scandata" = "PORT_UNUSED" + Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" + Info (12134): Parameter "port_scandone" = "PORT_UNUSED" + Info (12134): Parameter "port_scanread" = "PORT_UNUSED" + Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" + Info (12134): Parameter "port_clk0" = "PORT_USED" + Info (12134): Parameter "port_clk1" = "PORT_UNUSED" + Info (12134): Parameter "port_clk2" = "PORT_UNUSED" + Info (12134): Parameter "port_clk3" = "PORT_UNUSED" + Info (12134): Parameter "port_clk4" = "PORT_UNUSED" + Info (12134): Parameter "port_clk5" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" + Info (12134): Parameter "self_reset_on_loss_lock" = "ON" + Info (12134): Parameter "width_clock" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/my_pll_altpll1.v + Info (12023): Found entity 1: my_pll_altpll1 File: F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v Line: 30 +Info (12128): Elaborating entity "my_pll_altpll1" for hierarchy "my_pll:my_pll|altpll:altpll_component|my_pll_altpll1:auto_generated" File: d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf Line: 897 +Info (12128): Elaborating entity "timer_pwm" for hierarchy "timer_pwm:timer_pwm" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 43 +Warning (10036): Verilog HDL or VHDL warning at timer_pwm.v(22): object "r_tim_cr" assigned a value but never read File: F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v Line: 22 +Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "tim_ch[2]" is stuck at GND File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 12 + Warning (13410): Pin "tim_ch[3]" is stuck at GND File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 12 + Warning (13410): Pin "tim_ch[4]" is stuck at GND File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 12 + Warning (13410): Pin "tim_ch[5]" is stuck at GND File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 12 + Warning (13410): Pin "tim_ch[6]" is stuck at GND File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 12 + Warning (13410): Pin "tim_ch[7]" is stuck at GND File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 12 +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 32 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "tim_cr[0]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[1]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[2]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[3]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[4]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[5]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[6]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[7]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[8]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[9]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[10]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[11]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[12]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[13]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[14]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[15]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[16]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[17]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[18]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[19]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[20]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[21]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[22]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[23]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[24]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[25]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[26]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[27]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[28]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[29]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[30]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 + Warning (15610): No output dependent on input pin "tim_cr[31]" File: F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v Line: 17 +Info (21057): Implemented 159 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 66 input pins + Info (21059): Implemented 8 output pins + Info (21061): Implemented 84 logic cells + Info (21065): Implemented 1 PLLs +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 43 warnings + Info: Peak virtual memory: 4791 megabytes + Info: Processing ended: Sat Nov 03 15:43:20 2018 + Info: Elapsed time: 00:00:14 + Info: Total CPU time (on all processors): 00:00:33 + + diff --git a/timer_pwm/output_files/timer_pwm.map.summary b/timer_pwm/output_files/timer_pwm.map.summary new file mode 100644 index 0000000..be3cc24 --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Sat Nov 03 15:43:20 2018 +Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Standard Edition +Revision Name : timer_pwm +Top-level Entity Name : timer_pwm_top +Family : Cyclone IV E +Total logic elements : 83 + Total combinational functions : 50 + Dedicated logic registers : 51 +Total registers : 51 +Total pins : 74 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 1 diff --git a/timer_pwm/output_files/timer_pwm.pin b/timer_pwm/output_files/timer_pwm.pin new file mode 100644 index 0000000..bf171d3 --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.pin @@ -0,0 +1,326 @@ + -- Copyright (C) 2018 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +CHIP "timer_pwm" ASSIGNED TO AN: EP4CE10F17C8 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +VCCIO8 : A1 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +tim_cr[8] : A4 : input : 2.5 V : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : +tim_arr[4] : A8 : input : 2.5 V : : 8 : N +tim_cr[31] : A9 : input : 2.5 V : : 7 : N +tim_arr[13] : A10 : input : 2.5 V : : 7 : N +tim_ccr1[12] : A11 : input : 2.5 V : : 7 : N +tim_ccr1[8] : A12 : input : 2.5 V : : 7 : N +tim_ccr1[14] : A13 : input : 2.5 V : : 7 : N +tim_ccr1[0] : A14 : input : 2.5 V : : 7 : N +tim_arr[0] : A15 : input : 2.5 V : : 7 : N +VCCIO7 : A16 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 1 : +GND : B2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8 : +tim_ch[3] : B6 : output : 2.5 V : : 8 : N +tim_cr[29] : B7 : input : 2.5 V : : 8 : N +tim_arr[8] : B8 : input : 2.5 V : : 8 : N +tim_arr[9] : B9 : input : 2.5 V : : 7 : N +tim_arr[2] : B10 : input : 2.5 V : : 7 : N +tim_ccr1[15] : B11 : input : 2.5 V : : 7 : N +tim_ccr1[9] : B12 : input : 2.5 V : : 7 : N +tim_ccr1[13] : B13 : input : 2.5 V : : 7 : N +tim_ccr1[4] : B14 : input : 2.5 V : : 7 : N +GND : B15 : gnd : : : : +tim_cr[15] : B16 : input : 2.5 V : : 6 : N +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 : +VCCIO8 : C4 : power : : 2.5V : 8 : +GND : C5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +VCCIO8 : C7 : power : : 2.5V : 8 : +tim_cr[10] : C8 : input : 2.5 V : : 8 : N +tim_arr[15] : C9 : input : 2.5 V : : 7 : N +VCCIO7 : C10 : power : : 2.5V : 7 : +tim_arr[5] : C11 : input : 2.5 V : : 7 : N +GND : C12 : gnd : : : : +VCCIO7 : C13 : power : : 2.5V : 7 : +tim_ccr1[11] : C14 : input : 2.5 V : : 7 : N +tim_ch[1] : C15 : output : 2.5 V : : 6 : N +tim_ccr1[2] : C16 : input : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 : +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 : +tim_cr[19] : D6 : input : 2.5 V : : 8 : N +GND : D7 : gnd : : : : +tim_arr[3] : D8 : input : 2.5 V : : 8 : N +tim_arr[14] : D9 : input : 2.5 V : : 7 : N +GND : D10 : gnd : : : : +tim_ccr1[6] : D11 : input : 2.5 V : : 7 : N +tim_ccr1[10] : D12 : input : 2.5 V : : 7 : N +VCCD_PLL2 : D13 : power : : 1.2V : : +tim_ch[0] : D14 : output : 2.5 V : : 7 : N +tim_ccr1[1] : D15 : input : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 6 : +clk : E1 : input : 2.5 V : : 1 : N +GND : E2 : gnd : : : : +VCCIO1 : E3 : power : : 2.5V : 1 : +GND : E4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 : +tim_arr[11] : E9 : input : 2.5 V : : 7 : N +tim_ccr1[5] : E10 : input : 2.5 V : : 7 : N +tim_ccr1[3] : E11 : input : 2.5 V : : 7 : N +GNDA2 : E12 : gnd : : : : +GND : E13 : gnd : : : : +VCCIO6 : E14 : power : : 2.5V : 6 : +GND+ : E15 : : : : 6 : +GND+ : E16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 : +nSTATUS : F4 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 : +tim_cr[23] : F6 : input : 2.5 V : : 8 : N +tim_cr[24] : F7 : input : 2.5 V : : 8 : N +tim_arr[7] : F8 : input : 2.5 V : : 8 : N +tim_arr[6] : F9 : input : 2.5 V : : 7 : N +tim_arr[1] : F10 : input : 2.5 V : : 7 : N +tim_arr[12] : F11 : input : 2.5 V : : 7 : N +VCCA2 : F12 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 2.5 V : : 6 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 : +VCCIO1 : G3 : power : : 2.5V : 1 : +GND : G4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 : +VCCINT : G6 : power : : 1.2V : : +VCCINT : G7 : power : : 1.2V : : +VCCINT : G8 : power : : 1.2V : : +VCCINT : G9 : power : : 1.2V : : +VCCINT : G10 : power : : 1.2V : : +tim_ccr1[7] : G11 : input : 2.5 V : : 6 : N +MSEL2 : G12 : : : : 6 : +GND : G13 : gnd : : : : +VCCIO6 : G14 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 6 : +~ALTERA_DCLK~ : H1 : output : 2.5 V : : 1 : N +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V : : 1 : N +TCK : H3 : input : : : 1 : +TDI : H4 : input : : : 1 : +nCONFIG : H5 : : : : 1 : +VCCINT : H6 : power : : 1.2V : : +GND : H7 : gnd : : : : +GND : H8 : gnd : : : : +GND : H9 : gnd : : : : +GND : H10 : gnd : : : : +VCCINT : H11 : power : : 1.2V : : +MSEL1 : H12 : : : : 6 : +MSEL0 : H13 : : : : 6 : +CONF_DONE : H14 : : : : 6 : +GND : H15 : gnd : : : : +GND : H16 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J1 : : : : 2 : +tim_cr[27] : J2 : input : 2.5 V : : 2 : N +nCE : J3 : : : : 1 : +TDO : J4 : output : : : 1 : +TMS : J5 : input : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 2 : +GND : J7 : gnd : : : : +GND : J8 : gnd : : : : +GND : J9 : gnd : : : : +GND : J10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 2 : +VCCIO2 : K3 : power : : 2.5V : 2 : +GND : K4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K6 : : : : 2 : +VCCINT : K7 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K9 : : : : 4 : +tim_cr[22] : K10 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 5 : +GND : K13 : gnd : : : : +VCCIO5 : K14 : power : : 2.5V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 2 : +tim_cr[12] : L3 : input : 2.5 V : : 2 : N +tim_cr[28] : L4 : input : 2.5 V : : 2 : N +VCCA1 : L5 : power : : 2.5V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 3 : +tim_cr[4] : L8 : input : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L10 : : : : 4 : +tim_cr[5] : L11 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : L12 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L13 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L16 : : : : 5 : +tim_arr[10] : M1 : input : 2.5 V : : 2 : N +rst_n : M2 : input : 2.5 V : : 2 : N +VCCIO2 : M3 : power : : 2.5V : 2 : +GND : M4 : gnd : : : : +GNDA1 : M5 : gnd : : : : +tim_cr[17] : M6 : input : 2.5 V : : 3 : N +tim_ch[6] : M7 : output : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 3 : +tim_cr[13] : M9 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : M10 : : : : 4 : +tim_cr[7] : M11 : input : 2.5 V : : 4 : N +tim_cr[14] : M12 : input : 2.5 V : : 5 : N +GND : M13 : gnd : : : : +VCCIO5 : M14 : power : : 2.5V : 5 : +GND+ : M15 : : : : 5 : +GND+ : M16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N2 : : : : 2 : +tim_ch[2] : N3 : output : 2.5 V : : 3 : N +VCCD_PLL1 : N4 : power : : 1.2V : : +tim_cr[2] : N5 : input : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : N6 : : : : 3 : +GND : N7 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 : +tim_cr[16] : N9 : input : 2.5 V : : 4 : N +GND : N10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N11 : : : : 4 : +tim_cr[3] : N12 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : N13 : : : : 5 : +tim_cr[25] : N14 : input : 2.5 V : : 5 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : N15 : : : : 5 : +tim_cr[1] : N16 : input : 2.5 V : : 5 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3 : +VCCIO3 : P4 : power : : 2.5V : 3 : +GND : P5 : gnd : : : : +tim_cr[20] : P6 : input : 2.5 V : : 3 : N +VCCIO3 : P7 : power : : 2.5V : 3 : +tim_cr[26] : P8 : input : 2.5 V : : 3 : N +tim_ch[4] : P9 : output : 2.5 V : : 4 : N +VCCIO4 : P10 : power : : 2.5V : 4 : +tim_cr[30] : P11 : input : 2.5 V : : 4 : N +GND : P12 : gnd : : : : +VCCIO4 : P13 : power : : 2.5V : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 : +GND : R2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 3 : +tim_cr[9] : R7 : input : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R10 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R12 : : : : 4 : +tim_cr[6] : R13 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : +GND : R15 : gnd : : : : +tim_ch[5] : R16 : output : 2.5 V : : 5 : N +VCCIO3 : T1 : power : : 2.5V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T2 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T6 : : : : 3 : +tim_cr[18] : T7 : input : 2.5 V : : 3 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 3 : +tim_ch[7] : T9 : output : 2.5 V : : 4 : N +tim_cr[21] : T10 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : T11 : : : : 4 : +tim_cr[0] : T12 : input : 2.5 V : : 4 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : +tim_cr[11] : T15 : input : 2.5 V : : 4 : N +VCCIO4 : T16 : power : : 2.5V : 4 : diff --git a/timer_pwm/output_files/timer_pwm.sld b/timer_pwm/output_files/timer_pwm.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.sld @@ -0,0 +1 @@ + diff --git a/timer_pwm/output_files/timer_pwm.sof b/timer_pwm/output_files/timer_pwm.sof new file mode 100644 index 0000000..73a3b91 Binary files /dev/null and b/timer_pwm/output_files/timer_pwm.sof differ diff --git a/timer_pwm/output_files/timer_pwm.sta.rpt b/timer_pwm/output_files/timer_pwm.sta.rpt new file mode 100644 index 0000000..440b012 --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.sta.rpt @@ -0,0 +1,1349 @@ +Timing Analyzer report for timer_pwm +Sat Nov 03 15:43:34 2018 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1200mV 85C Model Fmax Summary + 7. Timing Closure Recommendations + 8. Slow 1200mV 85C Model Setup Summary + 9. Slow 1200mV 85C Model Hold Summary + 10. Slow 1200mV 85C Model Recovery Summary + 11. Slow 1200mV 85C Model Removal Summary + 12. Slow 1200mV 85C Model Minimum Pulse Width Summary + 13. Slow 1200mV 85C Model Setup: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' + 14. Slow 1200mV 85C Model Hold: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' + 15. Slow 1200mV 85C Model Metastability Summary + 16. Slow 1200mV 0C Model Fmax Summary + 17. Slow 1200mV 0C Model Setup Summary + 18. Slow 1200mV 0C Model Hold Summary + 19. Slow 1200mV 0C Model Recovery Summary + 20. Slow 1200mV 0C Model Removal Summary + 21. Slow 1200mV 0C Model Minimum Pulse Width Summary + 22. Slow 1200mV 0C Model Setup: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' + 23. Slow 1200mV 0C Model Hold: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' + 24. Slow 1200mV 0C Model Metastability Summary + 25. Fast 1200mV 0C Model Setup Summary + 26. Fast 1200mV 0C Model Hold Summary + 27. Fast 1200mV 0C Model Recovery Summary + 28. Fast 1200mV 0C Model Removal Summary + 29. Fast 1200mV 0C Model Minimum Pulse Width Summary + 30. Fast 1200mV 0C Model Setup: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' + 31. Fast 1200mV 0C Model Hold: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' + 32. Fast 1200mV 0C Model Metastability Summary + 33. Multicorner Timing Analysis Summary + 34. Board Trace Model Assignments + 35. Input Transition Times + 36. Signal Integrity Metrics (Slow 1200mv 0c Model) + 37. Signal Integrity Metrics (Slow 1200mv 85c Model) + 38. Signal Integrity Metrics (Fast 1200mv 0c Model) + 39. Setup Transfers + 40. Hold Transfers + 41. Report TCCS + 42. Report RSKM + 43. Unconstrained Paths Summary + 44. Clock Status Summary + 45. Unconstrained Input Ports + 46. Unconstrained Output Ports + 47. Unconstrained Input Ports + 48. Unconstrained Output Ports + 49. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+---------------------------------------------------------+ +; Quartus Prime Version ; Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; timer_pwm ; +; Device Family ; Cyclone IV E ; +; Device Name ; EP4CE10F17C8 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+---------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.01 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.4% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------+ +; SDC File List ; ++-------------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++-------------------+--------+--------------------------+ +; timer_pwm.out.sdc ; OK ; Sat Nov 03 15:43:33 2018 ; ++-------------------+--------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++----------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+------------------------------------------------------+--------------------------------------------------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++----------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+------------------------------------------------------+--------------------------------------------------------+ +; clk ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { clk } ; +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 5.000 ; 200.0 MHz ; 0.000 ; 2.500 ; 50.00 ; 1 ; 4 ; ; ; ; ; false ; clk ; my_pll|altpll_component|auto_generated|pll1|inclk[0] ; { my_pll|altpll_component|auto_generated|pll1|clk[0] } ; ++----------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+------------------------------------------------------+--------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+----------------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+----------------------------------------------------+------+ +; 229.99 MHz ; 229.99 MHz ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; ; ++------------+-----------------+----------------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + ++----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------+-------+---------------+ +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.652 ; 0.000 ; ++----------------------------------------------------+-------+---------------+ + + ++----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------+-------+---------------+ +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.762 ; 0.000 ; ++----------------------------------------------------+-------+---------------+ + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++----------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------+-------+---------------+ +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 2.222 ; 0.000 ; +; clk ; 9.934 ; 0.000 ; ++----------------------------------------------------+-------+---------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+-------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+-------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; 0.652 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.272 ; +; 0.652 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.272 ; +; 0.743 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.181 ; +; 0.743 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.181 ; +; 0.744 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.180 ; +; 0.744 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.180 ; +; 0.775 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.149 ; +; 0.775 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.149 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.778 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 4.143 ; +; 0.805 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.119 ; +; 0.805 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.119 ; +; 0.869 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.055 ; +; 0.869 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.055 ; +; 0.882 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.042 ; +; 0.882 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.042 ; +; 0.898 ; timer_pwm:timer_pwm|cnt[15] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.026 ; +; 0.898 ; timer_pwm:timer_pwm|cnt[15] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.026 ; +; 0.909 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.015 ; +; 0.909 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 4.015 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.927 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.994 ; +; 0.933 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 3.991 ; +; 0.933 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 3.991 ; +; 0.937 ; timer_pwm:timer_pwm|r_tim_ccr1[15] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.078 ; 3.986 ; +; 0.937 ; timer_pwm:timer_pwm|r_tim_ccr1[15] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.078 ; 3.986 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.938 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.983 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.961 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.960 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; +; 0.964 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 3.957 ; ++-------+------------------------------------+-------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-----------------------------+-----------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------------------------+-----------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; 0.762 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.054 ; +; 0.763 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.055 ; +; 0.763 ; timer_pwm:timer_pwm|cnt[13] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.055 ; +; 0.765 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.057 ; +; 0.765 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.057 ; +; 0.765 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.057 ; +; 0.766 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.058 ; +; 0.767 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.059 ; +; 0.767 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.059 ; +; 0.786 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.078 ; +; 0.787 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.079 ; +; 0.788 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.080 ; +; 0.788 ; timer_pwm:timer_pwm|cnt[15] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.080 ; +; 0.790 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.082 ; +; 0.790 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.082 ; +; 0.811 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.103 ; +; 1.117 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.409 ; +; 1.117 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.409 ; +; 1.118 ; timer_pwm:timer_pwm|cnt[13] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.410 ; +; 1.119 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.411 ; +; 1.126 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.418 ; +; 1.126 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.418 ; +; 1.127 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.419 ; +; 1.128 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.420 ; +; 1.128 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.420 ; +; 1.135 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.427 ; +; 1.135 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.427 ; +; 1.136 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.428 ; +; 1.137 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.429 ; +; 1.137 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.429 ; +; 1.141 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.433 ; +; 1.142 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.434 ; +; 1.142 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.434 ; +; 1.149 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.441 ; +; 1.151 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.443 ; +; 1.151 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.443 ; +; 1.158 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.450 ; +; 1.160 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.452 ; +; 1.248 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.540 ; +; 1.248 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.540 ; +; 1.249 ; timer_pwm:timer_pwm|cnt[13] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.541 ; +; 1.250 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.542 ; +; 1.257 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.549 ; +; 1.257 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.549 ; +; 1.259 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.551 ; +; 1.266 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.558 ; +; 1.266 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.558 ; +; 1.267 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.559 ; +; 1.268 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.560 ; +; 1.268 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.560 ; +; 1.272 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.564 ; +; 1.273 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.565 ; +; 1.273 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.565 ; +; 1.275 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.567 ; +; 1.275 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.567 ; +; 1.276 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.568 ; +; 1.277 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.569 ; +; 1.277 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.569 ; +; 1.281 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.573 ; +; 1.282 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.574 ; +; 1.282 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.574 ; +; 1.289 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.581 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.583 ; +; 1.298 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.590 ; +; 1.388 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.680 ; +; 1.388 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.680 ; +; 1.390 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.682 ; +; 1.397 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.689 ; +; 1.397 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.689 ; +; 1.399 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.691 ; +; 1.406 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.698 ; +; 1.406 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.698 ; +; 1.407 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.699 ; +; 1.408 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.700 ; +; 1.408 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.700 ; +; 1.412 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.704 ; +; 1.413 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.705 ; +; 1.413 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.705 ; +; 1.415 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.707 ; +; 1.415 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.707 ; +; 1.416 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.708 ; +; 1.417 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.709 ; +; 1.421 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.713 ; +; 1.422 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.714 ; +; 1.429 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.721 ; +; 1.438 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.730 ; +; 1.528 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.820 ; +; 1.528 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.820 ; +; 1.530 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.822 ; +; 1.537 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.829 ; +; 1.537 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.829 ; +; 1.539 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.831 ; +; 1.546 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.838 ; +; 1.546 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.838 ; +; 1.547 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.839 ; +; 1.548 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.840 ; +; 1.552 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.844 ; +; 1.553 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.845 ; +; 1.555 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.847 ; +; 1.555 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 1.847 ; ++-------+-----------------------------+-----------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++-----------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++-----------+-----------------+----------------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+----------------------------------------------------+------+ +; 247.1 MHz ; 247.1 MHz ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; ; ++-----------+-----------------+----------------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------+-------+---------------+ +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.953 ; 0.000 ; ++----------------------------------------------------+-------+---------------+ + + ++----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------+-------+---------------+ +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.705 ; 0.000 ; ++----------------------------------------------------+-------+---------------+ + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++----------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------+-------+---------------+ +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 2.220 ; 0.000 ; +; clk ; 9.943 ; 0.000 ; ++----------------------------------------------------+-------+---------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+-------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+-------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; 0.953 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.980 ; +; 0.953 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.980 ; +; 1.047 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.886 ; +; 1.047 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.886 ; +; 1.049 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.884 ; +; 1.049 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.884 ; +; 1.075 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.858 ; +; 1.075 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.858 ; +; 1.124 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.809 ; +; 1.124 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.809 ; +; 1.155 ; timer_pwm:timer_pwm|cnt[15] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.778 ; +; 1.155 ; timer_pwm:timer_pwm|cnt[15] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.778 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.756 ; +; 1.174 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.759 ; +; 1.174 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.759 ; +; 1.175 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.758 ; +; 1.175 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.758 ; +; 1.196 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.737 ; +; 1.196 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.737 ; +; 1.200 ; timer_pwm:timer_pwm|r_tim_ccr1[15] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.733 ; +; 1.200 ; timer_pwm:timer_pwm|r_tim_ccr1[15] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.733 ; +; 1.238 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.695 ; +; 1.238 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.695 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.255 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 3.675 ; +; 1.276 ; timer_pwm:timer_pwm|cnt[13] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.657 ; +; 1.276 ; timer_pwm:timer_pwm|cnt[13] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.657 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.291 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.638 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.315 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.073 ; 3.614 ; +; 1.316 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.617 ; +; 1.316 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.617 ; +; 1.320 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.613 ; +; 1.320 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.613 ; +; 1.332 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.601 ; +; 1.332 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.069 ; 3.601 ; +; 1.333 ; timer_pwm:timer_pwm|r_tim_arr[2] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.071 ; 3.598 ; +; 1.333 ; timer_pwm:timer_pwm|r_tim_arr[2] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.071 ; 3.598 ; +; 1.333 ; timer_pwm:timer_pwm|r_tim_arr[2] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.071 ; 3.598 ; +; 1.333 ; timer_pwm:timer_pwm|r_tim_arr[2] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.071 ; 3.598 ; +; 1.333 ; timer_pwm:timer_pwm|r_tim_arr[2] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.071 ; 3.598 ; +; 1.333 ; timer_pwm:timer_pwm|r_tim_arr[2] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.071 ; 3.598 ; ++-------+------------------------------------+-------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-----------------------------+-----------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------------------------+-----------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; 0.705 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.973 ; +; 0.705 ; timer_pwm:timer_pwm|cnt[13] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.973 ; +; 0.706 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.974 ; +; 0.707 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.975 ; +; 0.708 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.976 ; +; 0.710 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.978 ; +; 0.711 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.979 ; +; 0.711 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.979 ; +; 0.712 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.980 ; +; 0.727 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.995 ; +; 0.728 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.996 ; +; 0.729 ; timer_pwm:timer_pwm|cnt[15] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.997 ; +; 0.730 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 0.998 ; +; 0.733 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.001 ; +; 0.733 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.001 ; +; 0.755 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.023 ; +; 1.026 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.294 ; +; 1.027 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.295 ; +; 1.027 ; timer_pwm:timer_pwm|cnt[13] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.295 ; +; 1.028 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.296 ; +; 1.028 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.296 ; +; 1.029 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.297 ; +; 1.030 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.298 ; +; 1.030 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.298 ; +; 1.032 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.300 ; +; 1.041 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.309 ; +; 1.044 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.312 ; +; 1.045 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.313 ; +; 1.045 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.313 ; +; 1.046 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.314 ; +; 1.049 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.317 ; +; 1.049 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.317 ; +; 1.050 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.318 ; +; 1.050 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.318 ; +; 1.051 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.319 ; +; 1.054 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.322 ; +; 1.065 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.333 ; +; 1.067 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.335 ; +; 1.120 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.388 ; +; 1.121 ; timer_pwm:timer_pwm|cnt[13] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.389 ; +; 1.125 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.393 ; +; 1.128 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.396 ; +; 1.143 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.411 ; +; 1.143 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.411 ; +; 1.148 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.416 ; +; 1.149 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.417 ; +; 1.149 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.417 ; +; 1.150 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.418 ; +; 1.150 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.418 ; +; 1.151 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.419 ; +; 1.152 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.420 ; +; 1.152 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.420 ; +; 1.154 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.422 ; +; 1.163 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.431 ; +; 1.166 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.434 ; +; 1.167 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.435 ; +; 1.167 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.435 ; +; 1.168 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.436 ; +; 1.171 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.439 ; +; 1.171 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.439 ; +; 1.172 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.440 ; +; 1.173 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.441 ; +; 1.176 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.444 ; +; 1.187 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.455 ; +; 1.242 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.510 ; +; 1.247 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.515 ; +; 1.250 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.518 ; +; 1.265 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.533 ; +; 1.265 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.533 ; +; 1.270 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.538 ; +; 1.271 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.539 ; +; 1.271 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.539 ; +; 1.272 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.540 ; +; 1.272 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.540 ; +; 1.273 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.541 ; +; 1.274 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.542 ; +; 1.274 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.542 ; +; 1.276 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.544 ; +; 1.285 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.553 ; +; 1.288 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.556 ; +; 1.289 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.557 ; +; 1.290 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.558 ; +; 1.293 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.561 ; +; 1.293 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.561 ; +; 1.298 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.566 ; +; 1.309 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.577 ; +; 1.364 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.632 ; +; 1.369 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.637 ; +; 1.372 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.640 ; +; 1.387 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.655 ; +; 1.392 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.660 ; +; 1.393 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.661 ; +; 1.393 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.661 ; +; 1.394 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.662 ; +; 1.394 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.662 ; +; 1.396 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.664 ; +; 1.396 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.664 ; +; 1.398 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.666 ; +; 1.407 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.675 ; +; 1.410 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 1.678 ; ++-------+-----------------------------+-----------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------+-------+---------------+ +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 3.141 ; 0.000 ; ++----------------------------------------------------+-------+---------------+ + + ++----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------+-------+---------------+ +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.304 ; 0.000 ; ++----------------------------------------------------+-------+---------------+ + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++----------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++----------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------+-------+---------------+ +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 2.298 ; 0.000 ; +; clk ; 9.594 ; 0.000 ; ++----------------------------------------------------+-------+---------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------+-------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------+-------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; 3.141 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.813 ; +; 3.141 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.813 ; +; 3.154 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.800 ; +; 3.154 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.800 ; +; 3.166 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.788 ; +; 3.166 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.788 ; +; 3.185 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.769 ; +; 3.185 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.769 ; +; 3.190 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.764 ; +; 3.190 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.764 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.191 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.759 ; +; 3.200 ; timer_pwm:timer_pwm|cnt[15] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.754 ; +; 3.200 ; timer_pwm:timer_pwm|cnt[15] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.754 ; +; 3.218 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.736 ; +; 3.218 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.736 ; +; 3.221 ; timer_pwm:timer_pwm|r_tim_ccr1[15] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.733 ; +; 3.221 ; timer_pwm:timer_pwm|r_tim_ccr1[15] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.733 ; +; 3.234 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.720 ; +; 3.234 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.720 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.235 ; timer_pwm:timer_pwm|r_tim_arr[1] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.716 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.687 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.687 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.267 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.683 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.284 ; timer_pwm:timer_pwm|r_tim_arr[0] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.667 ; +; 3.285 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.669 ; +; 3.285 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.669 ; +; 3.295 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.659 ; +; 3.295 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.659 ; +; 3.304 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|tim_ch[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.650 ; +; 3.304 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|tim_ch[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.033 ; 1.650 ; +; 3.306 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.644 ; +; 3.306 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.644 ; +; 3.306 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.644 ; +; 3.306 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.644 ; +; 3.306 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.644 ; +; 3.306 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.644 ; +; 3.306 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.644 ; +; 3.306 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.644 ; +; 3.306 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.644 ; +; 3.306 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.037 ; 1.644 ; ++-------+------------------------------------+-------------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'my_pll|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-----------------------------+-----------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------------------------+-----------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ +; 0.304 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.425 ; +; 0.304 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.425 ; +; 0.304 ; timer_pwm:timer_pwm|cnt[13] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.425 ; +; 0.305 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.426 ; +; 0.305 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.426 ; +; 0.306 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.427 ; +; 0.306 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.427 ; +; 0.306 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.427 ; +; 0.307 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.428 ; +; 0.315 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.436 ; +; 0.315 ; timer_pwm:timer_pwm|cnt[15] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.436 ; +; 0.316 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.437 ; +; 0.317 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.438 ; +; 0.317 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.438 ; +; 0.318 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.439 ; +; 0.327 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.448 ; +; 0.453 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.574 ; +; 0.453 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.574 ; +; 0.453 ; timer_pwm:timer_pwm|cnt[13] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.574 ; +; 0.454 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.575 ; +; 0.463 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.584 ; +; 0.464 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.585 ; +; 0.464 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.585 ; +; 0.464 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.585 ; +; 0.464 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.585 ; +; 0.465 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.586 ; +; 0.465 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.586 ; +; 0.466 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.587 ; +; 0.466 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.587 ; +; 0.467 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.588 ; +; 0.467 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.588 ; +; 0.467 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.588 ; +; 0.468 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.589 ; +; 0.474 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[1] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.595 ; +; 0.475 ; timer_pwm:timer_pwm|cnt[14] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.596 ; +; 0.476 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.597 ; +; 0.477 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[2] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.598 ; +; 0.479 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.600 ; +; 0.516 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.637 ; +; 0.516 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.637 ; +; 0.516 ; timer_pwm:timer_pwm|cnt[13] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.637 ; +; 0.517 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.638 ; +; 0.519 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.640 ; +; 0.519 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.640 ; +; 0.520 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.641 ; +; 0.527 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.648 ; +; 0.528 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.649 ; +; 0.529 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.650 ; +; 0.529 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.650 ; +; 0.530 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.651 ; +; 0.530 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.651 ; +; 0.530 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.651 ; +; 0.530 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.651 ; +; 0.531 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.652 ; +; 0.531 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.652 ; +; 0.532 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.653 ; +; 0.532 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.653 ; +; 0.533 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.654 ; +; 0.533 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.654 ; +; 0.533 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.654 ; +; 0.534 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.655 ; +; 0.540 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[3] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.661 ; +; 0.542 ; timer_pwm:timer_pwm|cnt[12] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.663 ; +; 0.543 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[4] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.664 ; +; 0.582 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.703 ; +; 0.582 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.703 ; +; 0.583 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.704 ; +; 0.585 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.706 ; +; 0.585 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.706 ; +; 0.586 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.707 ; +; 0.593 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.714 ; +; 0.594 ; timer_pwm:timer_pwm|cnt[11] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.715 ; +; 0.595 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.716 ; +; 0.595 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.716 ; +; 0.596 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.717 ; +; 0.596 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.717 ; +; 0.596 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.717 ; +; 0.596 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.717 ; +; 0.597 ; timer_pwm:timer_pwm|cnt[10] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.718 ; +; 0.598 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.719 ; +; 0.598 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.719 ; +; 0.599 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.720 ; +; 0.599 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.720 ; +; 0.599 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.720 ; +; 0.606 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[5] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.727 ; +; 0.609 ; timer_pwm:timer_pwm|cnt[0] ; timer_pwm:timer_pwm|cnt[6] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.730 ; +; 0.648 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[7] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.769 ; +; 0.648 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.769 ; +; 0.649 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.770 ; +; 0.651 ; timer_pwm:timer_pwm|cnt[1] ; timer_pwm:timer_pwm|cnt[8] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.772 ; +; 0.651 ; timer_pwm:timer_pwm|cnt[3] ; timer_pwm:timer_pwm|cnt[10] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.772 ; +; 0.652 ; timer_pwm:timer_pwm|cnt[7] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.773 ; +; 0.659 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.780 ; +; 0.661 ; timer_pwm:timer_pwm|cnt[9] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.782 ; +; 0.661 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[13] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.782 ; +; 0.662 ; timer_pwm:timer_pwm|cnt[5] ; timer_pwm:timer_pwm|cnt[12] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.783 ; +; 0.662 ; timer_pwm:timer_pwm|cnt[2] ; timer_pwm:timer_pwm|cnt[9] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.783 ; +; 0.662 ; timer_pwm:timer_pwm|cnt[4] ; timer_pwm:timer_pwm|cnt[11] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.783 ; +; 0.662 ; timer_pwm:timer_pwm|cnt[8] ; timer_pwm:timer_pwm|cnt[15] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.783 ; +; 0.664 ; timer_pwm:timer_pwm|cnt[6] ; timer_pwm:timer_pwm|cnt[14] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.785 ; ++-------+-----------------------------+-----------------------------+----------------------------------------------------+----------------------------------------------------+--------------+------------+------------+ + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++-----------------------------------------------------+-------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++-----------------------------------------------------+-------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 0.652 ; 0.304 ; N/A ; N/A ; 2.220 ; +; clk ; N/A ; N/A ; N/A ; N/A ; 9.594 ; +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.652 ; 0.304 ; N/A ; N/A ; 2.220 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; clk ; N/A ; N/A ; N/A ; N/A ; 0.000 ; +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ++-----------------------------------------------------+-------+-------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; tim_ch[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tim_ch[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tim_ch[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tim_ch[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tim_ch[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tim_ch[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tim_ch[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tim_ch[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; tim_cr[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[14] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[15] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[16] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[17] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[18] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[19] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[20] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[21] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[22] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[23] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[24] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[25] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[26] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[27] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[28] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[29] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[30] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_cr[31] ; 2.5 V ; 2000 ps ; 2000 ps ; +; rst_n ; 2.5 V ; 2000 ps ; 2000 ps ; +; clk ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[15] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_ccr1[14] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[15] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[14] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; tim_arr[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; tim_ch[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tim_ch[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; tim_ch[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tim_ch[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tim_ch[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tim_ch[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; 2.32 V ; 2.07e-09 V ; 2.36 V ; -0.00737 V ; 0.209 V ; 0.012 V ; 5.22e-10 s ; 5.33e-10 s ; Yes ; Yes ; +; tim_ch[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; tim_ch[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; 2.32 V ; 2.8e-09 V ; 2.37 V ; -0.00373 V ; 0.104 V ; 0.011 V ; 4.34e-10 s ; 3.82e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; 2.32 V ; 1.74e-09 V ; 2.37 V ; -0.0346 V ; 0.198 V ; 0.094 V ; 3.14e-10 s ; 2.92e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; 2.32 V ; 2.57e-09 V ; 2.37 V ; -0.00683 V ; 0.171 V ; 0.018 V ; 4.97e-10 s ; 6.66e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; tim_ch[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tim_ch[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; tim_ch[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tim_ch[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tim_ch[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tim_ch[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; 2.32 V ; 1.93e-07 V ; 2.34 V ; -0.00869 V ; 0.14 V ; 0.046 V ; 6.89e-10 s ; 6.56e-10 s ; Yes ; Yes ; +; tim_ch[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; tim_ch[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; 2.32 V ; 2.85e-07 V ; 2.35 V ; -0.0123 V ; 0.144 V ; 0.042 V ; 4.81e-10 s ; 4.81e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; 2.32 V ; 1.55e-07 V ; 2.35 V ; -0.00221 V ; 0.097 V ; 0.005 V ; 4.49e-10 s ; 3.85e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; 2.32 V ; 2.54e-07 V ; 2.34 V ; -0.00774 V ; 0.109 V ; 0.026 V ; 6.58e-10 s ; 8.24e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; tim_ch[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tim_ch[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; tim_ch[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tim_ch[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tim_ch[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tim_ch[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; tim_ch[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; tim_ch[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Transfers ; ++----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+ +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 776 ; 0 ; 0 ; 0 ; ++----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold Transfers ; ++----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+ +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; 776 ; 0 ; 0 ; 0 ; ++----------------------------------------------------+----------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 33 ; 33 ; +; Unconstrained Input Port Paths ; 33 ; 33 ; +; Unconstrained Output Ports ; 2 ; 2 ; +; Unconstrained Output Port Paths ; 2 ; 2 ; ++---------------------------------+-------+------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Clock Status Summary ; ++----------------------------------------------------+----------------------------------------------------+-----------+-------------+ +; Target ; Clock ; Type ; Status ; ++----------------------------------------------------+----------------------------------------------------+-----------+-------------+ +; clk ; clk ; Base ; Constrained ; +; my_pll|altpll_component|auto_generated|pll1|clk[0] ; my_pll|altpll_component|auto_generated|pll1|clk[0] ; Generated ; Constrained ; ++----------------------------------------------------+----------------------------------------------------+-----------+-------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++--------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++--------------+--------------------------------------------------------------------------------------+ +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++--------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; tim_ch[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ch[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++--------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++--------------+--------------------------------------------------------------------------------------+ +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_arr[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ccr1[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++--------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; tim_ch[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tim_ch[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + Info: Processing started: Sat Nov 03 15:43:32 2018 +Info: Command: quartus_sta timer_pwm -c timer_pwm +Info: qsta_default_script.tcl version: #2 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (332104): Reading SDC File: 'timer_pwm.out.sdc' +Warning (332174): Ignored filter at timer_pwm.out.sdc(41): clk_tim could not be matched with a port File: F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc Line: 41 +Warning (332049): Ignored create_clock at timer_pwm.out.sdc(41): Argument is an empty collection File: F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc Line: 41 + Info (332050): create_clock -name {clk_tim} -period 3.000 -waveform { 0.000 1.500 } [get_ports {clk_tim}] File: F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc Line: 41 +Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks" +Info (332110): Deriving PLL clocks + Info (332110): create_clock -period 20.000 -waveform {0.000 10.000} -name clk clk + Info (332110): create_generated_clock -source {my_pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name {my_pll|altpll_component|auto_generated|pll1|clk[0]} {my_pll|altpll_component|auto_generated|pll1|clk[0]} +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Info (332146): Worst-case setup slack is 0.652 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.652 0.000 my_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case hold slack is 0.762 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.762 0.000 my_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 2.222 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 2.222 0.000 my_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.934 0.000 clk +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info (332146): Worst-case setup slack is 0.953 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.953 0.000 my_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case hold slack is 0.705 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.705 0.000 my_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 2.220 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 2.220 0.000 my_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.943 0.000 clk +Info: Analyzing Fast 1200mV 0C Model +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info (332146): Worst-case setup slack is 3.141 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 3.141 0.000 my_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case hold slack is 0.304 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.304 0.000 my_pll|altpll_component|auto_generated|pll1|clk[0] +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 2.298 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 2.298 0.000 my_pll|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.594 0.000 clk +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 4774 megabytes + Info: Processing ended: Sat Nov 03 15:43:34 2018 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/timer_pwm/output_files/timer_pwm.sta.summary b/timer_pwm/output_files/timer_pwm.sta.summary new file mode 100644 index 0000000..ee4d6cd --- /dev/null +++ b/timer_pwm/output_files/timer_pwm.sta.summary @@ -0,0 +1,53 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1200mV 85C Model Setup 'my_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.652 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'my_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.762 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'my_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 2.222 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk' +Slack : 9.934 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Setup 'my_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.953 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'my_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.705 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'my_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 2.220 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk' +Slack : 9.943 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Setup 'my_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 3.141 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'my_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.304 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'my_pll|altpll_component|auto_generated|pll1|clk[0]' +Slack : 2.298 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk' +Slack : 9.594 +TNS : 0.000 + +------------------------------------------------------------ diff --git a/timer_pwm/rtl/timer_pwm_top.v b/timer_pwm/rtl/timer_pwm_top.v new file mode 100644 index 0000000..0d7883a --- /dev/null +++ b/timer_pwm/rtl/timer_pwm_top.v @@ -0,0 +1,45 @@ +module timer_pwm_top( + + clk, + rst_n, + tim_cr, + tim_arr, + tim_ccr1, + tim_ch + +); + + output [7:0] tim_ch; + + input clk; + input rst_n; + input [15:0] tim_arr; + input [31:0] tim_cr; + + input [15:0] tim_ccr1; + + wire c0; + wire locked; + + wire areset; + + assign areset = ~rst_n; + + + my_pll my_pll( + .areset(areset), + .inclk0(clk), + .c0(c0), + .locked(locked) + ); + + timer_pwm timer_pwm( + .clk_tim(c0), + .rst_n(locked), + .tim_cr(tim_cr), + .tim_arr(tim_arr), + .tim_ccr1(tim_ccr1), + .tim_ch(tim_ch) +); + +endmodule diff --git a/timer_pwm/rtl/timer_pwm_top.v.bak b/timer_pwm/rtl/timer_pwm_top.v.bak new file mode 100644 index 0000000..897dbcc --- /dev/null +++ b/timer_pwm/rtl/timer_pwm_top.v.bak @@ -0,0 +1,13 @@ +module timer_pwm_top( + + + +) + + + + + + + +endmodule; diff --git a/timer_pwm/simulation/modelsim/gate_work/_info b/timer_pwm/simulation/modelsim/gate_work/_info new file mode 100644 index 0000000..ecf9e68 --- /dev/null +++ b/timer_pwm/simulation/modelsim/gate_work/_info @@ -0,0 +1,54 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dF:/Code/FPGA/reserve/timer_pwm/simulation/modelsim +vtimer_pwm_top +Z1 !s110 1541240257 +!i10b 1 +!s100 QoVhLQ2NB8l27>?MZJCEE0 +Ig6U[;VEge@=m;Y=Zh:3@E0 +Z2 VDg1SIo80bB@j0V0VzS_@n1 +R0 +w1541231016 +8F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo +FF:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo +L0 31 +Z3 OV;L;10.5b;63 +r1 +!s85 0 +31 +Z4 !s108 1541240257.000000 +!s107 F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+.|F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo| +!i113 1 +Z5 o-vlog01compat -work work +!s92 -vlog01compat -work work +incdir+. +Z6 tCvgOpt 0 +vtimer_pwm_top_tb +R1 +!i10b 1 +!s100 N>JUB680gfXh3Y2Kf`9352 +InEC 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/timer_pwm/simulation/modelsim/msim_transcript b/timer_pwm/simulation/modelsim/msim_transcript new file mode 100644 index 0000000..d960293 --- /dev/null +++ b/timer_pwm/simulation/modelsim/msim_transcript @@ -0,0 +1,139 @@ +# Reading D:/intelFPGA/18.0/modelsim_ase/tcl/vsim/pref.tcl +# do timer_pwm_run_msim_gate_verilog.do +# if {[file exists gate_work]} { +# vdel -lib gate_work -all +# } +# vlib gate_work +# vmap work gate_work +# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016 +# vmap work gate_work +# Copying D:/intelFPGA/18.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini +# Modifying modelsim.ini +# +# vlog -vlog01compat -work work +incdir+. {timer_pwm_8_1200mv_85c_slow.vo} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:16:33 on Nov 03,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+." timer_pwm_8_1200mv_85c_slow.vo +# -- Compiling module timer_pwm_top +# +# Top level modules: +# timer_pwm_top +# End time: 18:16:33 on Nov 03,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# +# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench {F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v} +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:16:35 on Nov 03,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/timer_pwm/testbench" F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v +# -- Compiling module timer_pwm_top_tb +# +# Top level modules: +# timer_pwm_top_tb +# End time: 18:16:35 on Nov 03,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# +# vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" timer_pwm_top_tb +# vsim -t 1ps "+transport_int_delays" "+transport_path_delays" -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs=""+acc"" timer_pwm_top_tb +# Start time: 18:16:36 on Nov 03,2018 +# Loading work.timer_pwm_top_tb +# Loading work.timer_pwm_top +# Loading cycloneive_ver.cycloneive_io_obuf +# Loading cycloneive_ver.cycloneive_io_ibuf +# Loading cycloneive_ver.cycloneive_clkctrl +# Loading cycloneive_ver.cycloneive_mux41 +# Loading cycloneive_ver.cycloneive_ena_reg +# Loading cycloneive_ver.cycloneive_pll +# Loading cycloneive_ver.cycloneive_m_cntr +# Loading cycloneive_ver.cycloneive_n_cntr +# Loading cycloneive_ver.cycloneive_scale_cntr +# Loading cycloneive_ver.cycloneive_lcell_comb +# Loading altera_ver.dffeas +# SDF 10.5b Compiler 2016.10 Oct 5 2016 +# +# Loading instances from timer_pwm_8_1200mv_85c_v_slow.sdo +# Loading altera_ver.PRIM_GDFF_LOW +# Loading timing data from timer_pwm_8_1200mv_85c_v_slow.sdo +# ** Note: (vsim-3587) SDF Backannotation Successfully Completed. +# Time: 0 ps Iteration: 0 Instance: /timer_pwm_top_tb File: F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v +# +# add wave * +# view structure +# .main_pane.structure.interior.cs.body.struct +# view signals +# .main_pane.objects.interior.cs.body.tree +# run -all +# Note : Cycloneive PLL self reset due to loss of lock +# Time: 0 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1 +# Note : Cycloneive PLL was reset +# Time: 1535 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1 +# Note : Cycloneive PLL locked to incoming clock +# Time: 4083102 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1 +# ** Note: $stop : F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v(46) +# Time: 84002 ns Iteration: 0 Instance: /timer_pwm_top_tb +# Break in Module timer_pwm_top_tb at F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v line 46 +vlog -vlog01compat -work work +incdir+. F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:17:35 on Nov 03,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+." F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo +# -- Compiling module timer_pwm_top +# +# Top level modules: +# timer_pwm_top +# End time: 18:17:35 on Nov 03,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:17:36 on Nov 03,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/timer_pwm/testbench" F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v +# -- Compiling module timer_pwm_top_tb +# +# Top level modules: +# timer_pwm_top_tb +# End time: 18:17:36 on Nov 03,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+. F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:17:37 on Nov 03,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+." F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo +# -- Compiling module timer_pwm_top +# +# Top level modules: +# timer_pwm_top +# End time: 18:17:37 on Nov 03,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v +# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 18:17:37 on Nov 03,2018 +# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/reserve/timer_pwm/testbench" F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v +# -- Compiling module timer_pwm_top_tb +# +# Top level modules: +# timer_pwm_top_tb +# End time: 18:17:37 on Nov 03,2018, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +restart +# Loading work.timer_pwm_top_tb +# Loading work.timer_pwm_top +# SDF 10.5b Compiler 2016.10 Oct 5 2016 +# +# Loading instances from timer_pwm_8_1200mv_85c_v_slow.sdo +# ** Warning: (vsim-3015) F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v(20): [PCDPC] - Port size (8) does not match connection size (2) for port 'tim_ch'. The port definition is at: F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo(37). +# Time: 0 ps Iteration: 0 Instance: /timer_pwm_top_tb/timer_pwm_top File: F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo +# Loading timing data from timer_pwm_8_1200mv_85c_v_slow.sdo +# ** Note: (vsim-3587) SDF Backannotation Successfully Completed. +# Time: 0 ps Iteration: 0 Instance: /timer_pwm_top_tb File: F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v +run -all +# GetModuleFileName: Ҳָģ顣 +# +# +# Note : Cycloneive PLL self reset due to loss of lock +# Time: 0 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1 +# Note : Cycloneive PLL was reset +# Time: 1535 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1 +# Note : Cycloneive PLL locked to incoming clock +# Time: 4083102 Instance: timer_pwm_top_tb.timer_pwm_top.\my_pll|altpll_component|auto_generated|pll1 +# ** Note: $stop : F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v(46) +# Time: 84002 ns Iteration: 0 Instance: /timer_pwm_top_tb +# Break in Module timer_pwm_top_tb at F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v line 46 +# End time: 19:35:19 on Nov 03,2018, Elapsed time: 1:18:43 +# Errors: 0, Warnings: 1 diff --git a/timer_pwm/simulation/modelsim/rtl_work/_info b/timer_pwm/simulation/modelsim/rtl_work/_info new file mode 100644 index 0000000..50d5b2d --- /dev/null +++ b/timer_pwm/simulation/modelsim/rtl_work/_info @@ -0,0 +1,120 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dF:/Code/FPGA/reserve/timer_pwm/simulation/modelsim +vmy_pll +Z1 !s110 1541221850 +!i10b 1 +!s100 oa]dQR]aL=3LC:PD43`JHe:P7OYFkYQiVI1 +IY<77ikIn1QhMeRmzff Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[1] => Location: PIN_N16, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[2] => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[3] => Location: PIN_N12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[4] => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[5] => Location: PIN_L11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[6] => Location: PIN_R13, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[7] => Location: PIN_M11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[8] => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[9] => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[10] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[11] => Location: PIN_T15, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[12] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[13] => Location: PIN_M9, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[14] => Location: PIN_M12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[15] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[16] => Location: PIN_N9, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[17] => Location: PIN_M6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[18] => Location: PIN_T7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[19] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[20] => Location: PIN_P6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[21] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[22] => Location: PIN_K10, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[23] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[24] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[25] => Location: PIN_N14, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[26] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[27] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[28] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[29] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[30] => Location: PIN_P11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[31] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[0] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[1] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[2] => Location: PIN_N3, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[3] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[4] => Location: PIN_P9, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[5] => Location: PIN_R16, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[6] => Location: PIN_M7, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[7] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[1] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[0] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[3] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[2] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[5] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[4] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[7] => Location: PIN_G11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[6] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[9] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[8] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[11] => Location: PIN_C14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[10] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[13] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[12] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[15] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[14] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[15] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[14] => Location: PIN_D9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[13] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[12] => Location: PIN_F11, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[11] => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[10] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[9] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[8] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[7] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[6] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[5] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[4] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[3] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[2] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[1] => Location: PIN_F10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[0] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("timer_pwm_v.sdo"); +// synopsys translate_on + +wire \tim_cr[0]~input_o ; +wire \tim_cr[1]~input_o ; +wire \tim_cr[2]~input_o ; +wire \tim_cr[3]~input_o ; +wire \tim_cr[4]~input_o ; +wire \tim_cr[5]~input_o ; +wire \tim_cr[6]~input_o ; +wire \tim_cr[7]~input_o ; +wire \tim_cr[8]~input_o ; +wire \tim_cr[9]~input_o ; +wire \tim_cr[10]~input_o ; +wire \tim_cr[11]~input_o ; +wire \tim_cr[12]~input_o ; +wire \tim_cr[13]~input_o ; +wire \tim_cr[14]~input_o ; +wire \tim_cr[15]~input_o ; +wire \tim_cr[16]~input_o ; +wire \tim_cr[17]~input_o ; +wire \tim_cr[18]~input_o ; +wire \tim_cr[19]~input_o ; +wire \tim_cr[20]~input_o ; +wire \tim_cr[21]~input_o ; +wire \tim_cr[22]~input_o ; +wire \tim_cr[23]~input_o ; +wire \tim_cr[24]~input_o ; +wire \tim_cr[25]~input_o ; +wire \tim_cr[26]~input_o ; +wire \tim_cr[27]~input_o ; +wire \tim_cr[28]~input_o ; +wire \tim_cr[29]~input_o ; +wire \tim_cr[30]~input_o ; +wire \tim_cr[31]~input_o ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \clk~input_o ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \timer_pwm|cnt[0]~16_combout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \my_pll|altpll_component|auto_generated|locked~combout ; +wire \my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ; +wire \tim_arr[15]~input_o ; +wire \timer_pwm|r_tim_arr[15]~feeder_combout ; +wire \timer_pwm|cnt[7]~31 ; +wire \timer_pwm|cnt[8]~32_combout ; +wire \timer_pwm|cnt[8]~33 ; +wire \timer_pwm|cnt[9]~34_combout ; +wire \timer_pwm|cnt[9]~35 ; +wire \timer_pwm|cnt[10]~36_combout ; +wire \timer_pwm|cnt[10]~37 ; +wire \timer_pwm|cnt[11]~38_combout ; +wire \timer_pwm|cnt[11]~39 ; +wire \timer_pwm|cnt[12]~40_combout ; +wire \timer_pwm|cnt[12]~41 ; +wire \timer_pwm|cnt[13]~42_combout ; +wire \timer_pwm|cnt[13]~43 ; +wire \timer_pwm|cnt[14]~44_combout ; +wire \timer_pwm|cnt[14]~45 ; +wire \timer_pwm|cnt[15]~46_combout ; +wire \tim_arr[14]~input_o ; +wire \timer_pwm|r_tim_arr[14]~feeder_combout ; +wire \tim_arr[13]~input_o ; +wire \tim_arr[12]~input_o ; +wire \tim_arr[11]~input_o ; +wire \timer_pwm|r_tim_arr[11]~feeder_combout ; +wire \tim_arr[10]~input_o ; +wire \timer_pwm|r_tim_arr[10]~feeder_combout ; +wire \tim_arr[9]~input_o ; +wire \tim_arr[8]~input_o ; +wire \tim_arr[7]~input_o ; +wire \tim_arr[6]~input_o ; +wire \tim_arr[5]~input_o ; +wire \tim_arr[4]~input_o ; +wire \timer_pwm|r_tim_arr[4]~feeder_combout ; +wire \tim_arr[3]~input_o ; +wire \tim_arr[2]~input_o ; +wire \timer_pwm|r_tim_arr[2]~feeder_combout ; +wire \tim_arr[1]~input_o ; +wire \tim_arr[0]~input_o ; +wire \timer_pwm|LessThan0~1_cout ; +wire \timer_pwm|LessThan0~3_cout ; +wire \timer_pwm|LessThan0~5_cout ; +wire \timer_pwm|LessThan0~7_cout ; +wire \timer_pwm|LessThan0~9_cout ; +wire \timer_pwm|LessThan0~11_cout ; +wire \timer_pwm|LessThan0~13_cout ; +wire \timer_pwm|LessThan0~15_cout ; +wire \timer_pwm|LessThan0~17_cout ; +wire \timer_pwm|LessThan0~19_cout ; +wire \timer_pwm|LessThan0~21_cout ; +wire \timer_pwm|LessThan0~23_cout ; +wire \timer_pwm|LessThan0~25_cout ; +wire \timer_pwm|LessThan0~27_cout ; +wire \timer_pwm|LessThan0~29_cout ; +wire \timer_pwm|LessThan0~30_combout ; +wire \timer_pwm|cnt[0]~17 ; +wire \timer_pwm|cnt[1]~18_combout ; +wire \timer_pwm|cnt[1]~19 ; +wire \timer_pwm|cnt[2]~20_combout ; +wire \timer_pwm|cnt[2]~21 ; +wire \timer_pwm|cnt[3]~22_combout ; +wire \timer_pwm|cnt[3]~23 ; +wire \timer_pwm|cnt[4]~24_combout ; +wire \timer_pwm|cnt[4]~25 ; +wire \timer_pwm|cnt[5]~26_combout ; +wire \timer_pwm|cnt[5]~27 ; +wire \timer_pwm|cnt[6]~28_combout ; +wire \timer_pwm|cnt[6]~29 ; +wire \timer_pwm|cnt[7]~30_combout ; +wire \timer_pwm|Equal0~1_combout ; +wire \timer_pwm|Equal0~2_combout ; +wire \timer_pwm|Equal0~0_combout ; +wire \timer_pwm|Equal0~3_combout ; +wire \timer_pwm|Equal0~4_combout ; +wire \timer_pwm|tim_ch[0]~1_combout ; +wire \tim_ccr1[7]~input_o ; +wire \timer_pwm|r_tim_ccr1[7]~feeder_combout ; +wire \tim_ccr1[6]~input_o ; +wire \timer_pwm|Equal1~3_combout ; +wire \tim_ccr1[5]~input_o ; +wire \timer_pwm|r_tim_ccr1[5]~feeder_combout ; +wire \tim_ccr1[4]~input_o ; +wire \timer_pwm|Equal1~2_combout ; +wire \tim_ccr1[2]~input_o ; +wire \tim_ccr1[3]~input_o ; +wire \timer_pwm|r_tim_ccr1[3]~feeder_combout ; +wire \timer_pwm|Equal1~1_combout ; +wire \tim_ccr1[1]~input_o ; +wire \tim_ccr1[0]~input_o ; +wire \timer_pwm|Equal1~0_combout ; +wire \timer_pwm|Equal1~4_combout ; +wire \tim_ccr1[15]~input_o ; +wire \timer_pwm|r_tim_ccr1[15]~feeder_combout ; +wire \tim_ccr1[14]~input_o ; +wire \timer_pwm|Equal1~8_combout ; +wire \tim_ccr1[8]~input_o ; +wire \tim_ccr1[9]~input_o ; +wire \timer_pwm|r_tim_ccr1[9]~feeder_combout ; +wire \timer_pwm|Equal1~5_combout ; +wire \tim_ccr1[11]~input_o ; +wire \tim_ccr1[10]~input_o ; +wire \timer_pwm|Equal1~6_combout ; +wire \tim_ccr1[12]~input_o ; +wire \tim_ccr1[13]~input_o ; +wire \timer_pwm|r_tim_ccr1[13]~feeder_combout ; +wire \timer_pwm|Equal1~7_combout ; +wire \timer_pwm|Equal1~9_combout ; +wire \timer_pwm|tim_ch[0]~0_combout ; +wire [15:0] \timer_pwm|cnt ; +wire [15:0] \timer_pwm|r_tim_arr ; +wire [4:0] \my_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [1:0] \timer_pwm|tim_ch ; +wire [15:0] \timer_pwm|r_tim_ccr1 ; + +wire [4:0] \my_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X32_Y24_N16 +cycloneive_io_obuf \tim_ch[0]~output ( + .i(\timer_pwm|tim_ch [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[0]), + .obar()); +// synopsys translate_off +defparam \tim_ch[0]~output .bus_hold = "false"; +defparam \tim_ch[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y20_N2 +cycloneive_io_obuf \tim_ch[1]~output ( + .i(\timer_pwm|tim_ch [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[1]), + .obar()); +// synopsys translate_off +defparam \tim_ch[1]~output .bus_hold = "false"; +defparam \tim_ch[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N23 +cycloneive_io_obuf \tim_ch[2]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[2]), + .obar()); +// synopsys translate_off +defparam \tim_ch[2]~output .bus_hold = "false"; +defparam \tim_ch[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y24_N23 +cycloneive_io_obuf \tim_ch[3]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[3]), + .obar()); +// synopsys translate_off +defparam \tim_ch[3]~output .bus_hold = "false"; +defparam \tim_ch[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X25_Y0_N2 +cycloneive_io_obuf \tim_ch[4]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[4]), + .obar()); +// synopsys translate_off +defparam \tim_ch[4]~output .bus_hold = "false"; +defparam \tim_ch[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y5_N16 +cycloneive_io_obuf \tim_ch[5]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[5]), + .obar()); +// synopsys translate_off +defparam \tim_ch[5]~output .bus_hold = "false"; +defparam \tim_ch[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y0_N23 +cycloneive_io_obuf \tim_ch[6]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[6]), + .obar()); +// synopsys translate_off +defparam \tim_ch[6]~output .bus_hold = "false"; +defparam \tim_ch[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N16 +cycloneive_io_obuf \tim_ch[7]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[7]), + .obar()); +// synopsys translate_off +defparam \tim_ch[7]~output .bus_hold = "false"; +defparam \tim_ch[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \my_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\my_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \my_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_high = 2; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_low = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_mode = "odd"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 4; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \my_pll|altpll_component|auto_generated|pll1 .m = 12; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \my_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "on"; +defparam \my_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \my_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N0 +cycloneive_lcell_comb \timer_pwm|cnt[0]~16 ( +// Equation(s): +// \timer_pwm|cnt[0]~16_combout = \timer_pwm|cnt [0] $ (VCC) +// \timer_pwm|cnt[0]~17 = CARRY(\timer_pwm|cnt [0]) + + .dataa(gnd), + .datab(\timer_pwm|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\timer_pwm|cnt[0]~16_combout ), + .cout(\timer_pwm|cnt[0]~17 )); +// synopsys translate_off +defparam \timer_pwm|cnt[0]~16 .lut_mask = 16'h33CC; +defparam \timer_pwm|cnt[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N28 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y8_N29 +dffeas \my_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N14 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|locked ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|locked~combout = (!\my_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\my_pll|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|locked~combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked .lut_mask = 16'h0FFF; +defparam \my_pll|altpll_component|auto_generated|locked .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G0 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|locked~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|locked~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N8 +cycloneive_io_ibuf \tim_arr[15]~input ( + .i(tim_arr[15]), + .ibar(gnd), + .o(\tim_arr[15]~input_o )); +// synopsys translate_off +defparam \tim_arr[15]~input .bus_hold = "false"; +defparam \tim_arr[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N12 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[15]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[15]~feeder_combout = \tim_arr[15]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[15]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[15]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N13 +dffeas \timer_pwm|r_tim_arr[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[15] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N14 +cycloneive_lcell_comb \timer_pwm|cnt[7]~30 ( +// Equation(s): +// \timer_pwm|cnt[7]~30_combout = (\timer_pwm|cnt [7] & (!\timer_pwm|cnt[6]~29 )) # (!\timer_pwm|cnt [7] & ((\timer_pwm|cnt[6]~29 ) # (GND))) +// \timer_pwm|cnt[7]~31 = CARRY((!\timer_pwm|cnt[6]~29 ) # (!\timer_pwm|cnt [7])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[6]~29 ), + .combout(\timer_pwm|cnt[7]~30_combout ), + .cout(\timer_pwm|cnt[7]~31 )); +// synopsys translate_off +defparam \timer_pwm|cnt[7]~30 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[7]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N16 +cycloneive_lcell_comb \timer_pwm|cnt[8]~32 ( +// Equation(s): +// \timer_pwm|cnt[8]~32_combout = (\timer_pwm|cnt [8] & (\timer_pwm|cnt[7]~31 $ (GND))) # (!\timer_pwm|cnt [8] & (!\timer_pwm|cnt[7]~31 & VCC)) +// \timer_pwm|cnt[8]~33 = CARRY((\timer_pwm|cnt [8] & !\timer_pwm|cnt[7]~31 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[7]~31 ), + .combout(\timer_pwm|cnt[8]~32_combout ), + .cout(\timer_pwm|cnt[8]~33 )); +// synopsys translate_off +defparam \timer_pwm|cnt[8]~32 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[8]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N17 +dffeas \timer_pwm|cnt[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[8]~32_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[8] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N18 +cycloneive_lcell_comb \timer_pwm|cnt[9]~34 ( +// Equation(s): +// \timer_pwm|cnt[9]~34_combout = (\timer_pwm|cnt [9] & (!\timer_pwm|cnt[8]~33 )) # (!\timer_pwm|cnt [9] & ((\timer_pwm|cnt[8]~33 ) # (GND))) +// \timer_pwm|cnt[9]~35 = CARRY((!\timer_pwm|cnt[8]~33 ) # (!\timer_pwm|cnt [9])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[8]~33 ), + .combout(\timer_pwm|cnt[9]~34_combout ), + .cout(\timer_pwm|cnt[9]~35 )); +// synopsys translate_off +defparam \timer_pwm|cnt[9]~34 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[9]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N19 +dffeas \timer_pwm|cnt[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[9]~34_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[9] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N20 +cycloneive_lcell_comb \timer_pwm|cnt[10]~36 ( +// Equation(s): +// \timer_pwm|cnt[10]~36_combout = (\timer_pwm|cnt [10] & (\timer_pwm|cnt[9]~35 $ (GND))) # (!\timer_pwm|cnt [10] & (!\timer_pwm|cnt[9]~35 & VCC)) +// \timer_pwm|cnt[10]~37 = CARRY((\timer_pwm|cnt [10] & !\timer_pwm|cnt[9]~35 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[9]~35 ), + .combout(\timer_pwm|cnt[10]~36_combout ), + .cout(\timer_pwm|cnt[10]~37 )); +// synopsys translate_off +defparam \timer_pwm|cnt[10]~36 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[10]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N21 +dffeas \timer_pwm|cnt[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[10]~36_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[10] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N22 +cycloneive_lcell_comb \timer_pwm|cnt[11]~38 ( +// Equation(s): +// \timer_pwm|cnt[11]~38_combout = (\timer_pwm|cnt [11] & (!\timer_pwm|cnt[10]~37 )) # (!\timer_pwm|cnt [11] & ((\timer_pwm|cnt[10]~37 ) # (GND))) +// \timer_pwm|cnt[11]~39 = CARRY((!\timer_pwm|cnt[10]~37 ) # (!\timer_pwm|cnt [11])) + + .dataa(\timer_pwm|cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[10]~37 ), + .combout(\timer_pwm|cnt[11]~38_combout ), + .cout(\timer_pwm|cnt[11]~39 )); +// synopsys translate_off +defparam \timer_pwm|cnt[11]~38 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[11]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N23 +dffeas \timer_pwm|cnt[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[11]~38_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[11] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N24 +cycloneive_lcell_comb \timer_pwm|cnt[12]~40 ( +// Equation(s): +// \timer_pwm|cnt[12]~40_combout = (\timer_pwm|cnt [12] & (\timer_pwm|cnt[11]~39 $ (GND))) # (!\timer_pwm|cnt [12] & (!\timer_pwm|cnt[11]~39 & VCC)) +// \timer_pwm|cnt[12]~41 = CARRY((\timer_pwm|cnt [12] & !\timer_pwm|cnt[11]~39 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [12]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[11]~39 ), + .combout(\timer_pwm|cnt[12]~40_combout ), + .cout(\timer_pwm|cnt[12]~41 )); +// synopsys translate_off +defparam \timer_pwm|cnt[12]~40 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[12]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N25 +dffeas \timer_pwm|cnt[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[12]~40_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[12] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N26 +cycloneive_lcell_comb \timer_pwm|cnt[13]~42 ( +// Equation(s): +// \timer_pwm|cnt[13]~42_combout = (\timer_pwm|cnt [13] & (!\timer_pwm|cnt[12]~41 )) # (!\timer_pwm|cnt [13] & ((\timer_pwm|cnt[12]~41 ) # (GND))) +// \timer_pwm|cnt[13]~43 = CARRY((!\timer_pwm|cnt[12]~41 ) # (!\timer_pwm|cnt [13])) + + .dataa(\timer_pwm|cnt [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[12]~41 ), + .combout(\timer_pwm|cnt[13]~42_combout ), + .cout(\timer_pwm|cnt[13]~43 )); +// synopsys translate_off +defparam \timer_pwm|cnt[13]~42 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[13]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N27 +dffeas \timer_pwm|cnt[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[13]~42_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[13] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N28 +cycloneive_lcell_comb \timer_pwm|cnt[14]~44 ( +// Equation(s): +// \timer_pwm|cnt[14]~44_combout = (\timer_pwm|cnt [14] & (\timer_pwm|cnt[13]~43 $ (GND))) # (!\timer_pwm|cnt [14] & (!\timer_pwm|cnt[13]~43 & VCC)) +// \timer_pwm|cnt[14]~45 = CARRY((\timer_pwm|cnt [14] & !\timer_pwm|cnt[13]~43 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [14]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[13]~43 ), + .combout(\timer_pwm|cnt[14]~44_combout ), + .cout(\timer_pwm|cnt[14]~45 )); +// synopsys translate_off +defparam \timer_pwm|cnt[14]~44 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[14]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N29 +dffeas \timer_pwm|cnt[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[14]~44_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[14] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N30 +cycloneive_lcell_comb \timer_pwm|cnt[15]~46 ( +// Equation(s): +// \timer_pwm|cnt[15]~46_combout = \timer_pwm|cnt [15] $ (\timer_pwm|cnt[14]~45 ) + + .dataa(\timer_pwm|cnt [15]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\timer_pwm|cnt[14]~45 ), + .combout(\timer_pwm|cnt[15]~46_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|cnt[15]~46 .lut_mask = 16'h5A5A; +defparam \timer_pwm|cnt[15]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N31 +dffeas \timer_pwm|cnt[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[15]~46_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[15] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[15] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N15 +cycloneive_io_ibuf \tim_arr[14]~input ( + .i(tim_arr[14]), + .ibar(gnd), + .o(\tim_arr[14]~input_o )); +// synopsys translate_off +defparam \tim_arr[14]~input .bus_hold = "false"; +defparam \tim_arr[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N14 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[14]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[14]~feeder_combout = \tim_arr[14]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[14]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[14]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N15 +dffeas \timer_pwm|r_tim_arr[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[14]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[14] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[14] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N8 +cycloneive_io_ibuf \tim_arr[13]~input ( + .i(tim_arr[13]), + .ibar(gnd), + .o(\tim_arr[13]~input_o )); +// synopsys translate_off +defparam \tim_arr[13]~input .bus_hold = "false"; +defparam \tim_arr[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N15 +dffeas \timer_pwm|r_tim_arr[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[13]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[13] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[13] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N22 +cycloneive_io_ibuf \tim_arr[12]~input ( + .i(tim_arr[12]), + .ibar(gnd), + .o(\tim_arr[12]~input_o )); +// synopsys translate_off +defparam \tim_arr[12]~input .bus_hold = "false"; +defparam \tim_arr[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X23_Y21_N9 +dffeas \timer_pwm|r_tim_arr[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[12]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[12] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[12] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N22 +cycloneive_io_ibuf \tim_arr[11]~input ( + .i(tim_arr[11]), + .ibar(gnd), + .o(\tim_arr[11]~input_o )); +// synopsys translate_off +defparam \tim_arr[11]~input .bus_hold = "false"; +defparam \tim_arr[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N2 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[11]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[11]~feeder_combout = \tim_arr[11]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[11]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[11]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N3 +dffeas \timer_pwm|r_tim_arr[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[11]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[11] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[11] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \tim_arr[10]~input ( + .i(tim_arr[10]), + .ibar(gnd), + .o(\tim_arr[10]~input_o )); +// synopsys translate_off +defparam \tim_arr[10]~input .bus_hold = "false"; +defparam \tim_arr[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N20 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[10]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[10]~feeder_combout = \tim_arr[10]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[10]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[10]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N21 +dffeas \timer_pwm|r_tim_arr[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[10] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N8 +cycloneive_io_ibuf \tim_arr[9]~input ( + .i(tim_arr[9]), + .ibar(gnd), + .o(\tim_arr[9]~input_o )); +// synopsys translate_off +defparam \tim_arr[9]~input .bus_hold = "false"; +defparam \tim_arr[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N31 +dffeas \timer_pwm|r_tim_arr[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[9]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[9] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[9] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N22 +cycloneive_io_ibuf \tim_arr[8]~input ( + .i(tim_arr[8]), + .ibar(gnd), + .o(\tim_arr[8]~input_o )); +// synopsys translate_off +defparam \tim_arr[8]~input .bus_hold = "false"; +defparam \tim_arr[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N7 +dffeas \timer_pwm|r_tim_arr[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[8]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[8] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[8] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N22 +cycloneive_io_ibuf \tim_arr[7]~input ( + .i(tim_arr[7]), + .ibar(gnd), + .o(\tim_arr[7]~input_o )); +// synopsys translate_off +defparam \tim_arr[7]~input .bus_hold = "false"; +defparam \tim_arr[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N21 +dffeas \timer_pwm|r_tim_arr[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[7]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[7] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N15 +cycloneive_io_ibuf \tim_arr[6]~input ( + .i(tim_arr[6]), + .ibar(gnd), + .o(\tim_arr[6]~input_o )); +// synopsys translate_off +defparam \tim_arr[6]~input .bus_hold = "false"; +defparam \tim_arr[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N5 +dffeas \timer_pwm|r_tim_arr[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[6]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[6] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[6] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N1 +cycloneive_io_ibuf \tim_arr[5]~input ( + .i(tim_arr[5]), + .ibar(gnd), + .o(\tim_arr[5]~input_o )); +// synopsys translate_off +defparam \tim_arr[5]~input .bus_hold = "false"; +defparam \tim_arr[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N3 +dffeas \timer_pwm|r_tim_arr[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[5]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[5] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N15 +cycloneive_io_ibuf \tim_arr[4]~input ( + .i(tim_arr[4]), + .ibar(gnd), + .o(\tim_arr[4]~input_o )); +// synopsys translate_off +defparam \tim_arr[4]~input .bus_hold = "false"; +defparam \tim_arr[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N10 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[4]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[4]~feeder_combout = \tim_arr[4]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[4]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[4]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N11 +dffeas \timer_pwm|r_tim_arr[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[4] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[4] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N8 +cycloneive_io_ibuf \tim_arr[3]~input ( + .i(tim_arr[3]), + .ibar(gnd), + .o(\tim_arr[3]~input_o )); +// synopsys translate_off +defparam \tim_arr[3]~input .bus_hold = "false"; +defparam \tim_arr[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N9 +dffeas \timer_pwm|r_tim_arr[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[3]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[3] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[3] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N15 +cycloneive_io_ibuf \tim_arr[2]~input ( + .i(tim_arr[2]), + .ibar(gnd), + .o(\tim_arr[2]~input_o )); +// synopsys translate_off +defparam \tim_arr[2]~input .bus_hold = "false"; +defparam \tim_arr[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[2]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[2]~feeder_combout = \tim_arr[2]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[2]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[2]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N25 +dffeas \timer_pwm|r_tim_arr[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[2] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[2] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N8 +cycloneive_io_ibuf \tim_arr[1]~input ( + .i(tim_arr[1]), + .ibar(gnd), + .o(\tim_arr[1]~input_o )); +// synopsys translate_off +defparam \tim_arr[1]~input .bus_hold = "false"; +defparam \tim_arr[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N23 +dffeas \timer_pwm|r_tim_arr[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[1]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[1] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N1 +cycloneive_io_ibuf \tim_arr[0]~input ( + .i(tim_arr[0]), + .ibar(gnd), + .o(\tim_arr[0]~input_o )); +// synopsys translate_off +defparam \tim_arr[0]~input .bus_hold = "false"; +defparam \tim_arr[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N29 +dffeas \timer_pwm|r_tim_arr[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[0]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[0] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N0 +cycloneive_lcell_comb \timer_pwm|LessThan0~1 ( +// Equation(s): +// \timer_pwm|LessThan0~1_cout = CARRY((\timer_pwm|r_tim_arr [0] & !\timer_pwm|cnt [0])) + + .dataa(\timer_pwm|r_tim_arr [0]), + .datab(\timer_pwm|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\timer_pwm|LessThan0~1_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~1 .lut_mask = 16'h0022; +defparam \timer_pwm|LessThan0~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N2 +cycloneive_lcell_comb \timer_pwm|LessThan0~3 ( +// Equation(s): +// \timer_pwm|LessThan0~3_cout = CARRY((\timer_pwm|cnt [1] & ((!\timer_pwm|LessThan0~1_cout ) # (!\timer_pwm|r_tim_arr [1]))) # (!\timer_pwm|cnt [1] & (!\timer_pwm|r_tim_arr [1] & !\timer_pwm|LessThan0~1_cout ))) + + .dataa(\timer_pwm|cnt [1]), + .datab(\timer_pwm|r_tim_arr [1]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~1_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~3_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~3 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N4 +cycloneive_lcell_comb \timer_pwm|LessThan0~5 ( +// Equation(s): +// \timer_pwm|LessThan0~5_cout = CARRY((\timer_pwm|cnt [2] & (\timer_pwm|r_tim_arr [2] & !\timer_pwm|LessThan0~3_cout )) # (!\timer_pwm|cnt [2] & ((\timer_pwm|r_tim_arr [2]) # (!\timer_pwm|LessThan0~3_cout )))) + + .dataa(\timer_pwm|cnt [2]), + .datab(\timer_pwm|r_tim_arr [2]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~3_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~5_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~5 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N6 +cycloneive_lcell_comb \timer_pwm|LessThan0~7 ( +// Equation(s): +// \timer_pwm|LessThan0~7_cout = CARRY((\timer_pwm|cnt [3] & ((!\timer_pwm|LessThan0~5_cout ) # (!\timer_pwm|r_tim_arr [3]))) # (!\timer_pwm|cnt [3] & (!\timer_pwm|r_tim_arr [3] & !\timer_pwm|LessThan0~5_cout ))) + + .dataa(\timer_pwm|cnt [3]), + .datab(\timer_pwm|r_tim_arr [3]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~5_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~7_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~7 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N8 +cycloneive_lcell_comb \timer_pwm|LessThan0~9 ( +// Equation(s): +// \timer_pwm|LessThan0~9_cout = CARRY((\timer_pwm|r_tim_arr [4] & ((!\timer_pwm|LessThan0~7_cout ) # (!\timer_pwm|cnt [4]))) # (!\timer_pwm|r_tim_arr [4] & (!\timer_pwm|cnt [4] & !\timer_pwm|LessThan0~7_cout ))) + + .dataa(\timer_pwm|r_tim_arr [4]), + .datab(\timer_pwm|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~7_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~9_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~9 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N10 +cycloneive_lcell_comb \timer_pwm|LessThan0~11 ( +// Equation(s): +// \timer_pwm|LessThan0~11_cout = CARRY((\timer_pwm|cnt [5] & ((!\timer_pwm|LessThan0~9_cout ) # (!\timer_pwm|r_tim_arr [5]))) # (!\timer_pwm|cnt [5] & (!\timer_pwm|r_tim_arr [5] & !\timer_pwm|LessThan0~9_cout ))) + + .dataa(\timer_pwm|cnt [5]), + .datab(\timer_pwm|r_tim_arr [5]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~9_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~11_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~11 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \timer_pwm|LessThan0~13 ( +// Equation(s): +// \timer_pwm|LessThan0~13_cout = CARRY((\timer_pwm|cnt [6] & (\timer_pwm|r_tim_arr [6] & !\timer_pwm|LessThan0~11_cout )) # (!\timer_pwm|cnt [6] & ((\timer_pwm|r_tim_arr [6]) # (!\timer_pwm|LessThan0~11_cout )))) + + .dataa(\timer_pwm|cnt [6]), + .datab(\timer_pwm|r_tim_arr [6]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~11_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~13_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~13 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N14 +cycloneive_lcell_comb \timer_pwm|LessThan0~15 ( +// Equation(s): +// \timer_pwm|LessThan0~15_cout = CARRY((\timer_pwm|r_tim_arr [7] & (\timer_pwm|cnt [7] & !\timer_pwm|LessThan0~13_cout )) # (!\timer_pwm|r_tim_arr [7] & ((\timer_pwm|cnt [7]) # (!\timer_pwm|LessThan0~13_cout )))) + + .dataa(\timer_pwm|r_tim_arr [7]), + .datab(\timer_pwm|cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~13_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~15_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~15 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N16 +cycloneive_lcell_comb \timer_pwm|LessThan0~17 ( +// Equation(s): +// \timer_pwm|LessThan0~17_cout = CARRY((\timer_pwm|r_tim_arr [8] & ((!\timer_pwm|LessThan0~15_cout ) # (!\timer_pwm|cnt [8]))) # (!\timer_pwm|r_tim_arr [8] & (!\timer_pwm|cnt [8] & !\timer_pwm|LessThan0~15_cout ))) + + .dataa(\timer_pwm|r_tim_arr [8]), + .datab(\timer_pwm|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~15_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~17_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~17 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N18 +cycloneive_lcell_comb \timer_pwm|LessThan0~19 ( +// Equation(s): +// \timer_pwm|LessThan0~19_cout = CARRY((\timer_pwm|r_tim_arr [9] & (\timer_pwm|cnt [9] & !\timer_pwm|LessThan0~17_cout )) # (!\timer_pwm|r_tim_arr [9] & ((\timer_pwm|cnt [9]) # (!\timer_pwm|LessThan0~17_cout )))) + + .dataa(\timer_pwm|r_tim_arr [9]), + .datab(\timer_pwm|cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~17_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~19_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~19 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N20 +cycloneive_lcell_comb \timer_pwm|LessThan0~21 ( +// Equation(s): +// \timer_pwm|LessThan0~21_cout = CARRY((\timer_pwm|cnt [10] & (\timer_pwm|r_tim_arr [10] & !\timer_pwm|LessThan0~19_cout )) # (!\timer_pwm|cnt [10] & ((\timer_pwm|r_tim_arr [10]) # (!\timer_pwm|LessThan0~19_cout )))) + + .dataa(\timer_pwm|cnt [10]), + .datab(\timer_pwm|r_tim_arr [10]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~19_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~21_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~21 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N22 +cycloneive_lcell_comb \timer_pwm|LessThan0~23 ( +// Equation(s): +// \timer_pwm|LessThan0~23_cout = CARRY((\timer_pwm|r_tim_arr [11] & (\timer_pwm|cnt [11] & !\timer_pwm|LessThan0~21_cout )) # (!\timer_pwm|r_tim_arr [11] & ((\timer_pwm|cnt [11]) # (!\timer_pwm|LessThan0~21_cout )))) + + .dataa(\timer_pwm|r_tim_arr [11]), + .datab(\timer_pwm|cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~21_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~23_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~23 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N24 +cycloneive_lcell_comb \timer_pwm|LessThan0~25 ( +// Equation(s): +// \timer_pwm|LessThan0~25_cout = CARRY((\timer_pwm|r_tim_arr [12] & ((!\timer_pwm|LessThan0~23_cout ) # (!\timer_pwm|cnt [12]))) # (!\timer_pwm|r_tim_arr [12] & (!\timer_pwm|cnt [12] & !\timer_pwm|LessThan0~23_cout ))) + + .dataa(\timer_pwm|r_tim_arr [12]), + .datab(\timer_pwm|cnt [12]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~23_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~25_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~25 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N26 +cycloneive_lcell_comb \timer_pwm|LessThan0~27 ( +// Equation(s): +// \timer_pwm|LessThan0~27_cout = CARRY((\timer_pwm|r_tim_arr [13] & (\timer_pwm|cnt [13] & !\timer_pwm|LessThan0~25_cout )) # (!\timer_pwm|r_tim_arr [13] & ((\timer_pwm|cnt [13]) # (!\timer_pwm|LessThan0~25_cout )))) + + .dataa(\timer_pwm|r_tim_arr [13]), + .datab(\timer_pwm|cnt [13]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~25_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~27_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~27 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N28 +cycloneive_lcell_comb \timer_pwm|LessThan0~29 ( +// Equation(s): +// \timer_pwm|LessThan0~29_cout = CARRY((\timer_pwm|r_tim_arr [14] & ((!\timer_pwm|LessThan0~27_cout ) # (!\timer_pwm|cnt [14]))) # (!\timer_pwm|r_tim_arr [14] & (!\timer_pwm|cnt [14] & !\timer_pwm|LessThan0~27_cout ))) + + .dataa(\timer_pwm|r_tim_arr [14]), + .datab(\timer_pwm|cnt [14]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~27_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~29_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~29 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N30 +cycloneive_lcell_comb \timer_pwm|LessThan0~30 ( +// Equation(s): +// \timer_pwm|LessThan0~30_combout = (\timer_pwm|r_tim_arr [15] & ((\timer_pwm|LessThan0~29_cout ) # (!\timer_pwm|cnt [15]))) # (!\timer_pwm|r_tim_arr [15] & (\timer_pwm|LessThan0~29_cout & !\timer_pwm|cnt [15])) + + .dataa(gnd), + .datab(\timer_pwm|r_tim_arr [15]), + .datac(gnd), + .datad(\timer_pwm|cnt [15]), + .cin(\timer_pwm|LessThan0~29_cout ), + .combout(\timer_pwm|LessThan0~30_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|LessThan0~30 .lut_mask = 16'hC0FC; +defparam \timer_pwm|LessThan0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N1 +dffeas \timer_pwm|cnt[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[0]~16_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[0] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N2 +cycloneive_lcell_comb \timer_pwm|cnt[1]~18 ( +// Equation(s): +// \timer_pwm|cnt[1]~18_combout = (\timer_pwm|cnt [1] & (!\timer_pwm|cnt[0]~17 )) # (!\timer_pwm|cnt [1] & ((\timer_pwm|cnt[0]~17 ) # (GND))) +// \timer_pwm|cnt[1]~19 = CARRY((!\timer_pwm|cnt[0]~17 ) # (!\timer_pwm|cnt [1])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[0]~17 ), + .combout(\timer_pwm|cnt[1]~18_combout ), + .cout(\timer_pwm|cnt[1]~19 )); +// synopsys translate_off +defparam \timer_pwm|cnt[1]~18 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N3 +dffeas \timer_pwm|cnt[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[1]~18_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[1] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N4 +cycloneive_lcell_comb \timer_pwm|cnt[2]~20 ( +// Equation(s): +// \timer_pwm|cnt[2]~20_combout = (\timer_pwm|cnt [2] & (\timer_pwm|cnt[1]~19 $ (GND))) # (!\timer_pwm|cnt [2] & (!\timer_pwm|cnt[1]~19 & VCC)) +// \timer_pwm|cnt[2]~21 = CARRY((\timer_pwm|cnt [2] & !\timer_pwm|cnt[1]~19 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[1]~19 ), + .combout(\timer_pwm|cnt[2]~20_combout ), + .cout(\timer_pwm|cnt[2]~21 )); +// synopsys translate_off +defparam \timer_pwm|cnt[2]~20 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N5 +dffeas \timer_pwm|cnt[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[2]~20_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[2] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N6 +cycloneive_lcell_comb \timer_pwm|cnt[3]~22 ( +// Equation(s): +// \timer_pwm|cnt[3]~22_combout = (\timer_pwm|cnt [3] & (!\timer_pwm|cnt[2]~21 )) # (!\timer_pwm|cnt [3] & ((\timer_pwm|cnt[2]~21 ) # (GND))) +// \timer_pwm|cnt[3]~23 = CARRY((!\timer_pwm|cnt[2]~21 ) # (!\timer_pwm|cnt [3])) + + .dataa(\timer_pwm|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[2]~21 ), + .combout(\timer_pwm|cnt[3]~22_combout ), + .cout(\timer_pwm|cnt[3]~23 )); +// synopsys translate_off +defparam \timer_pwm|cnt[3]~22 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N7 +dffeas \timer_pwm|cnt[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[3]~22_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[3] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N8 +cycloneive_lcell_comb \timer_pwm|cnt[4]~24 ( +// Equation(s): +// \timer_pwm|cnt[4]~24_combout = (\timer_pwm|cnt [4] & (\timer_pwm|cnt[3]~23 $ (GND))) # (!\timer_pwm|cnt [4] & (!\timer_pwm|cnt[3]~23 & VCC)) +// \timer_pwm|cnt[4]~25 = CARRY((\timer_pwm|cnt [4] & !\timer_pwm|cnt[3]~23 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[3]~23 ), + .combout(\timer_pwm|cnt[4]~24_combout ), + .cout(\timer_pwm|cnt[4]~25 )); +// synopsys translate_off +defparam \timer_pwm|cnt[4]~24 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N9 +dffeas \timer_pwm|cnt[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[4]~24_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[4] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N10 +cycloneive_lcell_comb \timer_pwm|cnt[5]~26 ( +// Equation(s): +// \timer_pwm|cnt[5]~26_combout = (\timer_pwm|cnt [5] & (!\timer_pwm|cnt[4]~25 )) # (!\timer_pwm|cnt [5] & ((\timer_pwm|cnt[4]~25 ) # (GND))) +// \timer_pwm|cnt[5]~27 = CARRY((!\timer_pwm|cnt[4]~25 ) # (!\timer_pwm|cnt [5])) + + .dataa(\timer_pwm|cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[4]~25 ), + .combout(\timer_pwm|cnt[5]~26_combout ), + .cout(\timer_pwm|cnt[5]~27 )); +// synopsys translate_off +defparam \timer_pwm|cnt[5]~26 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[5]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N11 +dffeas \timer_pwm|cnt[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[5]~26_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[5] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N12 +cycloneive_lcell_comb \timer_pwm|cnt[6]~28 ( +// Equation(s): +// \timer_pwm|cnt[6]~28_combout = (\timer_pwm|cnt [6] & (\timer_pwm|cnt[5]~27 $ (GND))) # (!\timer_pwm|cnt [6] & (!\timer_pwm|cnt[5]~27 & VCC)) +// \timer_pwm|cnt[6]~29 = CARRY((\timer_pwm|cnt [6] & !\timer_pwm|cnt[5]~27 )) + + .dataa(\timer_pwm|cnt [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[5]~27 ), + .combout(\timer_pwm|cnt[6]~28_combout ), + .cout(\timer_pwm|cnt[6]~29 )); +// synopsys translate_off +defparam \timer_pwm|cnt[6]~28 .lut_mask = 16'hA50A; +defparam \timer_pwm|cnt[6]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N13 +dffeas \timer_pwm|cnt[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[6]~28_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[6] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y21_N15 +dffeas \timer_pwm|cnt[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[7]~30_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[7] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \timer_pwm|Equal0~1 ( +// Equation(s): +// \timer_pwm|Equal0~1_combout = (!\timer_pwm|cnt [7] & (!\timer_pwm|cnt [6] & (!\timer_pwm|cnt [4] & !\timer_pwm|cnt [5]))) + + .dataa(\timer_pwm|cnt [7]), + .datab(\timer_pwm|cnt [6]), + .datac(\timer_pwm|cnt [4]), + .datad(\timer_pwm|cnt [5]), + .cin(gnd), + .combout(\timer_pwm|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~1 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N4 +cycloneive_lcell_comb \timer_pwm|Equal0~2 ( +// Equation(s): +// \timer_pwm|Equal0~2_combout = (!\timer_pwm|cnt [8] & (!\timer_pwm|cnt [11] & (!\timer_pwm|cnt [9] & !\timer_pwm|cnt [10]))) + + .dataa(\timer_pwm|cnt [8]), + .datab(\timer_pwm|cnt [11]), + .datac(\timer_pwm|cnt [9]), + .datad(\timer_pwm|cnt [10]), + .cin(gnd), + .combout(\timer_pwm|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~2 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \timer_pwm|Equal0~0 ( +// Equation(s): +// \timer_pwm|Equal0~0_combout = (!\timer_pwm|cnt [0] & (!\timer_pwm|cnt [3] & (!\timer_pwm|cnt [2] & !\timer_pwm|cnt [1]))) + + .dataa(\timer_pwm|cnt [0]), + .datab(\timer_pwm|cnt [3]), + .datac(\timer_pwm|cnt [2]), + .datad(\timer_pwm|cnt [1]), + .cin(gnd), + .combout(\timer_pwm|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~0 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \timer_pwm|Equal0~3 ( +// Equation(s): +// \timer_pwm|Equal0~3_combout = (!\timer_pwm|cnt [13] & (!\timer_pwm|cnt [15] & (!\timer_pwm|cnt [14] & !\timer_pwm|cnt [12]))) + + .dataa(\timer_pwm|cnt [13]), + .datab(\timer_pwm|cnt [15]), + .datac(\timer_pwm|cnt [14]), + .datad(\timer_pwm|cnt [12]), + .cin(gnd), + .combout(\timer_pwm|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~3 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \timer_pwm|Equal0~4 ( +// Equation(s): +// \timer_pwm|Equal0~4_combout = (\timer_pwm|Equal0~1_combout & (\timer_pwm|Equal0~2_combout & (\timer_pwm|Equal0~0_combout & \timer_pwm|Equal0~3_combout ))) + + .dataa(\timer_pwm|Equal0~1_combout ), + .datab(\timer_pwm|Equal0~2_combout ), + .datac(\timer_pwm|Equal0~0_combout ), + .datad(\timer_pwm|Equal0~3_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~4 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \timer_pwm|tim_ch[0]~1 ( +// Equation(s): +// \timer_pwm|tim_ch[0]~1_combout = !\timer_pwm|Equal0~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(\timer_pwm|Equal0~4_combout ), + .datad(gnd), + .cin(gnd), + .combout(\timer_pwm|tim_ch[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0]~1 .lut_mask = 16'h0F0F; +defparam \timer_pwm|tim_ch[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N15 +cycloneive_io_ibuf \tim_ccr1[7]~input ( + .i(tim_ccr1[7]), + .ibar(gnd), + .o(\tim_ccr1[7]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[7]~input .bus_hold = "false"; +defparam \tim_ccr1[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[7]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[7]~feeder_combout = \tim_ccr1[7]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[7]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[7]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N13 +dffeas \timer_pwm|r_tim_ccr1[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[7] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[6]~input ( + .i(tim_ccr1[6]), + .ibar(gnd), + .o(\tim_ccr1[6]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[6]~input .bus_hold = "false"; +defparam \tim_ccr1[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N27 +dffeas \timer_pwm|r_tim_ccr1[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[6]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[6] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \timer_pwm|Equal1~3 ( +// Equation(s): +// \timer_pwm|Equal1~3_combout = (\timer_pwm|r_tim_ccr1 [7] & (\timer_pwm|cnt [7] & (\timer_pwm|cnt [6] $ (!\timer_pwm|r_tim_ccr1 [6])))) # (!\timer_pwm|r_tim_ccr1 [7] & (!\timer_pwm|cnt [7] & (\timer_pwm|cnt [6] $ (!\timer_pwm|r_tim_ccr1 [6])))) + + .dataa(\timer_pwm|r_tim_ccr1 [7]), + .datab(\timer_pwm|cnt [6]), + .datac(\timer_pwm|r_tim_ccr1 [6]), + .datad(\timer_pwm|cnt [7]), + .cin(gnd), + .combout(\timer_pwm|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~3 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[5]~input ( + .i(tim_ccr1[5]), + .ibar(gnd), + .o(\tim_ccr1[5]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[5]~input .bus_hold = "false"; +defparam \tim_ccr1[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[5]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[5]~feeder_combout = \tim_ccr1[5]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[5]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[5]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N21 +dffeas \timer_pwm|r_tim_ccr1[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[5] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[4]~input ( + .i(tim_ccr1[4]), + .ibar(gnd), + .o(\tim_ccr1[4]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[4]~input .bus_hold = "false"; +defparam \tim_ccr1[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \timer_pwm|r_tim_ccr1[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[4]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[4] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \timer_pwm|Equal1~2 ( +// Equation(s): +// \timer_pwm|Equal1~2_combout = (\timer_pwm|cnt [4] & (\timer_pwm|r_tim_ccr1 [4] & (\timer_pwm|r_tim_ccr1 [5] $ (!\timer_pwm|cnt [5])))) # (!\timer_pwm|cnt [4] & (!\timer_pwm|r_tim_ccr1 [4] & (\timer_pwm|r_tim_ccr1 [5] $ (!\timer_pwm|cnt [5])))) + + .dataa(\timer_pwm|cnt [4]), + .datab(\timer_pwm|r_tim_ccr1 [5]), + .datac(\timer_pwm|r_tim_ccr1 [4]), + .datad(\timer_pwm|cnt [5]), + .cin(gnd), + .combout(\timer_pwm|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~2 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N8 +cycloneive_io_ibuf \tim_ccr1[2]~input ( + .i(tim_ccr1[2]), + .ibar(gnd), + .o(\tim_ccr1[2]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[2]~input .bus_hold = "false"; +defparam \tim_ccr1[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \timer_pwm|r_tim_ccr1[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[2]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[2] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[2] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N15 +cycloneive_io_ibuf \tim_ccr1[3]~input ( + .i(tim_ccr1[3]), + .ibar(gnd), + .o(\tim_ccr1[3]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[3]~input .bus_hold = "false"; +defparam \tim_ccr1[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[3]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[3]~feeder_combout = \tim_ccr1[3]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[3]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[3]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \timer_pwm|r_tim_ccr1[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[3] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \timer_pwm|Equal1~1 ( +// Equation(s): +// \timer_pwm|Equal1~1_combout = (\timer_pwm|cnt [3] & (\timer_pwm|r_tim_ccr1 [3] & (\timer_pwm|cnt [2] $ (!\timer_pwm|r_tim_ccr1 [2])))) # (!\timer_pwm|cnt [3] & (!\timer_pwm|r_tim_ccr1 [3] & (\timer_pwm|cnt [2] $ (!\timer_pwm|r_tim_ccr1 [2])))) + + .dataa(\timer_pwm|cnt [3]), + .datab(\timer_pwm|cnt [2]), + .datac(\timer_pwm|r_tim_ccr1 [2]), + .datad(\timer_pwm|r_tim_ccr1 [3]), + .cin(gnd), + .combout(\timer_pwm|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~1 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N1 +cycloneive_io_ibuf \tim_ccr1[1]~input ( + .i(tim_ccr1[1]), + .ibar(gnd), + .o(\tim_ccr1[1]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[1]~input .bus_hold = "false"; +defparam \tim_ccr1[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N17 +dffeas \timer_pwm|r_tim_ccr1[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[1]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[1] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[0]~input ( + .i(tim_ccr1[0]), + .ibar(gnd), + .o(\tim_ccr1[0]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[0]~input .bus_hold = "false"; +defparam \tim_ccr1[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N7 +dffeas \timer_pwm|r_tim_ccr1[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[0]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[0] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N6 +cycloneive_lcell_comb \timer_pwm|Equal1~0 ( +// Equation(s): +// \timer_pwm|Equal1~0_combout = (\timer_pwm|cnt [0] & (\timer_pwm|r_tim_ccr1 [0] & (\timer_pwm|r_tim_ccr1 [1] $ (!\timer_pwm|cnt [1])))) # (!\timer_pwm|cnt [0] & (!\timer_pwm|r_tim_ccr1 [0] & (\timer_pwm|r_tim_ccr1 [1] $ (!\timer_pwm|cnt [1])))) + + .dataa(\timer_pwm|cnt [0]), + .datab(\timer_pwm|r_tim_ccr1 [1]), + .datac(\timer_pwm|r_tim_ccr1 [0]), + .datad(\timer_pwm|cnt [1]), + .cin(gnd), + .combout(\timer_pwm|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~0 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \timer_pwm|Equal1~4 ( +// Equation(s): +// \timer_pwm|Equal1~4_combout = (\timer_pwm|Equal1~3_combout & (\timer_pwm|Equal1~2_combout & (\timer_pwm|Equal1~1_combout & \timer_pwm|Equal1~0_combout ))) + + .dataa(\timer_pwm|Equal1~3_combout ), + .datab(\timer_pwm|Equal1~2_combout ), + .datac(\timer_pwm|Equal1~1_combout ), + .datad(\timer_pwm|Equal1~0_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~4 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[15]~input ( + .i(tim_ccr1[15]), + .ibar(gnd), + .o(\tim_ccr1[15]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[15]~input .bus_hold = "false"; +defparam \tim_ccr1[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N28 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[15]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[15]~feeder_combout = \tim_ccr1[15]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[15]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[15]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N29 +dffeas \timer_pwm|r_tim_ccr1[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[15] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[15] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[14]~input ( + .i(tim_ccr1[14]), + .ibar(gnd), + .o(\tim_ccr1[14]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[14]~input .bus_hold = "false"; +defparam \tim_ccr1[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N23 +dffeas \timer_pwm|r_tim_ccr1[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[14]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[14] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \timer_pwm|Equal1~8 ( +// Equation(s): +// \timer_pwm|Equal1~8_combout = (\timer_pwm|r_tim_ccr1 [15] & (\timer_pwm|cnt [15] & (\timer_pwm|r_tim_ccr1 [14] $ (!\timer_pwm|cnt [14])))) # (!\timer_pwm|r_tim_ccr1 [15] & (!\timer_pwm|cnt [15] & (\timer_pwm|r_tim_ccr1 [14] $ (!\timer_pwm|cnt [14])))) + + .dataa(\timer_pwm|r_tim_ccr1 [15]), + .datab(\timer_pwm|cnt [15]), + .datac(\timer_pwm|r_tim_ccr1 [14]), + .datad(\timer_pwm|cnt [14]), + .cin(gnd), + .combout(\timer_pwm|Equal1~8_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~8 .lut_mask = 16'h9009; +defparam \timer_pwm|Equal1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[8]~input ( + .i(tim_ccr1[8]), + .ibar(gnd), + .o(\tim_ccr1[8]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[8]~input .bus_hold = "false"; +defparam \tim_ccr1[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N19 +dffeas \timer_pwm|r_tim_ccr1[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[8]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[8] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[8] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[9]~input ( + .i(tim_ccr1[9]), + .ibar(gnd), + .o(\tim_ccr1[9]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[9]~input .bus_hold = "false"; +defparam \tim_ccr1[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[9]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[9]~feeder_combout = \tim_ccr1[9]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[9]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[9]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N25 +dffeas \timer_pwm|r_tim_ccr1[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[9] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N18 +cycloneive_lcell_comb \timer_pwm|Equal1~5 ( +// Equation(s): +// \timer_pwm|Equal1~5_combout = (\timer_pwm|cnt [8] & (\timer_pwm|r_tim_ccr1 [8] & (\timer_pwm|cnt [9] $ (!\timer_pwm|r_tim_ccr1 [9])))) # (!\timer_pwm|cnt [8] & (!\timer_pwm|r_tim_ccr1 [8] & (\timer_pwm|cnt [9] $ (!\timer_pwm|r_tim_ccr1 [9])))) + + .dataa(\timer_pwm|cnt [8]), + .datab(\timer_pwm|cnt [9]), + .datac(\timer_pwm|r_tim_ccr1 [8]), + .datad(\timer_pwm|r_tim_ccr1 [9]), + .cin(gnd), + .combout(\timer_pwm|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~5 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[11]~input ( + .i(tim_ccr1[11]), + .ibar(gnd), + .o(\tim_ccr1[11]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[11]~input .bus_hold = "false"; +defparam \tim_ccr1[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N13 +dffeas \timer_pwm|r_tim_ccr1[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[11]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[11] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[11] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[10]~input ( + .i(tim_ccr1[10]), + .ibar(gnd), + .o(\tim_ccr1[10]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[10]~input .bus_hold = "false"; +defparam \tim_ccr1[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \timer_pwm|r_tim_ccr1[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[10]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[10] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \timer_pwm|Equal1~6 ( +// Equation(s): +// \timer_pwm|Equal1~6_combout = (\timer_pwm|r_tim_ccr1 [11] & (\timer_pwm|cnt [11] & (\timer_pwm|r_tim_ccr1 [10] $ (!\timer_pwm|cnt [10])))) # (!\timer_pwm|r_tim_ccr1 [11] & (!\timer_pwm|cnt [11] & (\timer_pwm|r_tim_ccr1 [10] $ (!\timer_pwm|cnt [10])))) + + .dataa(\timer_pwm|r_tim_ccr1 [11]), + .datab(\timer_pwm|cnt [11]), + .datac(\timer_pwm|r_tim_ccr1 [10]), + .datad(\timer_pwm|cnt [10]), + .cin(gnd), + .combout(\timer_pwm|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~6 .lut_mask = 16'h9009; +defparam \timer_pwm|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N15 +cycloneive_io_ibuf \tim_ccr1[12]~input ( + .i(tim_ccr1[12]), + .ibar(gnd), + .o(\tim_ccr1[12]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[12]~input .bus_hold = "false"; +defparam \tim_ccr1[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N11 +dffeas \timer_pwm|r_tim_ccr1[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[12]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[12] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[12] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[13]~input ( + .i(tim_ccr1[13]), + .ibar(gnd), + .o(\tim_ccr1[13]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[13]~input .bus_hold = "false"; +defparam \tim_ccr1[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[13]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[13]~feeder_combout = \tim_ccr1[13]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[13]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[13]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \timer_pwm|r_tim_ccr1[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[13]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[13] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N10 +cycloneive_lcell_comb \timer_pwm|Equal1~7 ( +// Equation(s): +// \timer_pwm|Equal1~7_combout = (\timer_pwm|cnt [13] & (\timer_pwm|r_tim_ccr1 [13] & (\timer_pwm|cnt [12] $ (!\timer_pwm|r_tim_ccr1 [12])))) # (!\timer_pwm|cnt [13] & (!\timer_pwm|r_tim_ccr1 [13] & (\timer_pwm|cnt [12] $ (!\timer_pwm|r_tim_ccr1 [12])))) + + .dataa(\timer_pwm|cnt [13]), + .datab(\timer_pwm|cnt [12]), + .datac(\timer_pwm|r_tim_ccr1 [12]), + .datad(\timer_pwm|r_tim_ccr1 [13]), + .cin(gnd), + .combout(\timer_pwm|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~7 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N20 +cycloneive_lcell_comb \timer_pwm|Equal1~9 ( +// Equation(s): +// \timer_pwm|Equal1~9_combout = (\timer_pwm|Equal1~8_combout & (\timer_pwm|Equal1~5_combout & (\timer_pwm|Equal1~6_combout & \timer_pwm|Equal1~7_combout ))) + + .dataa(\timer_pwm|Equal1~8_combout ), + .datab(\timer_pwm|Equal1~5_combout ), + .datac(\timer_pwm|Equal1~6_combout ), + .datad(\timer_pwm|Equal1~7_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal1~9_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~9 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \timer_pwm|tim_ch[0]~0 ( +// Equation(s): +// \timer_pwm|tim_ch[0]~0_combout = (\timer_pwm|Equal0~4_combout ) # ((\timer_pwm|Equal1~4_combout & \timer_pwm|Equal1~9_combout )) + + .dataa(gnd), + .datab(\timer_pwm|Equal1~4_combout ), + .datac(\timer_pwm|Equal0~4_combout ), + .datad(\timer_pwm|Equal1~9_combout ), + .cin(gnd), + .combout(\timer_pwm|tim_ch[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0]~0 .lut_mask = 16'hFCF0; +defparam \timer_pwm|tim_ch[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N29 +dffeas \timer_pwm|tim_ch[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|tim_ch[0]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\timer_pwm|tim_ch[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|tim_ch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0] .is_wysiwyg = "true"; +defparam \timer_pwm|tim_ch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \timer_pwm|tim_ch[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|Equal0~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\timer_pwm|tim_ch[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|tim_ch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|tim_ch[1] .is_wysiwyg = "true"; +defparam \timer_pwm|tim_ch[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y0_N22 +cycloneive_io_ibuf \tim_cr[0]~input ( + .i(tim_cr[0]), + .ibar(gnd), + .o(\tim_cr[0]~input_o )); +// synopsys translate_off +defparam \tim_cr[0]~input .bus_hold = "false"; +defparam \tim_cr[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y7_N22 +cycloneive_io_ibuf \tim_cr[1]~input ( + .i(tim_cr[1]), + .ibar(gnd), + .o(\tim_cr[1]~input_o )); +// synopsys translate_off +defparam \tim_cr[1]~input .bus_hold = "false"; +defparam \tim_cr[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N22 +cycloneive_io_ibuf \tim_cr[2]~input ( + .i(tim_cr[2]), + .ibar(gnd), + .o(\tim_cr[2]~input_o )); +// synopsys translate_off +defparam \tim_cr[2]~input .bus_hold = "false"; +defparam \tim_cr[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N1 +cycloneive_io_ibuf \tim_cr[3]~input ( + .i(tim_cr[3]), + .ibar(gnd), + .o(\tim_cr[3]~input_o )); +// synopsys translate_off +defparam \tim_cr[3]~input .bus_hold = "false"; +defparam \tim_cr[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y0_N15 +cycloneive_io_ibuf \tim_cr[4]~input ( + .i(tim_cr[4]), + .ibar(gnd), + .o(\tim_cr[4]~input_o )); +// synopsys translate_off +defparam \tim_cr[4]~input .bus_hold = "false"; +defparam \tim_cr[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N15 +cycloneive_io_ibuf \tim_cr[5]~input ( + .i(tim_cr[5]), + .ibar(gnd), + .o(\tim_cr[5]~input_o )); +// synopsys translate_off +defparam \tim_cr[5]~input .bus_hold = "false"; +defparam \tim_cr[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y0_N15 +cycloneive_io_ibuf \tim_cr[6]~input ( + .i(tim_cr[6]), + .ibar(gnd), + .o(\tim_cr[6]~input_o )); +// synopsys translate_off +defparam \tim_cr[6]~input .bus_hold = "false"; +defparam \tim_cr[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N8 +cycloneive_io_ibuf \tim_cr[7]~input ( + .i(tim_cr[7]), + .ibar(gnd), + .o(\tim_cr[7]~input_o )); +// synopsys translate_off +defparam \tim_cr[7]~input .bus_hold = "false"; +defparam \tim_cr[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N15 +cycloneive_io_ibuf \tim_cr[8]~input ( + .i(tim_cr[8]), + .ibar(gnd), + .o(\tim_cr[8]~input_o )); +// synopsys translate_off +defparam \tim_cr[8]~input .bus_hold = "false"; +defparam \tim_cr[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y0_N1 +cycloneive_io_ibuf \tim_cr[9]~input ( + .i(tim_cr[9]), + .ibar(gnd), + .o(\tim_cr[9]~input_o )); +// synopsys translate_off +defparam \tim_cr[9]~input .bus_hold = "false"; +defparam \tim_cr[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N1 +cycloneive_io_ibuf \tim_cr[10]~input ( + .i(tim_cr[10]), + .ibar(gnd), + .o(\tim_cr[10]~input_o )); +// synopsys translate_off +defparam \tim_cr[10]~input .bus_hold = "false"; +defparam \tim_cr[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y0_N8 +cycloneive_io_ibuf \tim_cr[11]~input ( + .i(tim_cr[11]), + .ibar(gnd), + .o(\tim_cr[11]~input_o )); +// synopsys translate_off +defparam \tim_cr[11]~input .bus_hold = "false"; +defparam \tim_cr[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N1 +cycloneive_io_ibuf \tim_cr[12]~input ( + .i(tim_cr[12]), + .ibar(gnd), + .o(\tim_cr[12]~input_o )); +// synopsys translate_off +defparam \tim_cr[12]~input .bus_hold = "false"; +defparam \tim_cr[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N22 +cycloneive_io_ibuf \tim_cr[13]~input ( + .i(tim_cr[13]), + .ibar(gnd), + .o(\tim_cr[13]~input_o )); +// synopsys translate_off +defparam \tim_cr[13]~input .bus_hold = "false"; +defparam \tim_cr[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y2_N15 +cycloneive_io_ibuf \tim_cr[14]~input ( + .i(tim_cr[14]), + .ibar(gnd), + .o(\tim_cr[14]~input_o )); +// synopsys translate_off +defparam \tim_cr[14]~input .bus_hold = "false"; +defparam \tim_cr[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N1 +cycloneive_io_ibuf \tim_cr[15]~input ( + .i(tim_cr[15]), + .ibar(gnd), + .o(\tim_cr[15]~input_o )); +// synopsys translate_off +defparam \tim_cr[15]~input .bus_hold = "false"; +defparam \tim_cr[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N15 +cycloneive_io_ibuf \tim_cr[16]~input ( + .i(tim_cr[16]), + .ibar(gnd), + .o(\tim_cr[16]~input_o )); +// synopsys translate_off +defparam \tim_cr[16]~input .bus_hold = "false"; +defparam \tim_cr[16]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N8 +cycloneive_io_ibuf \tim_cr[17]~input ( + .i(tim_cr[17]), + .ibar(gnd), + .o(\tim_cr[17]~input_o )); +// synopsys translate_off +defparam \tim_cr[17]~input .bus_hold = "false"; +defparam \tim_cr[17]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y0_N22 +cycloneive_io_ibuf \tim_cr[18]~input ( + .i(tim_cr[18]), + .ibar(gnd), + .o(\tim_cr[18]~input_o )); +// synopsys translate_off +defparam \tim_cr[18]~input .bus_hold = "false"; +defparam \tim_cr[18]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N8 +cycloneive_io_ibuf \tim_cr[19]~input ( + .i(tim_cr[19]), + .ibar(gnd), + .o(\tim_cr[19]~input_o )); +// synopsys translate_off +defparam \tim_cr[19]~input .bus_hold = "false"; +defparam \tim_cr[19]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N1 +cycloneive_io_ibuf \tim_cr[20]~input ( + .i(tim_cr[20]), + .ibar(gnd), + .o(\tim_cr[20]~input_o )); +// synopsys translate_off +defparam \tim_cr[20]~input .bus_hold = "false"; +defparam \tim_cr[20]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N1 +cycloneive_io_ibuf \tim_cr[21]~input ( + .i(tim_cr[21]), + .ibar(gnd), + .o(\tim_cr[21]~input_o )); +// synopsys translate_off +defparam \tim_cr[21]~input .bus_hold = "false"; +defparam \tim_cr[21]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y0_N15 +cycloneive_io_ibuf \tim_cr[22]~input ( + .i(tim_cr[22]), + .ibar(gnd), + .o(\tim_cr[22]~input_o )); +// synopsys translate_off +defparam \tim_cr[22]~input .bus_hold = "false"; +defparam \tim_cr[22]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N15 +cycloneive_io_ibuf \tim_cr[23]~input ( + .i(tim_cr[23]), + .ibar(gnd), + .o(\tim_cr[23]~input_o )); +// synopsys translate_off +defparam \tim_cr[23]~input .bus_hold = "false"; +defparam \tim_cr[23]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N22 +cycloneive_io_ibuf \tim_cr[24]~input ( + .i(tim_cr[24]), + .ibar(gnd), + .o(\tim_cr[24]~input_o )); +// synopsys translate_off +defparam \tim_cr[24]~input .bus_hold = "false"; +defparam \tim_cr[24]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y4_N22 +cycloneive_io_ibuf \tim_cr[25]~input ( + .i(tim_cr[25]), + .ibar(gnd), + .o(\tim_cr[25]~input_o )); +// synopsys translate_off +defparam \tim_cr[25]~input .bus_hold = "false"; +defparam \tim_cr[25]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y0_N15 +cycloneive_io_ibuf \tim_cr[26]~input ( + .i(tim_cr[26]), + .ibar(gnd), + .o(\tim_cr[26]~input_o )); +// synopsys translate_off +defparam \tim_cr[26]~input .bus_hold = "false"; +defparam \tim_cr[26]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N1 +cycloneive_io_ibuf \tim_cr[27]~input ( + .i(tim_cr[27]), + .ibar(gnd), + .o(\tim_cr[27]~input_o )); +// synopsys translate_off +defparam \tim_cr[27]~input .bus_hold = "false"; +defparam \tim_cr[27]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y6_N22 +cycloneive_io_ibuf \tim_cr[28]~input ( + .i(tim_cr[28]), + .ibar(gnd), + .o(\tim_cr[28]~input_o )); +// synopsys translate_off +defparam \tim_cr[28]~input .bus_hold = "false"; +defparam \tim_cr[28]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N8 +cycloneive_io_ibuf \tim_cr[29]~input ( + .i(tim_cr[29]), + .ibar(gnd), + .o(\tim_cr[29]~input_o )); +// synopsys translate_off +defparam \tim_cr[29]~input .bus_hold = "false"; +defparam \tim_cr[29]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y0_N22 +cycloneive_io_ibuf \tim_cr[30]~input ( + .i(tim_cr[30]), + .ibar(gnd), + .o(\tim_cr[30]~input_o )); +// synopsys translate_off +defparam \tim_cr[30]~input .bus_hold = "false"; +defparam \tim_cr[30]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N1 +cycloneive_io_ibuf \tim_cr[31]~input ( + .i(tim_cr[31]), + .ibar(gnd), + .o(\tim_cr[31]~input_o )); +// synopsys translate_off +defparam \tim_cr[31]~input .bus_hold = "false"; +defparam \tim_cr[31]~input .simulate_z_as = "z"; +// synopsys translate_on + +endmodule diff --git a/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_0c_slow.vo b/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..ff39d90 --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_0c_slow.vo @@ -0,0 +1,3276 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" + +// DATE "11/03/2018 15:43:36" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module timer_pwm_top ( + clk, + rst_n, + tim_cr, + tim_arr, + tim_ccr1, + tim_ch); +input clk; +input rst_n; +input [31:0] tim_cr; +input [15:0] tim_arr; +input [15:0] tim_ccr1; +output [7:0] tim_ch; + +// Design Ports Information +// tim_cr[0] => Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[1] => Location: PIN_N16, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[2] => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[3] => Location: PIN_N12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[4] => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[5] => Location: PIN_L11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[6] => Location: PIN_R13, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[7] => Location: PIN_M11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[8] => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[9] => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[10] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[11] => Location: PIN_T15, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[12] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[13] => Location: PIN_M9, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[14] => Location: PIN_M12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[15] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[16] => Location: PIN_N9, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[17] => Location: PIN_M6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[18] => Location: PIN_T7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[19] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[20] => Location: PIN_P6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[21] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[22] => Location: PIN_K10, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[23] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[24] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[25] => Location: PIN_N14, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[26] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[27] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[28] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[29] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[30] => Location: PIN_P11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[31] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[0] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[1] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[2] => Location: PIN_N3, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[3] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[4] => Location: PIN_P9, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[5] => Location: PIN_R16, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[6] => Location: PIN_M7, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[7] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[1] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[0] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[3] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[2] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[5] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[4] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[7] => Location: PIN_G11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[6] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[9] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[8] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[11] => Location: PIN_C14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[10] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[13] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[12] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[15] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[14] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[15] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[14] => Location: PIN_D9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[13] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[12] => Location: PIN_F11, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[11] => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[10] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[9] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[8] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[7] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[6] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[5] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[4] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[3] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[2] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[1] => Location: PIN_F10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[0] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("timer_pwm_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \tim_cr[0]~input_o ; +wire \tim_cr[1]~input_o ; +wire \tim_cr[2]~input_o ; +wire \tim_cr[3]~input_o ; +wire \tim_cr[4]~input_o ; +wire \tim_cr[5]~input_o ; +wire \tim_cr[6]~input_o ; +wire \tim_cr[7]~input_o ; +wire \tim_cr[8]~input_o ; +wire \tim_cr[9]~input_o ; +wire \tim_cr[10]~input_o ; +wire \tim_cr[11]~input_o ; +wire \tim_cr[12]~input_o ; +wire \tim_cr[13]~input_o ; +wire \tim_cr[14]~input_o ; +wire \tim_cr[15]~input_o ; +wire \tim_cr[16]~input_o ; +wire \tim_cr[17]~input_o ; +wire \tim_cr[18]~input_o ; +wire \tim_cr[19]~input_o ; +wire \tim_cr[20]~input_o ; +wire \tim_cr[21]~input_o ; +wire \tim_cr[22]~input_o ; +wire \tim_cr[23]~input_o ; +wire \tim_cr[24]~input_o ; +wire \tim_cr[25]~input_o ; +wire \tim_cr[26]~input_o ; +wire \tim_cr[27]~input_o ; +wire \tim_cr[28]~input_o ; +wire \tim_cr[29]~input_o ; +wire \tim_cr[30]~input_o ; +wire \tim_cr[31]~input_o ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \clk~input_o ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \timer_pwm|cnt[0]~16_combout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \my_pll|altpll_component|auto_generated|locked~combout ; +wire \my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ; +wire \tim_arr[15]~input_o ; +wire \timer_pwm|r_tim_arr[15]~feeder_combout ; +wire \timer_pwm|cnt[7]~31 ; +wire \timer_pwm|cnt[8]~32_combout ; +wire \timer_pwm|cnt[8]~33 ; +wire \timer_pwm|cnt[9]~34_combout ; +wire \timer_pwm|cnt[9]~35 ; +wire \timer_pwm|cnt[10]~36_combout ; +wire \timer_pwm|cnt[10]~37 ; +wire \timer_pwm|cnt[11]~38_combout ; +wire \timer_pwm|cnt[11]~39 ; +wire \timer_pwm|cnt[12]~40_combout ; +wire \timer_pwm|cnt[12]~41 ; +wire \timer_pwm|cnt[13]~42_combout ; +wire \timer_pwm|cnt[13]~43 ; +wire \timer_pwm|cnt[14]~44_combout ; +wire \timer_pwm|cnt[14]~45 ; +wire \timer_pwm|cnt[15]~46_combout ; +wire \tim_arr[14]~input_o ; +wire \timer_pwm|r_tim_arr[14]~feeder_combout ; +wire \tim_arr[13]~input_o ; +wire \tim_arr[12]~input_o ; +wire \tim_arr[11]~input_o ; +wire \timer_pwm|r_tim_arr[11]~feeder_combout ; +wire \tim_arr[10]~input_o ; +wire \timer_pwm|r_tim_arr[10]~feeder_combout ; +wire \tim_arr[9]~input_o ; +wire \tim_arr[8]~input_o ; +wire \tim_arr[7]~input_o ; +wire \tim_arr[6]~input_o ; +wire \tim_arr[5]~input_o ; +wire \tim_arr[4]~input_o ; +wire \timer_pwm|r_tim_arr[4]~feeder_combout ; +wire \tim_arr[3]~input_o ; +wire \tim_arr[2]~input_o ; +wire \timer_pwm|r_tim_arr[2]~feeder_combout ; +wire \tim_arr[1]~input_o ; +wire \tim_arr[0]~input_o ; +wire \timer_pwm|LessThan0~1_cout ; +wire \timer_pwm|LessThan0~3_cout ; +wire \timer_pwm|LessThan0~5_cout ; +wire \timer_pwm|LessThan0~7_cout ; +wire \timer_pwm|LessThan0~9_cout ; +wire \timer_pwm|LessThan0~11_cout ; +wire \timer_pwm|LessThan0~13_cout ; +wire \timer_pwm|LessThan0~15_cout ; +wire \timer_pwm|LessThan0~17_cout ; +wire \timer_pwm|LessThan0~19_cout ; +wire \timer_pwm|LessThan0~21_cout ; +wire \timer_pwm|LessThan0~23_cout ; +wire \timer_pwm|LessThan0~25_cout ; +wire \timer_pwm|LessThan0~27_cout ; +wire \timer_pwm|LessThan0~29_cout ; +wire \timer_pwm|LessThan0~30_combout ; +wire \timer_pwm|cnt[0]~17 ; +wire \timer_pwm|cnt[1]~18_combout ; +wire \timer_pwm|cnt[1]~19 ; +wire \timer_pwm|cnt[2]~20_combout ; +wire \timer_pwm|cnt[2]~21 ; +wire \timer_pwm|cnt[3]~22_combout ; +wire \timer_pwm|cnt[3]~23 ; +wire \timer_pwm|cnt[4]~24_combout ; +wire \timer_pwm|cnt[4]~25 ; +wire \timer_pwm|cnt[5]~26_combout ; +wire \timer_pwm|cnt[5]~27 ; +wire \timer_pwm|cnt[6]~28_combout ; +wire \timer_pwm|cnt[6]~29 ; +wire \timer_pwm|cnt[7]~30_combout ; +wire \timer_pwm|Equal0~1_combout ; +wire \timer_pwm|Equal0~2_combout ; +wire \timer_pwm|Equal0~0_combout ; +wire \timer_pwm|Equal0~3_combout ; +wire \timer_pwm|Equal0~4_combout ; +wire \timer_pwm|tim_ch[0]~1_combout ; +wire \tim_ccr1[7]~input_o ; +wire \timer_pwm|r_tim_ccr1[7]~feeder_combout ; +wire \tim_ccr1[6]~input_o ; +wire \timer_pwm|Equal1~3_combout ; +wire \tim_ccr1[5]~input_o ; +wire \timer_pwm|r_tim_ccr1[5]~feeder_combout ; +wire \tim_ccr1[4]~input_o ; +wire \timer_pwm|Equal1~2_combout ; +wire \tim_ccr1[2]~input_o ; +wire \tim_ccr1[3]~input_o ; +wire \timer_pwm|r_tim_ccr1[3]~feeder_combout ; +wire \timer_pwm|Equal1~1_combout ; +wire \tim_ccr1[1]~input_o ; +wire \tim_ccr1[0]~input_o ; +wire \timer_pwm|Equal1~0_combout ; +wire \timer_pwm|Equal1~4_combout ; +wire \tim_ccr1[15]~input_o ; +wire \timer_pwm|r_tim_ccr1[15]~feeder_combout ; +wire \tim_ccr1[14]~input_o ; +wire \timer_pwm|Equal1~8_combout ; +wire \tim_ccr1[8]~input_o ; +wire \tim_ccr1[9]~input_o ; +wire \timer_pwm|r_tim_ccr1[9]~feeder_combout ; +wire \timer_pwm|Equal1~5_combout ; +wire \tim_ccr1[11]~input_o ; +wire \tim_ccr1[10]~input_o ; +wire \timer_pwm|Equal1~6_combout ; +wire \tim_ccr1[12]~input_o ; +wire \tim_ccr1[13]~input_o ; +wire \timer_pwm|r_tim_ccr1[13]~feeder_combout ; +wire \timer_pwm|Equal1~7_combout ; +wire \timer_pwm|Equal1~9_combout ; +wire \timer_pwm|tim_ch[0]~0_combout ; +wire [15:0] \timer_pwm|cnt ; +wire [15:0] \timer_pwm|r_tim_arr ; +wire [4:0] \my_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [1:0] \timer_pwm|tim_ch ; +wire [15:0] \timer_pwm|r_tim_ccr1 ; + +wire [4:0] \my_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X32_Y24_N16 +cycloneive_io_obuf \tim_ch[0]~output ( + .i(\timer_pwm|tim_ch [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[0]), + .obar()); +// synopsys translate_off +defparam \tim_ch[0]~output .bus_hold = "false"; +defparam \tim_ch[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y20_N2 +cycloneive_io_obuf \tim_ch[1]~output ( + .i(\timer_pwm|tim_ch [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[1]), + .obar()); +// synopsys translate_off +defparam \tim_ch[1]~output .bus_hold = "false"; +defparam \tim_ch[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N23 +cycloneive_io_obuf \tim_ch[2]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[2]), + .obar()); +// synopsys translate_off +defparam \tim_ch[2]~output .bus_hold = "false"; +defparam \tim_ch[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y24_N23 +cycloneive_io_obuf \tim_ch[3]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[3]), + .obar()); +// synopsys translate_off +defparam \tim_ch[3]~output .bus_hold = "false"; +defparam \tim_ch[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X25_Y0_N2 +cycloneive_io_obuf \tim_ch[4]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[4]), + .obar()); +// synopsys translate_off +defparam \tim_ch[4]~output .bus_hold = "false"; +defparam \tim_ch[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y5_N16 +cycloneive_io_obuf \tim_ch[5]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[5]), + .obar()); +// synopsys translate_off +defparam \tim_ch[5]~output .bus_hold = "false"; +defparam \tim_ch[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y0_N23 +cycloneive_io_obuf \tim_ch[6]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[6]), + .obar()); +// synopsys translate_off +defparam \tim_ch[6]~output .bus_hold = "false"; +defparam \tim_ch[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N16 +cycloneive_io_obuf \tim_ch[7]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[7]), + .obar()); +// synopsys translate_off +defparam \tim_ch[7]~output .bus_hold = "false"; +defparam \tim_ch[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \my_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\my_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \my_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_high = 2; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_low = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_mode = "odd"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 4; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \my_pll|altpll_component|auto_generated|pll1 .m = 12; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \my_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "on"; +defparam \my_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \my_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N0 +cycloneive_lcell_comb \timer_pwm|cnt[0]~16 ( +// Equation(s): +// \timer_pwm|cnt[0]~16_combout = \timer_pwm|cnt [0] $ (VCC) +// \timer_pwm|cnt[0]~17 = CARRY(\timer_pwm|cnt [0]) + + .dataa(gnd), + .datab(\timer_pwm|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\timer_pwm|cnt[0]~16_combout ), + .cout(\timer_pwm|cnt[0]~17 )); +// synopsys translate_off +defparam \timer_pwm|cnt[0]~16 .lut_mask = 16'h33CC; +defparam \timer_pwm|cnt[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N28 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y8_N29 +dffeas \my_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N14 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|locked ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|locked~combout = (!\my_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\my_pll|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|locked~combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked .lut_mask = 16'h0FFF; +defparam \my_pll|altpll_component|auto_generated|locked .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G0 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|locked~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|locked~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N8 +cycloneive_io_ibuf \tim_arr[15]~input ( + .i(tim_arr[15]), + .ibar(gnd), + .o(\tim_arr[15]~input_o )); +// synopsys translate_off +defparam \tim_arr[15]~input .bus_hold = "false"; +defparam \tim_arr[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N12 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[15]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[15]~feeder_combout = \tim_arr[15]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[15]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[15]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N13 +dffeas \timer_pwm|r_tim_arr[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[15] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N14 +cycloneive_lcell_comb \timer_pwm|cnt[7]~30 ( +// Equation(s): +// \timer_pwm|cnt[7]~30_combout = (\timer_pwm|cnt [7] & (!\timer_pwm|cnt[6]~29 )) # (!\timer_pwm|cnt [7] & ((\timer_pwm|cnt[6]~29 ) # (GND))) +// \timer_pwm|cnt[7]~31 = CARRY((!\timer_pwm|cnt[6]~29 ) # (!\timer_pwm|cnt [7])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[6]~29 ), + .combout(\timer_pwm|cnt[7]~30_combout ), + .cout(\timer_pwm|cnt[7]~31 )); +// synopsys translate_off +defparam \timer_pwm|cnt[7]~30 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[7]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N16 +cycloneive_lcell_comb \timer_pwm|cnt[8]~32 ( +// Equation(s): +// \timer_pwm|cnt[8]~32_combout = (\timer_pwm|cnt [8] & (\timer_pwm|cnt[7]~31 $ (GND))) # (!\timer_pwm|cnt [8] & (!\timer_pwm|cnt[7]~31 & VCC)) +// \timer_pwm|cnt[8]~33 = CARRY((\timer_pwm|cnt [8] & !\timer_pwm|cnt[7]~31 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[7]~31 ), + .combout(\timer_pwm|cnt[8]~32_combout ), + .cout(\timer_pwm|cnt[8]~33 )); +// synopsys translate_off +defparam \timer_pwm|cnt[8]~32 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[8]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N17 +dffeas \timer_pwm|cnt[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[8]~32_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[8] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N18 +cycloneive_lcell_comb \timer_pwm|cnt[9]~34 ( +// Equation(s): +// \timer_pwm|cnt[9]~34_combout = (\timer_pwm|cnt [9] & (!\timer_pwm|cnt[8]~33 )) # (!\timer_pwm|cnt [9] & ((\timer_pwm|cnt[8]~33 ) # (GND))) +// \timer_pwm|cnt[9]~35 = CARRY((!\timer_pwm|cnt[8]~33 ) # (!\timer_pwm|cnt [9])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[8]~33 ), + .combout(\timer_pwm|cnt[9]~34_combout ), + .cout(\timer_pwm|cnt[9]~35 )); +// synopsys translate_off +defparam \timer_pwm|cnt[9]~34 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[9]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N19 +dffeas \timer_pwm|cnt[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[9]~34_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[9] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N20 +cycloneive_lcell_comb \timer_pwm|cnt[10]~36 ( +// Equation(s): +// \timer_pwm|cnt[10]~36_combout = (\timer_pwm|cnt [10] & (\timer_pwm|cnt[9]~35 $ (GND))) # (!\timer_pwm|cnt [10] & (!\timer_pwm|cnt[9]~35 & VCC)) +// \timer_pwm|cnt[10]~37 = CARRY((\timer_pwm|cnt [10] & !\timer_pwm|cnt[9]~35 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[9]~35 ), + .combout(\timer_pwm|cnt[10]~36_combout ), + .cout(\timer_pwm|cnt[10]~37 )); +// synopsys translate_off +defparam \timer_pwm|cnt[10]~36 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[10]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N21 +dffeas \timer_pwm|cnt[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[10]~36_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[10] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N22 +cycloneive_lcell_comb \timer_pwm|cnt[11]~38 ( +// Equation(s): +// \timer_pwm|cnt[11]~38_combout = (\timer_pwm|cnt [11] & (!\timer_pwm|cnt[10]~37 )) # (!\timer_pwm|cnt [11] & ((\timer_pwm|cnt[10]~37 ) # (GND))) +// \timer_pwm|cnt[11]~39 = CARRY((!\timer_pwm|cnt[10]~37 ) # (!\timer_pwm|cnt [11])) + + .dataa(\timer_pwm|cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[10]~37 ), + .combout(\timer_pwm|cnt[11]~38_combout ), + .cout(\timer_pwm|cnt[11]~39 )); +// synopsys translate_off +defparam \timer_pwm|cnt[11]~38 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[11]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N23 +dffeas \timer_pwm|cnt[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[11]~38_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[11] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N24 +cycloneive_lcell_comb \timer_pwm|cnt[12]~40 ( +// Equation(s): +// \timer_pwm|cnt[12]~40_combout = (\timer_pwm|cnt [12] & (\timer_pwm|cnt[11]~39 $ (GND))) # (!\timer_pwm|cnt [12] & (!\timer_pwm|cnt[11]~39 & VCC)) +// \timer_pwm|cnt[12]~41 = CARRY((\timer_pwm|cnt [12] & !\timer_pwm|cnt[11]~39 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [12]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[11]~39 ), + .combout(\timer_pwm|cnt[12]~40_combout ), + .cout(\timer_pwm|cnt[12]~41 )); +// synopsys translate_off +defparam \timer_pwm|cnt[12]~40 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[12]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N25 +dffeas \timer_pwm|cnt[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[12]~40_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[12] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N26 +cycloneive_lcell_comb \timer_pwm|cnt[13]~42 ( +// Equation(s): +// \timer_pwm|cnt[13]~42_combout = (\timer_pwm|cnt [13] & (!\timer_pwm|cnt[12]~41 )) # (!\timer_pwm|cnt [13] & ((\timer_pwm|cnt[12]~41 ) # (GND))) +// \timer_pwm|cnt[13]~43 = CARRY((!\timer_pwm|cnt[12]~41 ) # (!\timer_pwm|cnt [13])) + + .dataa(\timer_pwm|cnt [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[12]~41 ), + .combout(\timer_pwm|cnt[13]~42_combout ), + .cout(\timer_pwm|cnt[13]~43 )); +// synopsys translate_off +defparam \timer_pwm|cnt[13]~42 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[13]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N27 +dffeas \timer_pwm|cnt[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[13]~42_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[13] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N28 +cycloneive_lcell_comb \timer_pwm|cnt[14]~44 ( +// Equation(s): +// \timer_pwm|cnt[14]~44_combout = (\timer_pwm|cnt [14] & (\timer_pwm|cnt[13]~43 $ (GND))) # (!\timer_pwm|cnt [14] & (!\timer_pwm|cnt[13]~43 & VCC)) +// \timer_pwm|cnt[14]~45 = CARRY((\timer_pwm|cnt [14] & !\timer_pwm|cnt[13]~43 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [14]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[13]~43 ), + .combout(\timer_pwm|cnt[14]~44_combout ), + .cout(\timer_pwm|cnt[14]~45 )); +// synopsys translate_off +defparam \timer_pwm|cnt[14]~44 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[14]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N29 +dffeas \timer_pwm|cnt[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[14]~44_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[14] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N30 +cycloneive_lcell_comb \timer_pwm|cnt[15]~46 ( +// Equation(s): +// \timer_pwm|cnt[15]~46_combout = \timer_pwm|cnt [15] $ (\timer_pwm|cnt[14]~45 ) + + .dataa(\timer_pwm|cnt [15]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\timer_pwm|cnt[14]~45 ), + .combout(\timer_pwm|cnt[15]~46_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|cnt[15]~46 .lut_mask = 16'h5A5A; +defparam \timer_pwm|cnt[15]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N31 +dffeas \timer_pwm|cnt[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[15]~46_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[15] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[15] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N15 +cycloneive_io_ibuf \tim_arr[14]~input ( + .i(tim_arr[14]), + .ibar(gnd), + .o(\tim_arr[14]~input_o )); +// synopsys translate_off +defparam \tim_arr[14]~input .bus_hold = "false"; +defparam \tim_arr[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N14 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[14]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[14]~feeder_combout = \tim_arr[14]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[14]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[14]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N15 +dffeas \timer_pwm|r_tim_arr[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[14]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[14] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[14] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N8 +cycloneive_io_ibuf \tim_arr[13]~input ( + .i(tim_arr[13]), + .ibar(gnd), + .o(\tim_arr[13]~input_o )); +// synopsys translate_off +defparam \tim_arr[13]~input .bus_hold = "false"; +defparam \tim_arr[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N15 +dffeas \timer_pwm|r_tim_arr[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[13]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[13] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[13] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N22 +cycloneive_io_ibuf \tim_arr[12]~input ( + .i(tim_arr[12]), + .ibar(gnd), + .o(\tim_arr[12]~input_o )); +// synopsys translate_off +defparam \tim_arr[12]~input .bus_hold = "false"; +defparam \tim_arr[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X23_Y21_N9 +dffeas \timer_pwm|r_tim_arr[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[12]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[12] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[12] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N22 +cycloneive_io_ibuf \tim_arr[11]~input ( + .i(tim_arr[11]), + .ibar(gnd), + .o(\tim_arr[11]~input_o )); +// synopsys translate_off +defparam \tim_arr[11]~input .bus_hold = "false"; +defparam \tim_arr[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N2 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[11]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[11]~feeder_combout = \tim_arr[11]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[11]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[11]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N3 +dffeas \timer_pwm|r_tim_arr[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[11]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[11] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[11] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \tim_arr[10]~input ( + .i(tim_arr[10]), + .ibar(gnd), + .o(\tim_arr[10]~input_o )); +// synopsys translate_off +defparam \tim_arr[10]~input .bus_hold = "false"; +defparam \tim_arr[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N20 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[10]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[10]~feeder_combout = \tim_arr[10]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[10]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[10]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N21 +dffeas \timer_pwm|r_tim_arr[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[10] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N8 +cycloneive_io_ibuf \tim_arr[9]~input ( + .i(tim_arr[9]), + .ibar(gnd), + .o(\tim_arr[9]~input_o )); +// synopsys translate_off +defparam \tim_arr[9]~input .bus_hold = "false"; +defparam \tim_arr[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N31 +dffeas \timer_pwm|r_tim_arr[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[9]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[9] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[9] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N22 +cycloneive_io_ibuf \tim_arr[8]~input ( + .i(tim_arr[8]), + .ibar(gnd), + .o(\tim_arr[8]~input_o )); +// synopsys translate_off +defparam \tim_arr[8]~input .bus_hold = "false"; +defparam \tim_arr[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N7 +dffeas \timer_pwm|r_tim_arr[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[8]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[8] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[8] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N22 +cycloneive_io_ibuf \tim_arr[7]~input ( + .i(tim_arr[7]), + .ibar(gnd), + .o(\tim_arr[7]~input_o )); +// synopsys translate_off +defparam \tim_arr[7]~input .bus_hold = "false"; +defparam \tim_arr[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N21 +dffeas \timer_pwm|r_tim_arr[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[7]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[7] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N15 +cycloneive_io_ibuf \tim_arr[6]~input ( + .i(tim_arr[6]), + .ibar(gnd), + .o(\tim_arr[6]~input_o )); +// synopsys translate_off +defparam \tim_arr[6]~input .bus_hold = "false"; +defparam \tim_arr[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N5 +dffeas \timer_pwm|r_tim_arr[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[6]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[6] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[6] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N1 +cycloneive_io_ibuf \tim_arr[5]~input ( + .i(tim_arr[5]), + .ibar(gnd), + .o(\tim_arr[5]~input_o )); +// synopsys translate_off +defparam \tim_arr[5]~input .bus_hold = "false"; +defparam \tim_arr[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N3 +dffeas \timer_pwm|r_tim_arr[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[5]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[5] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N15 +cycloneive_io_ibuf \tim_arr[4]~input ( + .i(tim_arr[4]), + .ibar(gnd), + .o(\tim_arr[4]~input_o )); +// synopsys translate_off +defparam \tim_arr[4]~input .bus_hold = "false"; +defparam \tim_arr[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N10 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[4]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[4]~feeder_combout = \tim_arr[4]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[4]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[4]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N11 +dffeas \timer_pwm|r_tim_arr[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[4] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[4] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N8 +cycloneive_io_ibuf \tim_arr[3]~input ( + .i(tim_arr[3]), + .ibar(gnd), + .o(\tim_arr[3]~input_o )); +// synopsys translate_off +defparam \tim_arr[3]~input .bus_hold = "false"; +defparam \tim_arr[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N9 +dffeas \timer_pwm|r_tim_arr[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[3]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[3] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[3] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N15 +cycloneive_io_ibuf \tim_arr[2]~input ( + .i(tim_arr[2]), + .ibar(gnd), + .o(\tim_arr[2]~input_o )); +// synopsys translate_off +defparam \tim_arr[2]~input .bus_hold = "false"; +defparam \tim_arr[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[2]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[2]~feeder_combout = \tim_arr[2]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[2]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[2]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N25 +dffeas \timer_pwm|r_tim_arr[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[2] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[2] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N8 +cycloneive_io_ibuf \tim_arr[1]~input ( + .i(tim_arr[1]), + .ibar(gnd), + .o(\tim_arr[1]~input_o )); +// synopsys translate_off +defparam \tim_arr[1]~input .bus_hold = "false"; +defparam \tim_arr[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N23 +dffeas \timer_pwm|r_tim_arr[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[1]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[1] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N1 +cycloneive_io_ibuf \tim_arr[0]~input ( + .i(tim_arr[0]), + .ibar(gnd), + .o(\tim_arr[0]~input_o )); +// synopsys translate_off +defparam \tim_arr[0]~input .bus_hold = "false"; +defparam \tim_arr[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N29 +dffeas \timer_pwm|r_tim_arr[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[0]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[0] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N0 +cycloneive_lcell_comb \timer_pwm|LessThan0~1 ( +// Equation(s): +// \timer_pwm|LessThan0~1_cout = CARRY((\timer_pwm|r_tim_arr [0] & !\timer_pwm|cnt [0])) + + .dataa(\timer_pwm|r_tim_arr [0]), + .datab(\timer_pwm|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\timer_pwm|LessThan0~1_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~1 .lut_mask = 16'h0022; +defparam \timer_pwm|LessThan0~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N2 +cycloneive_lcell_comb \timer_pwm|LessThan0~3 ( +// Equation(s): +// \timer_pwm|LessThan0~3_cout = CARRY((\timer_pwm|cnt [1] & ((!\timer_pwm|LessThan0~1_cout ) # (!\timer_pwm|r_tim_arr [1]))) # (!\timer_pwm|cnt [1] & (!\timer_pwm|r_tim_arr [1] & !\timer_pwm|LessThan0~1_cout ))) + + .dataa(\timer_pwm|cnt [1]), + .datab(\timer_pwm|r_tim_arr [1]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~1_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~3_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~3 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N4 +cycloneive_lcell_comb \timer_pwm|LessThan0~5 ( +// Equation(s): +// \timer_pwm|LessThan0~5_cout = CARRY((\timer_pwm|cnt [2] & (\timer_pwm|r_tim_arr [2] & !\timer_pwm|LessThan0~3_cout )) # (!\timer_pwm|cnt [2] & ((\timer_pwm|r_tim_arr [2]) # (!\timer_pwm|LessThan0~3_cout )))) + + .dataa(\timer_pwm|cnt [2]), + .datab(\timer_pwm|r_tim_arr [2]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~3_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~5_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~5 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N6 +cycloneive_lcell_comb \timer_pwm|LessThan0~7 ( +// Equation(s): +// \timer_pwm|LessThan0~7_cout = CARRY((\timer_pwm|cnt [3] & ((!\timer_pwm|LessThan0~5_cout ) # (!\timer_pwm|r_tim_arr [3]))) # (!\timer_pwm|cnt [3] & (!\timer_pwm|r_tim_arr [3] & !\timer_pwm|LessThan0~5_cout ))) + + .dataa(\timer_pwm|cnt [3]), + .datab(\timer_pwm|r_tim_arr [3]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~5_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~7_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~7 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N8 +cycloneive_lcell_comb \timer_pwm|LessThan0~9 ( +// Equation(s): +// \timer_pwm|LessThan0~9_cout = CARRY((\timer_pwm|r_tim_arr [4] & ((!\timer_pwm|LessThan0~7_cout ) # (!\timer_pwm|cnt [4]))) # (!\timer_pwm|r_tim_arr [4] & (!\timer_pwm|cnt [4] & !\timer_pwm|LessThan0~7_cout ))) + + .dataa(\timer_pwm|r_tim_arr [4]), + .datab(\timer_pwm|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~7_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~9_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~9 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N10 +cycloneive_lcell_comb \timer_pwm|LessThan0~11 ( +// Equation(s): +// \timer_pwm|LessThan0~11_cout = CARRY((\timer_pwm|cnt [5] & ((!\timer_pwm|LessThan0~9_cout ) # (!\timer_pwm|r_tim_arr [5]))) # (!\timer_pwm|cnt [5] & (!\timer_pwm|r_tim_arr [5] & !\timer_pwm|LessThan0~9_cout ))) + + .dataa(\timer_pwm|cnt [5]), + .datab(\timer_pwm|r_tim_arr [5]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~9_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~11_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~11 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \timer_pwm|LessThan0~13 ( +// Equation(s): +// \timer_pwm|LessThan0~13_cout = CARRY((\timer_pwm|cnt [6] & (\timer_pwm|r_tim_arr [6] & !\timer_pwm|LessThan0~11_cout )) # (!\timer_pwm|cnt [6] & ((\timer_pwm|r_tim_arr [6]) # (!\timer_pwm|LessThan0~11_cout )))) + + .dataa(\timer_pwm|cnt [6]), + .datab(\timer_pwm|r_tim_arr [6]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~11_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~13_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~13 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N14 +cycloneive_lcell_comb \timer_pwm|LessThan0~15 ( +// Equation(s): +// \timer_pwm|LessThan0~15_cout = CARRY((\timer_pwm|r_tim_arr [7] & (\timer_pwm|cnt [7] & !\timer_pwm|LessThan0~13_cout )) # (!\timer_pwm|r_tim_arr [7] & ((\timer_pwm|cnt [7]) # (!\timer_pwm|LessThan0~13_cout )))) + + .dataa(\timer_pwm|r_tim_arr [7]), + .datab(\timer_pwm|cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~13_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~15_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~15 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N16 +cycloneive_lcell_comb \timer_pwm|LessThan0~17 ( +// Equation(s): +// \timer_pwm|LessThan0~17_cout = CARRY((\timer_pwm|r_tim_arr [8] & ((!\timer_pwm|LessThan0~15_cout ) # (!\timer_pwm|cnt [8]))) # (!\timer_pwm|r_tim_arr [8] & (!\timer_pwm|cnt [8] & !\timer_pwm|LessThan0~15_cout ))) + + .dataa(\timer_pwm|r_tim_arr [8]), + .datab(\timer_pwm|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~15_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~17_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~17 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N18 +cycloneive_lcell_comb \timer_pwm|LessThan0~19 ( +// Equation(s): +// \timer_pwm|LessThan0~19_cout = CARRY((\timer_pwm|r_tim_arr [9] & (\timer_pwm|cnt [9] & !\timer_pwm|LessThan0~17_cout )) # (!\timer_pwm|r_tim_arr [9] & ((\timer_pwm|cnt [9]) # (!\timer_pwm|LessThan0~17_cout )))) + + .dataa(\timer_pwm|r_tim_arr [9]), + .datab(\timer_pwm|cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~17_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~19_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~19 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N20 +cycloneive_lcell_comb \timer_pwm|LessThan0~21 ( +// Equation(s): +// \timer_pwm|LessThan0~21_cout = CARRY((\timer_pwm|cnt [10] & (\timer_pwm|r_tim_arr [10] & !\timer_pwm|LessThan0~19_cout )) # (!\timer_pwm|cnt [10] & ((\timer_pwm|r_tim_arr [10]) # (!\timer_pwm|LessThan0~19_cout )))) + + .dataa(\timer_pwm|cnt [10]), + .datab(\timer_pwm|r_tim_arr [10]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~19_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~21_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~21 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N22 +cycloneive_lcell_comb \timer_pwm|LessThan0~23 ( +// Equation(s): +// \timer_pwm|LessThan0~23_cout = CARRY((\timer_pwm|r_tim_arr [11] & (\timer_pwm|cnt [11] & !\timer_pwm|LessThan0~21_cout )) # (!\timer_pwm|r_tim_arr [11] & ((\timer_pwm|cnt [11]) # (!\timer_pwm|LessThan0~21_cout )))) + + .dataa(\timer_pwm|r_tim_arr [11]), + .datab(\timer_pwm|cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~21_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~23_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~23 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N24 +cycloneive_lcell_comb \timer_pwm|LessThan0~25 ( +// Equation(s): +// \timer_pwm|LessThan0~25_cout = CARRY((\timer_pwm|r_tim_arr [12] & ((!\timer_pwm|LessThan0~23_cout ) # (!\timer_pwm|cnt [12]))) # (!\timer_pwm|r_tim_arr [12] & (!\timer_pwm|cnt [12] & !\timer_pwm|LessThan0~23_cout ))) + + .dataa(\timer_pwm|r_tim_arr [12]), + .datab(\timer_pwm|cnt [12]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~23_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~25_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~25 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N26 +cycloneive_lcell_comb \timer_pwm|LessThan0~27 ( +// Equation(s): +// \timer_pwm|LessThan0~27_cout = CARRY((\timer_pwm|r_tim_arr [13] & (\timer_pwm|cnt [13] & !\timer_pwm|LessThan0~25_cout )) # (!\timer_pwm|r_tim_arr [13] & ((\timer_pwm|cnt [13]) # (!\timer_pwm|LessThan0~25_cout )))) + + .dataa(\timer_pwm|r_tim_arr [13]), + .datab(\timer_pwm|cnt [13]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~25_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~27_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~27 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N28 +cycloneive_lcell_comb \timer_pwm|LessThan0~29 ( +// Equation(s): +// \timer_pwm|LessThan0~29_cout = CARRY((\timer_pwm|r_tim_arr [14] & ((!\timer_pwm|LessThan0~27_cout ) # (!\timer_pwm|cnt [14]))) # (!\timer_pwm|r_tim_arr [14] & (!\timer_pwm|cnt [14] & !\timer_pwm|LessThan0~27_cout ))) + + .dataa(\timer_pwm|r_tim_arr [14]), + .datab(\timer_pwm|cnt [14]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~27_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~29_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~29 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N30 +cycloneive_lcell_comb \timer_pwm|LessThan0~30 ( +// Equation(s): +// \timer_pwm|LessThan0~30_combout = (\timer_pwm|r_tim_arr [15] & ((\timer_pwm|LessThan0~29_cout ) # (!\timer_pwm|cnt [15]))) # (!\timer_pwm|r_tim_arr [15] & (\timer_pwm|LessThan0~29_cout & !\timer_pwm|cnt [15])) + + .dataa(gnd), + .datab(\timer_pwm|r_tim_arr [15]), + .datac(gnd), + .datad(\timer_pwm|cnt [15]), + .cin(\timer_pwm|LessThan0~29_cout ), + .combout(\timer_pwm|LessThan0~30_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|LessThan0~30 .lut_mask = 16'hC0FC; +defparam \timer_pwm|LessThan0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N1 +dffeas \timer_pwm|cnt[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[0]~16_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[0] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N2 +cycloneive_lcell_comb \timer_pwm|cnt[1]~18 ( +// Equation(s): +// \timer_pwm|cnt[1]~18_combout = (\timer_pwm|cnt [1] & (!\timer_pwm|cnt[0]~17 )) # (!\timer_pwm|cnt [1] & ((\timer_pwm|cnt[0]~17 ) # (GND))) +// \timer_pwm|cnt[1]~19 = CARRY((!\timer_pwm|cnt[0]~17 ) # (!\timer_pwm|cnt [1])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[0]~17 ), + .combout(\timer_pwm|cnt[1]~18_combout ), + .cout(\timer_pwm|cnt[1]~19 )); +// synopsys translate_off +defparam \timer_pwm|cnt[1]~18 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N3 +dffeas \timer_pwm|cnt[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[1]~18_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[1] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N4 +cycloneive_lcell_comb \timer_pwm|cnt[2]~20 ( +// Equation(s): +// \timer_pwm|cnt[2]~20_combout = (\timer_pwm|cnt [2] & (\timer_pwm|cnt[1]~19 $ (GND))) # (!\timer_pwm|cnt [2] & (!\timer_pwm|cnt[1]~19 & VCC)) +// \timer_pwm|cnt[2]~21 = CARRY((\timer_pwm|cnt [2] & !\timer_pwm|cnt[1]~19 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[1]~19 ), + .combout(\timer_pwm|cnt[2]~20_combout ), + .cout(\timer_pwm|cnt[2]~21 )); +// synopsys translate_off +defparam \timer_pwm|cnt[2]~20 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N5 +dffeas \timer_pwm|cnt[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[2]~20_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[2] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N6 +cycloneive_lcell_comb \timer_pwm|cnt[3]~22 ( +// Equation(s): +// \timer_pwm|cnt[3]~22_combout = (\timer_pwm|cnt [3] & (!\timer_pwm|cnt[2]~21 )) # (!\timer_pwm|cnt [3] & ((\timer_pwm|cnt[2]~21 ) # (GND))) +// \timer_pwm|cnt[3]~23 = CARRY((!\timer_pwm|cnt[2]~21 ) # (!\timer_pwm|cnt [3])) + + .dataa(\timer_pwm|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[2]~21 ), + .combout(\timer_pwm|cnt[3]~22_combout ), + .cout(\timer_pwm|cnt[3]~23 )); +// synopsys translate_off +defparam \timer_pwm|cnt[3]~22 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N7 +dffeas \timer_pwm|cnt[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[3]~22_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[3] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N8 +cycloneive_lcell_comb \timer_pwm|cnt[4]~24 ( +// Equation(s): +// \timer_pwm|cnt[4]~24_combout = (\timer_pwm|cnt [4] & (\timer_pwm|cnt[3]~23 $ (GND))) # (!\timer_pwm|cnt [4] & (!\timer_pwm|cnt[3]~23 & VCC)) +// \timer_pwm|cnt[4]~25 = CARRY((\timer_pwm|cnt [4] & !\timer_pwm|cnt[3]~23 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[3]~23 ), + .combout(\timer_pwm|cnt[4]~24_combout ), + .cout(\timer_pwm|cnt[4]~25 )); +// synopsys translate_off +defparam \timer_pwm|cnt[4]~24 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N9 +dffeas \timer_pwm|cnt[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[4]~24_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[4] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N10 +cycloneive_lcell_comb \timer_pwm|cnt[5]~26 ( +// Equation(s): +// \timer_pwm|cnt[5]~26_combout = (\timer_pwm|cnt [5] & (!\timer_pwm|cnt[4]~25 )) # (!\timer_pwm|cnt [5] & ((\timer_pwm|cnt[4]~25 ) # (GND))) +// \timer_pwm|cnt[5]~27 = CARRY((!\timer_pwm|cnt[4]~25 ) # (!\timer_pwm|cnt [5])) + + .dataa(\timer_pwm|cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[4]~25 ), + .combout(\timer_pwm|cnt[5]~26_combout ), + .cout(\timer_pwm|cnt[5]~27 )); +// synopsys translate_off +defparam \timer_pwm|cnt[5]~26 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[5]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N11 +dffeas \timer_pwm|cnt[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[5]~26_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[5] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N12 +cycloneive_lcell_comb \timer_pwm|cnt[6]~28 ( +// Equation(s): +// \timer_pwm|cnt[6]~28_combout = (\timer_pwm|cnt [6] & (\timer_pwm|cnt[5]~27 $ (GND))) # (!\timer_pwm|cnt [6] & (!\timer_pwm|cnt[5]~27 & VCC)) +// \timer_pwm|cnt[6]~29 = CARRY((\timer_pwm|cnt [6] & !\timer_pwm|cnt[5]~27 )) + + .dataa(\timer_pwm|cnt [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[5]~27 ), + .combout(\timer_pwm|cnt[6]~28_combout ), + .cout(\timer_pwm|cnt[6]~29 )); +// synopsys translate_off +defparam \timer_pwm|cnt[6]~28 .lut_mask = 16'hA50A; +defparam \timer_pwm|cnt[6]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N13 +dffeas \timer_pwm|cnt[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[6]~28_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[6] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y21_N15 +dffeas \timer_pwm|cnt[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[7]~30_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[7] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \timer_pwm|Equal0~1 ( +// Equation(s): +// \timer_pwm|Equal0~1_combout = (!\timer_pwm|cnt [7] & (!\timer_pwm|cnt [6] & (!\timer_pwm|cnt [4] & !\timer_pwm|cnt [5]))) + + .dataa(\timer_pwm|cnt [7]), + .datab(\timer_pwm|cnt [6]), + .datac(\timer_pwm|cnt [4]), + .datad(\timer_pwm|cnt [5]), + .cin(gnd), + .combout(\timer_pwm|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~1 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N4 +cycloneive_lcell_comb \timer_pwm|Equal0~2 ( +// Equation(s): +// \timer_pwm|Equal0~2_combout = (!\timer_pwm|cnt [8] & (!\timer_pwm|cnt [11] & (!\timer_pwm|cnt [9] & !\timer_pwm|cnt [10]))) + + .dataa(\timer_pwm|cnt [8]), + .datab(\timer_pwm|cnt [11]), + .datac(\timer_pwm|cnt [9]), + .datad(\timer_pwm|cnt [10]), + .cin(gnd), + .combout(\timer_pwm|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~2 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \timer_pwm|Equal0~0 ( +// Equation(s): +// \timer_pwm|Equal0~0_combout = (!\timer_pwm|cnt [0] & (!\timer_pwm|cnt [3] & (!\timer_pwm|cnt [2] & !\timer_pwm|cnt [1]))) + + .dataa(\timer_pwm|cnt [0]), + .datab(\timer_pwm|cnt [3]), + .datac(\timer_pwm|cnt [2]), + .datad(\timer_pwm|cnt [1]), + .cin(gnd), + .combout(\timer_pwm|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~0 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \timer_pwm|Equal0~3 ( +// Equation(s): +// \timer_pwm|Equal0~3_combout = (!\timer_pwm|cnt [13] & (!\timer_pwm|cnt [15] & (!\timer_pwm|cnt [14] & !\timer_pwm|cnt [12]))) + + .dataa(\timer_pwm|cnt [13]), + .datab(\timer_pwm|cnt [15]), + .datac(\timer_pwm|cnt [14]), + .datad(\timer_pwm|cnt [12]), + .cin(gnd), + .combout(\timer_pwm|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~3 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \timer_pwm|Equal0~4 ( +// Equation(s): +// \timer_pwm|Equal0~4_combout = (\timer_pwm|Equal0~1_combout & (\timer_pwm|Equal0~2_combout & (\timer_pwm|Equal0~0_combout & \timer_pwm|Equal0~3_combout ))) + + .dataa(\timer_pwm|Equal0~1_combout ), + .datab(\timer_pwm|Equal0~2_combout ), + .datac(\timer_pwm|Equal0~0_combout ), + .datad(\timer_pwm|Equal0~3_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~4 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \timer_pwm|tim_ch[0]~1 ( +// Equation(s): +// \timer_pwm|tim_ch[0]~1_combout = !\timer_pwm|Equal0~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(\timer_pwm|Equal0~4_combout ), + .datad(gnd), + .cin(gnd), + .combout(\timer_pwm|tim_ch[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0]~1 .lut_mask = 16'h0F0F; +defparam \timer_pwm|tim_ch[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N15 +cycloneive_io_ibuf \tim_ccr1[7]~input ( + .i(tim_ccr1[7]), + .ibar(gnd), + .o(\tim_ccr1[7]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[7]~input .bus_hold = "false"; +defparam \tim_ccr1[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[7]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[7]~feeder_combout = \tim_ccr1[7]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[7]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[7]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N13 +dffeas \timer_pwm|r_tim_ccr1[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[7] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[6]~input ( + .i(tim_ccr1[6]), + .ibar(gnd), + .o(\tim_ccr1[6]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[6]~input .bus_hold = "false"; +defparam \tim_ccr1[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N27 +dffeas \timer_pwm|r_tim_ccr1[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[6]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[6] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \timer_pwm|Equal1~3 ( +// Equation(s): +// \timer_pwm|Equal1~3_combout = (\timer_pwm|r_tim_ccr1 [7] & (\timer_pwm|cnt [7] & (\timer_pwm|cnt [6] $ (!\timer_pwm|r_tim_ccr1 [6])))) # (!\timer_pwm|r_tim_ccr1 [7] & (!\timer_pwm|cnt [7] & (\timer_pwm|cnt [6] $ (!\timer_pwm|r_tim_ccr1 [6])))) + + .dataa(\timer_pwm|r_tim_ccr1 [7]), + .datab(\timer_pwm|cnt [6]), + .datac(\timer_pwm|r_tim_ccr1 [6]), + .datad(\timer_pwm|cnt [7]), + .cin(gnd), + .combout(\timer_pwm|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~3 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[5]~input ( + .i(tim_ccr1[5]), + .ibar(gnd), + .o(\tim_ccr1[5]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[5]~input .bus_hold = "false"; +defparam \tim_ccr1[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[5]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[5]~feeder_combout = \tim_ccr1[5]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[5]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[5]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N21 +dffeas \timer_pwm|r_tim_ccr1[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[5] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[4]~input ( + .i(tim_ccr1[4]), + .ibar(gnd), + .o(\tim_ccr1[4]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[4]~input .bus_hold = "false"; +defparam \tim_ccr1[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \timer_pwm|r_tim_ccr1[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[4]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[4] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \timer_pwm|Equal1~2 ( +// Equation(s): +// \timer_pwm|Equal1~2_combout = (\timer_pwm|cnt [4] & (\timer_pwm|r_tim_ccr1 [4] & (\timer_pwm|r_tim_ccr1 [5] $ (!\timer_pwm|cnt [5])))) # (!\timer_pwm|cnt [4] & (!\timer_pwm|r_tim_ccr1 [4] & (\timer_pwm|r_tim_ccr1 [5] $ (!\timer_pwm|cnt [5])))) + + .dataa(\timer_pwm|cnt [4]), + .datab(\timer_pwm|r_tim_ccr1 [5]), + .datac(\timer_pwm|r_tim_ccr1 [4]), + .datad(\timer_pwm|cnt [5]), + .cin(gnd), + .combout(\timer_pwm|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~2 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N8 +cycloneive_io_ibuf \tim_ccr1[2]~input ( + .i(tim_ccr1[2]), + .ibar(gnd), + .o(\tim_ccr1[2]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[2]~input .bus_hold = "false"; +defparam \tim_ccr1[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \timer_pwm|r_tim_ccr1[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[2]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[2] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[2] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N15 +cycloneive_io_ibuf \tim_ccr1[3]~input ( + .i(tim_ccr1[3]), + .ibar(gnd), + .o(\tim_ccr1[3]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[3]~input .bus_hold = "false"; +defparam \tim_ccr1[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[3]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[3]~feeder_combout = \tim_ccr1[3]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[3]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[3]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \timer_pwm|r_tim_ccr1[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[3] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \timer_pwm|Equal1~1 ( +// Equation(s): +// \timer_pwm|Equal1~1_combout = (\timer_pwm|cnt [3] & (\timer_pwm|r_tim_ccr1 [3] & (\timer_pwm|cnt [2] $ (!\timer_pwm|r_tim_ccr1 [2])))) # (!\timer_pwm|cnt [3] & (!\timer_pwm|r_tim_ccr1 [3] & (\timer_pwm|cnt [2] $ (!\timer_pwm|r_tim_ccr1 [2])))) + + .dataa(\timer_pwm|cnt [3]), + .datab(\timer_pwm|cnt [2]), + .datac(\timer_pwm|r_tim_ccr1 [2]), + .datad(\timer_pwm|r_tim_ccr1 [3]), + .cin(gnd), + .combout(\timer_pwm|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~1 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N1 +cycloneive_io_ibuf \tim_ccr1[1]~input ( + .i(tim_ccr1[1]), + .ibar(gnd), + .o(\tim_ccr1[1]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[1]~input .bus_hold = "false"; +defparam \tim_ccr1[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N17 +dffeas \timer_pwm|r_tim_ccr1[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[1]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[1] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[0]~input ( + .i(tim_ccr1[0]), + .ibar(gnd), + .o(\tim_ccr1[0]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[0]~input .bus_hold = "false"; +defparam \tim_ccr1[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N7 +dffeas \timer_pwm|r_tim_ccr1[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[0]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[0] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N6 +cycloneive_lcell_comb \timer_pwm|Equal1~0 ( +// Equation(s): +// \timer_pwm|Equal1~0_combout = (\timer_pwm|cnt [0] & (\timer_pwm|r_tim_ccr1 [0] & (\timer_pwm|r_tim_ccr1 [1] $ (!\timer_pwm|cnt [1])))) # (!\timer_pwm|cnt [0] & (!\timer_pwm|r_tim_ccr1 [0] & (\timer_pwm|r_tim_ccr1 [1] $ (!\timer_pwm|cnt [1])))) + + .dataa(\timer_pwm|cnt [0]), + .datab(\timer_pwm|r_tim_ccr1 [1]), + .datac(\timer_pwm|r_tim_ccr1 [0]), + .datad(\timer_pwm|cnt [1]), + .cin(gnd), + .combout(\timer_pwm|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~0 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \timer_pwm|Equal1~4 ( +// Equation(s): +// \timer_pwm|Equal1~4_combout = (\timer_pwm|Equal1~3_combout & (\timer_pwm|Equal1~2_combout & (\timer_pwm|Equal1~1_combout & \timer_pwm|Equal1~0_combout ))) + + .dataa(\timer_pwm|Equal1~3_combout ), + .datab(\timer_pwm|Equal1~2_combout ), + .datac(\timer_pwm|Equal1~1_combout ), + .datad(\timer_pwm|Equal1~0_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~4 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[15]~input ( + .i(tim_ccr1[15]), + .ibar(gnd), + .o(\tim_ccr1[15]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[15]~input .bus_hold = "false"; +defparam \tim_ccr1[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N28 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[15]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[15]~feeder_combout = \tim_ccr1[15]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[15]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[15]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N29 +dffeas \timer_pwm|r_tim_ccr1[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[15] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[15] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[14]~input ( + .i(tim_ccr1[14]), + .ibar(gnd), + .o(\tim_ccr1[14]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[14]~input .bus_hold = "false"; +defparam \tim_ccr1[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N23 +dffeas \timer_pwm|r_tim_ccr1[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[14]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[14] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \timer_pwm|Equal1~8 ( +// Equation(s): +// \timer_pwm|Equal1~8_combout = (\timer_pwm|r_tim_ccr1 [15] & (\timer_pwm|cnt [15] & (\timer_pwm|r_tim_ccr1 [14] $ (!\timer_pwm|cnt [14])))) # (!\timer_pwm|r_tim_ccr1 [15] & (!\timer_pwm|cnt [15] & (\timer_pwm|r_tim_ccr1 [14] $ (!\timer_pwm|cnt [14])))) + + .dataa(\timer_pwm|r_tim_ccr1 [15]), + .datab(\timer_pwm|cnt [15]), + .datac(\timer_pwm|r_tim_ccr1 [14]), + .datad(\timer_pwm|cnt [14]), + .cin(gnd), + .combout(\timer_pwm|Equal1~8_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~8 .lut_mask = 16'h9009; +defparam \timer_pwm|Equal1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[8]~input ( + .i(tim_ccr1[8]), + .ibar(gnd), + .o(\tim_ccr1[8]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[8]~input .bus_hold = "false"; +defparam \tim_ccr1[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N19 +dffeas \timer_pwm|r_tim_ccr1[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[8]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[8] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[8] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[9]~input ( + .i(tim_ccr1[9]), + .ibar(gnd), + .o(\tim_ccr1[9]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[9]~input .bus_hold = "false"; +defparam \tim_ccr1[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[9]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[9]~feeder_combout = \tim_ccr1[9]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[9]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[9]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N25 +dffeas \timer_pwm|r_tim_ccr1[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[9] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N18 +cycloneive_lcell_comb \timer_pwm|Equal1~5 ( +// Equation(s): +// \timer_pwm|Equal1~5_combout = (\timer_pwm|cnt [8] & (\timer_pwm|r_tim_ccr1 [8] & (\timer_pwm|cnt [9] $ (!\timer_pwm|r_tim_ccr1 [9])))) # (!\timer_pwm|cnt [8] & (!\timer_pwm|r_tim_ccr1 [8] & (\timer_pwm|cnt [9] $ (!\timer_pwm|r_tim_ccr1 [9])))) + + .dataa(\timer_pwm|cnt [8]), + .datab(\timer_pwm|cnt [9]), + .datac(\timer_pwm|r_tim_ccr1 [8]), + .datad(\timer_pwm|r_tim_ccr1 [9]), + .cin(gnd), + .combout(\timer_pwm|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~5 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[11]~input ( + .i(tim_ccr1[11]), + .ibar(gnd), + .o(\tim_ccr1[11]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[11]~input .bus_hold = "false"; +defparam \tim_ccr1[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N13 +dffeas \timer_pwm|r_tim_ccr1[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[11]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[11] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[11] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[10]~input ( + .i(tim_ccr1[10]), + .ibar(gnd), + .o(\tim_ccr1[10]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[10]~input .bus_hold = "false"; +defparam \tim_ccr1[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \timer_pwm|r_tim_ccr1[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[10]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[10] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \timer_pwm|Equal1~6 ( +// Equation(s): +// \timer_pwm|Equal1~6_combout = (\timer_pwm|r_tim_ccr1 [11] & (\timer_pwm|cnt [11] & (\timer_pwm|r_tim_ccr1 [10] $ (!\timer_pwm|cnt [10])))) # (!\timer_pwm|r_tim_ccr1 [11] & (!\timer_pwm|cnt [11] & (\timer_pwm|r_tim_ccr1 [10] $ (!\timer_pwm|cnt [10])))) + + .dataa(\timer_pwm|r_tim_ccr1 [11]), + .datab(\timer_pwm|cnt [11]), + .datac(\timer_pwm|r_tim_ccr1 [10]), + .datad(\timer_pwm|cnt [10]), + .cin(gnd), + .combout(\timer_pwm|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~6 .lut_mask = 16'h9009; +defparam \timer_pwm|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N15 +cycloneive_io_ibuf \tim_ccr1[12]~input ( + .i(tim_ccr1[12]), + .ibar(gnd), + .o(\tim_ccr1[12]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[12]~input .bus_hold = "false"; +defparam \tim_ccr1[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N11 +dffeas \timer_pwm|r_tim_ccr1[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[12]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[12] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[12] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[13]~input ( + .i(tim_ccr1[13]), + .ibar(gnd), + .o(\tim_ccr1[13]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[13]~input .bus_hold = "false"; +defparam \tim_ccr1[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[13]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[13]~feeder_combout = \tim_ccr1[13]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[13]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[13]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \timer_pwm|r_tim_ccr1[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[13]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[13] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N10 +cycloneive_lcell_comb \timer_pwm|Equal1~7 ( +// Equation(s): +// \timer_pwm|Equal1~7_combout = (\timer_pwm|cnt [13] & (\timer_pwm|r_tim_ccr1 [13] & (\timer_pwm|cnt [12] $ (!\timer_pwm|r_tim_ccr1 [12])))) # (!\timer_pwm|cnt [13] & (!\timer_pwm|r_tim_ccr1 [13] & (\timer_pwm|cnt [12] $ (!\timer_pwm|r_tim_ccr1 [12])))) + + .dataa(\timer_pwm|cnt [13]), + .datab(\timer_pwm|cnt [12]), + .datac(\timer_pwm|r_tim_ccr1 [12]), + .datad(\timer_pwm|r_tim_ccr1 [13]), + .cin(gnd), + .combout(\timer_pwm|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~7 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N20 +cycloneive_lcell_comb \timer_pwm|Equal1~9 ( +// Equation(s): +// \timer_pwm|Equal1~9_combout = (\timer_pwm|Equal1~8_combout & (\timer_pwm|Equal1~5_combout & (\timer_pwm|Equal1~6_combout & \timer_pwm|Equal1~7_combout ))) + + .dataa(\timer_pwm|Equal1~8_combout ), + .datab(\timer_pwm|Equal1~5_combout ), + .datac(\timer_pwm|Equal1~6_combout ), + .datad(\timer_pwm|Equal1~7_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal1~9_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~9 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \timer_pwm|tim_ch[0]~0 ( +// Equation(s): +// \timer_pwm|tim_ch[0]~0_combout = (\timer_pwm|Equal0~4_combout ) # ((\timer_pwm|Equal1~4_combout & \timer_pwm|Equal1~9_combout )) + + .dataa(gnd), + .datab(\timer_pwm|Equal1~4_combout ), + .datac(\timer_pwm|Equal0~4_combout ), + .datad(\timer_pwm|Equal1~9_combout ), + .cin(gnd), + .combout(\timer_pwm|tim_ch[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0]~0 .lut_mask = 16'hFCF0; +defparam \timer_pwm|tim_ch[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N29 +dffeas \timer_pwm|tim_ch[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|tim_ch[0]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\timer_pwm|tim_ch[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|tim_ch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0] .is_wysiwyg = "true"; +defparam \timer_pwm|tim_ch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \timer_pwm|tim_ch[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|Equal0~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\timer_pwm|tim_ch[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|tim_ch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|tim_ch[1] .is_wysiwyg = "true"; +defparam \timer_pwm|tim_ch[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y0_N22 +cycloneive_io_ibuf \tim_cr[0]~input ( + .i(tim_cr[0]), + .ibar(gnd), + .o(\tim_cr[0]~input_o )); +// synopsys translate_off +defparam \tim_cr[0]~input .bus_hold = "false"; +defparam \tim_cr[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y7_N22 +cycloneive_io_ibuf \tim_cr[1]~input ( + .i(tim_cr[1]), + .ibar(gnd), + .o(\tim_cr[1]~input_o )); +// synopsys translate_off +defparam \tim_cr[1]~input .bus_hold = "false"; +defparam \tim_cr[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N22 +cycloneive_io_ibuf \tim_cr[2]~input ( + .i(tim_cr[2]), + .ibar(gnd), + .o(\tim_cr[2]~input_o )); +// synopsys translate_off +defparam \tim_cr[2]~input .bus_hold = "false"; +defparam \tim_cr[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N1 +cycloneive_io_ibuf \tim_cr[3]~input ( + .i(tim_cr[3]), + .ibar(gnd), + .o(\tim_cr[3]~input_o )); +// synopsys translate_off +defparam \tim_cr[3]~input .bus_hold = "false"; +defparam \tim_cr[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y0_N15 +cycloneive_io_ibuf \tim_cr[4]~input ( + .i(tim_cr[4]), + .ibar(gnd), + .o(\tim_cr[4]~input_o )); +// synopsys translate_off +defparam \tim_cr[4]~input .bus_hold = "false"; +defparam \tim_cr[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N15 +cycloneive_io_ibuf \tim_cr[5]~input ( + .i(tim_cr[5]), + .ibar(gnd), + .o(\tim_cr[5]~input_o )); +// synopsys translate_off +defparam \tim_cr[5]~input .bus_hold = "false"; +defparam \tim_cr[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y0_N15 +cycloneive_io_ibuf \tim_cr[6]~input ( + .i(tim_cr[6]), + .ibar(gnd), + .o(\tim_cr[6]~input_o )); +// synopsys translate_off +defparam \tim_cr[6]~input .bus_hold = "false"; +defparam \tim_cr[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N8 +cycloneive_io_ibuf \tim_cr[7]~input ( + .i(tim_cr[7]), + .ibar(gnd), + .o(\tim_cr[7]~input_o )); +// synopsys translate_off +defparam \tim_cr[7]~input .bus_hold = "false"; +defparam \tim_cr[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N15 +cycloneive_io_ibuf \tim_cr[8]~input ( + .i(tim_cr[8]), + .ibar(gnd), + .o(\tim_cr[8]~input_o )); +// synopsys translate_off +defparam \tim_cr[8]~input .bus_hold = "false"; +defparam \tim_cr[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y0_N1 +cycloneive_io_ibuf \tim_cr[9]~input ( + .i(tim_cr[9]), + .ibar(gnd), + .o(\tim_cr[9]~input_o )); +// synopsys translate_off +defparam \tim_cr[9]~input .bus_hold = "false"; +defparam \tim_cr[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N1 +cycloneive_io_ibuf \tim_cr[10]~input ( + .i(tim_cr[10]), + .ibar(gnd), + .o(\tim_cr[10]~input_o )); +// synopsys translate_off +defparam \tim_cr[10]~input .bus_hold = "false"; +defparam \tim_cr[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y0_N8 +cycloneive_io_ibuf \tim_cr[11]~input ( + .i(tim_cr[11]), + .ibar(gnd), + .o(\tim_cr[11]~input_o )); +// synopsys translate_off +defparam \tim_cr[11]~input .bus_hold = "false"; +defparam \tim_cr[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N1 +cycloneive_io_ibuf \tim_cr[12]~input ( + .i(tim_cr[12]), + .ibar(gnd), + .o(\tim_cr[12]~input_o )); +// synopsys translate_off +defparam \tim_cr[12]~input .bus_hold = "false"; +defparam \tim_cr[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N22 +cycloneive_io_ibuf \tim_cr[13]~input ( + .i(tim_cr[13]), + .ibar(gnd), + .o(\tim_cr[13]~input_o )); +// synopsys translate_off +defparam \tim_cr[13]~input .bus_hold = "false"; +defparam \tim_cr[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y2_N15 +cycloneive_io_ibuf \tim_cr[14]~input ( + .i(tim_cr[14]), + .ibar(gnd), + .o(\tim_cr[14]~input_o )); +// synopsys translate_off +defparam \tim_cr[14]~input .bus_hold = "false"; +defparam \tim_cr[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N1 +cycloneive_io_ibuf \tim_cr[15]~input ( + .i(tim_cr[15]), + .ibar(gnd), + .o(\tim_cr[15]~input_o )); +// synopsys translate_off +defparam \tim_cr[15]~input .bus_hold = "false"; +defparam \tim_cr[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N15 +cycloneive_io_ibuf \tim_cr[16]~input ( + .i(tim_cr[16]), + .ibar(gnd), + .o(\tim_cr[16]~input_o )); +// synopsys translate_off +defparam \tim_cr[16]~input .bus_hold = "false"; +defparam \tim_cr[16]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N8 +cycloneive_io_ibuf \tim_cr[17]~input ( + .i(tim_cr[17]), + .ibar(gnd), + .o(\tim_cr[17]~input_o )); +// synopsys translate_off +defparam \tim_cr[17]~input .bus_hold = "false"; +defparam \tim_cr[17]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y0_N22 +cycloneive_io_ibuf \tim_cr[18]~input ( + .i(tim_cr[18]), + .ibar(gnd), + .o(\tim_cr[18]~input_o )); +// synopsys translate_off +defparam \tim_cr[18]~input .bus_hold = "false"; +defparam \tim_cr[18]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N8 +cycloneive_io_ibuf \tim_cr[19]~input ( + .i(tim_cr[19]), + .ibar(gnd), + .o(\tim_cr[19]~input_o )); +// synopsys translate_off +defparam \tim_cr[19]~input .bus_hold = "false"; +defparam \tim_cr[19]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N1 +cycloneive_io_ibuf \tim_cr[20]~input ( + .i(tim_cr[20]), + .ibar(gnd), + .o(\tim_cr[20]~input_o )); +// synopsys translate_off +defparam \tim_cr[20]~input .bus_hold = "false"; +defparam \tim_cr[20]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N1 +cycloneive_io_ibuf \tim_cr[21]~input ( + .i(tim_cr[21]), + .ibar(gnd), + .o(\tim_cr[21]~input_o )); +// synopsys translate_off +defparam \tim_cr[21]~input .bus_hold = "false"; +defparam \tim_cr[21]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y0_N15 +cycloneive_io_ibuf \tim_cr[22]~input ( + .i(tim_cr[22]), + .ibar(gnd), + .o(\tim_cr[22]~input_o )); +// synopsys translate_off +defparam \tim_cr[22]~input .bus_hold = "false"; +defparam \tim_cr[22]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N15 +cycloneive_io_ibuf \tim_cr[23]~input ( + .i(tim_cr[23]), + .ibar(gnd), + .o(\tim_cr[23]~input_o )); +// synopsys translate_off +defparam \tim_cr[23]~input .bus_hold = "false"; +defparam \tim_cr[23]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N22 +cycloneive_io_ibuf \tim_cr[24]~input ( + .i(tim_cr[24]), + .ibar(gnd), + .o(\tim_cr[24]~input_o )); +// synopsys translate_off +defparam \tim_cr[24]~input .bus_hold = "false"; +defparam \tim_cr[24]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y4_N22 +cycloneive_io_ibuf \tim_cr[25]~input ( + .i(tim_cr[25]), + .ibar(gnd), + .o(\tim_cr[25]~input_o )); +// synopsys translate_off +defparam \tim_cr[25]~input .bus_hold = "false"; +defparam \tim_cr[25]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y0_N15 +cycloneive_io_ibuf \tim_cr[26]~input ( + .i(tim_cr[26]), + .ibar(gnd), + .o(\tim_cr[26]~input_o )); +// synopsys translate_off +defparam \tim_cr[26]~input .bus_hold = "false"; +defparam \tim_cr[26]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N1 +cycloneive_io_ibuf \tim_cr[27]~input ( + .i(tim_cr[27]), + .ibar(gnd), + .o(\tim_cr[27]~input_o )); +// synopsys translate_off +defparam \tim_cr[27]~input .bus_hold = "false"; +defparam \tim_cr[27]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y6_N22 +cycloneive_io_ibuf \tim_cr[28]~input ( + .i(tim_cr[28]), + .ibar(gnd), + .o(\tim_cr[28]~input_o )); +// synopsys translate_off +defparam \tim_cr[28]~input .bus_hold = "false"; +defparam \tim_cr[28]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N8 +cycloneive_io_ibuf \tim_cr[29]~input ( + .i(tim_cr[29]), + .ibar(gnd), + .o(\tim_cr[29]~input_o )); +// synopsys translate_off +defparam \tim_cr[29]~input .bus_hold = "false"; +defparam \tim_cr[29]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y0_N22 +cycloneive_io_ibuf \tim_cr[30]~input ( + .i(tim_cr[30]), + .ibar(gnd), + .o(\tim_cr[30]~input_o )); +// synopsys translate_off +defparam \tim_cr[30]~input .bus_hold = "false"; +defparam \tim_cr[30]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N1 +cycloneive_io_ibuf \tim_cr[31]~input ( + .i(tim_cr[31]), + .ibar(gnd), + .o(\tim_cr[31]~input_o )); +// synopsys translate_off +defparam \tim_cr[31]~input .bus_hold = "false"; +defparam \tim_cr[31]~input .simulate_z_as = "z"; +// synopsys translate_on + +endmodule diff --git a/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_0c_v_slow.sdo b/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..45def1d --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,2064 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "timer_pwm_top") + (DATE "11/03/2018 15:43:36") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tim_ch\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1039:1039:1039) (884:884:884)) + (IOPATH i o (2773:2773:2773) (2737:2737:2737)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tim_ch\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (976:976:976) (832:832:832)) + (IOPATH i o (2800:2800:2800) (2762:2762:2762)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (758:758:758) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (194:194:194) (190:190:190)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (1180:1180:1180) (1180:1180:1180)) + (PORT inclk[0] (2058:2058:2058) (2058:2058:2058)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2046:2046:2046) (2011:2011:2011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (415:415:415)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1812:1812:1812) (2052:2052:2052)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1525:1525:1525) (1455:1455:1455)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked) + (DELAY + (ABSOLUTE + (PORT datac (1159:1159:1159) (1389:1389:1389)) + (PORT datad (277:277:277) (331:331:331)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1106:1106:1106) (1052:1052:1052)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3200:3200:3200) (3274:3274:3274)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1446:1446:1446) (1489:1489:1489)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1480:1480:1480) (1456:1456:1456)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[7\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[8\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[9\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (363:363:363) (418:418:418)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[10\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[11\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (425:425:425)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[12\]\~40) + (DELAY + (ABSOLUTE + (PORT datab (363:363:363) (418:418:418)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[13\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[14\]\~44) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (417:417:417)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[15\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (426:426:426)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (707:707:707) (731:731:731)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3133:3133:3133) (3221:3221:3221)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1446:1446:1446) (1489:1489:1489)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1480:1480:1480) (1456:1456:1456)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1447:1447:1447) (1490:1490:1490)) + (PORT asdata (3610:3610:3610) (3666:3666:3666)) + (PORT clrn (1481:1481:1481) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (747:747:747) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1446:1446:1446) (1489:1489:1489)) + (PORT asdata (3326:3326:3326) (3446:3446:3446)) + (PORT clrn (1480:1480:1480) (1456:1456:1456)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3125:3125:3125) (3210:3210:3210)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1446:1446:1446) (1489:1489:1489)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1480:1480:1480) (1456:1456:1456)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (758:758:758) (783:783:783)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1720:1720:1720) (1948:1948:1948)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1446:1446:1446) (1489:1489:1489)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1480:1480:1480) (1456:1456:1456)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1447:1447:1447) (1490:1490:1490)) + (PORT asdata (4006:4006:4006) (4009:4009:4009)) + (PORT clrn (1481:1481:1481) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1447:1447:1447) (1490:1490:1490)) + (PORT asdata (3977:3977:3977) (3981:3981:3981)) + (PORT clrn (1481:1481:1481) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1447:1447:1447) (1490:1490:1490)) + (PORT asdata (4373:4373:4373) (4301:4301:4301)) + (PORT clrn (1481:1481:1481) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1447:1447:1447) (1490:1490:1490)) + (PORT asdata (3268:3268:3268) (3414:3414:3414)) + (PORT clrn (1481:1481:1481) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1447:1447:1447) (1490:1490:1490)) + (PORT asdata (3646:3646:3646) (3690:3690:3690)) + (PORT clrn (1481:1481:1481) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3508:3508:3508) (3527:3527:3527)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1446:1446:1446) (1489:1489:1489)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1480:1480:1480) (1456:1456:1456)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1447:1447:1447) (1490:1490:1490)) + (PORT asdata (4307:4307:4307) (4249:4249:4249)) + (PORT clrn (1481:1481:1481) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (2899:2899:2899) (3030:3030:3030)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1446:1446:1446) (1489:1489:1489)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1480:1480:1480) (1456:1456:1456)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1447:1447:1447) (1490:1490:1490)) + (PORT asdata (3356:3356:3356) (3479:3479:3479)) + (PORT clrn (1481:1481:1481) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (767:767:767) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1447:1447:1447) (1490:1490:1490)) + (PORT asdata (3535:3535:3535) (3611:3611:3611)) + (PORT clrn (1481:1481:1481) (1457:1457:1457)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (519:519:519)) + (PORT datab (634:634:634) (588:588:588)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (557:557:557)) + (PORT datab (529:529:529) (513:513:513)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (626:626:626) (583:583:583)) + (PORT datab (580:580:580) (528:528:528)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (554:554:554)) + (PORT datab (317:317:317) (371:371:371)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (536:536:536)) + (PORT datab (617:617:617) (575:575:575)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (779:779:779)) + (PORT datab (317:317:317) (371:371:371)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (740:740:740)) + (PORT datab (317:317:317) (371:371:371)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (514:514:514)) + (PORT datab (617:617:617) (574:574:574)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (380:380:380)) + (PORT datab (932:932:932) (798:798:798)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (378:378:378)) + (PORT datab (638:638:638) (597:597:597)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~21) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (731:731:731)) + (PORT datab (578:578:578) (526:526:526)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~23) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (537:537:537)) + (PORT datab (632:632:632) (588:588:588)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~25) + (DELAY + (ABSOLUTE + (PORT dataa (523:523:523) (509:509:509)) + (PORT datab (632:632:632) (587:587:587)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~27) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (514:514:514)) + (PORT datab (846:846:846) (745:745:745)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~29) + (DELAY + (ABSOLUTE + (PORT dataa (525:525:525) (512:512:512)) + (PORT datab (576:576:576) (563:563:563)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~30) + (DELAY + (ABSOLUTE + (PORT datab (841:841:841) (740:740:740)) + (PORT datad (834:834:834) (736:736:736)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (393:393:393)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[5\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (425:425:425)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1491:1491:1491)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1482:1482:1482) (1458:1458:1458)) + (PORT sclr (979:979:979) (1097:1097:1097)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (868:868:868)) + (PORT datab (903:903:903) (843:843:843)) + (PORT datac (912:912:912) (836:836:836)) + (PORT datad (905:905:905) (834:834:834)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (556:556:556)) + (PORT datab (578:578:578) (556:556:556)) + (PORT datac (859:859:859) (786:786:786)) + (PORT datad (553:553:553) (526:526:526)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (853:853:853)) + (PORT datab (946:946:946) (858:858:858)) + (PORT datac (897:897:897) (830:830:830)) + (PORT datad (891:891:891) (825:825:825)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (584:584:584)) + (PORT datab (577:577:577) (554:554:554)) + (PORT datac (877:877:877) (798:798:798)) + (PORT datad (571:571:571) (542:542:542)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (285:285:285)) + (PORT datab (815:815:815) (693:693:693)) + (PORT datac (228:228:228) (244:244:244)) + (PORT datad (750:750:750) (637:637:637)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|tim_ch\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (231:231:231) (249:249:249)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (728:728:728) (753:753:753)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3267:3267:3267) (3321:3321:3321)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1452:1452:1452) (1495:1495:1495)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1486:1486:1486) (1462:1462:1462)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (707:707:707) (731:731:731)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1452:1452:1452) (1495:1495:1495)) + (PORT asdata (3579:3579:3579) (3651:3651:3651)) + (PORT clrn (1486:1486:1486) (1462:1462:1462)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (380:380:380)) + (PORT datab (904:904:904) (845:845:845)) + (PORT datad (909:909:909) (824:824:824)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (2870:2870:2870) (3013:3013:3013)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1452:1452:1452) (1495:1495:1495)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1486:1486:1486) (1462:1462:1462)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (747:747:747) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1452:1452:1452) (1495:1495:1495)) + (PORT asdata (3349:3349:3349) (3480:3480:3480)) + (PORT clrn (1486:1486:1486) (1462:1462:1462)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (874:874:874)) + (PORT datab (317:317:317) (372:372:372)) + (PORT datad (904:904:904) (833:833:833)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1452:1452:1452) (1495:1495:1495)) + (PORT asdata (3694:3694:3694) (3760:3760:3760)) + (PORT clrn (1486:1486:1486) (1462:1462:1462)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (707:707:707) (731:731:731)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (2917:2917:2917) (3050:3050:3050)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1452:1452:1452) (1495:1495:1495)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1486:1486:1486) (1462:1462:1462)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (848:848:848)) + (PORT datab (950:950:950) (866:866:866)) + (PORT datad (276:276:276) (331:331:331)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (738:738:738) (763:763:763)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1452:1452:1452) (1495:1495:1495)) + (PORT asdata (3679:3679:3679) (3734:3734:3734)) + (PORT clrn (1486:1486:1486) (1462:1462:1462)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1452:1452:1452) (1495:1495:1495)) + (PORT asdata (3339:3339:3339) (3470:3470:3470)) + (PORT clrn (1486:1486:1486) (1462:1462:1462)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (852:852:852)) + (PORT datab (318:318:318) (373:373:373)) + (PORT datad (890:890:890) (825:825:825)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (285:285:285)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (2940:2940:2940) (3061:3061:3061)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1492:1492:1492)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1483:1483:1483) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1492:1492:1492)) + (PORT asdata (3632:3632:3632) (3717:3717:3717)) + (PORT clrn (1483:1483:1483) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (515:515:515)) + (PORT datab (573:573:573) (550:550:550)) + (PORT datad (568:568:568) (538:538:538)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1492:1492:1492)) + (PORT asdata (3332:3332:3332) (3453:3453:3453)) + (PORT clrn (1483:1483:1483) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (2926:2926:2926) (3042:3042:3042)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1492:1492:1492)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1483:1483:1483) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (555:555:555)) + (PORT datab (571:571:571) (551:551:551)) + (PORT datad (276:276:276) (330:330:330)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1492:1492:1492)) + (PORT asdata (3961:3961:3961) (3961:3961:3961)) + (PORT clrn (1483:1483:1483) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1492:1492:1492)) + (PORT asdata (3681:3681:3681) (3755:3755:3755)) + (PORT clrn (1483:1483:1483) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (380:380:380)) + (PORT datab (576:576:576) (554:554:554)) + (PORT datad (551:551:551) (524:524:524)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (727:727:727) (751:751:751)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1492:1492:1492)) + (PORT asdata (3273:3273:3273) (3419:3419:3419)) + (PORT clrn (1483:1483:1483) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3236:3236:3236) (3316:3316:3316)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1448:1448:1448) (1492:1492:1492)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1483:1483:1483) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (583:583:583)) + (PORT datab (631:631:631) (582:582:582)) + (PORT datad (277:277:277) (332:332:332)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (282:282:282)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|tim_ch\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (234:234:234) (252:252:252)) + (PORT datad (788:788:788) (666:666:666)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|tim_ch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1452:1452:1452) (1495:1495:1495)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (973:973:973) (947:947:947)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|tim_ch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1452:1452:1452) (1495:1495:1495)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (973:973:973) (947:947:947)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) +) diff --git a/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo b/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..1fc75f5 --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_slow.vo @@ -0,0 +1,3276 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" + +// DATE "11/03/2018 15:43:36" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module timer_pwm_top ( + clk, + rst_n, + tim_cr, + tim_arr, + tim_ccr1, + tim_ch); +input clk; +input rst_n; +input [31:0] tim_cr; +input [15:0] tim_arr; +input [15:0] tim_ccr1; +output [7:0] tim_ch; + +// Design Ports Information +// tim_cr[0] => Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[1] => Location: PIN_N16, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[2] => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[3] => Location: PIN_N12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[4] => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[5] => Location: PIN_L11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[6] => Location: PIN_R13, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[7] => Location: PIN_M11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[8] => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[9] => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[10] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[11] => Location: PIN_T15, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[12] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[13] => Location: PIN_M9, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[14] => Location: PIN_M12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[15] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[16] => Location: PIN_N9, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[17] => Location: PIN_M6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[18] => Location: PIN_T7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[19] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[20] => Location: PIN_P6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[21] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[22] => Location: PIN_K10, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[23] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[24] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[25] => Location: PIN_N14, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[26] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[27] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[28] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[29] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[30] => Location: PIN_P11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[31] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[0] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[1] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[2] => Location: PIN_N3, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[3] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[4] => Location: PIN_P9, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[5] => Location: PIN_R16, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[6] => Location: PIN_M7, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[7] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[1] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[0] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[3] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[2] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[5] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[4] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[7] => Location: PIN_G11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[6] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[9] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[8] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[11] => Location: PIN_C14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[10] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[13] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[12] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[15] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[14] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[15] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[14] => Location: PIN_D9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[13] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[12] => Location: PIN_F11, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[11] => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[10] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[9] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[8] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[7] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[6] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[5] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[4] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[3] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[2] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[1] => Location: PIN_F10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[0] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("timer_pwm_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \tim_cr[0]~input_o ; +wire \tim_cr[1]~input_o ; +wire \tim_cr[2]~input_o ; +wire \tim_cr[3]~input_o ; +wire \tim_cr[4]~input_o ; +wire \tim_cr[5]~input_o ; +wire \tim_cr[6]~input_o ; +wire \tim_cr[7]~input_o ; +wire \tim_cr[8]~input_o ; +wire \tim_cr[9]~input_o ; +wire \tim_cr[10]~input_o ; +wire \tim_cr[11]~input_o ; +wire \tim_cr[12]~input_o ; +wire \tim_cr[13]~input_o ; +wire \tim_cr[14]~input_o ; +wire \tim_cr[15]~input_o ; +wire \tim_cr[16]~input_o ; +wire \tim_cr[17]~input_o ; +wire \tim_cr[18]~input_o ; +wire \tim_cr[19]~input_o ; +wire \tim_cr[20]~input_o ; +wire \tim_cr[21]~input_o ; +wire \tim_cr[22]~input_o ; +wire \tim_cr[23]~input_o ; +wire \tim_cr[24]~input_o ; +wire \tim_cr[25]~input_o ; +wire \tim_cr[26]~input_o ; +wire \tim_cr[27]~input_o ; +wire \tim_cr[28]~input_o ; +wire \tim_cr[29]~input_o ; +wire \tim_cr[30]~input_o ; +wire \tim_cr[31]~input_o ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \clk~input_o ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \timer_pwm|cnt[0]~16_combout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \my_pll|altpll_component|auto_generated|locked~combout ; +wire \my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ; +wire \tim_arr[15]~input_o ; +wire \timer_pwm|r_tim_arr[15]~feeder_combout ; +wire \timer_pwm|cnt[7]~31 ; +wire \timer_pwm|cnt[8]~32_combout ; +wire \timer_pwm|cnt[8]~33 ; +wire \timer_pwm|cnt[9]~34_combout ; +wire \timer_pwm|cnt[9]~35 ; +wire \timer_pwm|cnt[10]~36_combout ; +wire \timer_pwm|cnt[10]~37 ; +wire \timer_pwm|cnt[11]~38_combout ; +wire \timer_pwm|cnt[11]~39 ; +wire \timer_pwm|cnt[12]~40_combout ; +wire \timer_pwm|cnt[12]~41 ; +wire \timer_pwm|cnt[13]~42_combout ; +wire \timer_pwm|cnt[13]~43 ; +wire \timer_pwm|cnt[14]~44_combout ; +wire \timer_pwm|cnt[14]~45 ; +wire \timer_pwm|cnt[15]~46_combout ; +wire \tim_arr[14]~input_o ; +wire \timer_pwm|r_tim_arr[14]~feeder_combout ; +wire \tim_arr[13]~input_o ; +wire \tim_arr[12]~input_o ; +wire \tim_arr[11]~input_o ; +wire \timer_pwm|r_tim_arr[11]~feeder_combout ; +wire \tim_arr[10]~input_o ; +wire \timer_pwm|r_tim_arr[10]~feeder_combout ; +wire \tim_arr[9]~input_o ; +wire \tim_arr[8]~input_o ; +wire \tim_arr[7]~input_o ; +wire \tim_arr[6]~input_o ; +wire \tim_arr[5]~input_o ; +wire \tim_arr[4]~input_o ; +wire \timer_pwm|r_tim_arr[4]~feeder_combout ; +wire \tim_arr[3]~input_o ; +wire \tim_arr[2]~input_o ; +wire \timer_pwm|r_tim_arr[2]~feeder_combout ; +wire \tim_arr[1]~input_o ; +wire \tim_arr[0]~input_o ; +wire \timer_pwm|LessThan0~1_cout ; +wire \timer_pwm|LessThan0~3_cout ; +wire \timer_pwm|LessThan0~5_cout ; +wire \timer_pwm|LessThan0~7_cout ; +wire \timer_pwm|LessThan0~9_cout ; +wire \timer_pwm|LessThan0~11_cout ; +wire \timer_pwm|LessThan0~13_cout ; +wire \timer_pwm|LessThan0~15_cout ; +wire \timer_pwm|LessThan0~17_cout ; +wire \timer_pwm|LessThan0~19_cout ; +wire \timer_pwm|LessThan0~21_cout ; +wire \timer_pwm|LessThan0~23_cout ; +wire \timer_pwm|LessThan0~25_cout ; +wire \timer_pwm|LessThan0~27_cout ; +wire \timer_pwm|LessThan0~29_cout ; +wire \timer_pwm|LessThan0~30_combout ; +wire \timer_pwm|cnt[0]~17 ; +wire \timer_pwm|cnt[1]~18_combout ; +wire \timer_pwm|cnt[1]~19 ; +wire \timer_pwm|cnt[2]~20_combout ; +wire \timer_pwm|cnt[2]~21 ; +wire \timer_pwm|cnt[3]~22_combout ; +wire \timer_pwm|cnt[3]~23 ; +wire \timer_pwm|cnt[4]~24_combout ; +wire \timer_pwm|cnt[4]~25 ; +wire \timer_pwm|cnt[5]~26_combout ; +wire \timer_pwm|cnt[5]~27 ; +wire \timer_pwm|cnt[6]~28_combout ; +wire \timer_pwm|cnt[6]~29 ; +wire \timer_pwm|cnt[7]~30_combout ; +wire \timer_pwm|Equal0~1_combout ; +wire \timer_pwm|Equal0~2_combout ; +wire \timer_pwm|Equal0~0_combout ; +wire \timer_pwm|Equal0~3_combout ; +wire \timer_pwm|Equal0~4_combout ; +wire \timer_pwm|tim_ch[0]~1_combout ; +wire \tim_ccr1[7]~input_o ; +wire \timer_pwm|r_tim_ccr1[7]~feeder_combout ; +wire \tim_ccr1[6]~input_o ; +wire \timer_pwm|Equal1~3_combout ; +wire \tim_ccr1[5]~input_o ; +wire \timer_pwm|r_tim_ccr1[5]~feeder_combout ; +wire \tim_ccr1[4]~input_o ; +wire \timer_pwm|Equal1~2_combout ; +wire \tim_ccr1[2]~input_o ; +wire \tim_ccr1[3]~input_o ; +wire \timer_pwm|r_tim_ccr1[3]~feeder_combout ; +wire \timer_pwm|Equal1~1_combout ; +wire \tim_ccr1[1]~input_o ; +wire \tim_ccr1[0]~input_o ; +wire \timer_pwm|Equal1~0_combout ; +wire \timer_pwm|Equal1~4_combout ; +wire \tim_ccr1[15]~input_o ; +wire \timer_pwm|r_tim_ccr1[15]~feeder_combout ; +wire \tim_ccr1[14]~input_o ; +wire \timer_pwm|Equal1~8_combout ; +wire \tim_ccr1[8]~input_o ; +wire \tim_ccr1[9]~input_o ; +wire \timer_pwm|r_tim_ccr1[9]~feeder_combout ; +wire \timer_pwm|Equal1~5_combout ; +wire \tim_ccr1[11]~input_o ; +wire \tim_ccr1[10]~input_o ; +wire \timer_pwm|Equal1~6_combout ; +wire \tim_ccr1[12]~input_o ; +wire \tim_ccr1[13]~input_o ; +wire \timer_pwm|r_tim_ccr1[13]~feeder_combout ; +wire \timer_pwm|Equal1~7_combout ; +wire \timer_pwm|Equal1~9_combout ; +wire \timer_pwm|tim_ch[0]~0_combout ; +wire [15:0] \timer_pwm|cnt ; +wire [15:0] \timer_pwm|r_tim_arr ; +wire [4:0] \my_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [1:0] \timer_pwm|tim_ch ; +wire [15:0] \timer_pwm|r_tim_ccr1 ; + +wire [4:0] \my_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X32_Y24_N16 +cycloneive_io_obuf \tim_ch[0]~output ( + .i(\timer_pwm|tim_ch [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[0]), + .obar()); +// synopsys translate_off +defparam \tim_ch[0]~output .bus_hold = "false"; +defparam \tim_ch[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y20_N2 +cycloneive_io_obuf \tim_ch[1]~output ( + .i(\timer_pwm|tim_ch [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[1]), + .obar()); +// synopsys translate_off +defparam \tim_ch[1]~output .bus_hold = "false"; +defparam \tim_ch[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N23 +cycloneive_io_obuf \tim_ch[2]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[2]), + .obar()); +// synopsys translate_off +defparam \tim_ch[2]~output .bus_hold = "false"; +defparam \tim_ch[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y24_N23 +cycloneive_io_obuf \tim_ch[3]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[3]), + .obar()); +// synopsys translate_off +defparam \tim_ch[3]~output .bus_hold = "false"; +defparam \tim_ch[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X25_Y0_N2 +cycloneive_io_obuf \tim_ch[4]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[4]), + .obar()); +// synopsys translate_off +defparam \tim_ch[4]~output .bus_hold = "false"; +defparam \tim_ch[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y5_N16 +cycloneive_io_obuf \tim_ch[5]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[5]), + .obar()); +// synopsys translate_off +defparam \tim_ch[5]~output .bus_hold = "false"; +defparam \tim_ch[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y0_N23 +cycloneive_io_obuf \tim_ch[6]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[6]), + .obar()); +// synopsys translate_off +defparam \tim_ch[6]~output .bus_hold = "false"; +defparam \tim_ch[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N16 +cycloneive_io_obuf \tim_ch[7]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[7]), + .obar()); +// synopsys translate_off +defparam \tim_ch[7]~output .bus_hold = "false"; +defparam \tim_ch[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \my_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\my_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \my_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_high = 2; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_low = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_mode = "odd"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 4; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \my_pll|altpll_component|auto_generated|pll1 .m = 12; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \my_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "on"; +defparam \my_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \my_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N0 +cycloneive_lcell_comb \timer_pwm|cnt[0]~16 ( +// Equation(s): +// \timer_pwm|cnt[0]~16_combout = \timer_pwm|cnt [0] $ (VCC) +// \timer_pwm|cnt[0]~17 = CARRY(\timer_pwm|cnt [0]) + + .dataa(gnd), + .datab(\timer_pwm|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\timer_pwm|cnt[0]~16_combout ), + .cout(\timer_pwm|cnt[0]~17 )); +// synopsys translate_off +defparam \timer_pwm|cnt[0]~16 .lut_mask = 16'h33CC; +defparam \timer_pwm|cnt[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N28 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y8_N29 +dffeas \my_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N14 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|locked ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|locked~combout = (!\my_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\my_pll|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|locked~combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked .lut_mask = 16'h0FFF; +defparam \my_pll|altpll_component|auto_generated|locked .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G0 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|locked~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|locked~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N8 +cycloneive_io_ibuf \tim_arr[15]~input ( + .i(tim_arr[15]), + .ibar(gnd), + .o(\tim_arr[15]~input_o )); +// synopsys translate_off +defparam \tim_arr[15]~input .bus_hold = "false"; +defparam \tim_arr[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N12 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[15]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[15]~feeder_combout = \tim_arr[15]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[15]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[15]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N13 +dffeas \timer_pwm|r_tim_arr[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[15] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N14 +cycloneive_lcell_comb \timer_pwm|cnt[7]~30 ( +// Equation(s): +// \timer_pwm|cnt[7]~30_combout = (\timer_pwm|cnt [7] & (!\timer_pwm|cnt[6]~29 )) # (!\timer_pwm|cnt [7] & ((\timer_pwm|cnt[6]~29 ) # (GND))) +// \timer_pwm|cnt[7]~31 = CARRY((!\timer_pwm|cnt[6]~29 ) # (!\timer_pwm|cnt [7])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[6]~29 ), + .combout(\timer_pwm|cnt[7]~30_combout ), + .cout(\timer_pwm|cnt[7]~31 )); +// synopsys translate_off +defparam \timer_pwm|cnt[7]~30 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[7]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N16 +cycloneive_lcell_comb \timer_pwm|cnt[8]~32 ( +// Equation(s): +// \timer_pwm|cnt[8]~32_combout = (\timer_pwm|cnt [8] & (\timer_pwm|cnt[7]~31 $ (GND))) # (!\timer_pwm|cnt [8] & (!\timer_pwm|cnt[7]~31 & VCC)) +// \timer_pwm|cnt[8]~33 = CARRY((\timer_pwm|cnt [8] & !\timer_pwm|cnt[7]~31 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[7]~31 ), + .combout(\timer_pwm|cnt[8]~32_combout ), + .cout(\timer_pwm|cnt[8]~33 )); +// synopsys translate_off +defparam \timer_pwm|cnt[8]~32 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[8]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N17 +dffeas \timer_pwm|cnt[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[8]~32_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[8] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N18 +cycloneive_lcell_comb \timer_pwm|cnt[9]~34 ( +// Equation(s): +// \timer_pwm|cnt[9]~34_combout = (\timer_pwm|cnt [9] & (!\timer_pwm|cnt[8]~33 )) # (!\timer_pwm|cnt [9] & ((\timer_pwm|cnt[8]~33 ) # (GND))) +// \timer_pwm|cnt[9]~35 = CARRY((!\timer_pwm|cnt[8]~33 ) # (!\timer_pwm|cnt [9])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[8]~33 ), + .combout(\timer_pwm|cnt[9]~34_combout ), + .cout(\timer_pwm|cnt[9]~35 )); +// synopsys translate_off +defparam \timer_pwm|cnt[9]~34 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[9]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N19 +dffeas \timer_pwm|cnt[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[9]~34_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[9] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N20 +cycloneive_lcell_comb \timer_pwm|cnt[10]~36 ( +// Equation(s): +// \timer_pwm|cnt[10]~36_combout = (\timer_pwm|cnt [10] & (\timer_pwm|cnt[9]~35 $ (GND))) # (!\timer_pwm|cnt [10] & (!\timer_pwm|cnt[9]~35 & VCC)) +// \timer_pwm|cnt[10]~37 = CARRY((\timer_pwm|cnt [10] & !\timer_pwm|cnt[9]~35 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[9]~35 ), + .combout(\timer_pwm|cnt[10]~36_combout ), + .cout(\timer_pwm|cnt[10]~37 )); +// synopsys translate_off +defparam \timer_pwm|cnt[10]~36 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[10]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N21 +dffeas \timer_pwm|cnt[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[10]~36_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[10] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N22 +cycloneive_lcell_comb \timer_pwm|cnt[11]~38 ( +// Equation(s): +// \timer_pwm|cnt[11]~38_combout = (\timer_pwm|cnt [11] & (!\timer_pwm|cnt[10]~37 )) # (!\timer_pwm|cnt [11] & ((\timer_pwm|cnt[10]~37 ) # (GND))) +// \timer_pwm|cnt[11]~39 = CARRY((!\timer_pwm|cnt[10]~37 ) # (!\timer_pwm|cnt [11])) + + .dataa(\timer_pwm|cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[10]~37 ), + .combout(\timer_pwm|cnt[11]~38_combout ), + .cout(\timer_pwm|cnt[11]~39 )); +// synopsys translate_off +defparam \timer_pwm|cnt[11]~38 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[11]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N23 +dffeas \timer_pwm|cnt[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[11]~38_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[11] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N24 +cycloneive_lcell_comb \timer_pwm|cnt[12]~40 ( +// Equation(s): +// \timer_pwm|cnt[12]~40_combout = (\timer_pwm|cnt [12] & (\timer_pwm|cnt[11]~39 $ (GND))) # (!\timer_pwm|cnt [12] & (!\timer_pwm|cnt[11]~39 & VCC)) +// \timer_pwm|cnt[12]~41 = CARRY((\timer_pwm|cnt [12] & !\timer_pwm|cnt[11]~39 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [12]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[11]~39 ), + .combout(\timer_pwm|cnt[12]~40_combout ), + .cout(\timer_pwm|cnt[12]~41 )); +// synopsys translate_off +defparam \timer_pwm|cnt[12]~40 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[12]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N25 +dffeas \timer_pwm|cnt[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[12]~40_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[12] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N26 +cycloneive_lcell_comb \timer_pwm|cnt[13]~42 ( +// Equation(s): +// \timer_pwm|cnt[13]~42_combout = (\timer_pwm|cnt [13] & (!\timer_pwm|cnt[12]~41 )) # (!\timer_pwm|cnt [13] & ((\timer_pwm|cnt[12]~41 ) # (GND))) +// \timer_pwm|cnt[13]~43 = CARRY((!\timer_pwm|cnt[12]~41 ) # (!\timer_pwm|cnt [13])) + + .dataa(\timer_pwm|cnt [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[12]~41 ), + .combout(\timer_pwm|cnt[13]~42_combout ), + .cout(\timer_pwm|cnt[13]~43 )); +// synopsys translate_off +defparam \timer_pwm|cnt[13]~42 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[13]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N27 +dffeas \timer_pwm|cnt[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[13]~42_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[13] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N28 +cycloneive_lcell_comb \timer_pwm|cnt[14]~44 ( +// Equation(s): +// \timer_pwm|cnt[14]~44_combout = (\timer_pwm|cnt [14] & (\timer_pwm|cnt[13]~43 $ (GND))) # (!\timer_pwm|cnt [14] & (!\timer_pwm|cnt[13]~43 & VCC)) +// \timer_pwm|cnt[14]~45 = CARRY((\timer_pwm|cnt [14] & !\timer_pwm|cnt[13]~43 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [14]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[13]~43 ), + .combout(\timer_pwm|cnt[14]~44_combout ), + .cout(\timer_pwm|cnt[14]~45 )); +// synopsys translate_off +defparam \timer_pwm|cnt[14]~44 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[14]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N29 +dffeas \timer_pwm|cnt[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[14]~44_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[14] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N30 +cycloneive_lcell_comb \timer_pwm|cnt[15]~46 ( +// Equation(s): +// \timer_pwm|cnt[15]~46_combout = \timer_pwm|cnt [15] $ (\timer_pwm|cnt[14]~45 ) + + .dataa(\timer_pwm|cnt [15]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\timer_pwm|cnt[14]~45 ), + .combout(\timer_pwm|cnt[15]~46_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|cnt[15]~46 .lut_mask = 16'h5A5A; +defparam \timer_pwm|cnt[15]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N31 +dffeas \timer_pwm|cnt[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[15]~46_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[15] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[15] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N15 +cycloneive_io_ibuf \tim_arr[14]~input ( + .i(tim_arr[14]), + .ibar(gnd), + .o(\tim_arr[14]~input_o )); +// synopsys translate_off +defparam \tim_arr[14]~input .bus_hold = "false"; +defparam \tim_arr[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N14 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[14]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[14]~feeder_combout = \tim_arr[14]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[14]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[14]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N15 +dffeas \timer_pwm|r_tim_arr[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[14]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[14] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[14] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N8 +cycloneive_io_ibuf \tim_arr[13]~input ( + .i(tim_arr[13]), + .ibar(gnd), + .o(\tim_arr[13]~input_o )); +// synopsys translate_off +defparam \tim_arr[13]~input .bus_hold = "false"; +defparam \tim_arr[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N15 +dffeas \timer_pwm|r_tim_arr[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[13]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[13] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[13] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N22 +cycloneive_io_ibuf \tim_arr[12]~input ( + .i(tim_arr[12]), + .ibar(gnd), + .o(\tim_arr[12]~input_o )); +// synopsys translate_off +defparam \tim_arr[12]~input .bus_hold = "false"; +defparam \tim_arr[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X23_Y21_N9 +dffeas \timer_pwm|r_tim_arr[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[12]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[12] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[12] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N22 +cycloneive_io_ibuf \tim_arr[11]~input ( + .i(tim_arr[11]), + .ibar(gnd), + .o(\tim_arr[11]~input_o )); +// synopsys translate_off +defparam \tim_arr[11]~input .bus_hold = "false"; +defparam \tim_arr[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N2 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[11]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[11]~feeder_combout = \tim_arr[11]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[11]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[11]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N3 +dffeas \timer_pwm|r_tim_arr[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[11]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[11] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[11] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \tim_arr[10]~input ( + .i(tim_arr[10]), + .ibar(gnd), + .o(\tim_arr[10]~input_o )); +// synopsys translate_off +defparam \tim_arr[10]~input .bus_hold = "false"; +defparam \tim_arr[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N20 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[10]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[10]~feeder_combout = \tim_arr[10]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[10]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[10]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N21 +dffeas \timer_pwm|r_tim_arr[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[10] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N8 +cycloneive_io_ibuf \tim_arr[9]~input ( + .i(tim_arr[9]), + .ibar(gnd), + .o(\tim_arr[9]~input_o )); +// synopsys translate_off +defparam \tim_arr[9]~input .bus_hold = "false"; +defparam \tim_arr[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N31 +dffeas \timer_pwm|r_tim_arr[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[9]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[9] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[9] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N22 +cycloneive_io_ibuf \tim_arr[8]~input ( + .i(tim_arr[8]), + .ibar(gnd), + .o(\tim_arr[8]~input_o )); +// synopsys translate_off +defparam \tim_arr[8]~input .bus_hold = "false"; +defparam \tim_arr[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N7 +dffeas \timer_pwm|r_tim_arr[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[8]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[8] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[8] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N22 +cycloneive_io_ibuf \tim_arr[7]~input ( + .i(tim_arr[7]), + .ibar(gnd), + .o(\tim_arr[7]~input_o )); +// synopsys translate_off +defparam \tim_arr[7]~input .bus_hold = "false"; +defparam \tim_arr[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N21 +dffeas \timer_pwm|r_tim_arr[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[7]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[7] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N15 +cycloneive_io_ibuf \tim_arr[6]~input ( + .i(tim_arr[6]), + .ibar(gnd), + .o(\tim_arr[6]~input_o )); +// synopsys translate_off +defparam \tim_arr[6]~input .bus_hold = "false"; +defparam \tim_arr[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N5 +dffeas \timer_pwm|r_tim_arr[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[6]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[6] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[6] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N1 +cycloneive_io_ibuf \tim_arr[5]~input ( + .i(tim_arr[5]), + .ibar(gnd), + .o(\tim_arr[5]~input_o )); +// synopsys translate_off +defparam \tim_arr[5]~input .bus_hold = "false"; +defparam \tim_arr[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N3 +dffeas \timer_pwm|r_tim_arr[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[5]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[5] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N15 +cycloneive_io_ibuf \tim_arr[4]~input ( + .i(tim_arr[4]), + .ibar(gnd), + .o(\tim_arr[4]~input_o )); +// synopsys translate_off +defparam \tim_arr[4]~input .bus_hold = "false"; +defparam \tim_arr[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N10 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[4]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[4]~feeder_combout = \tim_arr[4]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[4]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[4]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N11 +dffeas \timer_pwm|r_tim_arr[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[4] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[4] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N8 +cycloneive_io_ibuf \tim_arr[3]~input ( + .i(tim_arr[3]), + .ibar(gnd), + .o(\tim_arr[3]~input_o )); +// synopsys translate_off +defparam \tim_arr[3]~input .bus_hold = "false"; +defparam \tim_arr[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N9 +dffeas \timer_pwm|r_tim_arr[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[3]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[3] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[3] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N15 +cycloneive_io_ibuf \tim_arr[2]~input ( + .i(tim_arr[2]), + .ibar(gnd), + .o(\tim_arr[2]~input_o )); +// synopsys translate_off +defparam \tim_arr[2]~input .bus_hold = "false"; +defparam \tim_arr[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[2]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[2]~feeder_combout = \tim_arr[2]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[2]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[2]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N25 +dffeas \timer_pwm|r_tim_arr[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[2] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[2] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N8 +cycloneive_io_ibuf \tim_arr[1]~input ( + .i(tim_arr[1]), + .ibar(gnd), + .o(\tim_arr[1]~input_o )); +// synopsys translate_off +defparam \tim_arr[1]~input .bus_hold = "false"; +defparam \tim_arr[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N23 +dffeas \timer_pwm|r_tim_arr[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[1]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[1] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N1 +cycloneive_io_ibuf \tim_arr[0]~input ( + .i(tim_arr[0]), + .ibar(gnd), + .o(\tim_arr[0]~input_o )); +// synopsys translate_off +defparam \tim_arr[0]~input .bus_hold = "false"; +defparam \tim_arr[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N29 +dffeas \timer_pwm|r_tim_arr[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[0]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[0] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N0 +cycloneive_lcell_comb \timer_pwm|LessThan0~1 ( +// Equation(s): +// \timer_pwm|LessThan0~1_cout = CARRY((\timer_pwm|r_tim_arr [0] & !\timer_pwm|cnt [0])) + + .dataa(\timer_pwm|r_tim_arr [0]), + .datab(\timer_pwm|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\timer_pwm|LessThan0~1_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~1 .lut_mask = 16'h0022; +defparam \timer_pwm|LessThan0~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N2 +cycloneive_lcell_comb \timer_pwm|LessThan0~3 ( +// Equation(s): +// \timer_pwm|LessThan0~3_cout = CARRY((\timer_pwm|cnt [1] & ((!\timer_pwm|LessThan0~1_cout ) # (!\timer_pwm|r_tim_arr [1]))) # (!\timer_pwm|cnt [1] & (!\timer_pwm|r_tim_arr [1] & !\timer_pwm|LessThan0~1_cout ))) + + .dataa(\timer_pwm|cnt [1]), + .datab(\timer_pwm|r_tim_arr [1]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~1_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~3_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~3 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N4 +cycloneive_lcell_comb \timer_pwm|LessThan0~5 ( +// Equation(s): +// \timer_pwm|LessThan0~5_cout = CARRY((\timer_pwm|cnt [2] & (\timer_pwm|r_tim_arr [2] & !\timer_pwm|LessThan0~3_cout )) # (!\timer_pwm|cnt [2] & ((\timer_pwm|r_tim_arr [2]) # (!\timer_pwm|LessThan0~3_cout )))) + + .dataa(\timer_pwm|cnt [2]), + .datab(\timer_pwm|r_tim_arr [2]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~3_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~5_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~5 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N6 +cycloneive_lcell_comb \timer_pwm|LessThan0~7 ( +// Equation(s): +// \timer_pwm|LessThan0~7_cout = CARRY((\timer_pwm|cnt [3] & ((!\timer_pwm|LessThan0~5_cout ) # (!\timer_pwm|r_tim_arr [3]))) # (!\timer_pwm|cnt [3] & (!\timer_pwm|r_tim_arr [3] & !\timer_pwm|LessThan0~5_cout ))) + + .dataa(\timer_pwm|cnt [3]), + .datab(\timer_pwm|r_tim_arr [3]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~5_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~7_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~7 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N8 +cycloneive_lcell_comb \timer_pwm|LessThan0~9 ( +// Equation(s): +// \timer_pwm|LessThan0~9_cout = CARRY((\timer_pwm|r_tim_arr [4] & ((!\timer_pwm|LessThan0~7_cout ) # (!\timer_pwm|cnt [4]))) # (!\timer_pwm|r_tim_arr [4] & (!\timer_pwm|cnt [4] & !\timer_pwm|LessThan0~7_cout ))) + + .dataa(\timer_pwm|r_tim_arr [4]), + .datab(\timer_pwm|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~7_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~9_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~9 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N10 +cycloneive_lcell_comb \timer_pwm|LessThan0~11 ( +// Equation(s): +// \timer_pwm|LessThan0~11_cout = CARRY((\timer_pwm|cnt [5] & ((!\timer_pwm|LessThan0~9_cout ) # (!\timer_pwm|r_tim_arr [5]))) # (!\timer_pwm|cnt [5] & (!\timer_pwm|r_tim_arr [5] & !\timer_pwm|LessThan0~9_cout ))) + + .dataa(\timer_pwm|cnt [5]), + .datab(\timer_pwm|r_tim_arr [5]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~9_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~11_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~11 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \timer_pwm|LessThan0~13 ( +// Equation(s): +// \timer_pwm|LessThan0~13_cout = CARRY((\timer_pwm|cnt [6] & (\timer_pwm|r_tim_arr [6] & !\timer_pwm|LessThan0~11_cout )) # (!\timer_pwm|cnt [6] & ((\timer_pwm|r_tim_arr [6]) # (!\timer_pwm|LessThan0~11_cout )))) + + .dataa(\timer_pwm|cnt [6]), + .datab(\timer_pwm|r_tim_arr [6]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~11_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~13_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~13 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N14 +cycloneive_lcell_comb \timer_pwm|LessThan0~15 ( +// Equation(s): +// \timer_pwm|LessThan0~15_cout = CARRY((\timer_pwm|r_tim_arr [7] & (\timer_pwm|cnt [7] & !\timer_pwm|LessThan0~13_cout )) # (!\timer_pwm|r_tim_arr [7] & ((\timer_pwm|cnt [7]) # (!\timer_pwm|LessThan0~13_cout )))) + + .dataa(\timer_pwm|r_tim_arr [7]), + .datab(\timer_pwm|cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~13_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~15_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~15 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N16 +cycloneive_lcell_comb \timer_pwm|LessThan0~17 ( +// Equation(s): +// \timer_pwm|LessThan0~17_cout = CARRY((\timer_pwm|r_tim_arr [8] & ((!\timer_pwm|LessThan0~15_cout ) # (!\timer_pwm|cnt [8]))) # (!\timer_pwm|r_tim_arr [8] & (!\timer_pwm|cnt [8] & !\timer_pwm|LessThan0~15_cout ))) + + .dataa(\timer_pwm|r_tim_arr [8]), + .datab(\timer_pwm|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~15_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~17_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~17 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N18 +cycloneive_lcell_comb \timer_pwm|LessThan0~19 ( +// Equation(s): +// \timer_pwm|LessThan0~19_cout = CARRY((\timer_pwm|r_tim_arr [9] & (\timer_pwm|cnt [9] & !\timer_pwm|LessThan0~17_cout )) # (!\timer_pwm|r_tim_arr [9] & ((\timer_pwm|cnt [9]) # (!\timer_pwm|LessThan0~17_cout )))) + + .dataa(\timer_pwm|r_tim_arr [9]), + .datab(\timer_pwm|cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~17_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~19_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~19 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N20 +cycloneive_lcell_comb \timer_pwm|LessThan0~21 ( +// Equation(s): +// \timer_pwm|LessThan0~21_cout = CARRY((\timer_pwm|cnt [10] & (\timer_pwm|r_tim_arr [10] & !\timer_pwm|LessThan0~19_cout )) # (!\timer_pwm|cnt [10] & ((\timer_pwm|r_tim_arr [10]) # (!\timer_pwm|LessThan0~19_cout )))) + + .dataa(\timer_pwm|cnt [10]), + .datab(\timer_pwm|r_tim_arr [10]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~19_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~21_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~21 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N22 +cycloneive_lcell_comb \timer_pwm|LessThan0~23 ( +// Equation(s): +// \timer_pwm|LessThan0~23_cout = CARRY((\timer_pwm|r_tim_arr [11] & (\timer_pwm|cnt [11] & !\timer_pwm|LessThan0~21_cout )) # (!\timer_pwm|r_tim_arr [11] & ((\timer_pwm|cnt [11]) # (!\timer_pwm|LessThan0~21_cout )))) + + .dataa(\timer_pwm|r_tim_arr [11]), + .datab(\timer_pwm|cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~21_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~23_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~23 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N24 +cycloneive_lcell_comb \timer_pwm|LessThan0~25 ( +// Equation(s): +// \timer_pwm|LessThan0~25_cout = CARRY((\timer_pwm|r_tim_arr [12] & ((!\timer_pwm|LessThan0~23_cout ) # (!\timer_pwm|cnt [12]))) # (!\timer_pwm|r_tim_arr [12] & (!\timer_pwm|cnt [12] & !\timer_pwm|LessThan0~23_cout ))) + + .dataa(\timer_pwm|r_tim_arr [12]), + .datab(\timer_pwm|cnt [12]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~23_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~25_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~25 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N26 +cycloneive_lcell_comb \timer_pwm|LessThan0~27 ( +// Equation(s): +// \timer_pwm|LessThan0~27_cout = CARRY((\timer_pwm|r_tim_arr [13] & (\timer_pwm|cnt [13] & !\timer_pwm|LessThan0~25_cout )) # (!\timer_pwm|r_tim_arr [13] & ((\timer_pwm|cnt [13]) # (!\timer_pwm|LessThan0~25_cout )))) + + .dataa(\timer_pwm|r_tim_arr [13]), + .datab(\timer_pwm|cnt [13]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~25_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~27_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~27 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N28 +cycloneive_lcell_comb \timer_pwm|LessThan0~29 ( +// Equation(s): +// \timer_pwm|LessThan0~29_cout = CARRY((\timer_pwm|r_tim_arr [14] & ((!\timer_pwm|LessThan0~27_cout ) # (!\timer_pwm|cnt [14]))) # (!\timer_pwm|r_tim_arr [14] & (!\timer_pwm|cnt [14] & !\timer_pwm|LessThan0~27_cout ))) + + .dataa(\timer_pwm|r_tim_arr [14]), + .datab(\timer_pwm|cnt [14]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~27_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~29_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~29 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N30 +cycloneive_lcell_comb \timer_pwm|LessThan0~30 ( +// Equation(s): +// \timer_pwm|LessThan0~30_combout = (\timer_pwm|r_tim_arr [15] & ((\timer_pwm|LessThan0~29_cout ) # (!\timer_pwm|cnt [15]))) # (!\timer_pwm|r_tim_arr [15] & (\timer_pwm|LessThan0~29_cout & !\timer_pwm|cnt [15])) + + .dataa(gnd), + .datab(\timer_pwm|r_tim_arr [15]), + .datac(gnd), + .datad(\timer_pwm|cnt [15]), + .cin(\timer_pwm|LessThan0~29_cout ), + .combout(\timer_pwm|LessThan0~30_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|LessThan0~30 .lut_mask = 16'hC0FC; +defparam \timer_pwm|LessThan0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N1 +dffeas \timer_pwm|cnt[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[0]~16_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[0] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N2 +cycloneive_lcell_comb \timer_pwm|cnt[1]~18 ( +// Equation(s): +// \timer_pwm|cnt[1]~18_combout = (\timer_pwm|cnt [1] & (!\timer_pwm|cnt[0]~17 )) # (!\timer_pwm|cnt [1] & ((\timer_pwm|cnt[0]~17 ) # (GND))) +// \timer_pwm|cnt[1]~19 = CARRY((!\timer_pwm|cnt[0]~17 ) # (!\timer_pwm|cnt [1])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[0]~17 ), + .combout(\timer_pwm|cnt[1]~18_combout ), + .cout(\timer_pwm|cnt[1]~19 )); +// synopsys translate_off +defparam \timer_pwm|cnt[1]~18 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N3 +dffeas \timer_pwm|cnt[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[1]~18_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[1] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N4 +cycloneive_lcell_comb \timer_pwm|cnt[2]~20 ( +// Equation(s): +// \timer_pwm|cnt[2]~20_combout = (\timer_pwm|cnt [2] & (\timer_pwm|cnt[1]~19 $ (GND))) # (!\timer_pwm|cnt [2] & (!\timer_pwm|cnt[1]~19 & VCC)) +// \timer_pwm|cnt[2]~21 = CARRY((\timer_pwm|cnt [2] & !\timer_pwm|cnt[1]~19 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[1]~19 ), + .combout(\timer_pwm|cnt[2]~20_combout ), + .cout(\timer_pwm|cnt[2]~21 )); +// synopsys translate_off +defparam \timer_pwm|cnt[2]~20 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N5 +dffeas \timer_pwm|cnt[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[2]~20_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[2] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N6 +cycloneive_lcell_comb \timer_pwm|cnt[3]~22 ( +// Equation(s): +// \timer_pwm|cnt[3]~22_combout = (\timer_pwm|cnt [3] & (!\timer_pwm|cnt[2]~21 )) # (!\timer_pwm|cnt [3] & ((\timer_pwm|cnt[2]~21 ) # (GND))) +// \timer_pwm|cnt[3]~23 = CARRY((!\timer_pwm|cnt[2]~21 ) # (!\timer_pwm|cnt [3])) + + .dataa(\timer_pwm|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[2]~21 ), + .combout(\timer_pwm|cnt[3]~22_combout ), + .cout(\timer_pwm|cnt[3]~23 )); +// synopsys translate_off +defparam \timer_pwm|cnt[3]~22 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N7 +dffeas \timer_pwm|cnt[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[3]~22_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[3] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N8 +cycloneive_lcell_comb \timer_pwm|cnt[4]~24 ( +// Equation(s): +// \timer_pwm|cnt[4]~24_combout = (\timer_pwm|cnt [4] & (\timer_pwm|cnt[3]~23 $ (GND))) # (!\timer_pwm|cnt [4] & (!\timer_pwm|cnt[3]~23 & VCC)) +// \timer_pwm|cnt[4]~25 = CARRY((\timer_pwm|cnt [4] & !\timer_pwm|cnt[3]~23 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[3]~23 ), + .combout(\timer_pwm|cnt[4]~24_combout ), + .cout(\timer_pwm|cnt[4]~25 )); +// synopsys translate_off +defparam \timer_pwm|cnt[4]~24 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N9 +dffeas \timer_pwm|cnt[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[4]~24_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[4] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N10 +cycloneive_lcell_comb \timer_pwm|cnt[5]~26 ( +// Equation(s): +// \timer_pwm|cnt[5]~26_combout = (\timer_pwm|cnt [5] & (!\timer_pwm|cnt[4]~25 )) # (!\timer_pwm|cnt [5] & ((\timer_pwm|cnt[4]~25 ) # (GND))) +// \timer_pwm|cnt[5]~27 = CARRY((!\timer_pwm|cnt[4]~25 ) # (!\timer_pwm|cnt [5])) + + .dataa(\timer_pwm|cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[4]~25 ), + .combout(\timer_pwm|cnt[5]~26_combout ), + .cout(\timer_pwm|cnt[5]~27 )); +// synopsys translate_off +defparam \timer_pwm|cnt[5]~26 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[5]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N11 +dffeas \timer_pwm|cnt[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[5]~26_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[5] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N12 +cycloneive_lcell_comb \timer_pwm|cnt[6]~28 ( +// Equation(s): +// \timer_pwm|cnt[6]~28_combout = (\timer_pwm|cnt [6] & (\timer_pwm|cnt[5]~27 $ (GND))) # (!\timer_pwm|cnt [6] & (!\timer_pwm|cnt[5]~27 & VCC)) +// \timer_pwm|cnt[6]~29 = CARRY((\timer_pwm|cnt [6] & !\timer_pwm|cnt[5]~27 )) + + .dataa(\timer_pwm|cnt [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[5]~27 ), + .combout(\timer_pwm|cnt[6]~28_combout ), + .cout(\timer_pwm|cnt[6]~29 )); +// synopsys translate_off +defparam \timer_pwm|cnt[6]~28 .lut_mask = 16'hA50A; +defparam \timer_pwm|cnt[6]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N13 +dffeas \timer_pwm|cnt[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[6]~28_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[6] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y21_N15 +dffeas \timer_pwm|cnt[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[7]~30_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[7] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \timer_pwm|Equal0~1 ( +// Equation(s): +// \timer_pwm|Equal0~1_combout = (!\timer_pwm|cnt [7] & (!\timer_pwm|cnt [6] & (!\timer_pwm|cnt [4] & !\timer_pwm|cnt [5]))) + + .dataa(\timer_pwm|cnt [7]), + .datab(\timer_pwm|cnt [6]), + .datac(\timer_pwm|cnt [4]), + .datad(\timer_pwm|cnt [5]), + .cin(gnd), + .combout(\timer_pwm|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~1 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N4 +cycloneive_lcell_comb \timer_pwm|Equal0~2 ( +// Equation(s): +// \timer_pwm|Equal0~2_combout = (!\timer_pwm|cnt [8] & (!\timer_pwm|cnt [11] & (!\timer_pwm|cnt [9] & !\timer_pwm|cnt [10]))) + + .dataa(\timer_pwm|cnt [8]), + .datab(\timer_pwm|cnt [11]), + .datac(\timer_pwm|cnt [9]), + .datad(\timer_pwm|cnt [10]), + .cin(gnd), + .combout(\timer_pwm|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~2 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \timer_pwm|Equal0~0 ( +// Equation(s): +// \timer_pwm|Equal0~0_combout = (!\timer_pwm|cnt [0] & (!\timer_pwm|cnt [3] & (!\timer_pwm|cnt [2] & !\timer_pwm|cnt [1]))) + + .dataa(\timer_pwm|cnt [0]), + .datab(\timer_pwm|cnt [3]), + .datac(\timer_pwm|cnt [2]), + .datad(\timer_pwm|cnt [1]), + .cin(gnd), + .combout(\timer_pwm|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~0 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \timer_pwm|Equal0~3 ( +// Equation(s): +// \timer_pwm|Equal0~3_combout = (!\timer_pwm|cnt [13] & (!\timer_pwm|cnt [15] & (!\timer_pwm|cnt [14] & !\timer_pwm|cnt [12]))) + + .dataa(\timer_pwm|cnt [13]), + .datab(\timer_pwm|cnt [15]), + .datac(\timer_pwm|cnt [14]), + .datad(\timer_pwm|cnt [12]), + .cin(gnd), + .combout(\timer_pwm|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~3 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \timer_pwm|Equal0~4 ( +// Equation(s): +// \timer_pwm|Equal0~4_combout = (\timer_pwm|Equal0~1_combout & (\timer_pwm|Equal0~2_combout & (\timer_pwm|Equal0~0_combout & \timer_pwm|Equal0~3_combout ))) + + .dataa(\timer_pwm|Equal0~1_combout ), + .datab(\timer_pwm|Equal0~2_combout ), + .datac(\timer_pwm|Equal0~0_combout ), + .datad(\timer_pwm|Equal0~3_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~4 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \timer_pwm|tim_ch[0]~1 ( +// Equation(s): +// \timer_pwm|tim_ch[0]~1_combout = !\timer_pwm|Equal0~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(\timer_pwm|Equal0~4_combout ), + .datad(gnd), + .cin(gnd), + .combout(\timer_pwm|tim_ch[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0]~1 .lut_mask = 16'h0F0F; +defparam \timer_pwm|tim_ch[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N15 +cycloneive_io_ibuf \tim_ccr1[7]~input ( + .i(tim_ccr1[7]), + .ibar(gnd), + .o(\tim_ccr1[7]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[7]~input .bus_hold = "false"; +defparam \tim_ccr1[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[7]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[7]~feeder_combout = \tim_ccr1[7]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[7]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[7]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N13 +dffeas \timer_pwm|r_tim_ccr1[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[7] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[6]~input ( + .i(tim_ccr1[6]), + .ibar(gnd), + .o(\tim_ccr1[6]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[6]~input .bus_hold = "false"; +defparam \tim_ccr1[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N27 +dffeas \timer_pwm|r_tim_ccr1[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[6]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[6] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \timer_pwm|Equal1~3 ( +// Equation(s): +// \timer_pwm|Equal1~3_combout = (\timer_pwm|r_tim_ccr1 [7] & (\timer_pwm|cnt [7] & (\timer_pwm|cnt [6] $ (!\timer_pwm|r_tim_ccr1 [6])))) # (!\timer_pwm|r_tim_ccr1 [7] & (!\timer_pwm|cnt [7] & (\timer_pwm|cnt [6] $ (!\timer_pwm|r_tim_ccr1 [6])))) + + .dataa(\timer_pwm|r_tim_ccr1 [7]), + .datab(\timer_pwm|cnt [6]), + .datac(\timer_pwm|r_tim_ccr1 [6]), + .datad(\timer_pwm|cnt [7]), + .cin(gnd), + .combout(\timer_pwm|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~3 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[5]~input ( + .i(tim_ccr1[5]), + .ibar(gnd), + .o(\tim_ccr1[5]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[5]~input .bus_hold = "false"; +defparam \tim_ccr1[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[5]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[5]~feeder_combout = \tim_ccr1[5]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[5]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[5]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N21 +dffeas \timer_pwm|r_tim_ccr1[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[5] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[4]~input ( + .i(tim_ccr1[4]), + .ibar(gnd), + .o(\tim_ccr1[4]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[4]~input .bus_hold = "false"; +defparam \tim_ccr1[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \timer_pwm|r_tim_ccr1[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[4]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[4] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \timer_pwm|Equal1~2 ( +// Equation(s): +// \timer_pwm|Equal1~2_combout = (\timer_pwm|cnt [4] & (\timer_pwm|r_tim_ccr1 [4] & (\timer_pwm|r_tim_ccr1 [5] $ (!\timer_pwm|cnt [5])))) # (!\timer_pwm|cnt [4] & (!\timer_pwm|r_tim_ccr1 [4] & (\timer_pwm|r_tim_ccr1 [5] $ (!\timer_pwm|cnt [5])))) + + .dataa(\timer_pwm|cnt [4]), + .datab(\timer_pwm|r_tim_ccr1 [5]), + .datac(\timer_pwm|r_tim_ccr1 [4]), + .datad(\timer_pwm|cnt [5]), + .cin(gnd), + .combout(\timer_pwm|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~2 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N8 +cycloneive_io_ibuf \tim_ccr1[2]~input ( + .i(tim_ccr1[2]), + .ibar(gnd), + .o(\tim_ccr1[2]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[2]~input .bus_hold = "false"; +defparam \tim_ccr1[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \timer_pwm|r_tim_ccr1[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[2]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[2] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[2] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N15 +cycloneive_io_ibuf \tim_ccr1[3]~input ( + .i(tim_ccr1[3]), + .ibar(gnd), + .o(\tim_ccr1[3]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[3]~input .bus_hold = "false"; +defparam \tim_ccr1[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[3]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[3]~feeder_combout = \tim_ccr1[3]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[3]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[3]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \timer_pwm|r_tim_ccr1[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[3] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \timer_pwm|Equal1~1 ( +// Equation(s): +// \timer_pwm|Equal1~1_combout = (\timer_pwm|cnt [3] & (\timer_pwm|r_tim_ccr1 [3] & (\timer_pwm|cnt [2] $ (!\timer_pwm|r_tim_ccr1 [2])))) # (!\timer_pwm|cnt [3] & (!\timer_pwm|r_tim_ccr1 [3] & (\timer_pwm|cnt [2] $ (!\timer_pwm|r_tim_ccr1 [2])))) + + .dataa(\timer_pwm|cnt [3]), + .datab(\timer_pwm|cnt [2]), + .datac(\timer_pwm|r_tim_ccr1 [2]), + .datad(\timer_pwm|r_tim_ccr1 [3]), + .cin(gnd), + .combout(\timer_pwm|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~1 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N1 +cycloneive_io_ibuf \tim_ccr1[1]~input ( + .i(tim_ccr1[1]), + .ibar(gnd), + .o(\tim_ccr1[1]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[1]~input .bus_hold = "false"; +defparam \tim_ccr1[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N17 +dffeas \timer_pwm|r_tim_ccr1[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[1]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[1] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[0]~input ( + .i(tim_ccr1[0]), + .ibar(gnd), + .o(\tim_ccr1[0]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[0]~input .bus_hold = "false"; +defparam \tim_ccr1[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N7 +dffeas \timer_pwm|r_tim_ccr1[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[0]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[0] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N6 +cycloneive_lcell_comb \timer_pwm|Equal1~0 ( +// Equation(s): +// \timer_pwm|Equal1~0_combout = (\timer_pwm|cnt [0] & (\timer_pwm|r_tim_ccr1 [0] & (\timer_pwm|r_tim_ccr1 [1] $ (!\timer_pwm|cnt [1])))) # (!\timer_pwm|cnt [0] & (!\timer_pwm|r_tim_ccr1 [0] & (\timer_pwm|r_tim_ccr1 [1] $ (!\timer_pwm|cnt [1])))) + + .dataa(\timer_pwm|cnt [0]), + .datab(\timer_pwm|r_tim_ccr1 [1]), + .datac(\timer_pwm|r_tim_ccr1 [0]), + .datad(\timer_pwm|cnt [1]), + .cin(gnd), + .combout(\timer_pwm|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~0 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \timer_pwm|Equal1~4 ( +// Equation(s): +// \timer_pwm|Equal1~4_combout = (\timer_pwm|Equal1~3_combout & (\timer_pwm|Equal1~2_combout & (\timer_pwm|Equal1~1_combout & \timer_pwm|Equal1~0_combout ))) + + .dataa(\timer_pwm|Equal1~3_combout ), + .datab(\timer_pwm|Equal1~2_combout ), + .datac(\timer_pwm|Equal1~1_combout ), + .datad(\timer_pwm|Equal1~0_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~4 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[15]~input ( + .i(tim_ccr1[15]), + .ibar(gnd), + .o(\tim_ccr1[15]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[15]~input .bus_hold = "false"; +defparam \tim_ccr1[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N28 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[15]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[15]~feeder_combout = \tim_ccr1[15]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[15]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[15]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N29 +dffeas \timer_pwm|r_tim_ccr1[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[15] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[15] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[14]~input ( + .i(tim_ccr1[14]), + .ibar(gnd), + .o(\tim_ccr1[14]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[14]~input .bus_hold = "false"; +defparam \tim_ccr1[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N23 +dffeas \timer_pwm|r_tim_ccr1[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[14]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[14] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \timer_pwm|Equal1~8 ( +// Equation(s): +// \timer_pwm|Equal1~8_combout = (\timer_pwm|r_tim_ccr1 [15] & (\timer_pwm|cnt [15] & (\timer_pwm|r_tim_ccr1 [14] $ (!\timer_pwm|cnt [14])))) # (!\timer_pwm|r_tim_ccr1 [15] & (!\timer_pwm|cnt [15] & (\timer_pwm|r_tim_ccr1 [14] $ (!\timer_pwm|cnt [14])))) + + .dataa(\timer_pwm|r_tim_ccr1 [15]), + .datab(\timer_pwm|cnt [15]), + .datac(\timer_pwm|r_tim_ccr1 [14]), + .datad(\timer_pwm|cnt [14]), + .cin(gnd), + .combout(\timer_pwm|Equal1~8_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~8 .lut_mask = 16'h9009; +defparam \timer_pwm|Equal1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[8]~input ( + .i(tim_ccr1[8]), + .ibar(gnd), + .o(\tim_ccr1[8]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[8]~input .bus_hold = "false"; +defparam \tim_ccr1[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N19 +dffeas \timer_pwm|r_tim_ccr1[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[8]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[8] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[8] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[9]~input ( + .i(tim_ccr1[9]), + .ibar(gnd), + .o(\tim_ccr1[9]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[9]~input .bus_hold = "false"; +defparam \tim_ccr1[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[9]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[9]~feeder_combout = \tim_ccr1[9]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[9]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[9]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N25 +dffeas \timer_pwm|r_tim_ccr1[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[9] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N18 +cycloneive_lcell_comb \timer_pwm|Equal1~5 ( +// Equation(s): +// \timer_pwm|Equal1~5_combout = (\timer_pwm|cnt [8] & (\timer_pwm|r_tim_ccr1 [8] & (\timer_pwm|cnt [9] $ (!\timer_pwm|r_tim_ccr1 [9])))) # (!\timer_pwm|cnt [8] & (!\timer_pwm|r_tim_ccr1 [8] & (\timer_pwm|cnt [9] $ (!\timer_pwm|r_tim_ccr1 [9])))) + + .dataa(\timer_pwm|cnt [8]), + .datab(\timer_pwm|cnt [9]), + .datac(\timer_pwm|r_tim_ccr1 [8]), + .datad(\timer_pwm|r_tim_ccr1 [9]), + .cin(gnd), + .combout(\timer_pwm|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~5 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[11]~input ( + .i(tim_ccr1[11]), + .ibar(gnd), + .o(\tim_ccr1[11]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[11]~input .bus_hold = "false"; +defparam \tim_ccr1[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N13 +dffeas \timer_pwm|r_tim_ccr1[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[11]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[11] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[11] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[10]~input ( + .i(tim_ccr1[10]), + .ibar(gnd), + .o(\tim_ccr1[10]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[10]~input .bus_hold = "false"; +defparam \tim_ccr1[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \timer_pwm|r_tim_ccr1[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[10]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[10] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \timer_pwm|Equal1~6 ( +// Equation(s): +// \timer_pwm|Equal1~6_combout = (\timer_pwm|r_tim_ccr1 [11] & (\timer_pwm|cnt [11] & (\timer_pwm|r_tim_ccr1 [10] $ (!\timer_pwm|cnt [10])))) # (!\timer_pwm|r_tim_ccr1 [11] & (!\timer_pwm|cnt [11] & (\timer_pwm|r_tim_ccr1 [10] $ (!\timer_pwm|cnt [10])))) + + .dataa(\timer_pwm|r_tim_ccr1 [11]), + .datab(\timer_pwm|cnt [11]), + .datac(\timer_pwm|r_tim_ccr1 [10]), + .datad(\timer_pwm|cnt [10]), + .cin(gnd), + .combout(\timer_pwm|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~6 .lut_mask = 16'h9009; +defparam \timer_pwm|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N15 +cycloneive_io_ibuf \tim_ccr1[12]~input ( + .i(tim_ccr1[12]), + .ibar(gnd), + .o(\tim_ccr1[12]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[12]~input .bus_hold = "false"; +defparam \tim_ccr1[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N11 +dffeas \timer_pwm|r_tim_ccr1[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[12]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[12] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[12] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[13]~input ( + .i(tim_ccr1[13]), + .ibar(gnd), + .o(\tim_ccr1[13]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[13]~input .bus_hold = "false"; +defparam \tim_ccr1[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[13]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[13]~feeder_combout = \tim_ccr1[13]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[13]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[13]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \timer_pwm|r_tim_ccr1[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[13]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[13] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N10 +cycloneive_lcell_comb \timer_pwm|Equal1~7 ( +// Equation(s): +// \timer_pwm|Equal1~7_combout = (\timer_pwm|cnt [13] & (\timer_pwm|r_tim_ccr1 [13] & (\timer_pwm|cnt [12] $ (!\timer_pwm|r_tim_ccr1 [12])))) # (!\timer_pwm|cnt [13] & (!\timer_pwm|r_tim_ccr1 [13] & (\timer_pwm|cnt [12] $ (!\timer_pwm|r_tim_ccr1 [12])))) + + .dataa(\timer_pwm|cnt [13]), + .datab(\timer_pwm|cnt [12]), + .datac(\timer_pwm|r_tim_ccr1 [12]), + .datad(\timer_pwm|r_tim_ccr1 [13]), + .cin(gnd), + .combout(\timer_pwm|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~7 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N20 +cycloneive_lcell_comb \timer_pwm|Equal1~9 ( +// Equation(s): +// \timer_pwm|Equal1~9_combout = (\timer_pwm|Equal1~8_combout & (\timer_pwm|Equal1~5_combout & (\timer_pwm|Equal1~6_combout & \timer_pwm|Equal1~7_combout ))) + + .dataa(\timer_pwm|Equal1~8_combout ), + .datab(\timer_pwm|Equal1~5_combout ), + .datac(\timer_pwm|Equal1~6_combout ), + .datad(\timer_pwm|Equal1~7_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal1~9_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~9 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \timer_pwm|tim_ch[0]~0 ( +// Equation(s): +// \timer_pwm|tim_ch[0]~0_combout = (\timer_pwm|Equal0~4_combout ) # ((\timer_pwm|Equal1~4_combout & \timer_pwm|Equal1~9_combout )) + + .dataa(gnd), + .datab(\timer_pwm|Equal1~4_combout ), + .datac(\timer_pwm|Equal0~4_combout ), + .datad(\timer_pwm|Equal1~9_combout ), + .cin(gnd), + .combout(\timer_pwm|tim_ch[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0]~0 .lut_mask = 16'hFCF0; +defparam \timer_pwm|tim_ch[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N29 +dffeas \timer_pwm|tim_ch[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|tim_ch[0]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\timer_pwm|tim_ch[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|tim_ch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0] .is_wysiwyg = "true"; +defparam \timer_pwm|tim_ch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \timer_pwm|tim_ch[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|Equal0~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\timer_pwm|tim_ch[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|tim_ch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|tim_ch[1] .is_wysiwyg = "true"; +defparam \timer_pwm|tim_ch[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y0_N22 +cycloneive_io_ibuf \tim_cr[0]~input ( + .i(tim_cr[0]), + .ibar(gnd), + .o(\tim_cr[0]~input_o )); +// synopsys translate_off +defparam \tim_cr[0]~input .bus_hold = "false"; +defparam \tim_cr[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y7_N22 +cycloneive_io_ibuf \tim_cr[1]~input ( + .i(tim_cr[1]), + .ibar(gnd), + .o(\tim_cr[1]~input_o )); +// synopsys translate_off +defparam \tim_cr[1]~input .bus_hold = "false"; +defparam \tim_cr[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N22 +cycloneive_io_ibuf \tim_cr[2]~input ( + .i(tim_cr[2]), + .ibar(gnd), + .o(\tim_cr[2]~input_o )); +// synopsys translate_off +defparam \tim_cr[2]~input .bus_hold = "false"; +defparam \tim_cr[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N1 +cycloneive_io_ibuf \tim_cr[3]~input ( + .i(tim_cr[3]), + .ibar(gnd), + .o(\tim_cr[3]~input_o )); +// synopsys translate_off +defparam \tim_cr[3]~input .bus_hold = "false"; +defparam \tim_cr[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y0_N15 +cycloneive_io_ibuf \tim_cr[4]~input ( + .i(tim_cr[4]), + .ibar(gnd), + .o(\tim_cr[4]~input_o )); +// synopsys translate_off +defparam \tim_cr[4]~input .bus_hold = "false"; +defparam \tim_cr[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N15 +cycloneive_io_ibuf \tim_cr[5]~input ( + .i(tim_cr[5]), + .ibar(gnd), + .o(\tim_cr[5]~input_o )); +// synopsys translate_off +defparam \tim_cr[5]~input .bus_hold = "false"; +defparam \tim_cr[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y0_N15 +cycloneive_io_ibuf \tim_cr[6]~input ( + .i(tim_cr[6]), + .ibar(gnd), + .o(\tim_cr[6]~input_o )); +// synopsys translate_off +defparam \tim_cr[6]~input .bus_hold = "false"; +defparam \tim_cr[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N8 +cycloneive_io_ibuf \tim_cr[7]~input ( + .i(tim_cr[7]), + .ibar(gnd), + .o(\tim_cr[7]~input_o )); +// synopsys translate_off +defparam \tim_cr[7]~input .bus_hold = "false"; +defparam \tim_cr[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N15 +cycloneive_io_ibuf \tim_cr[8]~input ( + .i(tim_cr[8]), + .ibar(gnd), + .o(\tim_cr[8]~input_o )); +// synopsys translate_off +defparam \tim_cr[8]~input .bus_hold = "false"; +defparam \tim_cr[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y0_N1 +cycloneive_io_ibuf \tim_cr[9]~input ( + .i(tim_cr[9]), + .ibar(gnd), + .o(\tim_cr[9]~input_o )); +// synopsys translate_off +defparam \tim_cr[9]~input .bus_hold = "false"; +defparam \tim_cr[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N1 +cycloneive_io_ibuf \tim_cr[10]~input ( + .i(tim_cr[10]), + .ibar(gnd), + .o(\tim_cr[10]~input_o )); +// synopsys translate_off +defparam \tim_cr[10]~input .bus_hold = "false"; +defparam \tim_cr[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y0_N8 +cycloneive_io_ibuf \tim_cr[11]~input ( + .i(tim_cr[11]), + .ibar(gnd), + .o(\tim_cr[11]~input_o )); +// synopsys translate_off +defparam \tim_cr[11]~input .bus_hold = "false"; +defparam \tim_cr[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N1 +cycloneive_io_ibuf \tim_cr[12]~input ( + .i(tim_cr[12]), + .ibar(gnd), + .o(\tim_cr[12]~input_o )); +// synopsys translate_off +defparam \tim_cr[12]~input .bus_hold = "false"; +defparam \tim_cr[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N22 +cycloneive_io_ibuf \tim_cr[13]~input ( + .i(tim_cr[13]), + .ibar(gnd), + .o(\tim_cr[13]~input_o )); +// synopsys translate_off +defparam \tim_cr[13]~input .bus_hold = "false"; +defparam \tim_cr[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y2_N15 +cycloneive_io_ibuf \tim_cr[14]~input ( + .i(tim_cr[14]), + .ibar(gnd), + .o(\tim_cr[14]~input_o )); +// synopsys translate_off +defparam \tim_cr[14]~input .bus_hold = "false"; +defparam \tim_cr[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N1 +cycloneive_io_ibuf \tim_cr[15]~input ( + .i(tim_cr[15]), + .ibar(gnd), + .o(\tim_cr[15]~input_o )); +// synopsys translate_off +defparam \tim_cr[15]~input .bus_hold = "false"; +defparam \tim_cr[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N15 +cycloneive_io_ibuf \tim_cr[16]~input ( + .i(tim_cr[16]), + .ibar(gnd), + .o(\tim_cr[16]~input_o )); +// synopsys translate_off +defparam \tim_cr[16]~input .bus_hold = "false"; +defparam \tim_cr[16]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N8 +cycloneive_io_ibuf \tim_cr[17]~input ( + .i(tim_cr[17]), + .ibar(gnd), + .o(\tim_cr[17]~input_o )); +// synopsys translate_off +defparam \tim_cr[17]~input .bus_hold = "false"; +defparam \tim_cr[17]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y0_N22 +cycloneive_io_ibuf \tim_cr[18]~input ( + .i(tim_cr[18]), + .ibar(gnd), + .o(\tim_cr[18]~input_o )); +// synopsys translate_off +defparam \tim_cr[18]~input .bus_hold = "false"; +defparam \tim_cr[18]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N8 +cycloneive_io_ibuf \tim_cr[19]~input ( + .i(tim_cr[19]), + .ibar(gnd), + .o(\tim_cr[19]~input_o )); +// synopsys translate_off +defparam \tim_cr[19]~input .bus_hold = "false"; +defparam \tim_cr[19]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N1 +cycloneive_io_ibuf \tim_cr[20]~input ( + .i(tim_cr[20]), + .ibar(gnd), + .o(\tim_cr[20]~input_o )); +// synopsys translate_off +defparam \tim_cr[20]~input .bus_hold = "false"; +defparam \tim_cr[20]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N1 +cycloneive_io_ibuf \tim_cr[21]~input ( + .i(tim_cr[21]), + .ibar(gnd), + .o(\tim_cr[21]~input_o )); +// synopsys translate_off +defparam \tim_cr[21]~input .bus_hold = "false"; +defparam \tim_cr[21]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y0_N15 +cycloneive_io_ibuf \tim_cr[22]~input ( + .i(tim_cr[22]), + .ibar(gnd), + .o(\tim_cr[22]~input_o )); +// synopsys translate_off +defparam \tim_cr[22]~input .bus_hold = "false"; +defparam \tim_cr[22]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N15 +cycloneive_io_ibuf \tim_cr[23]~input ( + .i(tim_cr[23]), + .ibar(gnd), + .o(\tim_cr[23]~input_o )); +// synopsys translate_off +defparam \tim_cr[23]~input .bus_hold = "false"; +defparam \tim_cr[23]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N22 +cycloneive_io_ibuf \tim_cr[24]~input ( + .i(tim_cr[24]), + .ibar(gnd), + .o(\tim_cr[24]~input_o )); +// synopsys translate_off +defparam \tim_cr[24]~input .bus_hold = "false"; +defparam \tim_cr[24]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y4_N22 +cycloneive_io_ibuf \tim_cr[25]~input ( + .i(tim_cr[25]), + .ibar(gnd), + .o(\tim_cr[25]~input_o )); +// synopsys translate_off +defparam \tim_cr[25]~input .bus_hold = "false"; +defparam \tim_cr[25]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y0_N15 +cycloneive_io_ibuf \tim_cr[26]~input ( + .i(tim_cr[26]), + .ibar(gnd), + .o(\tim_cr[26]~input_o )); +// synopsys translate_off +defparam \tim_cr[26]~input .bus_hold = "false"; +defparam \tim_cr[26]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N1 +cycloneive_io_ibuf \tim_cr[27]~input ( + .i(tim_cr[27]), + .ibar(gnd), + .o(\tim_cr[27]~input_o )); +// synopsys translate_off +defparam \tim_cr[27]~input .bus_hold = "false"; +defparam \tim_cr[27]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y6_N22 +cycloneive_io_ibuf \tim_cr[28]~input ( + .i(tim_cr[28]), + .ibar(gnd), + .o(\tim_cr[28]~input_o )); +// synopsys translate_off +defparam \tim_cr[28]~input .bus_hold = "false"; +defparam \tim_cr[28]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N8 +cycloneive_io_ibuf \tim_cr[29]~input ( + .i(tim_cr[29]), + .ibar(gnd), + .o(\tim_cr[29]~input_o )); +// synopsys translate_off +defparam \tim_cr[29]~input .bus_hold = "false"; +defparam \tim_cr[29]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y0_N22 +cycloneive_io_ibuf \tim_cr[30]~input ( + .i(tim_cr[30]), + .ibar(gnd), + .o(\tim_cr[30]~input_o )); +// synopsys translate_off +defparam \tim_cr[30]~input .bus_hold = "false"; +defparam \tim_cr[30]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N1 +cycloneive_io_ibuf \tim_cr[31]~input ( + .i(tim_cr[31]), + .ibar(gnd), + .o(\tim_cr[31]~input_o )); +// synopsys translate_off +defparam \tim_cr[31]~input .bus_hold = "false"; +defparam \tim_cr[31]~input .simulate_z_as = "z"; +// synopsys translate_on + +endmodule diff --git a/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_v_slow.sdo b/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..28a7a2b --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,2064 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "timer_pwm_top") + (DATE "11/03/2018 15:43:36") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tim_ch\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1078:1078:1078) (988:988:988)) + (IOPATH i o (3127:3127:3127) (3075:3075:3075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tim_ch\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1007:1007:1007) (931:931:931)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (1327:1327:1327) (1327:1327:1327)) + (PORT inclk[0] (2336:2336:2336) (2336:2336:2336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2340:2340:2340) (2307:2307:2307)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (382:382:382) (459:459:459)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2010:2010:2010) (2138:2138:2138)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked) + (DELAY + (ABSOLUTE + (PORT datac (1302:1302:1302) (1421:1421:1421)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1172:1172:1172) (1153:1153:1153)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3628:3628:3628) (3804:3804:3804)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[7\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[8\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[9\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (462:462:462)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[10\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[11\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[12\]\~40) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (462:462:462)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[13\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[14\]\~44) + (DELAY + (ABSOLUTE + (PORT datab (384:384:384) (461:461:461)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[15\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (473:473:473)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3556:3556:3556) (3742:3742:3742)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4068:4068:4068) (4229:4229:4229)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT asdata (3770:3770:3770) (3978:3978:3978)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3547:3547:3547) (3732:3732:3732)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1932:1932:1932) (2009:2009:2009)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4484:4484:4484) (4614:4614:4614)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4447:4447:4447) (4579:4579:4579)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4854:4854:4854) (4943:4943:4943)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (3716:3716:3716) (3946:3946:3946)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4095:4095:4095) (4265:4265:4265)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3938:3938:3938) (4087:4087:4087)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4783:4783:4783) (4887:4887:4887)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3305:3305:3305) (3533:3533:3533)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (3805:3805:3805) (4015:4015:4015)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (784:784:784) (831:831:831)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (3996:3996:3996) (4166:4166:4166)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (581:581:581)) + (PORT datab (653:653:653) (655:655:655)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (623:623:623)) + (PORT datab (538:538:538) (574:574:574)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (654:654:654)) + (PORT datab (590:590:590) (596:596:596)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (620:620:620)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (605:605:605)) + (PORT datab (637:637:637) (645:645:645)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (879:879:879)) + (PORT datab (333:333:333) (408:408:408)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (836:836:836)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (576:576:576)) + (PORT datab (637:637:637) (645:645:645)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (420:420:420)) + (PORT datab (949:949:949) (904:904:904)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (419:419:419)) + (PORT datab (657:657:657) (666:666:666)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~21) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (826:826:826)) + (PORT datab (589:589:589) (595:595:595)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~23) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (606:606:606)) + (PORT datab (650:650:650) (656:656:656)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~25) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (573:573:573)) + (PORT datab (649:649:649) (654:654:654)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~27) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (576:576:576)) + (PORT datab (868:868:868) (840:840:840)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~29) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (577:577:577)) + (PORT datab (595:595:595) (623:623:623)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~30) + (DELAY + (ABSOLUTE + (PORT datab (858:858:858) (831:831:831)) + (PORT datad (850:850:850) (828:828:828)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[5\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (968:968:968)) + (PORT datab (939:939:939) (941:941:941)) + (PORT datac (946:946:946) (928:928:928)) + (PORT datad (945:945:945) (929:929:929)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (625:625:625)) + (PORT datab (596:596:596) (623:623:623)) + (PORT datac (899:899:899) (877:877:877)) + (PORT datad (574:574:574) (593:593:593)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (951:951:951)) + (PORT datab (979:979:979) (955:955:955)) + (PORT datac (935:935:935) (927:927:927)) + (PORT datad (932:932:932) (922:922:922)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (658:658:658)) + (PORT datab (594:594:594) (620:620:620)) + (PORT datac (917:917:917) (896:896:896)) + (PORT datad (591:591:591) (607:607:607)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (315:315:315)) + (PORT datab (835:835:835) (776:776:776)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (771:771:771) (714:714:714)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|tim_ch\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (243:243:243) (273:273:273)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3678:3678:3678) (3862:3862:3862)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT asdata (4035:4035:4035) (4217:4217:4217)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (421:421:421)) + (PORT datab (940:940:940) (943:943:943)) + (PORT datad (942:942:942) (916:916:916)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3278:3278:3278) (3512:3512:3512)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT asdata (3800:3800:3800) (4020:4020:4020)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (974:974:974)) + (PORT datab (333:333:333) (409:409:409)) + (PORT datad (945:945:945) (929:929:929)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT asdata (4154:4154:4154) (4333:4333:4333)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3328:3328:3328) (3555:3555:3555)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (947:947:947)) + (PORT datab (989:989:989) (968:968:968)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT asdata (4135:4135:4135) (4303:4303:4303)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT asdata (3788:3788:3788) (4010:4010:4010)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (951:951:951)) + (PORT datab (335:335:335) (411:411:411)) + (PORT datad (932:932:932) (922:922:922)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (238:238:238) (265:265:265)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3351:3351:3351) (3567:3567:3567)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT asdata (4089:4089:4089) (4285:4285:4285)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (577:577:577)) + (PORT datab (590:590:590) (616:616:616)) + (PORT datad (589:589:589) (604:604:604)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT asdata (3777:3777:3777) (3986:3986:3986)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3333:3333:3333) (3543:3543:3543)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (625:625:625)) + (PORT datab (590:590:590) (616:616:616)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT asdata (4421:4421:4421) (4558:4558:4558)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT asdata (4135:4135:4135) (4322:4322:4322)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (421:421:421)) + (PORT datab (594:594:594) (620:620:620)) + (PORT datad (572:572:572) (592:592:592)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT asdata (3720:3720:3720) (3952:3952:3952)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3649:3649:3649) (3856:3856:3856)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (658:658:658)) + (PORT datab (650:650:650) (655:655:655)) + (PORT datad (295:295:295) (364:364:364)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|tim_ch\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (245:245:245) (276:276:276)) + (PORT datad (808:808:808) (750:750:750)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|tim_ch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|tim_ch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) +) diff --git a/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_v_slow.sdo_typ.csd b/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_v_slow.sdo_typ.csd new file mode 100644 index 0000000..433b1ba Binary files /dev/null and b/timer_pwm/simulation/modelsim/timer_pwm_8_1200mv_85c_v_slow.sdo_typ.csd differ diff --git a/timer_pwm/simulation/modelsim/timer_pwm_min_1200mv_0c_fast.vo b/timer_pwm/simulation/modelsim/timer_pwm_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..134c1ad --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_min_1200mv_0c_fast.vo @@ -0,0 +1,3276 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" + +// DATE "11/03/2018 15:43:36" + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module timer_pwm_top ( + clk, + rst_n, + tim_cr, + tim_arr, + tim_ccr1, + tim_ch); +input clk; +input rst_n; +input [31:0] tim_cr; +input [15:0] tim_arr; +input [15:0] tim_ccr1; +output [7:0] tim_ch; + +// Design Ports Information +// tim_cr[0] => Location: PIN_T12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[1] => Location: PIN_N16, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[2] => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[3] => Location: PIN_N12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[4] => Location: PIN_L8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[5] => Location: PIN_L11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[6] => Location: PIN_R13, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[7] => Location: PIN_M11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[8] => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[9] => Location: PIN_R7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[10] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[11] => Location: PIN_T15, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[12] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[13] => Location: PIN_M9, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[14] => Location: PIN_M12, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[15] => Location: PIN_B16, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[16] => Location: PIN_N9, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[17] => Location: PIN_M6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[18] => Location: PIN_T7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[19] => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[20] => Location: PIN_P6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[21] => Location: PIN_T10, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[22] => Location: PIN_K10, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[23] => Location: PIN_F6, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[24] => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[25] => Location: PIN_N14, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[26] => Location: PIN_P8, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[27] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[28] => Location: PIN_L4, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[29] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[30] => Location: PIN_P11, I/O Standard: 2.5 V, Current Strength: Default +// tim_cr[31] => Location: PIN_A9, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[0] => Location: PIN_D14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[1] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[2] => Location: PIN_N3, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[3] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[4] => Location: PIN_P9, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[5] => Location: PIN_R16, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[6] => Location: PIN_M7, I/O Standard: 2.5 V, Current Strength: Default +// tim_ch[7] => Location: PIN_T9, I/O Standard: 2.5 V, Current Strength: Default +// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[1] => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[0] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[3] => Location: PIN_E11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[2] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[5] => Location: PIN_E10, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[4] => Location: PIN_B14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[7] => Location: PIN_G11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[6] => Location: PIN_D11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[9] => Location: PIN_B12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[8] => Location: PIN_A12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[11] => Location: PIN_C14, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[10] => Location: PIN_D12, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[13] => Location: PIN_B13, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[12] => Location: PIN_A11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[15] => Location: PIN_B11, I/O Standard: 2.5 V, Current Strength: Default +// tim_ccr1[14] => Location: PIN_A13, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[15] => Location: PIN_C9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[14] => Location: PIN_D9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[13] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[12] => Location: PIN_F11, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[11] => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[10] => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[9] => Location: PIN_B9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[8] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[7] => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[6] => Location: PIN_F9, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[5] => Location: PIN_C11, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[4] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[3] => Location: PIN_D8, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[2] => Location: PIN_B10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[1] => Location: PIN_F10, I/O Standard: 2.5 V, Current Strength: Default +// tim_arr[0] => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("timer_pwm_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \tim_cr[0]~input_o ; +wire \tim_cr[1]~input_o ; +wire \tim_cr[2]~input_o ; +wire \tim_cr[3]~input_o ; +wire \tim_cr[4]~input_o ; +wire \tim_cr[5]~input_o ; +wire \tim_cr[6]~input_o ; +wire \tim_cr[7]~input_o ; +wire \tim_cr[8]~input_o ; +wire \tim_cr[9]~input_o ; +wire \tim_cr[10]~input_o ; +wire \tim_cr[11]~input_o ; +wire \tim_cr[12]~input_o ; +wire \tim_cr[13]~input_o ; +wire \tim_cr[14]~input_o ; +wire \tim_cr[15]~input_o ; +wire \tim_cr[16]~input_o ; +wire \tim_cr[17]~input_o ; +wire \tim_cr[18]~input_o ; +wire \tim_cr[19]~input_o ; +wire \tim_cr[20]~input_o ; +wire \tim_cr[21]~input_o ; +wire \tim_cr[22]~input_o ; +wire \tim_cr[23]~input_o ; +wire \tim_cr[24]~input_o ; +wire \tim_cr[25]~input_o ; +wire \tim_cr[26]~input_o ; +wire \tim_cr[27]~input_o ; +wire \tim_cr[28]~input_o ; +wire \tim_cr[29]~input_o ; +wire \tim_cr[30]~input_o ; +wire \tim_cr[31]~input_o ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DCLK~~padout ; +wire \~ALTERA_DATA0~~ibuf_o ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_nCEO~~padout ; +wire \~ALTERA_DCLK~~obuf_o ; +wire \~ALTERA_nCEO~~obuf_o ; +wire \rst_n~input_o ; +wire \rst_n~inputclkctrl_outclk ; +wire \clk~input_o ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_fbout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \timer_pwm|cnt[0]~16_combout ; +wire \my_pll|altpll_component|auto_generated|wire_pll1_locked ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \my_pll|altpll_component|auto_generated|pll_lock_sync~q ; +wire \my_pll|altpll_component|auto_generated|locked~combout ; +wire \my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ; +wire \tim_arr[15]~input_o ; +wire \timer_pwm|r_tim_arr[15]~feeder_combout ; +wire \timer_pwm|cnt[7]~31 ; +wire \timer_pwm|cnt[8]~32_combout ; +wire \timer_pwm|cnt[8]~33 ; +wire \timer_pwm|cnt[9]~34_combout ; +wire \timer_pwm|cnt[9]~35 ; +wire \timer_pwm|cnt[10]~36_combout ; +wire \timer_pwm|cnt[10]~37 ; +wire \timer_pwm|cnt[11]~38_combout ; +wire \timer_pwm|cnt[11]~39 ; +wire \timer_pwm|cnt[12]~40_combout ; +wire \timer_pwm|cnt[12]~41 ; +wire \timer_pwm|cnt[13]~42_combout ; +wire \timer_pwm|cnt[13]~43 ; +wire \timer_pwm|cnt[14]~44_combout ; +wire \timer_pwm|cnt[14]~45 ; +wire \timer_pwm|cnt[15]~46_combout ; +wire \tim_arr[14]~input_o ; +wire \timer_pwm|r_tim_arr[14]~feeder_combout ; +wire \tim_arr[13]~input_o ; +wire \tim_arr[12]~input_o ; +wire \tim_arr[11]~input_o ; +wire \timer_pwm|r_tim_arr[11]~feeder_combout ; +wire \tim_arr[10]~input_o ; +wire \timer_pwm|r_tim_arr[10]~feeder_combout ; +wire \tim_arr[9]~input_o ; +wire \tim_arr[8]~input_o ; +wire \tim_arr[7]~input_o ; +wire \tim_arr[6]~input_o ; +wire \tim_arr[5]~input_o ; +wire \tim_arr[4]~input_o ; +wire \timer_pwm|r_tim_arr[4]~feeder_combout ; +wire \tim_arr[3]~input_o ; +wire \tim_arr[2]~input_o ; +wire \timer_pwm|r_tim_arr[2]~feeder_combout ; +wire \tim_arr[1]~input_o ; +wire \tim_arr[0]~input_o ; +wire \timer_pwm|LessThan0~1_cout ; +wire \timer_pwm|LessThan0~3_cout ; +wire \timer_pwm|LessThan0~5_cout ; +wire \timer_pwm|LessThan0~7_cout ; +wire \timer_pwm|LessThan0~9_cout ; +wire \timer_pwm|LessThan0~11_cout ; +wire \timer_pwm|LessThan0~13_cout ; +wire \timer_pwm|LessThan0~15_cout ; +wire \timer_pwm|LessThan0~17_cout ; +wire \timer_pwm|LessThan0~19_cout ; +wire \timer_pwm|LessThan0~21_cout ; +wire \timer_pwm|LessThan0~23_cout ; +wire \timer_pwm|LessThan0~25_cout ; +wire \timer_pwm|LessThan0~27_cout ; +wire \timer_pwm|LessThan0~29_cout ; +wire \timer_pwm|LessThan0~30_combout ; +wire \timer_pwm|cnt[0]~17 ; +wire \timer_pwm|cnt[1]~18_combout ; +wire \timer_pwm|cnt[1]~19 ; +wire \timer_pwm|cnt[2]~20_combout ; +wire \timer_pwm|cnt[2]~21 ; +wire \timer_pwm|cnt[3]~22_combout ; +wire \timer_pwm|cnt[3]~23 ; +wire \timer_pwm|cnt[4]~24_combout ; +wire \timer_pwm|cnt[4]~25 ; +wire \timer_pwm|cnt[5]~26_combout ; +wire \timer_pwm|cnt[5]~27 ; +wire \timer_pwm|cnt[6]~28_combout ; +wire \timer_pwm|cnt[6]~29 ; +wire \timer_pwm|cnt[7]~30_combout ; +wire \timer_pwm|Equal0~1_combout ; +wire \timer_pwm|Equal0~2_combout ; +wire \timer_pwm|Equal0~0_combout ; +wire \timer_pwm|Equal0~3_combout ; +wire \timer_pwm|Equal0~4_combout ; +wire \timer_pwm|tim_ch[0]~1_combout ; +wire \tim_ccr1[7]~input_o ; +wire \timer_pwm|r_tim_ccr1[7]~feeder_combout ; +wire \tim_ccr1[6]~input_o ; +wire \timer_pwm|Equal1~3_combout ; +wire \tim_ccr1[5]~input_o ; +wire \timer_pwm|r_tim_ccr1[5]~feeder_combout ; +wire \tim_ccr1[4]~input_o ; +wire \timer_pwm|Equal1~2_combout ; +wire \tim_ccr1[2]~input_o ; +wire \tim_ccr1[3]~input_o ; +wire \timer_pwm|r_tim_ccr1[3]~feeder_combout ; +wire \timer_pwm|Equal1~1_combout ; +wire \tim_ccr1[1]~input_o ; +wire \tim_ccr1[0]~input_o ; +wire \timer_pwm|Equal1~0_combout ; +wire \timer_pwm|Equal1~4_combout ; +wire \tim_ccr1[15]~input_o ; +wire \timer_pwm|r_tim_ccr1[15]~feeder_combout ; +wire \tim_ccr1[14]~input_o ; +wire \timer_pwm|Equal1~8_combout ; +wire \tim_ccr1[8]~input_o ; +wire \tim_ccr1[9]~input_o ; +wire \timer_pwm|r_tim_ccr1[9]~feeder_combout ; +wire \timer_pwm|Equal1~5_combout ; +wire \tim_ccr1[11]~input_o ; +wire \tim_ccr1[10]~input_o ; +wire \timer_pwm|Equal1~6_combout ; +wire \tim_ccr1[12]~input_o ; +wire \tim_ccr1[13]~input_o ; +wire \timer_pwm|r_tim_ccr1[13]~feeder_combout ; +wire \timer_pwm|Equal1~7_combout ; +wire \timer_pwm|Equal1~9_combout ; +wire \timer_pwm|tim_ch[0]~0_combout ; +wire [15:0] \timer_pwm|cnt ; +wire [15:0] \timer_pwm|r_tim_arr ; +wire [4:0] \my_pll|altpll_component|auto_generated|wire_pll1_clk ; +wire [1:0] \timer_pwm|tim_ch ; +wire [15:0] \timer_pwm|r_tim_ccr1 ; + +wire [4:0] \my_pll|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: IOOBUF_X32_Y24_N16 +cycloneive_io_obuf \tim_ch[0]~output ( + .i(\timer_pwm|tim_ch [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[0]), + .obar()); +// synopsys translate_off +defparam \tim_ch[0]~output .bus_hold = "false"; +defparam \tim_ch[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y20_N2 +cycloneive_io_obuf \tim_ch[1]~output ( + .i(\timer_pwm|tim_ch [1]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[1]), + .obar()); +// synopsys translate_off +defparam \tim_ch[1]~output .bus_hold = "false"; +defparam \tim_ch[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y0_N23 +cycloneive_io_obuf \tim_ch[2]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[2]), + .obar()); +// synopsys translate_off +defparam \tim_ch[2]~output .bus_hold = "false"; +defparam \tim_ch[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y24_N23 +cycloneive_io_obuf \tim_ch[3]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[3]), + .obar()); +// synopsys translate_off +defparam \tim_ch[3]~output .bus_hold = "false"; +defparam \tim_ch[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X25_Y0_N2 +cycloneive_io_obuf \tim_ch[4]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[4]), + .obar()); +// synopsys translate_off +defparam \tim_ch[4]~output .bus_hold = "false"; +defparam \tim_ch[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X34_Y5_N16 +cycloneive_io_obuf \tim_ch[5]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[5]), + .obar()); +// synopsys translate_off +defparam \tim_ch[5]~output .bus_hold = "false"; +defparam \tim_ch[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y0_N23 +cycloneive_io_obuf \tim_ch[6]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[6]), + .obar()); +// synopsys translate_off +defparam \tim_ch[6]~output .bus_hold = "false"; +defparam \tim_ch[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X18_Y0_N16 +cycloneive_io_obuf \tim_ch[7]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tim_ch[7]), + .obar()); +// synopsys translate_off +defparam \tim_ch[7]~output .bus_hold = "false"; +defparam \tim_ch[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \rst_n~input ( + .i(rst_n), + .ibar(gnd), + .o(\rst_n~input_o )); +// synopsys translate_off +defparam \rst_n~input .bus_hold = "false"; +defparam \rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G4 +cycloneive_clkctrl \rst_n~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~inputclkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~inputclkctrl .clock_type = "global clock"; +defparam \rst_n~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N8 +cycloneive_io_ibuf \clk~input ( + .i(clk), + .ibar(gnd), + .o(\clk~input_o )); +// synopsys translate_off +defparam \clk~input .bus_hold = "false"; +defparam \clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_1 +cycloneive_pll \my_pll|altpll_component|auto_generated|pll1 ( + .areset(!\rst_n~inputclkctrl_outclk ), + .pfdena(vcc), + .fbin(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\my_pll|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \my_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_high = 2; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_low = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_mode = "odd"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \my_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 4; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \my_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \my_pll|altpll_component|auto_generated|pll1 .m = 12; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .n = 1; +defparam \my_pll|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \my_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "on"; +defparam \my_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \my_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \my_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N0 +cycloneive_lcell_comb \timer_pwm|cnt[0]~16 ( +// Equation(s): +// \timer_pwm|cnt[0]~16_combout = \timer_pwm|cnt [0] $ (VCC) +// \timer_pwm|cnt[0]~17 = CARRY(\timer_pwm|cnt [0]) + + .dataa(gnd), + .datab(\timer_pwm|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\timer_pwm|cnt[0]~16_combout ), + .cout(\timer_pwm|cnt[0]~17 )); +// synopsys translate_off +defparam \timer_pwm|cnt[0]~16 .lut_mask = 16'h33CC; +defparam \timer_pwm|cnt[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N28 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X1_Y8_N29 +dffeas \my_pll|altpll_component|auto_generated|pll_lock_sync ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .d(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\rst_n~inputclkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y8_N14 +cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|locked ( +// Equation(s): +// \my_pll|altpll_component|auto_generated|locked~combout = (!\my_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\my_pll|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(gnd), + .datab(gnd), + .datac(\my_pll|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\my_pll|altpll_component|auto_generated|locked~combout ), + .cout()); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked .lut_mask = 16'h0FFF; +defparam \my_pll|altpll_component|auto_generated|locked .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G0 +cycloneive_clkctrl \my_pll|altpll_component|auto_generated|locked~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|locked~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk )); +// synopsys translate_off +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .clock_type = "global clock"; +defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N8 +cycloneive_io_ibuf \tim_arr[15]~input ( + .i(tim_arr[15]), + .ibar(gnd), + .o(\tim_arr[15]~input_o )); +// synopsys translate_off +defparam \tim_arr[15]~input .bus_hold = "false"; +defparam \tim_arr[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N12 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[15]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[15]~feeder_combout = \tim_arr[15]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[15]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[15]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N13 +dffeas \timer_pwm|r_tim_arr[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[15] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N14 +cycloneive_lcell_comb \timer_pwm|cnt[7]~30 ( +// Equation(s): +// \timer_pwm|cnt[7]~30_combout = (\timer_pwm|cnt [7] & (!\timer_pwm|cnt[6]~29 )) # (!\timer_pwm|cnt [7] & ((\timer_pwm|cnt[6]~29 ) # (GND))) +// \timer_pwm|cnt[7]~31 = CARRY((!\timer_pwm|cnt[6]~29 ) # (!\timer_pwm|cnt [7])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[6]~29 ), + .combout(\timer_pwm|cnt[7]~30_combout ), + .cout(\timer_pwm|cnt[7]~31 )); +// synopsys translate_off +defparam \timer_pwm|cnt[7]~30 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[7]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N16 +cycloneive_lcell_comb \timer_pwm|cnt[8]~32 ( +// Equation(s): +// \timer_pwm|cnt[8]~32_combout = (\timer_pwm|cnt [8] & (\timer_pwm|cnt[7]~31 $ (GND))) # (!\timer_pwm|cnt [8] & (!\timer_pwm|cnt[7]~31 & VCC)) +// \timer_pwm|cnt[8]~33 = CARRY((\timer_pwm|cnt [8] & !\timer_pwm|cnt[7]~31 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[7]~31 ), + .combout(\timer_pwm|cnt[8]~32_combout ), + .cout(\timer_pwm|cnt[8]~33 )); +// synopsys translate_off +defparam \timer_pwm|cnt[8]~32 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[8]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N17 +dffeas \timer_pwm|cnt[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[8]~32_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[8] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N18 +cycloneive_lcell_comb \timer_pwm|cnt[9]~34 ( +// Equation(s): +// \timer_pwm|cnt[9]~34_combout = (\timer_pwm|cnt [9] & (!\timer_pwm|cnt[8]~33 )) # (!\timer_pwm|cnt [9] & ((\timer_pwm|cnt[8]~33 ) # (GND))) +// \timer_pwm|cnt[9]~35 = CARRY((!\timer_pwm|cnt[8]~33 ) # (!\timer_pwm|cnt [9])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[8]~33 ), + .combout(\timer_pwm|cnt[9]~34_combout ), + .cout(\timer_pwm|cnt[9]~35 )); +// synopsys translate_off +defparam \timer_pwm|cnt[9]~34 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[9]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N19 +dffeas \timer_pwm|cnt[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[9]~34_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[9] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N20 +cycloneive_lcell_comb \timer_pwm|cnt[10]~36 ( +// Equation(s): +// \timer_pwm|cnt[10]~36_combout = (\timer_pwm|cnt [10] & (\timer_pwm|cnt[9]~35 $ (GND))) # (!\timer_pwm|cnt [10] & (!\timer_pwm|cnt[9]~35 & VCC)) +// \timer_pwm|cnt[10]~37 = CARRY((\timer_pwm|cnt [10] & !\timer_pwm|cnt[9]~35 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[9]~35 ), + .combout(\timer_pwm|cnt[10]~36_combout ), + .cout(\timer_pwm|cnt[10]~37 )); +// synopsys translate_off +defparam \timer_pwm|cnt[10]~36 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[10]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N21 +dffeas \timer_pwm|cnt[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[10]~36_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[10] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N22 +cycloneive_lcell_comb \timer_pwm|cnt[11]~38 ( +// Equation(s): +// \timer_pwm|cnt[11]~38_combout = (\timer_pwm|cnt [11] & (!\timer_pwm|cnt[10]~37 )) # (!\timer_pwm|cnt [11] & ((\timer_pwm|cnt[10]~37 ) # (GND))) +// \timer_pwm|cnt[11]~39 = CARRY((!\timer_pwm|cnt[10]~37 ) # (!\timer_pwm|cnt [11])) + + .dataa(\timer_pwm|cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[10]~37 ), + .combout(\timer_pwm|cnt[11]~38_combout ), + .cout(\timer_pwm|cnt[11]~39 )); +// synopsys translate_off +defparam \timer_pwm|cnt[11]~38 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[11]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N23 +dffeas \timer_pwm|cnt[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[11]~38_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[11] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N24 +cycloneive_lcell_comb \timer_pwm|cnt[12]~40 ( +// Equation(s): +// \timer_pwm|cnt[12]~40_combout = (\timer_pwm|cnt [12] & (\timer_pwm|cnt[11]~39 $ (GND))) # (!\timer_pwm|cnt [12] & (!\timer_pwm|cnt[11]~39 & VCC)) +// \timer_pwm|cnt[12]~41 = CARRY((\timer_pwm|cnt [12] & !\timer_pwm|cnt[11]~39 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [12]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[11]~39 ), + .combout(\timer_pwm|cnt[12]~40_combout ), + .cout(\timer_pwm|cnt[12]~41 )); +// synopsys translate_off +defparam \timer_pwm|cnt[12]~40 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[12]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N25 +dffeas \timer_pwm|cnt[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[12]~40_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[12] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N26 +cycloneive_lcell_comb \timer_pwm|cnt[13]~42 ( +// Equation(s): +// \timer_pwm|cnt[13]~42_combout = (\timer_pwm|cnt [13] & (!\timer_pwm|cnt[12]~41 )) # (!\timer_pwm|cnt [13] & ((\timer_pwm|cnt[12]~41 ) # (GND))) +// \timer_pwm|cnt[13]~43 = CARRY((!\timer_pwm|cnt[12]~41 ) # (!\timer_pwm|cnt [13])) + + .dataa(\timer_pwm|cnt [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[12]~41 ), + .combout(\timer_pwm|cnt[13]~42_combout ), + .cout(\timer_pwm|cnt[13]~43 )); +// synopsys translate_off +defparam \timer_pwm|cnt[13]~42 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[13]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N27 +dffeas \timer_pwm|cnt[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[13]~42_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[13] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N28 +cycloneive_lcell_comb \timer_pwm|cnt[14]~44 ( +// Equation(s): +// \timer_pwm|cnt[14]~44_combout = (\timer_pwm|cnt [14] & (\timer_pwm|cnt[13]~43 $ (GND))) # (!\timer_pwm|cnt [14] & (!\timer_pwm|cnt[13]~43 & VCC)) +// \timer_pwm|cnt[14]~45 = CARRY((\timer_pwm|cnt [14] & !\timer_pwm|cnt[13]~43 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [14]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[13]~43 ), + .combout(\timer_pwm|cnt[14]~44_combout ), + .cout(\timer_pwm|cnt[14]~45 )); +// synopsys translate_off +defparam \timer_pwm|cnt[14]~44 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[14]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N29 +dffeas \timer_pwm|cnt[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[14]~44_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[14] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N30 +cycloneive_lcell_comb \timer_pwm|cnt[15]~46 ( +// Equation(s): +// \timer_pwm|cnt[15]~46_combout = \timer_pwm|cnt [15] $ (\timer_pwm|cnt[14]~45 ) + + .dataa(\timer_pwm|cnt [15]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\timer_pwm|cnt[14]~45 ), + .combout(\timer_pwm|cnt[15]~46_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|cnt[15]~46 .lut_mask = 16'h5A5A; +defparam \timer_pwm|cnt[15]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N31 +dffeas \timer_pwm|cnt[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[15]~46_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[15] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[15] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N15 +cycloneive_io_ibuf \tim_arr[14]~input ( + .i(tim_arr[14]), + .ibar(gnd), + .o(\tim_arr[14]~input_o )); +// synopsys translate_off +defparam \tim_arr[14]~input .bus_hold = "false"; +defparam \tim_arr[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N14 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[14]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[14]~feeder_combout = \tim_arr[14]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[14]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[14]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N15 +dffeas \timer_pwm|r_tim_arr[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[14]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[14] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[14] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N8 +cycloneive_io_ibuf \tim_arr[13]~input ( + .i(tim_arr[13]), + .ibar(gnd), + .o(\tim_arr[13]~input_o )); +// synopsys translate_off +defparam \tim_arr[13]~input .bus_hold = "false"; +defparam \tim_arr[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N15 +dffeas \timer_pwm|r_tim_arr[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[13]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[13] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[13] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N22 +cycloneive_io_ibuf \tim_arr[12]~input ( + .i(tim_arr[12]), + .ibar(gnd), + .o(\tim_arr[12]~input_o )); +// synopsys translate_off +defparam \tim_arr[12]~input .bus_hold = "false"; +defparam \tim_arr[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X23_Y21_N9 +dffeas \timer_pwm|r_tim_arr[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[12]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[12] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[12] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X18_Y24_N22 +cycloneive_io_ibuf \tim_arr[11]~input ( + .i(tim_arr[11]), + .ibar(gnd), + .o(\tim_arr[11]~input_o )); +// synopsys translate_off +defparam \tim_arr[11]~input .bus_hold = "false"; +defparam \tim_arr[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N2 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[11]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[11]~feeder_combout = \tim_arr[11]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[11]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[11]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[11]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[11]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N3 +dffeas \timer_pwm|r_tim_arr[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[11]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[11] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[11] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \tim_arr[10]~input ( + .i(tim_arr[10]), + .ibar(gnd), + .o(\tim_arr[10]~input_o )); +// synopsys translate_off +defparam \tim_arr[10]~input .bus_hold = "false"; +defparam \tim_arr[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N20 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[10]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[10]~feeder_combout = \tim_arr[10]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[10]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[10]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N21 +dffeas \timer_pwm|r_tim_arr[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[10] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[10] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N8 +cycloneive_io_ibuf \tim_arr[9]~input ( + .i(tim_arr[9]), + .ibar(gnd), + .o(\tim_arr[9]~input_o )); +// synopsys translate_off +defparam \tim_arr[9]~input .bus_hold = "false"; +defparam \tim_arr[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N31 +dffeas \timer_pwm|r_tim_arr[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[9]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[9] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[9] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N22 +cycloneive_io_ibuf \tim_arr[8]~input ( + .i(tim_arr[8]), + .ibar(gnd), + .o(\tim_arr[8]~input_o )); +// synopsys translate_off +defparam \tim_arr[8]~input .bus_hold = "false"; +defparam \tim_arr[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N7 +dffeas \timer_pwm|r_tim_arr[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[8]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[8] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[8] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N22 +cycloneive_io_ibuf \tim_arr[7]~input ( + .i(tim_arr[7]), + .ibar(gnd), + .o(\tim_arr[7]~input_o )); +// synopsys translate_off +defparam \tim_arr[7]~input .bus_hold = "false"; +defparam \tim_arr[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N21 +dffeas \timer_pwm|r_tim_arr[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[7]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[7] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N15 +cycloneive_io_ibuf \tim_arr[6]~input ( + .i(tim_arr[6]), + .ibar(gnd), + .o(\tim_arr[6]~input_o )); +// synopsys translate_off +defparam \tim_arr[6]~input .bus_hold = "false"; +defparam \tim_arr[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N5 +dffeas \timer_pwm|r_tim_arr[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[6]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[6] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[6] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N1 +cycloneive_io_ibuf \tim_arr[5]~input ( + .i(tim_arr[5]), + .ibar(gnd), + .o(\tim_arr[5]~input_o )); +// synopsys translate_off +defparam \tim_arr[5]~input .bus_hold = "false"; +defparam \tim_arr[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N3 +dffeas \timer_pwm|r_tim_arr[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[5]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[5] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N15 +cycloneive_io_ibuf \tim_arr[4]~input ( + .i(tim_arr[4]), + .ibar(gnd), + .o(\tim_arr[4]~input_o )); +// synopsys translate_off +defparam \tim_arr[4]~input .bus_hold = "false"; +defparam \tim_arr[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N10 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[4]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[4]~feeder_combout = \tim_arr[4]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[4]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[4]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N11 +dffeas \timer_pwm|r_tim_arr[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[4] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[4] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N8 +cycloneive_io_ibuf \tim_arr[3]~input ( + .i(tim_arr[3]), + .ibar(gnd), + .o(\tim_arr[3]~input_o )); +// synopsys translate_off +defparam \tim_arr[3]~input .bus_hold = "false"; +defparam \tim_arr[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N9 +dffeas \timer_pwm|r_tim_arr[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[3]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[3] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[3] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N15 +cycloneive_io_ibuf \tim_arr[2]~input ( + .i(tim_arr[2]), + .ibar(gnd), + .o(\tim_arr[2]~input_o )); +// synopsys translate_off +defparam \tim_arr[2]~input .bus_hold = "false"; +defparam \tim_arr[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_arr[2]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_arr[2]~feeder_combout = \tim_arr[2]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_arr[2]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_arr[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[2]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_arr[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N25 +dffeas \timer_pwm|r_tim_arr[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_arr[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[2] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[2] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X23_Y24_N8 +cycloneive_io_ibuf \tim_arr[1]~input ( + .i(tim_arr[1]), + .ibar(gnd), + .o(\tim_arr[1]~input_o )); +// synopsys translate_off +defparam \tim_arr[1]~input .bus_hold = "false"; +defparam \tim_arr[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N23 +dffeas \timer_pwm|r_tim_arr[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[1]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[1] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y24_N1 +cycloneive_io_ibuf \tim_arr[0]~input ( + .i(tim_arr[0]), + .ibar(gnd), + .o(\tim_arr[0]~input_o )); +// synopsys translate_off +defparam \tim_arr[0]~input .bus_hold = "false"; +defparam \tim_arr[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X24_Y21_N29 +dffeas \timer_pwm|r_tim_arr[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_arr[0]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_arr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_arr[0] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_arr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N0 +cycloneive_lcell_comb \timer_pwm|LessThan0~1 ( +// Equation(s): +// \timer_pwm|LessThan0~1_cout = CARRY((\timer_pwm|r_tim_arr [0] & !\timer_pwm|cnt [0])) + + .dataa(\timer_pwm|r_tim_arr [0]), + .datab(\timer_pwm|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\timer_pwm|LessThan0~1_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~1 .lut_mask = 16'h0022; +defparam \timer_pwm|LessThan0~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N2 +cycloneive_lcell_comb \timer_pwm|LessThan0~3 ( +// Equation(s): +// \timer_pwm|LessThan0~3_cout = CARRY((\timer_pwm|cnt [1] & ((!\timer_pwm|LessThan0~1_cout ) # (!\timer_pwm|r_tim_arr [1]))) # (!\timer_pwm|cnt [1] & (!\timer_pwm|r_tim_arr [1] & !\timer_pwm|LessThan0~1_cout ))) + + .dataa(\timer_pwm|cnt [1]), + .datab(\timer_pwm|r_tim_arr [1]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~1_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~3_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~3 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N4 +cycloneive_lcell_comb \timer_pwm|LessThan0~5 ( +// Equation(s): +// \timer_pwm|LessThan0~5_cout = CARRY((\timer_pwm|cnt [2] & (\timer_pwm|r_tim_arr [2] & !\timer_pwm|LessThan0~3_cout )) # (!\timer_pwm|cnt [2] & ((\timer_pwm|r_tim_arr [2]) # (!\timer_pwm|LessThan0~3_cout )))) + + .dataa(\timer_pwm|cnt [2]), + .datab(\timer_pwm|r_tim_arr [2]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~3_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~5_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~5 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N6 +cycloneive_lcell_comb \timer_pwm|LessThan0~7 ( +// Equation(s): +// \timer_pwm|LessThan0~7_cout = CARRY((\timer_pwm|cnt [3] & ((!\timer_pwm|LessThan0~5_cout ) # (!\timer_pwm|r_tim_arr [3]))) # (!\timer_pwm|cnt [3] & (!\timer_pwm|r_tim_arr [3] & !\timer_pwm|LessThan0~5_cout ))) + + .dataa(\timer_pwm|cnt [3]), + .datab(\timer_pwm|r_tim_arr [3]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~5_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~7_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~7 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N8 +cycloneive_lcell_comb \timer_pwm|LessThan0~9 ( +// Equation(s): +// \timer_pwm|LessThan0~9_cout = CARRY((\timer_pwm|r_tim_arr [4] & ((!\timer_pwm|LessThan0~7_cout ) # (!\timer_pwm|cnt [4]))) # (!\timer_pwm|r_tim_arr [4] & (!\timer_pwm|cnt [4] & !\timer_pwm|LessThan0~7_cout ))) + + .dataa(\timer_pwm|r_tim_arr [4]), + .datab(\timer_pwm|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~7_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~9_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~9 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N10 +cycloneive_lcell_comb \timer_pwm|LessThan0~11 ( +// Equation(s): +// \timer_pwm|LessThan0~11_cout = CARRY((\timer_pwm|cnt [5] & ((!\timer_pwm|LessThan0~9_cout ) # (!\timer_pwm|r_tim_arr [5]))) # (!\timer_pwm|cnt [5] & (!\timer_pwm|r_tim_arr [5] & !\timer_pwm|LessThan0~9_cout ))) + + .dataa(\timer_pwm|cnt [5]), + .datab(\timer_pwm|r_tim_arr [5]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~9_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~11_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~11 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \timer_pwm|LessThan0~13 ( +// Equation(s): +// \timer_pwm|LessThan0~13_cout = CARRY((\timer_pwm|cnt [6] & (\timer_pwm|r_tim_arr [6] & !\timer_pwm|LessThan0~11_cout )) # (!\timer_pwm|cnt [6] & ((\timer_pwm|r_tim_arr [6]) # (!\timer_pwm|LessThan0~11_cout )))) + + .dataa(\timer_pwm|cnt [6]), + .datab(\timer_pwm|r_tim_arr [6]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~11_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~13_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~13 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N14 +cycloneive_lcell_comb \timer_pwm|LessThan0~15 ( +// Equation(s): +// \timer_pwm|LessThan0~15_cout = CARRY((\timer_pwm|r_tim_arr [7] & (\timer_pwm|cnt [7] & !\timer_pwm|LessThan0~13_cout )) # (!\timer_pwm|r_tim_arr [7] & ((\timer_pwm|cnt [7]) # (!\timer_pwm|LessThan0~13_cout )))) + + .dataa(\timer_pwm|r_tim_arr [7]), + .datab(\timer_pwm|cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~13_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~15_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~15 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N16 +cycloneive_lcell_comb \timer_pwm|LessThan0~17 ( +// Equation(s): +// \timer_pwm|LessThan0~17_cout = CARRY((\timer_pwm|r_tim_arr [8] & ((!\timer_pwm|LessThan0~15_cout ) # (!\timer_pwm|cnt [8]))) # (!\timer_pwm|r_tim_arr [8] & (!\timer_pwm|cnt [8] & !\timer_pwm|LessThan0~15_cout ))) + + .dataa(\timer_pwm|r_tim_arr [8]), + .datab(\timer_pwm|cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~15_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~17_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~17 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N18 +cycloneive_lcell_comb \timer_pwm|LessThan0~19 ( +// Equation(s): +// \timer_pwm|LessThan0~19_cout = CARRY((\timer_pwm|r_tim_arr [9] & (\timer_pwm|cnt [9] & !\timer_pwm|LessThan0~17_cout )) # (!\timer_pwm|r_tim_arr [9] & ((\timer_pwm|cnt [9]) # (!\timer_pwm|LessThan0~17_cout )))) + + .dataa(\timer_pwm|r_tim_arr [9]), + .datab(\timer_pwm|cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~17_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~19_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~19 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N20 +cycloneive_lcell_comb \timer_pwm|LessThan0~21 ( +// Equation(s): +// \timer_pwm|LessThan0~21_cout = CARRY((\timer_pwm|cnt [10] & (\timer_pwm|r_tim_arr [10] & !\timer_pwm|LessThan0~19_cout )) # (!\timer_pwm|cnt [10] & ((\timer_pwm|r_tim_arr [10]) # (!\timer_pwm|LessThan0~19_cout )))) + + .dataa(\timer_pwm|cnt [10]), + .datab(\timer_pwm|r_tim_arr [10]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~19_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~21_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~21 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N22 +cycloneive_lcell_comb \timer_pwm|LessThan0~23 ( +// Equation(s): +// \timer_pwm|LessThan0~23_cout = CARRY((\timer_pwm|r_tim_arr [11] & (\timer_pwm|cnt [11] & !\timer_pwm|LessThan0~21_cout )) # (!\timer_pwm|r_tim_arr [11] & ((\timer_pwm|cnt [11]) # (!\timer_pwm|LessThan0~21_cout )))) + + .dataa(\timer_pwm|r_tim_arr [11]), + .datab(\timer_pwm|cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~21_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~23_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~23 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N24 +cycloneive_lcell_comb \timer_pwm|LessThan0~25 ( +// Equation(s): +// \timer_pwm|LessThan0~25_cout = CARRY((\timer_pwm|r_tim_arr [12] & ((!\timer_pwm|LessThan0~23_cout ) # (!\timer_pwm|cnt [12]))) # (!\timer_pwm|r_tim_arr [12] & (!\timer_pwm|cnt [12] & !\timer_pwm|LessThan0~23_cout ))) + + .dataa(\timer_pwm|r_tim_arr [12]), + .datab(\timer_pwm|cnt [12]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~23_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~25_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~25 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N26 +cycloneive_lcell_comb \timer_pwm|LessThan0~27 ( +// Equation(s): +// \timer_pwm|LessThan0~27_cout = CARRY((\timer_pwm|r_tim_arr [13] & (\timer_pwm|cnt [13] & !\timer_pwm|LessThan0~25_cout )) # (!\timer_pwm|r_tim_arr [13] & ((\timer_pwm|cnt [13]) # (!\timer_pwm|LessThan0~25_cout )))) + + .dataa(\timer_pwm|r_tim_arr [13]), + .datab(\timer_pwm|cnt [13]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~25_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~27_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~27 .lut_mask = 16'h004D; +defparam \timer_pwm|LessThan0~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N28 +cycloneive_lcell_comb \timer_pwm|LessThan0~29 ( +// Equation(s): +// \timer_pwm|LessThan0~29_cout = CARRY((\timer_pwm|r_tim_arr [14] & ((!\timer_pwm|LessThan0~27_cout ) # (!\timer_pwm|cnt [14]))) # (!\timer_pwm|r_tim_arr [14] & (!\timer_pwm|cnt [14] & !\timer_pwm|LessThan0~27_cout ))) + + .dataa(\timer_pwm|r_tim_arr [14]), + .datab(\timer_pwm|cnt [14]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|LessThan0~27_cout ), + .combout(), + .cout(\timer_pwm|LessThan0~29_cout )); +// synopsys translate_off +defparam \timer_pwm|LessThan0~29 .lut_mask = 16'h002B; +defparam \timer_pwm|LessThan0~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N30 +cycloneive_lcell_comb \timer_pwm|LessThan0~30 ( +// Equation(s): +// \timer_pwm|LessThan0~30_combout = (\timer_pwm|r_tim_arr [15] & ((\timer_pwm|LessThan0~29_cout ) # (!\timer_pwm|cnt [15]))) # (!\timer_pwm|r_tim_arr [15] & (\timer_pwm|LessThan0~29_cout & !\timer_pwm|cnt [15])) + + .dataa(gnd), + .datab(\timer_pwm|r_tim_arr [15]), + .datac(gnd), + .datad(\timer_pwm|cnt [15]), + .cin(\timer_pwm|LessThan0~29_cout ), + .combout(\timer_pwm|LessThan0~30_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|LessThan0~30 .lut_mask = 16'hC0FC; +defparam \timer_pwm|LessThan0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N1 +dffeas \timer_pwm|cnt[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[0]~16_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[0] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N2 +cycloneive_lcell_comb \timer_pwm|cnt[1]~18 ( +// Equation(s): +// \timer_pwm|cnt[1]~18_combout = (\timer_pwm|cnt [1] & (!\timer_pwm|cnt[0]~17 )) # (!\timer_pwm|cnt [1] & ((\timer_pwm|cnt[0]~17 ) # (GND))) +// \timer_pwm|cnt[1]~19 = CARRY((!\timer_pwm|cnt[0]~17 ) # (!\timer_pwm|cnt [1])) + + .dataa(gnd), + .datab(\timer_pwm|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[0]~17 ), + .combout(\timer_pwm|cnt[1]~18_combout ), + .cout(\timer_pwm|cnt[1]~19 )); +// synopsys translate_off +defparam \timer_pwm|cnt[1]~18 .lut_mask = 16'h3C3F; +defparam \timer_pwm|cnt[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N3 +dffeas \timer_pwm|cnt[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[1]~18_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[1] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N4 +cycloneive_lcell_comb \timer_pwm|cnt[2]~20 ( +// Equation(s): +// \timer_pwm|cnt[2]~20_combout = (\timer_pwm|cnt [2] & (\timer_pwm|cnt[1]~19 $ (GND))) # (!\timer_pwm|cnt [2] & (!\timer_pwm|cnt[1]~19 & VCC)) +// \timer_pwm|cnt[2]~21 = CARRY((\timer_pwm|cnt [2] & !\timer_pwm|cnt[1]~19 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[1]~19 ), + .combout(\timer_pwm|cnt[2]~20_combout ), + .cout(\timer_pwm|cnt[2]~21 )); +// synopsys translate_off +defparam \timer_pwm|cnt[2]~20 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N5 +dffeas \timer_pwm|cnt[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[2]~20_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[2] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N6 +cycloneive_lcell_comb \timer_pwm|cnt[3]~22 ( +// Equation(s): +// \timer_pwm|cnt[3]~22_combout = (\timer_pwm|cnt [3] & (!\timer_pwm|cnt[2]~21 )) # (!\timer_pwm|cnt [3] & ((\timer_pwm|cnt[2]~21 ) # (GND))) +// \timer_pwm|cnt[3]~23 = CARRY((!\timer_pwm|cnt[2]~21 ) # (!\timer_pwm|cnt [3])) + + .dataa(\timer_pwm|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[2]~21 ), + .combout(\timer_pwm|cnt[3]~22_combout ), + .cout(\timer_pwm|cnt[3]~23 )); +// synopsys translate_off +defparam \timer_pwm|cnt[3]~22 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N7 +dffeas \timer_pwm|cnt[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[3]~22_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[3] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N8 +cycloneive_lcell_comb \timer_pwm|cnt[4]~24 ( +// Equation(s): +// \timer_pwm|cnt[4]~24_combout = (\timer_pwm|cnt [4] & (\timer_pwm|cnt[3]~23 $ (GND))) # (!\timer_pwm|cnt [4] & (!\timer_pwm|cnt[3]~23 & VCC)) +// \timer_pwm|cnt[4]~25 = CARRY((\timer_pwm|cnt [4] & !\timer_pwm|cnt[3]~23 )) + + .dataa(gnd), + .datab(\timer_pwm|cnt [4]), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[3]~23 ), + .combout(\timer_pwm|cnt[4]~24_combout ), + .cout(\timer_pwm|cnt[4]~25 )); +// synopsys translate_off +defparam \timer_pwm|cnt[4]~24 .lut_mask = 16'hC30C; +defparam \timer_pwm|cnt[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N9 +dffeas \timer_pwm|cnt[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[4]~24_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[4] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N10 +cycloneive_lcell_comb \timer_pwm|cnt[5]~26 ( +// Equation(s): +// \timer_pwm|cnt[5]~26_combout = (\timer_pwm|cnt [5] & (!\timer_pwm|cnt[4]~25 )) # (!\timer_pwm|cnt [5] & ((\timer_pwm|cnt[4]~25 ) # (GND))) +// \timer_pwm|cnt[5]~27 = CARRY((!\timer_pwm|cnt[4]~25 ) # (!\timer_pwm|cnt [5])) + + .dataa(\timer_pwm|cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[4]~25 ), + .combout(\timer_pwm|cnt[5]~26_combout ), + .cout(\timer_pwm|cnt[5]~27 )); +// synopsys translate_off +defparam \timer_pwm|cnt[5]~26 .lut_mask = 16'h5A5F; +defparam \timer_pwm|cnt[5]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N11 +dffeas \timer_pwm|cnt[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[5]~26_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[5] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X25_Y21_N12 +cycloneive_lcell_comb \timer_pwm|cnt[6]~28 ( +// Equation(s): +// \timer_pwm|cnt[6]~28_combout = (\timer_pwm|cnt [6] & (\timer_pwm|cnt[5]~27 $ (GND))) # (!\timer_pwm|cnt [6] & (!\timer_pwm|cnt[5]~27 & VCC)) +// \timer_pwm|cnt[6]~29 = CARRY((\timer_pwm|cnt [6] & !\timer_pwm|cnt[5]~27 )) + + .dataa(\timer_pwm|cnt [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\timer_pwm|cnt[5]~27 ), + .combout(\timer_pwm|cnt[6]~28_combout ), + .cout(\timer_pwm|cnt[6]~29 )); +// synopsys translate_off +defparam \timer_pwm|cnt[6]~28 .lut_mask = 16'hA50A; +defparam \timer_pwm|cnt[6]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X25_Y21_N13 +dffeas \timer_pwm|cnt[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[6]~28_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[6] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X25_Y21_N15 +dffeas \timer_pwm|cnt[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|cnt[7]~30_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(!\timer_pwm|LessThan0~30_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|cnt[7] .is_wysiwyg = "true"; +defparam \timer_pwm|cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \timer_pwm|Equal0~1 ( +// Equation(s): +// \timer_pwm|Equal0~1_combout = (!\timer_pwm|cnt [7] & (!\timer_pwm|cnt [6] & (!\timer_pwm|cnt [4] & !\timer_pwm|cnt [5]))) + + .dataa(\timer_pwm|cnt [7]), + .datab(\timer_pwm|cnt [6]), + .datac(\timer_pwm|cnt [4]), + .datad(\timer_pwm|cnt [5]), + .cin(gnd), + .combout(\timer_pwm|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~1 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N4 +cycloneive_lcell_comb \timer_pwm|Equal0~2 ( +// Equation(s): +// \timer_pwm|Equal0~2_combout = (!\timer_pwm|cnt [8] & (!\timer_pwm|cnt [11] & (!\timer_pwm|cnt [9] & !\timer_pwm|cnt [10]))) + + .dataa(\timer_pwm|cnt [8]), + .datab(\timer_pwm|cnt [11]), + .datac(\timer_pwm|cnt [9]), + .datad(\timer_pwm|cnt [10]), + .cin(gnd), + .combout(\timer_pwm|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~2 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \timer_pwm|Equal0~0 ( +// Equation(s): +// \timer_pwm|Equal0~0_combout = (!\timer_pwm|cnt [0] & (!\timer_pwm|cnt [3] & (!\timer_pwm|cnt [2] & !\timer_pwm|cnt [1]))) + + .dataa(\timer_pwm|cnt [0]), + .datab(\timer_pwm|cnt [3]), + .datac(\timer_pwm|cnt [2]), + .datad(\timer_pwm|cnt [1]), + .cin(gnd), + .combout(\timer_pwm|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~0 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \timer_pwm|Equal0~3 ( +// Equation(s): +// \timer_pwm|Equal0~3_combout = (!\timer_pwm|cnt [13] & (!\timer_pwm|cnt [15] & (!\timer_pwm|cnt [14] & !\timer_pwm|cnt [12]))) + + .dataa(\timer_pwm|cnt [13]), + .datab(\timer_pwm|cnt [15]), + .datac(\timer_pwm|cnt [14]), + .datad(\timer_pwm|cnt [12]), + .cin(gnd), + .combout(\timer_pwm|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~3 .lut_mask = 16'h0001; +defparam \timer_pwm|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \timer_pwm|Equal0~4 ( +// Equation(s): +// \timer_pwm|Equal0~4_combout = (\timer_pwm|Equal0~1_combout & (\timer_pwm|Equal0~2_combout & (\timer_pwm|Equal0~0_combout & \timer_pwm|Equal0~3_combout ))) + + .dataa(\timer_pwm|Equal0~1_combout ), + .datab(\timer_pwm|Equal0~2_combout ), + .datac(\timer_pwm|Equal0~0_combout ), + .datad(\timer_pwm|Equal0~3_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal0~4 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \timer_pwm|tim_ch[0]~1 ( +// Equation(s): +// \timer_pwm|tim_ch[0]~1_combout = !\timer_pwm|Equal0~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(\timer_pwm|Equal0~4_combout ), + .datad(gnd), + .cin(gnd), + .combout(\timer_pwm|tim_ch[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0]~1 .lut_mask = 16'h0F0F; +defparam \timer_pwm|tim_ch[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N15 +cycloneive_io_ibuf \tim_ccr1[7]~input ( + .i(tim_ccr1[7]), + .ibar(gnd), + .o(\tim_ccr1[7]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[7]~input .bus_hold = "false"; +defparam \tim_ccr1[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[7]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[7]~feeder_combout = \tim_ccr1[7]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[7]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[7]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N13 +dffeas \timer_pwm|r_tim_ccr1[7] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [7]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[7] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[7] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[6]~input ( + .i(tim_ccr1[6]), + .ibar(gnd), + .o(\tim_ccr1[6]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[6]~input .bus_hold = "false"; +defparam \tim_ccr1[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N27 +dffeas \timer_pwm|r_tim_ccr1[6] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[6]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [6]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[6] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \timer_pwm|Equal1~3 ( +// Equation(s): +// \timer_pwm|Equal1~3_combout = (\timer_pwm|r_tim_ccr1 [7] & (\timer_pwm|cnt [7] & (\timer_pwm|cnt [6] $ (!\timer_pwm|r_tim_ccr1 [6])))) # (!\timer_pwm|r_tim_ccr1 [7] & (!\timer_pwm|cnt [7] & (\timer_pwm|cnt [6] $ (!\timer_pwm|r_tim_ccr1 [6])))) + + .dataa(\timer_pwm|r_tim_ccr1 [7]), + .datab(\timer_pwm|cnt [6]), + .datac(\timer_pwm|r_tim_ccr1 [6]), + .datad(\timer_pwm|cnt [7]), + .cin(gnd), + .combout(\timer_pwm|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~3 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[5]~input ( + .i(tim_ccr1[5]), + .ibar(gnd), + .o(\tim_ccr1[5]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[5]~input .bus_hold = "false"; +defparam \tim_ccr1[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[5]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[5]~feeder_combout = \tim_ccr1[5]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[5]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[5]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N21 +dffeas \timer_pwm|r_tim_ccr1[5] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [5]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[5] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[5] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[4]~input ( + .i(tim_ccr1[4]), + .ibar(gnd), + .o(\tim_ccr1[4]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[4]~input .bus_hold = "false"; +defparam \tim_ccr1[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \timer_pwm|r_tim_ccr1[4] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[4]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [4]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[4] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \timer_pwm|Equal1~2 ( +// Equation(s): +// \timer_pwm|Equal1~2_combout = (\timer_pwm|cnt [4] & (\timer_pwm|r_tim_ccr1 [4] & (\timer_pwm|r_tim_ccr1 [5] $ (!\timer_pwm|cnt [5])))) # (!\timer_pwm|cnt [4] & (!\timer_pwm|r_tim_ccr1 [4] & (\timer_pwm|r_tim_ccr1 [5] $ (!\timer_pwm|cnt [5])))) + + .dataa(\timer_pwm|cnt [4]), + .datab(\timer_pwm|r_tim_ccr1 [5]), + .datac(\timer_pwm|r_tim_ccr1 [4]), + .datad(\timer_pwm|cnt [5]), + .cin(gnd), + .combout(\timer_pwm|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~2 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y20_N8 +cycloneive_io_ibuf \tim_ccr1[2]~input ( + .i(tim_ccr1[2]), + .ibar(gnd), + .o(\tim_ccr1[2]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[2]~input .bus_hold = "false"; +defparam \tim_ccr1[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \timer_pwm|r_tim_ccr1[2] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[2]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[2] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[2] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N15 +cycloneive_io_ibuf \tim_ccr1[3]~input ( + .i(tim_ccr1[3]), + .ibar(gnd), + .o(\tim_ccr1[3]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[3]~input .bus_hold = "false"; +defparam \tim_ccr1[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[3]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[3]~feeder_combout = \tim_ccr1[3]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[3]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[3]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \timer_pwm|r_tim_ccr1[3] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[3] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \timer_pwm|Equal1~1 ( +// Equation(s): +// \timer_pwm|Equal1~1_combout = (\timer_pwm|cnt [3] & (\timer_pwm|r_tim_ccr1 [3] & (\timer_pwm|cnt [2] $ (!\timer_pwm|r_tim_ccr1 [2])))) # (!\timer_pwm|cnt [3] & (!\timer_pwm|r_tim_ccr1 [3] & (\timer_pwm|cnt [2] $ (!\timer_pwm|r_tim_ccr1 [2])))) + + .dataa(\timer_pwm|cnt [3]), + .datab(\timer_pwm|cnt [2]), + .datac(\timer_pwm|r_tim_ccr1 [2]), + .datad(\timer_pwm|r_tim_ccr1 [3]), + .cin(gnd), + .combout(\timer_pwm|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~1 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y19_N1 +cycloneive_io_ibuf \tim_ccr1[1]~input ( + .i(tim_ccr1[1]), + .ibar(gnd), + .o(\tim_ccr1[1]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[1]~input .bus_hold = "false"; +defparam \tim_ccr1[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N17 +dffeas \timer_pwm|r_tim_ccr1[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[1]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[1] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[0]~input ( + .i(tim_ccr1[0]), + .ibar(gnd), + .o(\tim_ccr1[0]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[0]~input .bus_hold = "false"; +defparam \tim_ccr1[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X28_Y21_N7 +dffeas \timer_pwm|r_tim_ccr1[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[0]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[0] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N6 +cycloneive_lcell_comb \timer_pwm|Equal1~0 ( +// Equation(s): +// \timer_pwm|Equal1~0_combout = (\timer_pwm|cnt [0] & (\timer_pwm|r_tim_ccr1 [0] & (\timer_pwm|r_tim_ccr1 [1] $ (!\timer_pwm|cnt [1])))) # (!\timer_pwm|cnt [0] & (!\timer_pwm|r_tim_ccr1 [0] & (\timer_pwm|r_tim_ccr1 [1] $ (!\timer_pwm|cnt [1])))) + + .dataa(\timer_pwm|cnt [0]), + .datab(\timer_pwm|r_tim_ccr1 [1]), + .datac(\timer_pwm|r_tim_ccr1 [0]), + .datad(\timer_pwm|cnt [1]), + .cin(gnd), + .combout(\timer_pwm|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~0 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \timer_pwm|Equal1~4 ( +// Equation(s): +// \timer_pwm|Equal1~4_combout = (\timer_pwm|Equal1~3_combout & (\timer_pwm|Equal1~2_combout & (\timer_pwm|Equal1~1_combout & \timer_pwm|Equal1~0_combout ))) + + .dataa(\timer_pwm|Equal1~3_combout ), + .datab(\timer_pwm|Equal1~2_combout ), + .datac(\timer_pwm|Equal1~1_combout ), + .datad(\timer_pwm|Equal1~0_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~4 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[15]~input ( + .i(tim_ccr1[15]), + .ibar(gnd), + .o(\tim_ccr1[15]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[15]~input .bus_hold = "false"; +defparam \tim_ccr1[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N28 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[15]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[15]~feeder_combout = \tim_ccr1[15]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[15]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[15]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N29 +dffeas \timer_pwm|r_tim_ccr1[15] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [15]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[15] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[15] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[14]~input ( + .i(tim_ccr1[14]), + .ibar(gnd), + .o(\tim_ccr1[14]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[14]~input .bus_hold = "false"; +defparam \tim_ccr1[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N23 +dffeas \timer_pwm|r_tim_ccr1[14] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[14]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [14]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[14] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \timer_pwm|Equal1~8 ( +// Equation(s): +// \timer_pwm|Equal1~8_combout = (\timer_pwm|r_tim_ccr1 [15] & (\timer_pwm|cnt [15] & (\timer_pwm|r_tim_ccr1 [14] $ (!\timer_pwm|cnt [14])))) # (!\timer_pwm|r_tim_ccr1 [15] & (!\timer_pwm|cnt [15] & (\timer_pwm|r_tim_ccr1 [14] $ (!\timer_pwm|cnt [14])))) + + .dataa(\timer_pwm|r_tim_ccr1 [15]), + .datab(\timer_pwm|cnt [15]), + .datac(\timer_pwm|r_tim_ccr1 [14]), + .datad(\timer_pwm|cnt [14]), + .cin(gnd), + .combout(\timer_pwm|Equal1~8_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~8 .lut_mask = 16'h9009; +defparam \timer_pwm|Equal1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[8]~input ( + .i(tim_ccr1[8]), + .ibar(gnd), + .o(\tim_ccr1[8]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[8]~input .bus_hold = "false"; +defparam \tim_ccr1[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N19 +dffeas \timer_pwm|r_tim_ccr1[8] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[8]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [8]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[8] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[8] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[9]~input ( + .i(tim_ccr1[9]), + .ibar(gnd), + .o(\tim_ccr1[9]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[9]~input .bus_hold = "false"; +defparam \tim_ccr1[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N24 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[9]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[9]~feeder_combout = \tim_ccr1[9]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[9]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[9]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N25 +dffeas \timer_pwm|r_tim_ccr1[9] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [9]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[9] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N18 +cycloneive_lcell_comb \timer_pwm|Equal1~5 ( +// Equation(s): +// \timer_pwm|Equal1~5_combout = (\timer_pwm|cnt [8] & (\timer_pwm|r_tim_ccr1 [8] & (\timer_pwm|cnt [9] $ (!\timer_pwm|r_tim_ccr1 [9])))) # (!\timer_pwm|cnt [8] & (!\timer_pwm|r_tim_ccr1 [8] & (\timer_pwm|cnt [9] $ (!\timer_pwm|r_tim_ccr1 [9])))) + + .dataa(\timer_pwm|cnt [8]), + .datab(\timer_pwm|cnt [9]), + .datac(\timer_pwm|r_tim_ccr1 [8]), + .datad(\timer_pwm|r_tim_ccr1 [9]), + .cin(gnd), + .combout(\timer_pwm|Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~5 .lut_mask = 16'h8421; +defparam \timer_pwm|Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y24_N8 +cycloneive_io_ibuf \tim_ccr1[11]~input ( + .i(tim_ccr1[11]), + .ibar(gnd), + .o(\tim_ccr1[11]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[11]~input .bus_hold = "false"; +defparam \tim_ccr1[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N13 +dffeas \timer_pwm|r_tim_ccr1[11] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[11]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [11]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[11] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[11] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N1 +cycloneive_io_ibuf \tim_ccr1[10]~input ( + .i(tim_ccr1[10]), + .ibar(gnd), + .o(\tim_ccr1[10]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[10]~input .bus_hold = "false"; +defparam \tim_ccr1[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \timer_pwm|r_tim_ccr1[10] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[10]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [10]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[10] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \timer_pwm|Equal1~6 ( +// Equation(s): +// \timer_pwm|Equal1~6_combout = (\timer_pwm|r_tim_ccr1 [11] & (\timer_pwm|cnt [11] & (\timer_pwm|r_tim_ccr1 [10] $ (!\timer_pwm|cnt [10])))) # (!\timer_pwm|r_tim_ccr1 [11] & (!\timer_pwm|cnt [11] & (\timer_pwm|r_tim_ccr1 [10] $ (!\timer_pwm|cnt [10])))) + + .dataa(\timer_pwm|r_tim_ccr1 [11]), + .datab(\timer_pwm|cnt [11]), + .datac(\timer_pwm|r_tim_ccr1 [10]), + .datad(\timer_pwm|cnt [10]), + .cin(gnd), + .combout(\timer_pwm|Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~6 .lut_mask = 16'h9009; +defparam \timer_pwm|Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y24_N15 +cycloneive_io_ibuf \tim_ccr1[12]~input ( + .i(tim_ccr1[12]), + .ibar(gnd), + .o(\tim_ccr1[12]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[12]~input .bus_hold = "false"; +defparam \tim_ccr1[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X26_Y21_N11 +dffeas \timer_pwm|r_tim_ccr1[12] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\tim_ccr1[12]~input_o ), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [12]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[12] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[12] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y24_N22 +cycloneive_io_ibuf \tim_ccr1[13]~input ( + .i(tim_ccr1[13]), + .ibar(gnd), + .o(\tim_ccr1[13]~input_o )); +// synopsys translate_off +defparam \tim_ccr1[13]~input .bus_hold = "false"; +defparam \tim_ccr1[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \timer_pwm|r_tim_ccr1[13]~feeder ( +// Equation(s): +// \timer_pwm|r_tim_ccr1[13]~feeder_combout = \tim_ccr1[13]~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\tim_ccr1[13]~input_o ), + .cin(gnd), + .combout(\timer_pwm|r_tim_ccr1[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[13]~feeder .lut_mask = 16'hFF00; +defparam \timer_pwm|r_tim_ccr1[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \timer_pwm|r_tim_ccr1[13] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|r_tim_ccr1[13]~feeder_combout ), + .asdata(vcc), + .clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|r_tim_ccr1 [13]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|r_tim_ccr1[13] .is_wysiwyg = "true"; +defparam \timer_pwm|r_tim_ccr1[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N10 +cycloneive_lcell_comb \timer_pwm|Equal1~7 ( +// Equation(s): +// \timer_pwm|Equal1~7_combout = (\timer_pwm|cnt [13] & (\timer_pwm|r_tim_ccr1 [13] & (\timer_pwm|cnt [12] $ (!\timer_pwm|r_tim_ccr1 [12])))) # (!\timer_pwm|cnt [13] & (!\timer_pwm|r_tim_ccr1 [13] & (\timer_pwm|cnt [12] $ (!\timer_pwm|r_tim_ccr1 [12])))) + + .dataa(\timer_pwm|cnt [13]), + .datab(\timer_pwm|cnt [12]), + .datac(\timer_pwm|r_tim_ccr1 [12]), + .datad(\timer_pwm|r_tim_ccr1 [13]), + .cin(gnd), + .combout(\timer_pwm|Equal1~7_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~7 .lut_mask = 16'h8241; +defparam \timer_pwm|Equal1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N20 +cycloneive_lcell_comb \timer_pwm|Equal1~9 ( +// Equation(s): +// \timer_pwm|Equal1~9_combout = (\timer_pwm|Equal1~8_combout & (\timer_pwm|Equal1~5_combout & (\timer_pwm|Equal1~6_combout & \timer_pwm|Equal1~7_combout ))) + + .dataa(\timer_pwm|Equal1~8_combout ), + .datab(\timer_pwm|Equal1~5_combout ), + .datac(\timer_pwm|Equal1~6_combout ), + .datad(\timer_pwm|Equal1~7_combout ), + .cin(gnd), + .combout(\timer_pwm|Equal1~9_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|Equal1~9 .lut_mask = 16'h8000; +defparam \timer_pwm|Equal1~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \timer_pwm|tim_ch[0]~0 ( +// Equation(s): +// \timer_pwm|tim_ch[0]~0_combout = (\timer_pwm|Equal0~4_combout ) # ((\timer_pwm|Equal1~4_combout & \timer_pwm|Equal1~9_combout )) + + .dataa(gnd), + .datab(\timer_pwm|Equal1~4_combout ), + .datac(\timer_pwm|Equal0~4_combout ), + .datad(\timer_pwm|Equal1~9_combout ), + .cin(gnd), + .combout(\timer_pwm|tim_ch[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0]~0 .lut_mask = 16'hFCF0; +defparam \timer_pwm|tim_ch[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N29 +dffeas \timer_pwm|tim_ch[0] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|tim_ch[0]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\timer_pwm|tim_ch[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|tim_ch [0]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|tim_ch[0] .is_wysiwyg = "true"; +defparam \timer_pwm|tim_ch[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \timer_pwm|tim_ch[1] ( + .clk(\my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\timer_pwm|Equal0~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\timer_pwm|tim_ch[0]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\timer_pwm|tim_ch [1]), + .prn(vcc)); +// synopsys translate_off +defparam \timer_pwm|tim_ch[1] .is_wysiwyg = "true"; +defparam \timer_pwm|tim_ch[1] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y0_N22 +cycloneive_io_ibuf \tim_cr[0]~input ( + .i(tim_cr[0]), + .ibar(gnd), + .o(\tim_cr[0]~input_o )); +// synopsys translate_off +defparam \tim_cr[0]~input .bus_hold = "false"; +defparam \tim_cr[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y7_N22 +cycloneive_io_ibuf \tim_cr[1]~input ( + .i(tim_cr[1]), + .ibar(gnd), + .o(\tim_cr[1]~input_o )); +// synopsys translate_off +defparam \tim_cr[1]~input .bus_hold = "false"; +defparam \tim_cr[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N22 +cycloneive_io_ibuf \tim_cr[2]~input ( + .i(tim_cr[2]), + .ibar(gnd), + .o(\tim_cr[2]~input_o )); +// synopsys translate_off +defparam \tim_cr[2]~input .bus_hold = "false"; +defparam \tim_cr[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N1 +cycloneive_io_ibuf \tim_cr[3]~input ( + .i(tim_cr[3]), + .ibar(gnd), + .o(\tim_cr[3]~input_o )); +// synopsys translate_off +defparam \tim_cr[3]~input .bus_hold = "false"; +defparam \tim_cr[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y0_N15 +cycloneive_io_ibuf \tim_cr[4]~input ( + .i(tim_cr[4]), + .ibar(gnd), + .o(\tim_cr[4]~input_o )); +// synopsys translate_off +defparam \tim_cr[4]~input .bus_hold = "false"; +defparam \tim_cr[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N15 +cycloneive_io_ibuf \tim_cr[5]~input ( + .i(tim_cr[5]), + .ibar(gnd), + .o(\tim_cr[5]~input_o )); +// synopsys translate_off +defparam \tim_cr[5]~input .bus_hold = "false"; +defparam \tim_cr[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y0_N15 +cycloneive_io_ibuf \tim_cr[6]~input ( + .i(tim_cr[6]), + .ibar(gnd), + .o(\tim_cr[6]~input_o )); +// synopsys translate_off +defparam \tim_cr[6]~input .bus_hold = "false"; +defparam \tim_cr[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X32_Y0_N8 +cycloneive_io_ibuf \tim_cr[7]~input ( + .i(tim_cr[7]), + .ibar(gnd), + .o(\tim_cr[7]~input_o )); +// synopsys translate_off +defparam \tim_cr[7]~input .bus_hold = "false"; +defparam \tim_cr[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X5_Y24_N15 +cycloneive_io_ibuf \tim_cr[8]~input ( + .i(tim_cr[8]), + .ibar(gnd), + .o(\tim_cr[8]~input_o )); +// synopsys translate_off +defparam \tim_cr[8]~input .bus_hold = "false"; +defparam \tim_cr[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y0_N1 +cycloneive_io_ibuf \tim_cr[9]~input ( + .i(tim_cr[9]), + .ibar(gnd), + .o(\tim_cr[9]~input_o )); +// synopsys translate_off +defparam \tim_cr[9]~input .bus_hold = "false"; +defparam \tim_cr[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y24_N1 +cycloneive_io_ibuf \tim_cr[10]~input ( + .i(tim_cr[10]), + .ibar(gnd), + .o(\tim_cr[10]~input_o )); +// synopsys translate_off +defparam \tim_cr[10]~input .bus_hold = "false"; +defparam \tim_cr[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X30_Y0_N8 +cycloneive_io_ibuf \tim_cr[11]~input ( + .i(tim_cr[11]), + .ibar(gnd), + .o(\tim_cr[11]~input_o )); +// synopsys translate_off +defparam \tim_cr[11]~input .bus_hold = "false"; +defparam \tim_cr[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N1 +cycloneive_io_ibuf \tim_cr[12]~input ( + .i(tim_cr[12]), + .ibar(gnd), + .o(\tim_cr[12]~input_o )); +// synopsys translate_off +defparam \tim_cr[12]~input .bus_hold = "false"; +defparam \tim_cr[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N22 +cycloneive_io_ibuf \tim_cr[13]~input ( + .i(tim_cr[13]), + .ibar(gnd), + .o(\tim_cr[13]~input_o )); +// synopsys translate_off +defparam \tim_cr[13]~input .bus_hold = "false"; +defparam \tim_cr[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y2_N15 +cycloneive_io_ibuf \tim_cr[14]~input ( + .i(tim_cr[14]), + .ibar(gnd), + .o(\tim_cr[14]~input_o )); +// synopsys translate_off +defparam \tim_cr[14]~input .bus_hold = "false"; +defparam \tim_cr[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y18_N1 +cycloneive_io_ibuf \tim_cr[15]~input ( + .i(tim_cr[15]), + .ibar(gnd), + .o(\tim_cr[15]~input_o )); +// synopsys translate_off +defparam \tim_cr[15]~input .bus_hold = "false"; +defparam \tim_cr[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N15 +cycloneive_io_ibuf \tim_cr[16]~input ( + .i(tim_cr[16]), + .ibar(gnd), + .o(\tim_cr[16]~input_o )); +// synopsys translate_off +defparam \tim_cr[16]~input .bus_hold = "false"; +defparam \tim_cr[16]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N8 +cycloneive_io_ibuf \tim_cr[17]~input ( + .i(tim_cr[17]), + .ibar(gnd), + .o(\tim_cr[17]~input_o )); +// synopsys translate_off +defparam \tim_cr[17]~input .bus_hold = "false"; +defparam \tim_cr[17]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X13_Y0_N22 +cycloneive_io_ibuf \tim_cr[18]~input ( + .i(tim_cr[18]), + .ibar(gnd), + .o(\tim_cr[18]~input_o )); +// synopsys translate_off +defparam \tim_cr[18]~input .bus_hold = "false"; +defparam \tim_cr[18]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y24_N8 +cycloneive_io_ibuf \tim_cr[19]~input ( + .i(tim_cr[19]), + .ibar(gnd), + .o(\tim_cr[19]~input_o )); +// synopsys translate_off +defparam \tim_cr[19]~input .bus_hold = "false"; +defparam \tim_cr[19]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X7_Y0_N1 +cycloneive_io_ibuf \tim_cr[20]~input ( + .i(tim_cr[20]), + .ibar(gnd), + .o(\tim_cr[20]~input_o )); +// synopsys translate_off +defparam \tim_cr[20]~input .bus_hold = "false"; +defparam \tim_cr[20]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X21_Y0_N1 +cycloneive_io_ibuf \tim_cr[21]~input ( + .i(tim_cr[21]), + .ibar(gnd), + .o(\tim_cr[21]~input_o )); +// synopsys translate_off +defparam \tim_cr[21]~input .bus_hold = "false"; +defparam \tim_cr[21]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X25_Y0_N15 +cycloneive_io_ibuf \tim_cr[22]~input ( + .i(tim_cr[22]), + .ibar(gnd), + .o(\tim_cr[22]~input_o )); +// synopsys translate_off +defparam \tim_cr[22]~input .bus_hold = "false"; +defparam \tim_cr[22]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N15 +cycloneive_io_ibuf \tim_cr[23]~input ( + .i(tim_cr[23]), + .ibar(gnd), + .o(\tim_cr[23]~input_o )); +// synopsys translate_off +defparam \tim_cr[23]~input .bus_hold = "false"; +defparam \tim_cr[23]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N22 +cycloneive_io_ibuf \tim_cr[24]~input ( + .i(tim_cr[24]), + .ibar(gnd), + .o(\tim_cr[24]~input_o )); +// synopsys translate_off +defparam \tim_cr[24]~input .bus_hold = "false"; +defparam \tim_cr[24]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X34_Y4_N22 +cycloneive_io_ibuf \tim_cr[25]~input ( + .i(tim_cr[25]), + .ibar(gnd), + .o(\tim_cr[25]~input_o )); +// synopsys translate_off +defparam \tim_cr[25]~input .bus_hold = "false"; +defparam \tim_cr[25]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y0_N15 +cycloneive_io_ibuf \tim_cr[26]~input ( + .i(tim_cr[26]), + .ibar(gnd), + .o(\tim_cr[26]~input_o )); +// synopsys translate_off +defparam \tim_cr[26]~input .bus_hold = "false"; +defparam \tim_cr[26]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y10_N1 +cycloneive_io_ibuf \tim_cr[27]~input ( + .i(tim_cr[27]), + .ibar(gnd), + .o(\tim_cr[27]~input_o )); +// synopsys translate_off +defparam \tim_cr[27]~input .bus_hold = "false"; +defparam \tim_cr[27]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y6_N22 +cycloneive_io_ibuf \tim_cr[28]~input ( + .i(tim_cr[28]), + .ibar(gnd), + .o(\tim_cr[28]~input_o )); +// synopsys translate_off +defparam \tim_cr[28]~input .bus_hold = "false"; +defparam \tim_cr[28]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y24_N8 +cycloneive_io_ibuf \tim_cr[29]~input ( + .i(tim_cr[29]), + .ibar(gnd), + .o(\tim_cr[29]~input_o )); +// synopsys translate_off +defparam \tim_cr[29]~input .bus_hold = "false"; +defparam \tim_cr[29]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X28_Y0_N22 +cycloneive_io_ibuf \tim_cr[30]~input ( + .i(tim_cr[30]), + .ibar(gnd), + .o(\tim_cr[30]~input_o )); +// synopsys translate_off +defparam \tim_cr[30]~input .bus_hold = "false"; +defparam \tim_cr[30]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X16_Y24_N1 +cycloneive_io_ibuf \tim_cr[31]~input ( + .i(tim_cr[31]), + .ibar(gnd), + .o(\tim_cr[31]~input_o )); +// synopsys translate_off +defparam \tim_cr[31]~input .bus_hold = "false"; +defparam \tim_cr[31]~input .simulate_z_as = "z"; +// synopsys translate_on + +endmodule diff --git a/timer_pwm/simulation/modelsim/timer_pwm_min_1200mv_0c_v_fast.sdo b/timer_pwm/simulation/modelsim/timer_pwm_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..f2b059f --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,2064 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE10F17C8, +// with speed grade M, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "timer_pwm_top") + (DATE "11/03/2018 15:43:36") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tim_ch\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (410:410:410) (466:466:466)) + (IOPATH i o (1582:1582:1582) (1585:1585:1585)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tim_ch\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (378:378:378) (428:428:428)) + (IOPATH i o (1599:1599:1599) (1624:1624:1624)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (108:108:108) (89:89:89)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (618:618:618) (618:618:618)) + (PORT inclk[0] (1111:1111:1111) (1111:1111:1111)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1121:1121:1121) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (152:152:152) (200:200:200)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (973:973:973) (870:870:870)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (775:775:775) (747:747:747)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked) + (DELAY + (ABSOLUTE + (PORT datac (657:657:657) (559:559:559)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (491:491:491) (546:546:546)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1732:1732:1732) (1922:1922:1922)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (770:770:770)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (737:737:737) (754:754:754)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[7\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[8\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[9\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (202:202:202)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[10\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[11\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (205:205:205)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[12\]\~40) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (202:202:202)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[13\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[14\]\~44) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (201:201:201)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[15\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (205:205:205)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (657:657:657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1704:1704:1704) (1893:1893:1893)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (770:770:770)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (737:737:737) (754:754:754)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (753:753:753) (771:771:771)) + (PORT asdata (1893:1893:1893) (2077:2077:2077)) + (PORT clrn (738:738:738) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (697:697:697)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (770:770:770)) + (PORT asdata (1777:1777:1777) (1954:1954:1954)) + (PORT clrn (737:737:737) (754:754:754)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1699:1699:1699) (1885:1885:1885)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (770:770:770)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (737:737:737) (754:754:754)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (708:708:708)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (981:981:981) (855:855:855)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (770:770:770)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (737:737:737) (754:754:754)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (753:753:753) (771:771:771)) + (PORT asdata (2071:2071:2071) (2284:2284:2284)) + (PORT clrn (738:738:738) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (753:753:753) (771:771:771)) + (PORT asdata (2054:2054:2054) (2265:2265:2265)) + (PORT clrn (738:738:738) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (753:753:753) (771:771:771)) + (PORT asdata (2220:2220:2220) (2460:2460:2460)) + (PORT clrn (738:738:738) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (753:753:753) (771:771:771)) + (PORT asdata (1760:1760:1760) (1938:1938:1938)) + (PORT clrn (738:738:738) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (753:753:753) (771:771:771)) + (PORT asdata (1901:1901:1901) (2096:2096:2096)) + (PORT clrn (738:738:738) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1867:1867:1867) (2073:2073:2073)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (770:770:770)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (737:737:737) (754:754:754)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (753:753:753) (771:771:771)) + (PORT asdata (2183:2183:2183) (2421:2421:2421)) + (PORT clrn (738:738:738) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1605:1605:1605) (1785:1785:1785)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (752:752:752) (770:770:770)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (737:737:737) (754:754:754)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (753:753:753) (771:771:771)) + (PORT asdata (1795:1795:1795) (1972:1972:1972)) + (PORT clrn (738:738:738) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (338:338:338) (717:717:717)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (753:753:753) (771:771:771)) + (PORT asdata (1864:1864:1864) (2047:2047:2047)) + (PORT clrn (738:738:738) (755:755:755)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (205:205:205) (263:263:263)) + (PORT datab (239:239:239) (295:295:295)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (281:281:281)) + (PORT datab (203:203:203) (260:260:260)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (294:294:294)) + (PORT datab (214:214:214) (269:269:269)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (279:279:279)) + (PORT datab (130:130:130) (177:177:177)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (271:271:271)) + (PORT datab (233:233:233) (291:291:291)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (401:401:401)) + (PORT datab (130:130:130) (178:178:178)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (383:383:383)) + (PORT datab (130:130:130) (178:178:178)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (259:259:259)) + (PORT datab (233:233:233) (292:292:292)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (347:347:347) (416:416:416)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (244:244:244) (301:301:301)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~21) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (380:380:380)) + (PORT datab (213:213:213) (268:268:268)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~23) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (273:273:273)) + (PORT datab (240:240:240) (295:295:295)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~25) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (258:258:258)) + (PORT datab (239:239:239) (294:294:294)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~27) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (259:259:259)) + (PORT datab (320:320:320) (388:388:388)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~29) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (260:260:260)) + (PORT datab (225:225:225) (281:281:281)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~30) + (DELAY + (ABSOLUTE + (PORT datab (317:317:317) (384:384:384)) + (PORT datad (321:321:321) (376:376:376)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[5\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (204:204:204)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (PORT sclr (404:404:404) (423:423:423)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (462:462:462)) + (PORT datab (376:376:376) (450:450:450)) + (PORT datac (376:376:376) (443:443:443)) + (PORT datad (378:378:378) (442:442:442)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (283:283:283)) + (PORT datab (228:228:228) (282:282:282)) + (PORT datac (345:345:345) (400:400:400)) + (PORT datad (217:217:217) (266:266:266)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (452:452:452)) + (PORT datab (385:385:385) (456:456:456)) + (PORT datac (370:370:370) (442:442:442)) + (PORT datad (371:371:371) (440:440:440)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (299:299:299)) + (PORT datab (227:227:227) (281:281:281)) + (PORT datac (343:343:343) (407:407:407)) + (PORT datad (225:225:225) (273:273:273)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (327:327:327) (377:377:377)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (306:306:306) (346:346:346)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|tim_ch\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (92:92:92) (116:116:116)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (678:678:678)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1734:1734:1734) (1933:1933:1933)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (758:758:758) (776:776:776)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (743:743:743) (760:760:760)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (657:657:657)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (758:758:758) (776:776:776)) + (PORT asdata (1888:1888:1888) (2073:2073:2073)) + (PORT clrn (743:743:743) (760:760:760)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (378:378:378) (451:451:451)) + (PORT datad (375:375:375) (437:437:437)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1599:1599:1599) (1776:1776:1776)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (758:758:758) (776:776:776)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (743:743:743) (760:760:760)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (697:697:697)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (758:758:758) (776:776:776)) + (PORT asdata (1792:1792:1792) (1977:1977:1977)) + (PORT clrn (743:743:743) (760:760:760)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (466:466:466)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (378:378:378) (441:441:441)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (758:758:758) (776:776:776)) + (PORT asdata (1922:1922:1922) (2118:2118:2118)) + (PORT clrn (743:743:743) (760:760:760)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (278:278:278) (657:657:657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1614:1614:1614) (1797:1797:1797)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (758:758:758) (776:776:776)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (743:743:743) (760:760:760)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (453:453:453)) + (PORT datab (390:390:390) (465:465:465)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (688:688:688)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (758:758:758) (776:776:776)) + (PORT asdata (1912:1912:1912) (2106:2106:2106)) + (PORT clrn (743:743:743) (760:760:760)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (758:758:758) (776:776:776)) + (PORT asdata (1787:1787:1787) (1970:1970:1970)) + (PORT clrn (743:743:743) (760:760:760)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (452:452:452)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (371:371:371) (439:439:439)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (139:139:139)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1619:1619:1619) (1804:1804:1804)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT asdata (1924:1924:1924) (2118:2118:2118)) + (PORT clrn (739:739:739) (756:756:756)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (202:202:202) (259:259:259)) + (PORT datab (223:223:223) (277:277:277)) + (PORT datad (221:221:221) (270:270:270)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT asdata (1780:1780:1780) (1959:1959:1959)) + (PORT clrn (739:739:739) (756:756:756)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1615:1615:1615) (1791:1791:1791)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (282:282:282)) + (PORT datab (224:224:224) (278:278:278)) + (PORT datad (118:118:118) (154:154:154)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT asdata (2047:2047:2047) (2252:2252:2252)) + (PORT clrn (739:739:739) (756:756:756)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT asdata (1939:1939:1939) (2136:2136:2136)) + (PORT clrn (739:739:739) (756:756:756)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (225:225:225) (279:279:279)) + (PORT datad (215:215:215) (264:264:264)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (298:298:298) (677:677:677)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT asdata (1763:1763:1763) (1942:1942:1942)) + (PORT clrn (739:739:739) (756:756:756)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1757:1757:1757) (1955:1955:1955)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (754:754:754) (772:772:772)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (739:739:739) (756:756:756)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (298:298:298)) + (PORT datab (243:243:243) (297:297:297)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|tim_ch\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (96:96:96) (121:121:121)) + (PORT datad (315:315:315) (360:360:360)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|tim_ch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (758:758:758) (776:776:776)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (407:407:407) (428:428:428)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|tim_ch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (758:758:758) (776:776:776)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (407:407:407) (428:428:428)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) +) diff --git a/timer_pwm/simulation/modelsim/timer_pwm_modelsim.xrf b/timer_pwm/simulation/modelsim/timer_pwm_modelsim.xrf new file mode 100644 index 0000000..b84cb8b --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_modelsim.xrf @@ -0,0 +1,213 @@ +vendor_name = ModelSim +source_file = 1, F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v +source_file = 1, F:/Code/FPGA/reserve/timer_pwm/timer_pwm.out.sdc +source_file = 1, F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.qip +source_file = 1, F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v +source_file = 1, F:/Code/FPGA/reserve/timer_pwm/testbench/my_pll_tb.v +source_file = 1, F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v +source_file = 1, F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/altpll.tdf +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/aglobal180.inc +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/stratix_pll.inc +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/stratixii_pll.inc +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/cycloneii_pll.inc +source_file = 1, d:/intelfpga/18.0/quartus/libraries/megafunctions/cbx.lst +source_file = 1, F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll1.v +design_name = timer_pwm_top +instance = comp, \tim_ch[0]~output , tim_ch[0]~output, timer_pwm_top, 1 +instance = comp, \tim_ch[1]~output , tim_ch[1]~output, timer_pwm_top, 1 +instance = comp, \tim_ch[2]~output , tim_ch[2]~output, timer_pwm_top, 1 +instance = comp, \tim_ch[3]~output , tim_ch[3]~output, timer_pwm_top, 1 +instance = comp, \tim_ch[4]~output , tim_ch[4]~output, timer_pwm_top, 1 +instance = comp, \tim_ch[5]~output , tim_ch[5]~output, timer_pwm_top, 1 +instance = comp, \tim_ch[6]~output , tim_ch[6]~output, timer_pwm_top, 1 +instance = comp, \tim_ch[7]~output , tim_ch[7]~output, timer_pwm_top, 1 +instance = comp, \~ALTERA_DCLK~~obuf , ~ALTERA_DCLK~~obuf, timer_pwm_top, 1 +instance = comp, \~ALTERA_nCEO~~obuf , ~ALTERA_nCEO~~obuf, timer_pwm_top, 1 +instance = comp, \rst_n~input , rst_n~input, timer_pwm_top, 1 +instance = comp, \rst_n~inputclkctrl , rst_n~inputclkctrl, timer_pwm_top, 1 +instance = comp, \clk~input , clk~input, timer_pwm_top, 1 +instance = comp, \my_pll|altpll_component|auto_generated|pll1 , my_pll|altpll_component|auto_generated|pll1, timer_pwm_top, 1 +instance = comp, \my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , my_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[0]~16 , timer_pwm|cnt[0]~16, timer_pwm_top, 1 +instance = comp, \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder , my_pll|altpll_component|auto_generated|pll_lock_sync~feeder, timer_pwm_top, 1 +instance = comp, \my_pll|altpll_component|auto_generated|pll_lock_sync , my_pll|altpll_component|auto_generated|pll_lock_sync, timer_pwm_top, 1 +instance = comp, \my_pll|altpll_component|auto_generated|locked , my_pll|altpll_component|auto_generated|locked, timer_pwm_top, 1 +instance = comp, \my_pll|altpll_component|auto_generated|locked~clkctrl , my_pll|altpll_component|auto_generated|locked~clkctrl, timer_pwm_top, 1 +instance = comp, \tim_arr[15]~input , tim_arr[15]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[15]~feeder , timer_pwm|r_tim_arr[15]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[15] , timer_pwm|r_tim_arr[15], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[7]~30 , timer_pwm|cnt[7]~30, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[8]~32 , timer_pwm|cnt[8]~32, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[8] , timer_pwm|cnt[8], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[9]~34 , timer_pwm|cnt[9]~34, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[9] , timer_pwm|cnt[9], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[10]~36 , timer_pwm|cnt[10]~36, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[10] , timer_pwm|cnt[10], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[11]~38 , timer_pwm|cnt[11]~38, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[11] , timer_pwm|cnt[11], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[12]~40 , timer_pwm|cnt[12]~40, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[12] , timer_pwm|cnt[12], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[13]~42 , timer_pwm|cnt[13]~42, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[13] , timer_pwm|cnt[13], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[14]~44 , timer_pwm|cnt[14]~44, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[14] , timer_pwm|cnt[14], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[15]~46 , timer_pwm|cnt[15]~46, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[15] , timer_pwm|cnt[15], timer_pwm_top, 1 +instance = comp, \tim_arr[14]~input , tim_arr[14]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[14]~feeder , timer_pwm|r_tim_arr[14]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[14] , timer_pwm|r_tim_arr[14], timer_pwm_top, 1 +instance = comp, \tim_arr[13]~input , tim_arr[13]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[13] , timer_pwm|r_tim_arr[13], timer_pwm_top, 1 +instance = comp, \tim_arr[12]~input , tim_arr[12]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[12] , timer_pwm|r_tim_arr[12], timer_pwm_top, 1 +instance = comp, \tim_arr[11]~input , tim_arr[11]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[11]~feeder , timer_pwm|r_tim_arr[11]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[11] , timer_pwm|r_tim_arr[11], timer_pwm_top, 1 +instance = comp, \tim_arr[10]~input , tim_arr[10]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[10]~feeder , timer_pwm|r_tim_arr[10]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[10] , timer_pwm|r_tim_arr[10], timer_pwm_top, 1 +instance = comp, \tim_arr[9]~input , tim_arr[9]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[9] , timer_pwm|r_tim_arr[9], timer_pwm_top, 1 +instance = comp, \tim_arr[8]~input , tim_arr[8]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[8] , timer_pwm|r_tim_arr[8], timer_pwm_top, 1 +instance = comp, \tim_arr[7]~input , tim_arr[7]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[7] , timer_pwm|r_tim_arr[7], timer_pwm_top, 1 +instance = comp, \tim_arr[6]~input , tim_arr[6]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[6] , timer_pwm|r_tim_arr[6], timer_pwm_top, 1 +instance = comp, \tim_arr[5]~input , tim_arr[5]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[5] , timer_pwm|r_tim_arr[5], timer_pwm_top, 1 +instance = comp, \tim_arr[4]~input , tim_arr[4]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[4]~feeder , timer_pwm|r_tim_arr[4]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[4] , timer_pwm|r_tim_arr[4], timer_pwm_top, 1 +instance = comp, \tim_arr[3]~input , tim_arr[3]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[3] , timer_pwm|r_tim_arr[3], timer_pwm_top, 1 +instance = comp, \tim_arr[2]~input , tim_arr[2]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[2]~feeder , timer_pwm|r_tim_arr[2]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[2] , timer_pwm|r_tim_arr[2], timer_pwm_top, 1 +instance = comp, \tim_arr[1]~input , tim_arr[1]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[1] , timer_pwm|r_tim_arr[1], timer_pwm_top, 1 +instance = comp, \tim_arr[0]~input , tim_arr[0]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_arr[0] , timer_pwm|r_tim_arr[0], timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~1 , timer_pwm|LessThan0~1, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~3 , timer_pwm|LessThan0~3, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~5 , timer_pwm|LessThan0~5, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~7 , timer_pwm|LessThan0~7, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~9 , timer_pwm|LessThan0~9, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~11 , timer_pwm|LessThan0~11, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~13 , timer_pwm|LessThan0~13, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~15 , timer_pwm|LessThan0~15, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~17 , timer_pwm|LessThan0~17, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~19 , timer_pwm|LessThan0~19, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~21 , timer_pwm|LessThan0~21, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~23 , timer_pwm|LessThan0~23, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~25 , timer_pwm|LessThan0~25, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~27 , timer_pwm|LessThan0~27, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~29 , timer_pwm|LessThan0~29, timer_pwm_top, 1 +instance = comp, \timer_pwm|LessThan0~30 , timer_pwm|LessThan0~30, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[0] , timer_pwm|cnt[0], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[1]~18 , timer_pwm|cnt[1]~18, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[1] , timer_pwm|cnt[1], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[2]~20 , timer_pwm|cnt[2]~20, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[2] , timer_pwm|cnt[2], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[3]~22 , timer_pwm|cnt[3]~22, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[3] , timer_pwm|cnt[3], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[4]~24 , timer_pwm|cnt[4]~24, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[4] , timer_pwm|cnt[4], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[5]~26 , timer_pwm|cnt[5]~26, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[5] , timer_pwm|cnt[5], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[6]~28 , timer_pwm|cnt[6]~28, timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[6] , timer_pwm|cnt[6], timer_pwm_top, 1 +instance = comp, \timer_pwm|cnt[7] , timer_pwm|cnt[7], timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal0~1 , timer_pwm|Equal0~1, timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal0~2 , timer_pwm|Equal0~2, timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal0~0 , timer_pwm|Equal0~0, timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal0~3 , timer_pwm|Equal0~3, timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal0~4 , timer_pwm|Equal0~4, timer_pwm_top, 1 +instance = comp, \timer_pwm|tim_ch[0]~1 , timer_pwm|tim_ch[0]~1, timer_pwm_top, 1 +instance = comp, \tim_ccr1[7]~input , tim_ccr1[7]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[7]~feeder , timer_pwm|r_tim_ccr1[7]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[7] , timer_pwm|r_tim_ccr1[7], timer_pwm_top, 1 +instance = comp, \tim_ccr1[6]~input , tim_ccr1[6]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[6] , timer_pwm|r_tim_ccr1[6], timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal1~3 , timer_pwm|Equal1~3, timer_pwm_top, 1 +instance = comp, \tim_ccr1[5]~input , tim_ccr1[5]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[5]~feeder , timer_pwm|r_tim_ccr1[5]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[5] , timer_pwm|r_tim_ccr1[5], timer_pwm_top, 1 +instance = comp, \tim_ccr1[4]~input , tim_ccr1[4]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[4] , timer_pwm|r_tim_ccr1[4], timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal1~2 , timer_pwm|Equal1~2, timer_pwm_top, 1 +instance = comp, \tim_ccr1[2]~input , tim_ccr1[2]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[2] , timer_pwm|r_tim_ccr1[2], timer_pwm_top, 1 +instance = comp, \tim_ccr1[3]~input , tim_ccr1[3]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[3]~feeder , timer_pwm|r_tim_ccr1[3]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[3] , timer_pwm|r_tim_ccr1[3], timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal1~1 , timer_pwm|Equal1~1, timer_pwm_top, 1 +instance = comp, \tim_ccr1[1]~input , tim_ccr1[1]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[1] , timer_pwm|r_tim_ccr1[1], timer_pwm_top, 1 +instance = comp, \tim_ccr1[0]~input , tim_ccr1[0]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[0] , timer_pwm|r_tim_ccr1[0], timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal1~0 , timer_pwm|Equal1~0, timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal1~4 , timer_pwm|Equal1~4, timer_pwm_top, 1 +instance = comp, \tim_ccr1[15]~input , tim_ccr1[15]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[15]~feeder , timer_pwm|r_tim_ccr1[15]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[15] , timer_pwm|r_tim_ccr1[15], timer_pwm_top, 1 +instance = comp, \tim_ccr1[14]~input , tim_ccr1[14]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[14] , timer_pwm|r_tim_ccr1[14], timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal1~8 , timer_pwm|Equal1~8, timer_pwm_top, 1 +instance = comp, \tim_ccr1[8]~input , tim_ccr1[8]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[8] , timer_pwm|r_tim_ccr1[8], timer_pwm_top, 1 +instance = comp, \tim_ccr1[9]~input , tim_ccr1[9]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[9]~feeder , timer_pwm|r_tim_ccr1[9]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[9] , timer_pwm|r_tim_ccr1[9], timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal1~5 , timer_pwm|Equal1~5, timer_pwm_top, 1 +instance = comp, \tim_ccr1[11]~input , tim_ccr1[11]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[11] , timer_pwm|r_tim_ccr1[11], timer_pwm_top, 1 +instance = comp, \tim_ccr1[10]~input , tim_ccr1[10]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[10] , timer_pwm|r_tim_ccr1[10], timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal1~6 , timer_pwm|Equal1~6, timer_pwm_top, 1 +instance = comp, \tim_ccr1[12]~input , tim_ccr1[12]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[12] , timer_pwm|r_tim_ccr1[12], timer_pwm_top, 1 +instance = comp, \tim_ccr1[13]~input , tim_ccr1[13]~input, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[13]~feeder , timer_pwm|r_tim_ccr1[13]~feeder, timer_pwm_top, 1 +instance = comp, \timer_pwm|r_tim_ccr1[13] , timer_pwm|r_tim_ccr1[13], timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal1~7 , timer_pwm|Equal1~7, timer_pwm_top, 1 +instance = comp, \timer_pwm|Equal1~9 , timer_pwm|Equal1~9, timer_pwm_top, 1 +instance = comp, \timer_pwm|tim_ch[0]~0 , timer_pwm|tim_ch[0]~0, timer_pwm_top, 1 +instance = comp, \timer_pwm|tim_ch[0] , timer_pwm|tim_ch[0], timer_pwm_top, 1 +instance = comp, \timer_pwm|tim_ch[1] , timer_pwm|tim_ch[1], timer_pwm_top, 1 +instance = comp, \tim_cr[0]~input , tim_cr[0]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[1]~input , tim_cr[1]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[2]~input , tim_cr[2]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[3]~input , tim_cr[3]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[4]~input , tim_cr[4]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[5]~input , tim_cr[5]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[6]~input , tim_cr[6]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[7]~input , tim_cr[7]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[8]~input , tim_cr[8]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[9]~input , tim_cr[9]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[10]~input , tim_cr[10]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[11]~input , tim_cr[11]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[12]~input , tim_cr[12]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[13]~input , tim_cr[13]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[14]~input , tim_cr[14]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[15]~input , tim_cr[15]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[16]~input , tim_cr[16]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[17]~input , tim_cr[17]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[18]~input , tim_cr[18]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[19]~input , tim_cr[19]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[20]~input , tim_cr[20]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[21]~input , tim_cr[21]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[22]~input , tim_cr[22]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[23]~input , tim_cr[23]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[24]~input , tim_cr[24]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[25]~input , tim_cr[25]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[26]~input , tim_cr[26]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[27]~input , tim_cr[27]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[28]~input , tim_cr[28]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[29]~input , tim_cr[29]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[30]~input , tim_cr[30]~input, timer_pwm_top, 1 +instance = comp, \tim_cr[31]~input , tim_cr[31]~input, timer_pwm_top, 1 +instance = comp, \~ALTERA_ASDO_DATA1~~ibuf , ~ALTERA_ASDO_DATA1~~ibuf, timer_pwm_top, 1 +instance = comp, \~ALTERA_FLASH_nCE_nCSO~~ibuf , ~ALTERA_FLASH_nCE_nCSO~~ibuf, timer_pwm_top, 1 +instance = comp, \~ALTERA_DATA0~~ibuf , ~ALTERA_DATA0~~ibuf, timer_pwm_top, 1 diff --git a/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do new file mode 100644 index 0000000..8fab661 --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {timer_pwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench {F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" timer_pwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do.bak b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do.bak new file mode 100644 index 0000000..8fab661 --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do.bak @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {timer_pwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench {F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" timer_pwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do.bak1 b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do.bak1 new file mode 100644 index 0000000..8fab661 --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do.bak1 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {timer_pwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench {F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" timer_pwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do.bak2 b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do.bak2 new file mode 100644 index 0000000..8fab661 --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_gate_verilog.do.bak2 @@ -0,0 +1,17 @@ +transcript on +if {[file exists gate_work]} { + vdel -lib gate_work -all +} +vlib gate_work +vmap work gate_work + +vlog -vlog01compat -work work +incdir+. {timer_pwm_8_1200mv_85c_slow.vo} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench {F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v} + +vsim -t 1ps +transport_int_delays +transport_path_delays -L altera_ver -L cycloneive_ver -L gate_work -L work -voptargs="+acc" timer_pwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do new file mode 100644 index 0000000..0304745 --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm {F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/ip {F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/rtl {F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/db {F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench {F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" timer_pwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do.bak b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do.bak new file mode 100644 index 0000000..179eb09 --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do.bak @@ -0,0 +1,17 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm {F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench {F:/Code/FPGA/reserve/timer_pwm/testbench/my_pll_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" my_pll_tb + +add wave * +view structure +view signals +run -all diff --git a/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do.bak1 b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do.bak1 new file mode 100644 index 0000000..2f76dc6 --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do.bak1 @@ -0,0 +1,18 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/ip {F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/db {F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench {F:/Code/FPGA/reserve/timer_pwm/testbench/my_pll_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" my_pll_tb + +add wave * +view structure +view signals +run -all diff --git a/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do.bak2 b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do.bak2 new file mode 100644 index 0000000..0304745 --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_run_msim_rtl_verilog.do.bak2 @@ -0,0 +1,20 @@ +transcript on +if {[file exists rtl_work]} { + vdel -lib rtl_work -all +} +vlib rtl_work +vmap work rtl_work + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm {F:/Code/FPGA/reserve/timer_pwm/timer_pwm.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/ip {F:/Code/FPGA/reserve/timer_pwm/ip/my_pll.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/rtl {F:/Code/FPGA/reserve/timer_pwm/rtl/timer_pwm_top.v} +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/db {F:/Code/FPGA/reserve/timer_pwm/db/my_pll_altpll.v} + +vlog -vlog01compat -work work +incdir+F:/Code/FPGA/reserve/timer_pwm/testbench {F:/Code/FPGA/reserve/timer_pwm/testbench/timer_pwm_top_tb.v} + +vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" timer_pwm_top_tb + +add wave * +view structure +view signals +run -all diff --git a/timer_pwm/simulation/modelsim/timer_pwm_v.sdo b/timer_pwm/simulation/modelsim/timer_pwm_v.sdo new file mode 100644 index 0000000..28a7a2b --- /dev/null +++ b/timer_pwm/simulation/modelsim/timer_pwm_v.sdo @@ -0,0 +1,2064 @@ +// Copyright (C) 2018 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + +// +// Device: Altera EP4CE10F17C8 Package FBGA256 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE10F17C8, +// with speed grade 8, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "timer_pwm_top") + (DATE "11/03/2018 15:43:36") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tim_ch\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1078:1078:1078) (988:988:988)) + (IOPATH i o (3127:3127:3127) (3075:3075:3075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tim_ch\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1007:1007:1007) (931:931:931)) + (IOPATH i o (3138:3138:3138) (3115:3115:3115)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (222:222:222) (208:208:208)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (1327:1327:1327) (1327:1327:1327)) + (PORT inclk[0] (2336:2336:2336) (2336:2336:2336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2340:2340:2340) (2307:2307:2307)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (382:382:382) (459:459:459)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE my_pll\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2010:2010:2010) (2138:2138:2138)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked) + (DELAY + (ABSOLUTE + (PORT datac (1302:1302:1302) (1421:1421:1421)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE my_pll\|altpll_component\|auto_generated\|locked\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1172:1172:1172) (1153:1153:1153)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3628:3628:3628) (3804:3804:3804)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[7\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[8\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[9\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (462:462:462)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[10\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[11\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[12\]\~40) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (462:462:462)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[13\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[14\]\~44) + (DELAY + (ABSOLUTE + (PORT datab (384:384:384) (461:461:461)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[15\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (473:473:473)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3556:3556:3556) (3742:3742:3742)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4068:4068:4068) (4229:4229:4229)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT asdata (3770:3770:3770) (3978:3978:3978)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[11\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3547:3547:3547) (3732:3732:3732)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (776:776:776) (822:822:822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1932:1932:1932) (2009:2009:2009)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4484:4484:4484) (4614:4614:4614)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4447:4447:4447) (4579:4579:4579)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4854:4854:4854) (4943:4943:4943)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (3716:3716:3716) (3946:3946:3946)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4095:4095:4095) (4265:4265:4265)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3938:3938:3938) (4087:4087:4087)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (4783:4783:4783) (4887:4887:4887)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_arr\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3305:3305:3305) (3533:3533:3533)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1608:1608:1608) (1645:1645:1645)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1642:1642:1642) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (3805:3805:3805) (4015:4015:4015)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_arr\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (784:784:784) (831:831:831)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_arr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1646:1646:1646)) + (PORT asdata (3996:3996:3996) (4166:4166:4166)) + (PORT clrn (1643:1643:1643) (1639:1639:1639)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (581:581:581)) + (PORT datab (653:653:653) (655:655:655)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (623:623:623)) + (PORT datab (538:538:538) (574:574:574)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (654:654:654)) + (PORT datab (590:590:590) (596:596:596)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (620:620:620)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~9) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (605:605:605)) + (PORT datab (637:637:637) (645:645:645)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~11) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (879:879:879)) + (PORT datab (333:333:333) (408:408:408)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~13) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (836:836:836)) + (PORT datab (333:333:333) (409:409:409)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~15) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (576:576:576)) + (PORT datab (637:637:637) (645:645:645)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~17) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (420:420:420)) + (PORT datab (949:949:949) (904:904:904)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~19) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (419:419:419)) + (PORT datab (657:657:657) (666:666:666)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~21) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (826:826:826)) + (PORT datab (589:589:589) (595:595:595)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~23) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (606:606:606)) + (PORT datab (650:650:650) (656:656:656)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~25) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (573:573:573)) + (PORT datab (649:649:649) (654:654:654)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~27) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (576:576:576)) + (PORT datab (868:868:868) (840:840:840)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~29) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (577:577:577)) + (PORT datab (595:595:595) (623:623:623)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|LessThan0\~30) + (DELAY + (ABSOLUTE + (PORT datab (858:858:858) (831:831:831)) + (PORT datad (850:850:850) (828:828:828)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[5\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|cnt\[6\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1644:1644:1644) (1640:1640:1640)) + (PORT sclr (1067:1067:1067) (1153:1153:1153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (968:968:968)) + (PORT datab (939:939:939) (941:941:941)) + (PORT datac (946:946:946) (928:928:928)) + (PORT datad (945:945:945) (929:929:929)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (625:625:625)) + (PORT datab (596:596:596) (623:623:623)) + (PORT datac (899:899:899) (877:877:877)) + (PORT datad (574:574:574) (593:593:593)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (951:951:951)) + (PORT datab (979:979:979) (955:955:955)) + (PORT datac (935:935:935) (927:927:927)) + (PORT datad (932:932:932) (922:922:922)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (658:658:658)) + (PORT datab (594:594:594) (620:620:620)) + (PORT datac (917:917:917) (896:896:896)) + (PORT datad (591:591:591) (607:607:607)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (315:315:315)) + (PORT datab (835:835:835) (776:776:776)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (771:771:771) (714:714:714)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|tim_ch\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (243:243:243) (273:273:273)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (746:746:746) (792:792:792)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3678:3678:3678) (3862:3862:3862)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT asdata (4035:4035:4035) (4217:4217:4217)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (421:421:421)) + (PORT datab (940:940:940) (943:943:943)) + (PORT datad (942:942:942) (916:916:916)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3278:3278:3278) (3512:3512:3512)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT asdata (3800:3800:3800) (4020:4020:4020)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (974:974:974)) + (PORT datab (333:333:333) (409:409:409)) + (PORT datad (945:945:945) (929:929:929)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT asdata (4154:4154:4154) (4333:4333:4333)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (724:724:724) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3328:3328:3328) (3555:3555:3555)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (947:947:947)) + (PORT datab (989:989:989) (968:968:968)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (756:756:756) (802:802:802)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT asdata (4135:4135:4135) (4303:4303:4303)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT asdata (3788:3788:3788) (4010:4010:4010)) + (PORT clrn (1648:1648:1648) (1644:1644:1644)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (951:951:951)) + (PORT datab (335:335:335) (411:411:411)) + (PORT datad (932:932:932) (922:922:922)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (238:238:238) (265:265:265)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[15\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3351:3351:3351) (3567:3567:3567)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[14\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT asdata (4089:4089:4089) (4285:4285:4285)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (577:577:577)) + (PORT datab (590:590:590) (616:616:616)) + (PORT datad (589:589:589) (604:604:604)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[8\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT asdata (3777:3777:3777) (3986:3986:3986)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[9\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3333:3333:3333) (3543:3543:3543)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (625:625:625)) + (PORT datab (590:590:590) (616:616:616)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[11\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT asdata (4421:4421:4421) (4558:4558:4558)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[10\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT asdata (4135:4135:4135) (4322:4322:4322)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (421:421:421)) + (PORT datab (594:594:594) (620:620:620)) + (PORT datad (572:572:572) (592:592:592)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[12\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (744:744:744) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT asdata (3720:3720:3720) (3952:3952:3952)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE tim_ccr1\[13\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|r_tim_ccr1\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (3649:3649:3649) (3856:3856:3856)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|r_tim_ccr1\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1610:1610:1610) (1647:1647:1647)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1645:1645:1645) (1641:1641:1641)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (658:658:658)) + (PORT datab (650:650:650) (655:655:655)) + (PORT datad (295:295:295) (364:364:364)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|Equal1\~9) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE timer_pwm\|tim_ch\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (245:245:245) (276:276:276)) + (PORT datad (808:808:808) (750:750:750)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|tim_ch\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE timer_pwm\|tim_ch\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1613:1613:1613) (1650:1650:1650)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) +) diff --git a/timer_pwm/simulation/modelsim/vsim.wlf b/timer_pwm/simulation/modelsim/vsim.wlf new file mode 100644 index 0000000..b195278 Binary files /dev/null and b/timer_pwm/simulation/modelsim/vsim.wlf differ diff --git a/timer_pwm/testbench/my_pll_tb.v b/timer_pwm/testbench/my_pll_tb.v new file mode 100644 index 0000000..b2ad86a --- /dev/null +++ b/timer_pwm/testbench/my_pll_tb.v @@ -0,0 +1,39 @@ +`timescale 1ns/1ns + +`define clk_period 20 + +module my_pll_tb; + +//source define + reg areset; + reg clk; + wire c0; + wire locked; + +//probe define + + +//instant user module + my_pll my_pll( + .areset(areset), + .inclk0(clk), + .c0(c0), + .locked(locked) + ); + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + //integer i; + + initial begin + areset = 0; + #(`clk_period*20); + #2 areset = 1; + + + $stop; + end + +endmodule diff --git a/timer_pwm/testbench/my_pll_tb.v.bak b/timer_pwm/testbench/my_pll_tb.v.bak new file mode 100644 index 0000000..8158a09 --- /dev/null +++ b/timer_pwm/testbench/my_pll_tb.v.bak @@ -0,0 +1,39 @@ +`timescale 1ns/1ns + +`define clk_period 20 + +module my_pll_tb; + +//source define + reg areset; + reg inclk0; + wire c0; + wire locked; + +//probe define + + +//instant user module +my_pll my_pll( + areset(areset), + inclk0(clk), + c0(c0), + locked(locked) + ); + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + //integer i; + + initial begin + areset = 0; + #(`clk_period*20); + #2 areset = 1; + + + $stop; + end + +endmodule diff --git a/timer_pwm/testbench/timer_pwm_top_tb.v b/timer_pwm/testbench/timer_pwm_top_tb.v new file mode 100644 index 0000000..3b0e921 --- /dev/null +++ b/timer_pwm/testbench/timer_pwm_top_tb.v @@ -0,0 +1,49 @@ +`timescale 1ns/1ns + +`define clk_period 20 + +module timer_pwm_top_tb; + +//source define + wire [1:0] tim_ch; + + reg clk; + reg rst_n; + reg [15:0] tim_arr; + reg [31:0] tim_cr; + reg [15:0] tim_ccr1; + +//probe define + + +//instant user module +timer_pwm_top timer_pwm_top( + .clk(clk), + .rst_n(rst_n), + .tim_cr(tim_cr), + .tim_arr(tim_arr), + .tim_ccr1(tim_ccr1), + .tim_ch(tim_ch) +); + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + //integer i; + + initial begin + rst_n = 0; + + tim_arr = 3999; + tim_ccr1 = 500; + #(`clk_period*200); + #2 rst_n = 1; + #(`clk_period*2000); + tim_ccr1 = 501; + #(`clk_period*2000); + + $stop; + end + +endmodule diff --git a/timer_pwm/testbench/timer_pwm_top_tb.v.bak b/timer_pwm/testbench/timer_pwm_top_tb.v.bak new file mode 100644 index 0000000..dc3fe46 --- /dev/null +++ b/timer_pwm/testbench/timer_pwm_top_tb.v.bak @@ -0,0 +1,48 @@ +`timescale 1ns/1ns + +`define clk_period 20 + +module timer_pwm_top_tb; + +//source define + + +//probe define + + +//instant user module +timer_pwm_top timer_pwm_top( + .clk(clk), + .rst_n(rst_n), + .tim_cr(tim_cr), + .tim_psc(tim_psc), + .tim_arr(tim_arr), + .tim_ccr1(tim_ccr1), + .tim_ccr2(tim_ccr2), + .tim_ccr3(tim_ccr3), + .tim_ccr4(tim_ccr4), + .tim_ch(tim_ch) +); + +//generater clock + initial clk = 1; + always #(`clk_period/2)clk = ~clk; + + //integer i; + + initial begin + rst_n = 0; + tim_psc = 0; + tim_arr = 1499; + tim_ccr1 = 300; + tim_ccr2 = 600; + tim_ccr3 = 900; + tim_ccr4 = 1200 ; + #(`clk_period*20); + #2 rst_n = 1; + + + $stop; + end + +endmodule diff --git a/timer_pwm/timer_pwm.out.sdc b/timer_pwm/timer_pwm.out.sdc new file mode 100644 index 0000000..9939adf --- /dev/null +++ b/timer_pwm/timer_pwm.out.sdc @@ -0,0 +1,107 @@ +## Generated SDC file "timer_pwm.out.sdc" + +## Copyright (C) 2018 Intel Corporation. All rights reserved. +## Your use of Intel Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Intel Program License +## Subscription Agreement, the Intel Quartus Prime License Agreement, +## the Intel FPGA IP License Agreement, or other applicable license +## agreement, including, without limitation, that your use is for +## the sole purpose of programming logic devices manufactured by +## Intel and sold by Intel or its authorized distributors. Please +## refer to the applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus Prime" +## VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" + +## DATE "Sat Nov 03 12:09:36 2018" + +## +## DEVICE "EP4CE10F17C8" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {clk_tim} -period 3.000 -waveform { 0.000 1.500 } [get_ports {clk_tim}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/timer_pwm/timer_pwm.qpf b/timer_pwm/timer_pwm.qpf new file mode 100644 index 0000000..668d585 --- /dev/null +++ b/timer_pwm/timer_pwm.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +# Date created = 11:26:43 November 03, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.0" +DATE = "11:26:43 November 03, 2018" + +# Revisions + +PROJECT_REVISION = "timer_pwm" diff --git a/timer_pwm/timer_pwm.qsf b/timer_pwm/timer_pwm.qsf new file mode 100644 index 0000000..46eb117 --- /dev/null +++ b/timer_pwm/timer_pwm.qsf @@ -0,0 +1,76 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +# Date created = 11:26:43 November 03, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# timer_pwm_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE10F17C8 +set_global_assignment -name TOP_LEVEL_ENTITY timer_pwm_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:26:43 NOVEMBER 03, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_FILE timer_pwm.v +set_global_assignment -name SDC_FILE timer_pwm.out.sdc +set_global_assignment -name QIP_FILE ip/my_pll.qip +set_global_assignment -name VERILOG_FILE testbench/my_pll_tb.v +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH timer_pwm_top_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME my_pll_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id my_pll_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME my_pll_tb -section_id my_pll_tb +set_global_assignment -name VERILOG_FILE rtl/timer_pwm_top.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VERILOG_FILE testbench/timer_pwm_top_tb.v +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/my_pll_tb.v -section_id my_pll_tb +set_global_assignment -name EDA_TEST_BENCH_NAME timer_pwm_top_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id timer_pwm_top_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME timer_pwm_top_tb -section_id timer_pwm_top_tb +set_global_assignment -name EDA_TEST_BENCH_FILE testbench/timer_pwm_top_tb.v -section_id timer_pwm_top_tb +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/timer_pwm/timer_pwm.qws b/timer_pwm/timer_pwm.qws new file mode 100644 index 0000000..703465a Binary files /dev/null and b/timer_pwm/timer_pwm.qws differ diff --git a/timer_pwm/timer_pwm.v b/timer_pwm/timer_pwm.v new file mode 100644 index 0000000..d5e3060 --- /dev/null +++ b/timer_pwm/timer_pwm.v @@ -0,0 +1,59 @@ +module timer_pwm( + + clk_tim, + rst_n, + tim_cr, + tim_arr, + tim_ccr1, + tim_ch + + +); + input clk_tim; + input rst_n; + input [15:0] tim_arr; + input [31:0] tim_cr; + + input [15:0] tim_ccr1; + + + output reg [1:0] tim_ch;//[7:0] {...tim_ch1,tim_ch1n} + + reg [31:0] r_tim_cr; + + reg [15:0] r_tim_cnt; + reg [15:0] r_tim_psc; + reg [15:0] r_tim_arr; + + reg [15:0] r_tim_ccr1; + + reg [15:0] cnt; //整个定时器的计数值 + + always @ (posedge clk_tim)//tim_ch,tim_chn + if(cnt == 0) + tim_ch[1:0] <= 2'b10; + else if(cnt == r_tim_ccr1) + tim_ch[1:0] <= 2'b01; + + always @ (posedge clk_tim or negedge rst_n) + if(!rst_n) + cnt <= 16'd0; + else if(cnt >= r_tim_arr) + cnt <= 16'd0; + else + cnt <= cnt + 1'b1; + + always @ (posedge clk_tim or negedge rst_n) + if(!rst_n) begin + r_tim_arr <= 16'd0; + r_tim_ccr1 <= 16'd0; + r_tim_cr <= 32'd0; + end + else + begin + r_tim_arr <= tim_arr; + r_tim_cr <= tim_cr; + r_tim_ccr1 <= tim_ccr1; + end +endmodule + diff --git a/timer_pwm/timer_pwm.v.bak b/timer_pwm/timer_pwm.v.bak new file mode 100644 index 0000000..2006a38 --- /dev/null +++ b/timer_pwm/timer_pwm.v.bak @@ -0,0 +1,123 @@ +module timer_pwm( + + clk_tim, + rst_n, + tim_cr, + tim_cnt, + tim_psc, + tim_arr, + tim_ccr, + tim_ccr1, + tim_ccr2, + tim_ccr3, + tim_ccr4, + tim_ch + + +); + input clk_tim; + input rst_n; + input [15:0] tim_cnt; + input [15:0] tim_psc; + input [15:0] tim_arr; + input [15:0] tim_ccr; + input [31:0] tim_cr; + + input [15:0] tim_ccr1; + input [15:0] tim_ccr2; + input [15:0] tim_ccr3; + input [15:0] tim_ccr4; + + output reg [7:0] tim_ch;//[7:0] {...tim_ch1,tim_ch1n} + + reg [31:0] r_tim_cr; + + reg [15:0] r_tim_cnt; + reg [15:0] r_tim_psc; + reg [15:0] r_tim_arr; + reg [15:0] r_tim_ccr; + + + reg [15:0] r_tim_ccr1; + reg [15:0] r_tim_ccr2; + reg [15:0] r_tim_ccr3; + reg [15:0] r_tim_ccr4; + + reg [15:0] cnt_psc;//分频计数器，多久计数一次等于clk/( r_tim_psc[15:0]+1)。 + + reg [15:0] cnt; //整个定时器的计数值 + + always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn + if(!rst_n) + tim_ch[1:0] <= 2'b01; + else if(cnt < r_tim_ccr1) + tim_ch[1:0] <= 2'b01; + else + tim_ch[1:0] <= 2'b10; + + always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn + if(!rst_n) + tim_ch[3:2] <= 2'b01; + else if(cnt < r_tim_ccr2) + tim_ch[3:2] <= 2'b01; + else + tim_ch[3:2] <= 2'b10; + + always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn + if(!rst_n) + tim_ch[5:4] <= 2'b01; + else if(cnt < r_tim_ccr3) + tim_ch[5:4] <= 2'b01; + else + tim_ch[5:4] <= 2'b10; + + always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn + if(!rst_n) + tim_ch[7:6] <= 2'b01; + else if(cnt < r_tim_ccr4) + tim_ch[7:6] <= 2'b01; + else + tim_ch[7:6] <= 2'b10; + + always @ (posedge clk_tim or negedge rst_n) + if(!rst_n) + cnt <= 16'd0; + else if(cnt >= tim_arr) + cnt <= 16'd0; + else if(cnt_psc >= r_tim_psc) + cnt <= cnt + 1'b1; + + always @ (posedge clk_tim or negedge rst_n) + if(!rst_n) + cnt_psc <= 16'd0; + else if(cnt_psc >= r_tim_psc) + cnt_psc <= 16'd0; + else + cnt_psc <= cnt_psc + 1'b1; + + always @ (posedge clk_tim or negedge rst_n) + if(!rst_n) begin + r_tim_cnt <= 16'd0; + r_tim_psc <= 16'd0; + r_tim_arr <= 16'd0; + r_tim_ccr <= 16'd0; + r_tim_cr <= 32'd0; + r_tim_ccr1 <= 16'd0; + r_tim_ccr2 <= 16'd0; + r_tim_ccr3 <= 16'd0; + r_tim_ccr4 <= 16'd0; + end + else + begin + r_tim_cnt <= tim_cnt; + r_tim_psc <= tim_psc; + r_tim_arr <= tim_arr; + r_tim_ccr <= tim_ccr; + r_tim_cr <= tim_cr; + r_tim_ccr1 <= tim_ccr1; + r_tim_ccr2 <= tim_ccr2; + r_tim_ccr3 <= tim_ccr3; + r_tim_ccr4 <= tim_ccr4; + end +endmodule + diff --git a/timer_pwm/timer_pwm_nativelink_simulation.rpt b/timer_pwm/timer_pwm_nativelink_simulation.rpt new file mode 100644 index 0000000..16d2b10 --- /dev/null +++ b/timer_pwm/timer_pwm_nativelink_simulation.rpt @@ -0,0 +1,22 @@ +Info: Start Nativelink Simulation process + +========= EDA Simulation Settings ===================== + +Sim Mode : Gate +Family : cycloneive +Quartus root : d:/intelfpga/18.0/quartus/bin64/ +Quartus sim root : d:/intelfpga/18.0/quartus/eda/sim_lib +Simulation Tool : modelsim-altera +Simulation Language : verilog +Simulation Mode : GUI +Sim Output File : timer_pwm_8_1200mv_85c_slow.vo +Sim SDF File : timer_pwm_8_1200mv_85c_v_slow.sdo +Sim dir : simulation\modelsim + +======================================================= + +Info: Starting NativeLink simulation with ModelSim-Altera software +Sourced NativeLink script d:/intelfpga/18.0/quartus/common/tcl/internal/nativelink/modelsim.tcl +Warning: File timer_pwm_run_msim_gate_verilog.do already exists - backing up current file as timer_pwm_run_msim_gate_verilog.do.bak2 +Info: Spawning ModelSim-Altera Simulation software +Info: NativeLink simulation flow was successful