{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1541231015768 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1541231015781 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 03 15:43:35 2018 " "Processing started: Sat Nov 03 15:43:35 2018" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1541231015781 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1541231015781 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off timer_pwm -c timer_pwm " "Command: quartus_eda --read_settings_files=off --write_settings_files=off timer_pwm -c timer_pwm" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1541231015782 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1541231016472 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_8_1200mv_85c_slow.vo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_8_1200mv_85c_slow.vo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016639 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_8_1200mv_0c_slow.vo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_8_1200mv_0c_slow.vo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016673 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_min_1200mv_0c_fast.vo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_min_1200mv_0c_fast.vo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016712 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm.vo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm.vo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016748 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_8_1200mv_85c_v_slow.sdo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_8_1200mv_85c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016773 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_8_1200mv_0c_v_slow.sdo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_8_1200mv_0c_v_slow.sdo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016798 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_min_1200mv_0c_v_fast.sdo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_min_1200mv_0c_v_fast.sdo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016824 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "timer_pwm_v.sdo F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/ simulation " "Generated file timer_pwm_v.sdo in folder \"F:/Code/FPGA/reserve/timer_pwm/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1541231016854 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4660 " "Peak virtual memory: 4660 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1541231016895 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Nov 03 15:43:36 2018 " "Processing ended: Sat Nov 03 15:43:36 2018" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1541231016895 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1541231016895 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1541231016895 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1541231016895 ""}