module timer_pwm(

	clk_tim,
	rst_n,
	tim_cr,
	tim_arr,
	tim_ccr1,
	tim_ch
	

); 
	input clk_tim;
	input rst_n;
	input [15:0] tim_arr;
	input [31:0] tim_cr;
	
	input [15:0] tim_ccr1;

	
	output reg [1:0] tim_ch;//[7:0] {...tim_ch1,tim_ch1n}
	
	reg [31:0] r_tim_cr;
	
	reg [15:0] r_tim_cnt;
	reg [15:0] r_tim_psc;
	reg [15:0] r_tim_arr;
	
	reg [15:0] r_tim_ccr1;
		
	reg [15:0] cnt; //整个定时器的计数值
	
	always @ (posedge clk_tim)//tim_ch,tim_chn
	if(cnt == 0)
		tim_ch[1:0] <= 2'b10;
	else if(cnt == r_tim_ccr1)
		tim_ch[1:0] <= 2'b01;
		
	always @ (posedge clk_tim or negedge rst_n)
	if(!rst_n)
		cnt <= 16'd0;
	else if(cnt >= r_tim_arr)
		cnt <= 16'd0;
	else
		cnt <= cnt + 1'b1;
		
	always @ (posedge clk_tim or negedge rst_n)
	if(!rst_n) begin
      r_tim_arr  <= 16'd0;
		r_tim_ccr1 <= 16'd0;
		r_tim_cr   <= 32'd0; 
	end
	else
	begin
      r_tim_arr  <= tim_arr;
		r_tim_cr   <= tim_cr;
	   r_tim_ccr1 <= tim_ccr1;
	end
endmodule