module timer_pwm(

	clk_tim,
	rst_n,
	tim_cr,
	tim_cnt,
	tim_psc,
	tim_arr,
	tim_ccr,
	tim_ccr1,
	tim_ccr2,
	tim_ccr3,
	tim_ccr4,
	tim_ch
	

); 
	input clk_tim;
	input rst_n;
	input [15:0] tim_cnt;
	input [15:0] tim_psc;
	input [15:0] tim_arr;
	input [15:0] tim_ccr;
	input [31:0] tim_cr;
	
	input [15:0] tim_ccr1;
	input [15:0] tim_ccr2;
	input [15:0] tim_ccr3;
	input [15:0] tim_ccr4;
	
	output reg [7:0] tim_ch;//[7:0] {...tim_ch1,tim_ch1n}
	
	reg [31:0] r_tim_cr;
	
	reg [15:0] r_tim_cnt;
	reg [15:0] r_tim_psc;
	reg [15:0] r_tim_arr;
	reg [15:0] r_tim_ccr;

	
	reg [15:0] r_tim_ccr1;
	reg [15:0] r_tim_ccr2;
	reg [15:0] r_tim_ccr3;
	reg [15:0] r_tim_ccr4;
	
	reg [15:0] cnt_psc;//分频计数器，多久计数一次等于clk/( r_tim_psc[15:0]+1)。
	
	reg [15:0] cnt; //整个定时器的计数值
	
	always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn
	if(!rst_n)
		tim_ch[1:0] <= 2'b01;
	else if(cnt < r_tim_ccr1)
		tim_ch[1:0] <= 2'b01;
	else
		tim_ch[1:0] <= 2'b10;
		
	always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn
	if(!rst_n)
		tim_ch[3:2] <= 2'b01;
	else if(cnt < r_tim_ccr2)
		tim_ch[3:2] <= 2'b01;
	else
		tim_ch[3:2] <= 2'b10;
		
	always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn
	if(!rst_n)
		tim_ch[5:4] <= 2'b01;
	else if(cnt < r_tim_ccr3)
		tim_ch[5:4] <= 2'b01;
	else
		tim_ch[5:4] <= 2'b10;
		
	always @ (posedge clk_tim or negedge rst_n)//tim_ch,tim_chn
	if(!rst_n)
		tim_ch[7:6] <= 2'b01;
	else if(cnt < r_tim_ccr4)
		tim_ch[7:6] <= 2'b01;
	else
		tim_ch[7:6] <= 2'b10;
	
	always @ (posedge clk_tim or negedge rst_n)
	if(!rst_n)
		cnt <= 16'd0;
	else if(cnt >= tim_arr)
		cnt <= 16'd0;
	else if(cnt_psc >= r_tim_psc)
		cnt <= cnt + 1'b1;
		
	always @ (posedge clk_tim or negedge rst_n)
	if(!rst_n)
		cnt_psc <= 16'd0;
	else if(cnt_psc >= r_tim_psc) 
		cnt_psc <= 16'd0;
	else
		cnt_psc <= cnt_psc + 1'b1;
	
	always @ (posedge clk_tim or negedge rst_n)
	if(!rst_n) begin
		r_tim_cnt  <= 16'd0;
        r_tim_psc  <= 16'd0;
        r_tim_arr  <= 16'd0;
		r_tim_ccr  <= 16'd0;
		r_tim_cr   <= 32'd0;
		r_tim_ccr1 <= 16'd0;
		r_tim_ccr2 <= 16'd0;
		r_tim_ccr3 <= 16'd0;
		r_tim_ccr4 <= 16'd0; 
	end
	else
	begin
		r_tim_cnt  <= tim_cnt;
        r_tim_psc  <= tim_psc;
        r_tim_arr  <= tim_arr;
		r_tim_ccr  <= tim_ccr;
		r_tim_cr   <= tim_cr;
	    r_tim_ccr1 <= tim_ccr1;
		r_tim_ccr2 <= tim_ccr2;
		r_tim_ccr3 <= tim_ccr3;
		r_tim_ccr4 <= tim_ccr4;
	end
endmodule