148 lines
11 KiB
Plaintext
148 lines
11 KiB
Plaintext
Flow report for dpwm
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Mon Nov 05 21:21:20 2018
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Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Flow Summary
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3. Flow Settings
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4. Flow Non-Default Global Settings
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5. Flow Elapsed Time
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6. Flow OS Summary
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7. Flow Log
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8. Flow Messages
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9. Flow Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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+--------------------------------------------------------------------------------------+
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; Flow Summary ;
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+------------------------------------+-------------------------------------------------+
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; Flow Status ; Successful - Mon Nov 05 21:21:20 2018 ;
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; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ;
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; Revision Name ; dpwm ;
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; Top-level Entity Name ; dpwm_top ;
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; Family ; Cyclone IV E ;
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; Device ; EP4CE10F17C8 ;
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; Timing Models ; Final ;
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; Total logic elements ; 29 / 10,320 ( < 1 % ) ;
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; Total combinational functions ; 29 / 10,320 ( < 1 % ) ;
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; Dedicated logic registers ; 11 / 10,320 ( < 1 % ) ;
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; Total registers ; 11 ;
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; Total pins ; 19 / 180 ( 11 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 0 / 423,936 ( 0 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 46 ( 0 % ) ;
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; Total PLLs ; 1 / 2 ( 50 % ) ;
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+------------------------------------+-------------------------------------------------+
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+-----------------------------------------+
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; Flow Settings ;
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+-------------------+---------------------+
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; Option ; Setting ;
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+-------------------+---------------------+
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; Start date & time ; 11/05/2018 21:20:43 ;
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; Main task ; Compilation ;
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; Revision Name ; dpwm ;
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+-------------------+---------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------+
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; Flow Non-Default Global Settings ;
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+----------------------------------------------+----------------------------------------+---------------+-------------+----------------+
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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+----------------------------------------------+----------------------------------------+---------------+-------------+----------------+
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; COMPILER_SIGNATURE_ID ; 93383153531551.154142404319612 ; -- ; -- ; -- ;
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; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; dpwm_top_tb ;
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; EDA_DESIGN_INSTANCE_NAME ; NA ; -- ; -- ; dpwm_tb ;
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; EDA_NATIVELINK_SIMULATION_TEST_BENCH ; dpwm_top_tb ; -- ; -- ; eda_simulation ;
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; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
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; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
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; EDA_TEST_BENCH_ENABLE_STATUS ; TEST_BENCH_MODE ; -- ; -- ; eda_simulation ;
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; EDA_TEST_BENCH_FILE ; testbench/dpwm_top_tb.v ; -- ; -- ; dpwm_top_tb ;
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; EDA_TEST_BENCH_FILE ; testbench/dpwm_tb.v ; -- ; -- ; dpwm_tb ;
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; EDA_TEST_BENCH_FILE ; rtl/dpwm.v ; -- ; -- ; dpwm_tb ;
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; EDA_TEST_BENCH_FILE ; ip/my_pll.qip ; -- ; -- ; dpwm_tb ;
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; EDA_TEST_BENCH_MODULE_NAME ; dpwm_top_tb ; -- ; -- ; dpwm_top_tb ;
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; EDA_TEST_BENCH_MODULE_NAME ; dpwm_tb ; -- ; -- ; dpwm_tb ;
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; EDA_TEST_BENCH_NAME ; dpwm_tb ; -- ; -- ; eda_simulation ;
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; EDA_TEST_BENCH_NAME ; dpwm_top_tb ; -- ; -- ; eda_simulation ;
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; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
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; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
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; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
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; MISC_FILE ; ip/my_pll_bb.v ; -- ; -- ; -- ;
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; MISC_FILE ; ip/my_pll.ppf ; -- ; -- ; -- ;
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; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; dpwm_top ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; dpwm_top ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; dpwm_top ; Top ;
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; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
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; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
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; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
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; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; On ; Auto ; -- ; -- ;
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; TOP_LEVEL_ENTITY ; dpwm_top ; dpwm ; -- ; -- ;
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+----------------------------------------------+----------------------------------------+---------------+-------------+----------------+
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+--------------------------------------------------------------------------------------------------------------------------+
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; Flow Elapsed Time ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Analysis & Synthesis ; 00:00:19 ; 1.0 ; 4790 MB ; 00:00:43 ;
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; Fitter ; 00:00:06 ; 1.0 ; 5562 MB ; 00:00:08 ;
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; Assembler ; 00:00:02 ; 1.0 ; 4693 MB ; 00:00:02 ;
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; Timing Analyzer ; 00:00:02 ; 1.0 ; 4776 MB ; 00:00:03 ;
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; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4658 MB ; 00:00:02 ;
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; Total ; 00:00:30 ; -- ; -- ; 00:00:58 ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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+------------------------------------------------------------------------------------+
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; Flow OS Summary ;
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+----------------------+------------------+------------+------------+----------------+
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; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
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+----------------------+------------------+------------+------------+----------------+
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; Analysis & Synthesis ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ;
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; Fitter ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ;
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; Assembler ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ;
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; Timing Analyzer ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ;
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; EDA Netlist Writer ; DESKTOP-U8FBMPE ; Windows 10 ; 10.0 ; x86_64 ;
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+----------------------+------------------+------------+------------+----------------+
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------------
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; Flow Log ;
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------------
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quartus_map --read_settings_files=on --write_settings_files=off dpwm -c dpwm
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quartus_fit --read_settings_files=off --write_settings_files=off dpwm -c dpwm
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quartus_asm --read_settings_files=off --write_settings_files=off dpwm -c dpwm
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quartus_sta dpwm -c dpwm
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quartus_eda --read_settings_files=off --write_settings_files=off dpwm -c dpwm
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