1225 lines
39 KiB
Plaintext
1225 lines
39 KiB
Plaintext
// Copyright (C) 2018 Intel Corporation. All rights reserved.
|
|
// Your use of Intel Corporation's design tools, logic functions
|
|
// and other software and tools, and its AMPP partner logic
|
|
// functions, and any output files from any of the foregoing
|
|
// (including device programming or simulation files), and any
|
|
// associated documentation or information are expressly subject
|
|
// to the terms and conditions of the Intel Program License
|
|
// Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
// the Intel FPGA IP License Agreement, or other applicable license
|
|
// agreement, including, without limitation, that your use is for
|
|
// the sole purpose of programming logic devices manufactured by
|
|
// Intel and sold by Intel or its authorized distributors. Please
|
|
// refer to the applicable agreement for further details.
|
|
|
|
// VENDOR "Altera"
|
|
// PROGRAM "Quartus Prime"
|
|
// VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition"
|
|
|
|
// DATE "11/05/2018 21:21:20"
|
|
|
|
//
|
|
// Device: Altera EP4CE10F17C8 Package FBGA256
|
|
//
|
|
|
|
//
|
|
// This Verilog file should be used for ModelSim-Altera (Verilog) only
|
|
//
|
|
|
|
`timescale 1 ps/ 1 ps
|
|
|
|
module dpwm_top (
|
|
clk,
|
|
rst_n,
|
|
dpid,
|
|
delay_out,
|
|
pwm_out);
|
|
input clk;
|
|
input rst_n;
|
|
input [7:0] dpid;
|
|
output [7:0] delay_out;
|
|
output pwm_out;
|
|
|
|
// Design Ports Information
|
|
// delay_out[0] => Location: PIN_G16, I/O Standard: 2.5 V, Current Strength: Default
|
|
// delay_out[1] => Location: PIN_G15, I/O Standard: 2.5 V, Current Strength: Default
|
|
// delay_out[2] => Location: PIN_F13, I/O Standard: 2.5 V, Current Strength: Default
|
|
// delay_out[3] => Location: PIN_F15, I/O Standard: 2.5 V, Current Strength: Default
|
|
// delay_out[4] => Location: PIN_A10, I/O Standard: 2.5 V, Current Strength: Default
|
|
// delay_out[5] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default
|
|
// delay_out[6] => Location: PIN_A14, I/O Standard: 2.5 V, Current Strength: Default
|
|
// delay_out[7] => Location: PIN_R10, I/O Standard: 2.5 V, Current Strength: Default
|
|
// pwm_out => Location: PIN_K16, I/O Standard: 2.5 V, Current Strength: Default
|
|
// clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default
|
|
// dpid[7] => Location: PIN_E16, I/O Standard: 2.5 V, Current Strength: Default
|
|
// dpid[6] => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default
|
|
// dpid[5] => Location: PIN_K15, I/O Standard: 2.5 V, Current Strength: Default
|
|
// dpid[4] => Location: PIN_J13, I/O Standard: 2.5 V, Current Strength: Default
|
|
// dpid[3] => Location: PIN_J16, I/O Standard: 2.5 V, Current Strength: Default
|
|
// dpid[2] => Location: PIN_J15, I/O Standard: 2.5 V, Current Strength: Default
|
|
// dpid[1] => Location: PIN_J12, I/O Standard: 2.5 V, Current Strength: Default
|
|
// dpid[0] => Location: PIN_J14, I/O Standard: 2.5 V, Current Strength: Default
|
|
// rst_n => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default
|
|
|
|
|
|
wire gnd;
|
|
wire vcc;
|
|
wire unknown;
|
|
|
|
assign gnd = 1'b0;
|
|
assign vcc = 1'b1;
|
|
assign unknown = 1'bx;
|
|
|
|
tri1 devclrn;
|
|
tri1 devpor;
|
|
tri1 devoe;
|
|
// synopsys translate_off
|
|
initial $sdf_annotate("dpwm_8_1200mv_85c_v_slow.sdo");
|
|
// synopsys translate_on
|
|
|
|
wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
|
|
wire \~ALTERA_ASDO_DATA1~~padout ;
|
|
wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
|
|
wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
|
|
wire \~ALTERA_DCLK~~padout ;
|
|
wire \~ALTERA_DATA0~~ibuf_o ;
|
|
wire \~ALTERA_DATA0~~padout ;
|
|
wire \~ALTERA_nCEO~~padout ;
|
|
wire \~ALTERA_DCLK~~obuf_o ;
|
|
wire \~ALTERA_nCEO~~obuf_o ;
|
|
wire \clk~input_o ;
|
|
wire \clk~inputclkctrl_outclk ;
|
|
wire \rst_n~input_o ;
|
|
wire \rst_n~inputclkctrl_outclk ;
|
|
wire \my_pll|altpll_component|auto_generated|wire_pll1_fbout ;
|
|
wire \my_pll|altpll_component|auto_generated|wire_pll1_locked ;
|
|
wire \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ;
|
|
wire \my_pll|altpll_component|auto_generated|pll_lock_sync~q ;
|
|
wire \my_pll|altpll_component|auto_generated|locked~combout ;
|
|
wire \my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ;
|
|
wire \dpwm|out_8bit[0]~0_combout ;
|
|
wire \dpwm|Add0~0_combout ;
|
|
wire \dpwm|Add0~1 ;
|
|
wire \dpwm|Add0~2_combout ;
|
|
wire \dpwm|Add0~3 ;
|
|
wire \dpwm|Add0~4_combout ;
|
|
wire \dpwm|Add0~5 ;
|
|
wire \dpwm|Add0~6_combout ;
|
|
wire \dpwm|Add0~7 ;
|
|
wire \dpwm|Add0~8_combout ;
|
|
wire \dpwm|Add0~9 ;
|
|
wire \dpwm|Add0~10_combout ;
|
|
wire \dpwm|Add0~11 ;
|
|
wire \dpwm|Add0~12_combout ;
|
|
wire \dpid[7]~input_o ;
|
|
wire \dpid[6]~input_o ;
|
|
wire \dpid[5]~input_o ;
|
|
wire \dpid[4]~input_o ;
|
|
wire \dpid[3]~input_o ;
|
|
wire \dpid[2]~input_o ;
|
|
wire \dpid[1]~input_o ;
|
|
wire \dpid[0]~input_o ;
|
|
wire \dpwm|LessThan0~1_cout ;
|
|
wire \dpwm|LessThan0~3_cout ;
|
|
wire \dpwm|LessThan0~5_cout ;
|
|
wire \dpwm|LessThan0~7_cout ;
|
|
wire \dpwm|LessThan0~9_cout ;
|
|
wire \dpwm|LessThan0~11_cout ;
|
|
wire \dpwm|LessThan0~13_cout ;
|
|
wire \dpwm|LessThan0~14_combout ;
|
|
wire \dpwm|delay0~combout ;
|
|
wire \dpwm|de7~combout ;
|
|
wire \dpwm|delay1~combout ;
|
|
wire \dpwm|de6~combout ;
|
|
wire \dpwm|delay2~combout ;
|
|
wire \dpwm|de5~combout ;
|
|
wire \dpwm|delay3~combout ;
|
|
wire \dpwm|de4~combout ;
|
|
wire \dpwm|bit_high_syn~0_combout ;
|
|
wire \dpwm|bit_high_syn~q ;
|
|
wire \dpwm|n_bit_high_syn~0_combout ;
|
|
wire \dpwm|n_bit_high_syn~q ;
|
|
wire \dpwm|pwm_out~combout ;
|
|
wire [4:0] \my_pll|altpll_component|auto_generated|wire_pll1_clk ;
|
|
wire [7:0] \dpwm|out_8bit ;
|
|
|
|
wire [4:0] \my_pll|altpll_component|auto_generated|pll1_CLK_bus ;
|
|
|
|
assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [0] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [0];
|
|
assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [1] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [1];
|
|
assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [2] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [2];
|
|
assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [3] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [3];
|
|
assign \my_pll|altpll_component|auto_generated|wire_pll1_clk [4] = \my_pll|altpll_component|auto_generated|pll1_CLK_bus [4];
|
|
|
|
// Location: IOOBUF_X34_Y17_N23
|
|
cycloneive_io_obuf \delay_out[0]~output (
|
|
.i(\dpwm|de7~combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(delay_out[0]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \delay_out[0]~output .bus_hold = "false";
|
|
defparam \delay_out[0]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X34_Y17_N16
|
|
cycloneive_io_obuf \delay_out[1]~output (
|
|
.i(\dpwm|de6~combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(delay_out[1]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \delay_out[1]~output .bus_hold = "false";
|
|
defparam \delay_out[1]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X34_Y17_N2
|
|
cycloneive_io_obuf \delay_out[2]~output (
|
|
.i(\dpwm|de5~combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(delay_out[2]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \delay_out[2]~output .bus_hold = "false";
|
|
defparam \delay_out[2]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X34_Y18_N16
|
|
cycloneive_io_obuf \delay_out[3]~output (
|
|
.i(\dpwm|de4~combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(delay_out[3]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \delay_out[3]~output .bus_hold = "false";
|
|
defparam \delay_out[3]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X21_Y24_N9
|
|
cycloneive_io_obuf \delay_out[4]~output (
|
|
.i(gnd),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(delay_out[4]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \delay_out[4]~output .bus_hold = "false";
|
|
defparam \delay_out[4]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X3_Y24_N23
|
|
cycloneive_io_obuf \delay_out[5]~output (
|
|
.i(gnd),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(delay_out[5]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \delay_out[5]~output .bus_hold = "false";
|
|
defparam \delay_out[5]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X28_Y24_N2
|
|
cycloneive_io_obuf \delay_out[6]~output (
|
|
.i(gnd),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(delay_out[6]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \delay_out[6]~output .bus_hold = "false";
|
|
defparam \delay_out[6]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X21_Y0_N9
|
|
cycloneive_io_obuf \delay_out[7]~output (
|
|
.i(gnd),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(delay_out[7]),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \delay_out[7]~output .bus_hold = "false";
|
|
defparam \delay_out[7]~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOOBUF_X34_Y9_N16
|
|
cycloneive_io_obuf \pwm_out~output (
|
|
.i(\dpwm|pwm_out~combout ),
|
|
.oe(vcc),
|
|
.seriesterminationcontrol(16'b0000000000000000),
|
|
.devoe(devoe),
|
|
.o(pwm_out),
|
|
.obar());
|
|
// synopsys translate_off
|
|
defparam \pwm_out~output .bus_hold = "false";
|
|
defparam \pwm_out~output .open_drain_output = "false";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X0_Y11_N8
|
|
cycloneive_io_ibuf \clk~input (
|
|
.i(clk),
|
|
.ibar(gnd),
|
|
.o(\clk~input_o ));
|
|
// synopsys translate_off
|
|
defparam \clk~input .bus_hold = "false";
|
|
defparam \clk~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: CLKCTRL_G2
|
|
cycloneive_clkctrl \clk~inputclkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\clk~input_o }),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\clk~inputclkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \clk~inputclkctrl .clock_type = "global clock";
|
|
defparam \clk~inputclkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X0_Y11_N15
|
|
cycloneive_io_ibuf \rst_n~input (
|
|
.i(rst_n),
|
|
.ibar(gnd),
|
|
.o(\rst_n~input_o ));
|
|
// synopsys translate_off
|
|
defparam \rst_n~input .bus_hold = "false";
|
|
defparam \rst_n~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: CLKCTRL_G4
|
|
cycloneive_clkctrl \rst_n~inputclkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\rst_n~input_o }),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\rst_n~inputclkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \rst_n~inputclkctrl .clock_type = "global clock";
|
|
defparam \rst_n~inputclkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: PLL_1
|
|
cycloneive_pll \my_pll|altpll_component|auto_generated|pll1 (
|
|
.areset(!\rst_n~inputclkctrl_outclk ),
|
|
.pfdena(vcc),
|
|
.fbin(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ),
|
|
.phaseupdown(gnd),
|
|
.phasestep(gnd),
|
|
.scandata(gnd),
|
|
.scanclk(gnd),
|
|
.scanclkena(vcc),
|
|
.configupdate(gnd),
|
|
.clkswitch(gnd),
|
|
.inclk({gnd,\clk~input_o }),
|
|
.phasecounterselect(3'b000),
|
|
.phasedone(),
|
|
.scandataout(),
|
|
.scandone(),
|
|
.activeclock(),
|
|
.locked(\my_pll|altpll_component|auto_generated|wire_pll1_locked ),
|
|
.vcooverrange(),
|
|
.vcounderrange(),
|
|
.fbout(\my_pll|altpll_component|auto_generated|wire_pll1_fbout ),
|
|
.clk(\my_pll|altpll_component|auto_generated|pll1_CLK_bus ),
|
|
.clkbad());
|
|
// synopsys translate_off
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .auto_settings = "false";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .bandwidth_type = "medium";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c0_high = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c0_initial = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c0_low = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c0_mode = "bypass";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c0_ph = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c1_high = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c1_initial = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c1_low = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c1_mode = "bypass";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c1_ph = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c2_high = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c2_initial = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c2_low = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c2_mode = "bypass";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c2_ph = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c3_high = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c3_initial = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c3_low = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c3_mode = "bypass";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c3_ph = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c4_high = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c4_initial = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c4_low = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c4_mode = "bypass";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c4_ph = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_counter = "unused";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_divide_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_multiply_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_counter = "unused";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_divide_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_counter = "unused";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_divide_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_counter = "unused";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_divide_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_counter = "unused";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_divide_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .m = 12;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .m_initial = 1;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .m_ph = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .n = 1;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .operation_mode = "no compensation";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_max = 200000;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .pfd_min = 3076;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .simulation_type = "timing";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .switch_over_type = "auto";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .vco_center = 1538;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .vco_divide_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto";
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .vco_max = 3333;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .vco_min = 1538;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .vco_multiply_by = 0;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208;
|
|
defparam \my_pll|altpll_component|auto_generated|pll1 .vco_post_scale = 2;
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y4_N28
|
|
cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder (
|
|
// Equation(s):
|
|
// \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF;
|
|
defparam \my_pll|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X1_Y4_N29
|
|
dffeas \my_pll|altpll_component|auto_generated|pll_lock_sync (
|
|
.clk(\my_pll|altpll_component|auto_generated|wire_pll1_locked ),
|
|
.d(\my_pll|altpll_component|auto_generated|pll_lock_sync~feeder_combout ),
|
|
.asdata(vcc),
|
|
.clrn(\rst_n~inputclkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true";
|
|
defparam \my_pll|altpll_component|auto_generated|pll_lock_sync .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X1_Y4_N14
|
|
cycloneive_lcell_comb \my_pll|altpll_component|auto_generated|locked (
|
|
// Equation(s):
|
|
// \my_pll|altpll_component|auto_generated|locked~combout = (!\my_pll|altpll_component|auto_generated|pll_lock_sync~q ) # (!\my_pll|altpll_component|auto_generated|wire_pll1_locked )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\my_pll|altpll_component|auto_generated|wire_pll1_locked ),
|
|
.datad(\my_pll|altpll_component|auto_generated|pll_lock_sync~q ),
|
|
.cin(gnd),
|
|
.combout(\my_pll|altpll_component|auto_generated|locked~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \my_pll|altpll_component|auto_generated|locked .lut_mask = 16'h0FFF;
|
|
defparam \my_pll|altpll_component|auto_generated|locked .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: CLKCTRL_G1
|
|
cycloneive_clkctrl \my_pll|altpll_component|auto_generated|locked~clkctrl (
|
|
.ena(vcc),
|
|
.inclk({vcc,vcc,vcc,\my_pll|altpll_component|auto_generated|locked~combout }),
|
|
.clkselect(2'b00),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.outclk(\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ));
|
|
// synopsys translate_off
|
|
defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .clock_type = "global clock";
|
|
defparam \my_pll|altpll_component|auto_generated|locked~clkctrl .ena_register_mode = "none";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X33_Y12_N31
|
|
dffeas \dpwm|out_8bit[7] (
|
|
.clk(\clk~inputclkctrl_outclk ),
|
|
.d(\dpwm|Add0~12_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\dpwm|out_8bit [7]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \dpwm|out_8bit[7] .is_wysiwyg = "true";
|
|
defparam \dpwm|out_8bit[7] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N16
|
|
cycloneive_lcell_comb \dpwm|out_8bit[0]~0 (
|
|
// Equation(s):
|
|
// \dpwm|out_8bit[0]~0_combout = !\dpwm|out_8bit [0]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\dpwm|out_8bit [0]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\dpwm|out_8bit[0]~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|out_8bit[0]~0 .lut_mask = 16'h0F0F;
|
|
defparam \dpwm|out_8bit[0]~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X33_Y12_N17
|
|
dffeas \dpwm|out_8bit[0] (
|
|
.clk(\clk~inputclkctrl_outclk ),
|
|
.d(\dpwm|out_8bit[0]~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\dpwm|out_8bit [0]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \dpwm|out_8bit[0] .is_wysiwyg = "true";
|
|
defparam \dpwm|out_8bit[0] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N18
|
|
cycloneive_lcell_comb \dpwm|Add0~0 (
|
|
// Equation(s):
|
|
// \dpwm|Add0~0_combout = (\dpwm|out_8bit [1] & (\dpwm|out_8bit [0] $ (VCC))) # (!\dpwm|out_8bit [1] & (\dpwm|out_8bit [0] & VCC))
|
|
// \dpwm|Add0~1 = CARRY((\dpwm|out_8bit [1] & \dpwm|out_8bit [0]))
|
|
|
|
.dataa(\dpwm|out_8bit [1]),
|
|
.datab(\dpwm|out_8bit [0]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(gnd),
|
|
.combout(\dpwm|Add0~0_combout ),
|
|
.cout(\dpwm|Add0~1 ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|Add0~0 .lut_mask = 16'h6688;
|
|
defparam \dpwm|Add0~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X33_Y12_N19
|
|
dffeas \dpwm|out_8bit[1] (
|
|
.clk(\clk~inputclkctrl_outclk ),
|
|
.d(\dpwm|Add0~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\dpwm|out_8bit [1]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \dpwm|out_8bit[1] .is_wysiwyg = "true";
|
|
defparam \dpwm|out_8bit[1] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N20
|
|
cycloneive_lcell_comb \dpwm|Add0~2 (
|
|
// Equation(s):
|
|
// \dpwm|Add0~2_combout = (\dpwm|out_8bit [2] & (!\dpwm|Add0~1 )) # (!\dpwm|out_8bit [2] & ((\dpwm|Add0~1 ) # (GND)))
|
|
// \dpwm|Add0~3 = CARRY((!\dpwm|Add0~1 ) # (!\dpwm|out_8bit [2]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\dpwm|out_8bit [2]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\dpwm|Add0~1 ),
|
|
.combout(\dpwm|Add0~2_combout ),
|
|
.cout(\dpwm|Add0~3 ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|Add0~2 .lut_mask = 16'h3C3F;
|
|
defparam \dpwm|Add0~2 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X33_Y12_N21
|
|
dffeas \dpwm|out_8bit[2] (
|
|
.clk(\clk~inputclkctrl_outclk ),
|
|
.d(\dpwm|Add0~2_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\dpwm|out_8bit [2]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \dpwm|out_8bit[2] .is_wysiwyg = "true";
|
|
defparam \dpwm|out_8bit[2] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N22
|
|
cycloneive_lcell_comb \dpwm|Add0~4 (
|
|
// Equation(s):
|
|
// \dpwm|Add0~4_combout = (\dpwm|out_8bit [3] & (\dpwm|Add0~3 $ (GND))) # (!\dpwm|out_8bit [3] & (!\dpwm|Add0~3 & VCC))
|
|
// \dpwm|Add0~5 = CARRY((\dpwm|out_8bit [3] & !\dpwm|Add0~3 ))
|
|
|
|
.dataa(\dpwm|out_8bit [3]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\dpwm|Add0~3 ),
|
|
.combout(\dpwm|Add0~4_combout ),
|
|
.cout(\dpwm|Add0~5 ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|Add0~4 .lut_mask = 16'hA50A;
|
|
defparam \dpwm|Add0~4 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X33_Y12_N23
|
|
dffeas \dpwm|out_8bit[3] (
|
|
.clk(\clk~inputclkctrl_outclk ),
|
|
.d(\dpwm|Add0~4_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\dpwm|out_8bit [3]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \dpwm|out_8bit[3] .is_wysiwyg = "true";
|
|
defparam \dpwm|out_8bit[3] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N24
|
|
cycloneive_lcell_comb \dpwm|Add0~6 (
|
|
// Equation(s):
|
|
// \dpwm|Add0~6_combout = (\dpwm|out_8bit [4] & (!\dpwm|Add0~5 )) # (!\dpwm|out_8bit [4] & ((\dpwm|Add0~5 ) # (GND)))
|
|
// \dpwm|Add0~7 = CARRY((!\dpwm|Add0~5 ) # (!\dpwm|out_8bit [4]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\dpwm|out_8bit [4]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\dpwm|Add0~5 ),
|
|
.combout(\dpwm|Add0~6_combout ),
|
|
.cout(\dpwm|Add0~7 ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|Add0~6 .lut_mask = 16'h3C3F;
|
|
defparam \dpwm|Add0~6 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X33_Y12_N25
|
|
dffeas \dpwm|out_8bit[4] (
|
|
.clk(\clk~inputclkctrl_outclk ),
|
|
.d(\dpwm|Add0~6_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\dpwm|out_8bit [4]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \dpwm|out_8bit[4] .is_wysiwyg = "true";
|
|
defparam \dpwm|out_8bit[4] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N26
|
|
cycloneive_lcell_comb \dpwm|Add0~8 (
|
|
// Equation(s):
|
|
// \dpwm|Add0~8_combout = (\dpwm|out_8bit [5] & (\dpwm|Add0~7 $ (GND))) # (!\dpwm|out_8bit [5] & (!\dpwm|Add0~7 & VCC))
|
|
// \dpwm|Add0~9 = CARRY((\dpwm|out_8bit [5] & !\dpwm|Add0~7 ))
|
|
|
|
.dataa(\dpwm|out_8bit [5]),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\dpwm|Add0~7 ),
|
|
.combout(\dpwm|Add0~8_combout ),
|
|
.cout(\dpwm|Add0~9 ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|Add0~8 .lut_mask = 16'hA50A;
|
|
defparam \dpwm|Add0~8 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X33_Y12_N27
|
|
dffeas \dpwm|out_8bit[5] (
|
|
.clk(\clk~inputclkctrl_outclk ),
|
|
.d(\dpwm|Add0~8_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\dpwm|out_8bit [5]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \dpwm|out_8bit[5] .is_wysiwyg = "true";
|
|
defparam \dpwm|out_8bit[5] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N28
|
|
cycloneive_lcell_comb \dpwm|Add0~10 (
|
|
// Equation(s):
|
|
// \dpwm|Add0~10_combout = (\dpwm|out_8bit [6] & (!\dpwm|Add0~9 )) # (!\dpwm|out_8bit [6] & ((\dpwm|Add0~9 ) # (GND)))
|
|
// \dpwm|Add0~11 = CARRY((!\dpwm|Add0~9 ) # (!\dpwm|out_8bit [6]))
|
|
|
|
.dataa(gnd),
|
|
.datab(\dpwm|out_8bit [6]),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\dpwm|Add0~9 ),
|
|
.combout(\dpwm|Add0~10_combout ),
|
|
.cout(\dpwm|Add0~11 ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|Add0~10 .lut_mask = 16'h3C3F;
|
|
defparam \dpwm|Add0~10 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X33_Y12_N29
|
|
dffeas \dpwm|out_8bit[6] (
|
|
.clk(\clk~inputclkctrl_outclk ),
|
|
.d(\dpwm|Add0~10_combout ),
|
|
.asdata(vcc),
|
|
.clrn(!\my_pll|altpll_component|auto_generated|locked~clkctrl_outclk ),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\dpwm|out_8bit [6]),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \dpwm|out_8bit[6] .is_wysiwyg = "true";
|
|
defparam \dpwm|out_8bit[6] .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N30
|
|
cycloneive_lcell_comb \dpwm|Add0~12 (
|
|
// Equation(s):
|
|
// \dpwm|Add0~12_combout = \dpwm|Add0~11 $ (!\dpwm|out_8bit [7])
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\dpwm|out_8bit [7]),
|
|
.cin(\dpwm|Add0~11 ),
|
|
.combout(\dpwm|Add0~12_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|Add0~12 .lut_mask = 16'hF00F;
|
|
defparam \dpwm|Add0~12 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X34_Y12_N8
|
|
cycloneive_io_ibuf \dpid[7]~input (
|
|
.i(dpid[7]),
|
|
.ibar(gnd),
|
|
.o(\dpid[7]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \dpid[7]~input .bus_hold = "false";
|
|
defparam \dpid[7]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X34_Y12_N1
|
|
cycloneive_io_ibuf \dpid[6]~input (
|
|
.i(dpid[6]),
|
|
.ibar(gnd),
|
|
.o(\dpid[6]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \dpid[6]~input .bus_hold = "false";
|
|
defparam \dpid[6]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X34_Y9_N8
|
|
cycloneive_io_ibuf \dpid[5]~input (
|
|
.i(dpid[5]),
|
|
.ibar(gnd),
|
|
.o(\dpid[5]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \dpid[5]~input .bus_hold = "false";
|
|
defparam \dpid[5]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X34_Y11_N1
|
|
cycloneive_io_ibuf \dpid[4]~input (
|
|
.i(dpid[4]),
|
|
.ibar(gnd),
|
|
.o(\dpid[4]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \dpid[4]~input .bus_hold = "false";
|
|
defparam \dpid[4]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X34_Y9_N1
|
|
cycloneive_io_ibuf \dpid[3]~input (
|
|
.i(dpid[3]),
|
|
.ibar(gnd),
|
|
.o(\dpid[3]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \dpid[3]~input .bus_hold = "false";
|
|
defparam \dpid[3]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X34_Y10_N8
|
|
cycloneive_io_ibuf \dpid[2]~input (
|
|
.i(dpid[2]),
|
|
.ibar(gnd),
|
|
.o(\dpid[2]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \dpid[2]~input .bus_hold = "false";
|
|
defparam \dpid[2]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X34_Y11_N8
|
|
cycloneive_io_ibuf \dpid[1]~input (
|
|
.i(dpid[1]),
|
|
.ibar(gnd),
|
|
.o(\dpid[1]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \dpid[1]~input .bus_hold = "false";
|
|
defparam \dpid[1]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: IOIBUF_X34_Y10_N1
|
|
cycloneive_io_ibuf \dpid[0]~input (
|
|
.i(dpid[0]),
|
|
.ibar(gnd),
|
|
.o(\dpid[0]~input_o ));
|
|
// synopsys translate_off
|
|
defparam \dpid[0]~input .bus_hold = "false";
|
|
defparam \dpid[0]~input .simulate_z_as = "z";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N0
|
|
cycloneive_lcell_comb \dpwm|LessThan0~1 (
|
|
// Equation(s):
|
|
// \dpwm|LessThan0~1_cout = CARRY((\dpwm|out_8bit [0] & \dpid[0]~input_o ))
|
|
|
|
.dataa(\dpwm|out_8bit [0]),
|
|
.datab(\dpid[0]~input_o ),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(gnd),
|
|
.combout(),
|
|
.cout(\dpwm|LessThan0~1_cout ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|LessThan0~1 .lut_mask = 16'h0088;
|
|
defparam \dpwm|LessThan0~1 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N2
|
|
cycloneive_lcell_comb \dpwm|LessThan0~3 (
|
|
// Equation(s):
|
|
// \dpwm|LessThan0~3_cout = CARRY((\dpid[1]~input_o & (\dpwm|Add0~0_combout & !\dpwm|LessThan0~1_cout )) # (!\dpid[1]~input_o & ((\dpwm|Add0~0_combout ) # (!\dpwm|LessThan0~1_cout ))))
|
|
|
|
.dataa(\dpid[1]~input_o ),
|
|
.datab(\dpwm|Add0~0_combout ),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\dpwm|LessThan0~1_cout ),
|
|
.combout(),
|
|
.cout(\dpwm|LessThan0~3_cout ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|LessThan0~3 .lut_mask = 16'h004D;
|
|
defparam \dpwm|LessThan0~3 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N4
|
|
cycloneive_lcell_comb \dpwm|LessThan0~5 (
|
|
// Equation(s):
|
|
// \dpwm|LessThan0~5_cout = CARRY((\dpwm|Add0~2_combout & (\dpid[2]~input_o & !\dpwm|LessThan0~3_cout )) # (!\dpwm|Add0~2_combout & ((\dpid[2]~input_o ) # (!\dpwm|LessThan0~3_cout ))))
|
|
|
|
.dataa(\dpwm|Add0~2_combout ),
|
|
.datab(\dpid[2]~input_o ),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\dpwm|LessThan0~3_cout ),
|
|
.combout(),
|
|
.cout(\dpwm|LessThan0~5_cout ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|LessThan0~5 .lut_mask = 16'h004D;
|
|
defparam \dpwm|LessThan0~5 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N6
|
|
cycloneive_lcell_comb \dpwm|LessThan0~7 (
|
|
// Equation(s):
|
|
// \dpwm|LessThan0~7_cout = CARRY((\dpid[3]~input_o & (\dpwm|Add0~4_combout & !\dpwm|LessThan0~5_cout )) # (!\dpid[3]~input_o & ((\dpwm|Add0~4_combout ) # (!\dpwm|LessThan0~5_cout ))))
|
|
|
|
.dataa(\dpid[3]~input_o ),
|
|
.datab(\dpwm|Add0~4_combout ),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\dpwm|LessThan0~5_cout ),
|
|
.combout(),
|
|
.cout(\dpwm|LessThan0~7_cout ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|LessThan0~7 .lut_mask = 16'h004D;
|
|
defparam \dpwm|LessThan0~7 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N8
|
|
cycloneive_lcell_comb \dpwm|LessThan0~9 (
|
|
// Equation(s):
|
|
// \dpwm|LessThan0~9_cout = CARRY((\dpwm|Add0~6_combout & (\dpid[4]~input_o & !\dpwm|LessThan0~7_cout )) # (!\dpwm|Add0~6_combout & ((\dpid[4]~input_o ) # (!\dpwm|LessThan0~7_cout ))))
|
|
|
|
.dataa(\dpwm|Add0~6_combout ),
|
|
.datab(\dpid[4]~input_o ),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\dpwm|LessThan0~7_cout ),
|
|
.combout(),
|
|
.cout(\dpwm|LessThan0~9_cout ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|LessThan0~9 .lut_mask = 16'h004D;
|
|
defparam \dpwm|LessThan0~9 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N10
|
|
cycloneive_lcell_comb \dpwm|LessThan0~11 (
|
|
// Equation(s):
|
|
// \dpwm|LessThan0~11_cout = CARRY((\dpid[5]~input_o & (\dpwm|Add0~8_combout & !\dpwm|LessThan0~9_cout )) # (!\dpid[5]~input_o & ((\dpwm|Add0~8_combout ) # (!\dpwm|LessThan0~9_cout ))))
|
|
|
|
.dataa(\dpid[5]~input_o ),
|
|
.datab(\dpwm|Add0~8_combout ),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\dpwm|LessThan0~9_cout ),
|
|
.combout(),
|
|
.cout(\dpwm|LessThan0~11_cout ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|LessThan0~11 .lut_mask = 16'h004D;
|
|
defparam \dpwm|LessThan0~11 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N12
|
|
cycloneive_lcell_comb \dpwm|LessThan0~13 (
|
|
// Equation(s):
|
|
// \dpwm|LessThan0~13_cout = CARRY((\dpwm|Add0~10_combout & (\dpid[6]~input_o & !\dpwm|LessThan0~11_cout )) # (!\dpwm|Add0~10_combout & ((\dpid[6]~input_o ) # (!\dpwm|LessThan0~11_cout ))))
|
|
|
|
.dataa(\dpwm|Add0~10_combout ),
|
|
.datab(\dpid[6]~input_o ),
|
|
.datac(gnd),
|
|
.datad(vcc),
|
|
.cin(\dpwm|LessThan0~11_cout ),
|
|
.combout(),
|
|
.cout(\dpwm|LessThan0~13_cout ));
|
|
// synopsys translate_off
|
|
defparam \dpwm|LessThan0~13 .lut_mask = 16'h004D;
|
|
defparam \dpwm|LessThan0~13 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y12_N14
|
|
cycloneive_lcell_comb \dpwm|LessThan0~14 (
|
|
// Equation(s):
|
|
// \dpwm|LessThan0~14_combout = (\dpwm|Add0~12_combout & (\dpwm|LessThan0~13_cout & \dpid[7]~input_o )) # (!\dpwm|Add0~12_combout & ((\dpwm|LessThan0~13_cout ) # (\dpid[7]~input_o )))
|
|
|
|
.dataa(\dpwm|Add0~12_combout ),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\dpid[7]~input_o ),
|
|
.cin(\dpwm|LessThan0~13_cout ),
|
|
.combout(\dpwm|LessThan0~14_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|LessThan0~14 .lut_mask = 16'hF550;
|
|
defparam \dpwm|LessThan0~14 .sum_lutc_input = "cin";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y17_N10
|
|
cycloneive_lcell_comb \dpwm|delay0 (
|
|
// Equation(s):
|
|
// \dpwm|delay0~combout = LCELL(!\dpwm|LessThan0~14_combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\dpwm|LessThan0~14_combout ),
|
|
.cin(gnd),
|
|
.combout(\dpwm|delay0~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|delay0 .lut_mask = 16'h00FF;
|
|
defparam \dpwm|delay0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y17_N4
|
|
cycloneive_lcell_comb \dpwm|de7 (
|
|
// Equation(s):
|
|
// \dpwm|de7~combout = LCELL(\dpwm|delay0~combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\dpwm|delay0~combout ),
|
|
.cin(gnd),
|
|
.combout(\dpwm|de7~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|de7 .lut_mask = 16'hFF00;
|
|
defparam \dpwm|de7 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y17_N12
|
|
cycloneive_lcell_comb \dpwm|delay1 (
|
|
// Equation(s):
|
|
// \dpwm|delay1~combout = LCELL(\dpwm|de7~combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\dpwm|de7~combout ),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\dpwm|delay1~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|delay1 .lut_mask = 16'hF0F0;
|
|
defparam \dpwm|delay1 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y17_N2
|
|
cycloneive_lcell_comb \dpwm|de6 (
|
|
// Equation(s):
|
|
// \dpwm|de6~combout = LCELL(\dpwm|delay1~combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\dpwm|delay1~combout ),
|
|
.cin(gnd),
|
|
.combout(\dpwm|de6~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|de6 .lut_mask = 16'hFF00;
|
|
defparam \dpwm|de6 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y17_N18
|
|
cycloneive_lcell_comb \dpwm|delay2 (
|
|
// Equation(s):
|
|
// \dpwm|delay2~combout = LCELL(\dpwm|de6~combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\dpwm|de6~combout ),
|
|
.cin(gnd),
|
|
.combout(\dpwm|delay2~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|delay2 .lut_mask = 16'hFF00;
|
|
defparam \dpwm|delay2 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y17_N28
|
|
cycloneive_lcell_comb \dpwm|de5 (
|
|
// Equation(s):
|
|
// \dpwm|de5~combout = LCELL(\dpwm|delay2~combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\dpwm|delay2~combout ),
|
|
.cin(gnd),
|
|
.combout(\dpwm|de5~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|de5 .lut_mask = 16'hFF00;
|
|
defparam \dpwm|de5 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y17_N0
|
|
cycloneive_lcell_comb \dpwm|delay3 (
|
|
// Equation(s):
|
|
// \dpwm|delay3~combout = LCELL(\dpwm|de5~combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\dpwm|de5~combout ),
|
|
.cin(gnd),
|
|
.combout(\dpwm|delay3~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|delay3 .lut_mask = 16'hFF00;
|
|
defparam \dpwm|delay3 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X33_Y18_N4
|
|
cycloneive_lcell_comb \dpwm|de4 (
|
|
// Equation(s):
|
|
// \dpwm|de4~combout = LCELL(\dpwm|delay3~combout )
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\dpwm|delay3~combout ),
|
|
.cin(gnd),
|
|
.combout(\dpwm|de4~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|de4 .lut_mask = 16'hFF00;
|
|
defparam \dpwm|de4 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N28
|
|
cycloneive_lcell_comb \dpwm|bit_high_syn~0 (
|
|
// Equation(s):
|
|
// \dpwm|bit_high_syn~0_combout = !\dpwm|out_8bit [7]
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(\dpwm|out_8bit [7]),
|
|
.datad(gnd),
|
|
.cin(gnd),
|
|
.combout(\dpwm|bit_high_syn~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|bit_high_syn~0 .lut_mask = 16'h0F0F;
|
|
defparam \dpwm|bit_high_syn~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y12_N29
|
|
dffeas \dpwm|bit_high_syn (
|
|
.clk(\clk~inputclkctrl_outclk ),
|
|
.d(\dpwm|bit_high_syn~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\dpwm|bit_high_syn~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \dpwm|bit_high_syn .is_wysiwyg = "true";
|
|
defparam \dpwm|bit_high_syn .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N18
|
|
cycloneive_lcell_comb \dpwm|n_bit_high_syn~0 (
|
|
// Equation(s):
|
|
// \dpwm|n_bit_high_syn~0_combout = !\dpwm|bit_high_syn~q
|
|
|
|
.dataa(gnd),
|
|
.datab(gnd),
|
|
.datac(gnd),
|
|
.datad(\dpwm|bit_high_syn~q ),
|
|
.cin(gnd),
|
|
.combout(\dpwm|n_bit_high_syn~0_combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|n_bit_high_syn~0 .lut_mask = 16'h00FF;
|
|
defparam \dpwm|n_bit_high_syn~0 .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
// Location: FF_X32_Y12_N19
|
|
dffeas \dpwm|n_bit_high_syn (
|
|
.clk(\clk~inputclkctrl_outclk ),
|
|
.d(\dpwm|n_bit_high_syn~0_combout ),
|
|
.asdata(vcc),
|
|
.clrn(vcc),
|
|
.aload(gnd),
|
|
.sclr(gnd),
|
|
.sload(gnd),
|
|
.ena(vcc),
|
|
.devclrn(devclrn),
|
|
.devpor(devpor),
|
|
.q(\dpwm|n_bit_high_syn~q ),
|
|
.prn(vcc));
|
|
// synopsys translate_off
|
|
defparam \dpwm|n_bit_high_syn .is_wysiwyg = "true";
|
|
defparam \dpwm|n_bit_high_syn .power_up = "low";
|
|
// synopsys translate_on
|
|
|
|
// Location: LCCOMB_X32_Y12_N8
|
|
cycloneive_lcell_comb \dpwm|pwm_out (
|
|
// Equation(s):
|
|
// \dpwm|pwm_out~combout = (\dpwm|n_bit_high_syn~q & \dpwm|bit_high_syn~q )
|
|
|
|
.dataa(gnd),
|
|
.datab(\dpwm|n_bit_high_syn~q ),
|
|
.datac(gnd),
|
|
.datad(\dpwm|bit_high_syn~q ),
|
|
.cin(gnd),
|
|
.combout(\dpwm|pwm_out~combout ),
|
|
.cout());
|
|
// synopsys translate_off
|
|
defparam \dpwm|pwm_out .lut_mask = 16'hCC00;
|
|
defparam \dpwm|pwm_out .sum_lutc_input = "datac";
|
|
// synopsys translate_on
|
|
|
|
endmodule
|